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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-009 / 8f13179aabb3377fdbb3f9f5b53eaffbfba934b0
commit8f13179aabb3377fdbb3f9f5b53eaffbfba934b0[log] [tgz]
authorManar <manarabdelatty@aucegypt.edu>Wed Nov 11 16:38:32 2020 +0200
committerManar <manarabdelatty@aucegypt.edu>Wed Nov 11 16:38:32 2020 +0200
tree58c9800d646545204beeb4e243696a7e49f673b1
parentb41204cbd952dd5cf2e633b809eab21da963020d [diff]
Updated custom memory

- dv simulations pass
4 files changed
tree: 58c9800d646545204beeb4e243696a7e49f673b1
  1. def/
  2. doc/
  3. gds/
  4. lef/
  5. macros/
  6. mag/
  7. openlane/
  8. scripts/
  9. spi/
  10. verilog/
  11. info.yaml
  12. LICENSE
  13. README.md
README.md

CIIC Harness

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware that can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC is given below
(NOTE: This needs updating; see the README file for an updated list.)

Mega Project Area

This is the user space. It has limited silicon area (TBD, about 2.8mm x 2.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.