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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-007 / fc7ff6812893a5fbef651bdc6778a4bec9fc6ba3 / . / verilog / dv / caravel / defs.h
blob: 2402f475ef0e37e395bfa8fa95ffdb906302d909 [file] [log] [blame]
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]1#ifndef _STRIVE_H_
2#define _STRIVE_H_
3
4#include <stdint.h>
5#include <stdbool.h>
6
7// a pointer to this is a null pointer, but the compiler does not
8// know that because "sram" is a linker symbol from sections.lds.
9extern uint32_t sram;
10
11// Pointer to firmware flash routines
12extern uint32_t flashio_worker_begin;
13extern uint32_t flashio_worker_end;
14
Manar55ec3692020-10-30 16:32:18 +0200[diff] [blame]15// Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
Manarffe6cad2020-11-09 19:09:04 +0200[diff] [blame]16#define reg_rw_block0 (*(volatile uint32_t*)0x01000000)
17#define reg_rw_block1 (*(volatile uint32_t*)0x01100000)
18#define reg_ro_block0 (*(volatile uint32_t*)0x02000000)
Manar14d35ac2020-10-21 22:47:15 +0200[diff] [blame]19
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]20// UART (0x2000_0000)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]21#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
22#define reg_uart_data (*(volatile uint32_t*)0x20000004)
Tim Edwardsca2f3182020-10-06 10:05:11 -0400[diff] [blame]23#define reg_uart_enable (*(volatile uint32_t*)0x20000008)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]24
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]25// GPIO (0x2100_0000)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]26#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
27#define reg_gpio_ena (*(volatile uint32_t*)0x21000004)
28#define reg_gpio_pu (*(volatile uint32_t*)0x21000008)
29#define reg_gpio_pd (*(volatile uint32_t*)0x2100000c)
30
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]31// Logic Analyzer (0x2200_0000)
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]32#define reg_la0_data (*(volatile uint32_t*)0x25000000)
33#define reg_la1_data (*(volatile uint32_t*)0x25000004)
34#define reg_la2_data (*(volatile uint32_t*)0x25000008)
35#define reg_la3_data (*(volatile uint32_t*)0x2500000c)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]36
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]37#define reg_la0_ena (*(volatile uint32_t*)0x25000010)
38#define reg_la1_ena (*(volatile uint32_t*)0x25000014)
39#define reg_la2_ena (*(volatile uint32_t*)0x25000018)
40#define reg_la3_ena (*(volatile uint32_t*)0x2500001c)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]41
Tim Edwardsba328902020-10-27 15:03:22 -0400[diff] [blame]42// User Project Control (0x2300_0000)
43#define reg_mprj_xfer (*(volatile uint32_t*)0x26000000)
44#define reg_mprj_pwr (*(volatile uint32_t*)0x26000004)
45#define reg_mprj_datal (*(volatile uint32_t*)0x26000008)
46#define reg_mprj_datah (*(volatile uint32_t*)0x2600000c)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]47
Tim Edwardsba328902020-10-27 15:03:22 -0400[diff] [blame]48#define reg_mprj_io_0 (*(volatile uint32_t*)0x26000020)
49#define reg_mprj_io_1 (*(volatile uint32_t*)0x26000024)
50#define reg_mprj_io_2 (*(volatile uint32_t*)0x26000028)
51#define reg_mprj_io_3 (*(volatile uint32_t*)0x2600002c)
52#define reg_mprj_io_4 (*(volatile uint32_t*)0x26000030)
53#define reg_mprj_io_5 (*(volatile uint32_t*)0x26000034)
54#define reg_mprj_io_6 (*(volatile uint32_t*)0x26000038)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]55
Tim Edwardsba328902020-10-27 15:03:22 -0400[diff] [blame]56#define reg_mprj_io_7 (*(volatile uint32_t*)0x2600003c)
57#define reg_mprj_io_8 (*(volatile uint32_t*)0x26000040)
58#define reg_mprj_io_9 (*(volatile uint32_t*)0x26000044)
59#define reg_mprj_io_10 (*(volatile uint32_t*)0x26000048)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]60
Tim Edwardsba328902020-10-27 15:03:22 -0400[diff] [blame]61#define reg_mprj_io_11 (*(volatile uint32_t*)0x2600004c)
62#define reg_mprj_io_12 (*(volatile uint32_t*)0x26000050)
63#define reg_mprj_io_13 (*(volatile uint32_t*)0x26000054)
64#define reg_mprj_io_14 (*(volatile uint32_t*)0x26000058)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]65
Tim Edwardsba328902020-10-27 15:03:22 -0400[diff] [blame]66#define reg_mprj_io_15 (*(volatile uint32_t*)0x2600005c)
67#define reg_mprj_io_16 (*(volatile uint32_t*)0x26000060)
68#define reg_mprj_io_17 (*(volatile uint32_t*)0x26000064)
69#define reg_mprj_io_18 (*(volatile uint32_t*)0x26000068)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]70
Tim Edwardsba328902020-10-27 15:03:22 -0400[diff] [blame]71#define reg_mprj_io_19 (*(volatile uint32_t*)0x2600006c)
72#define reg_mprj_io_20 (*(volatile uint32_t*)0x26000070)
73#define reg_mprj_io_21 (*(volatile uint32_t*)0x26000074)
74#define reg_mprj_io_22 (*(volatile uint32_t*)0x26000078)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]75
Tim Edwardsba328902020-10-27 15:03:22 -0400[diff] [blame]76#define reg_mprj_io_23 (*(volatile uint32_t*)0x2600007c)
77#define reg_mprj_io_24 (*(volatile uint32_t*)0x26000080)
78#define reg_mprj_io_25 (*(volatile uint32_t*)0x26000084)
79#define reg_mprj_io_26 (*(volatile uint32_t*)0x26000088)
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]80
Tim Edwardsba328902020-10-27 15:03:22 -0400[diff] [blame]81#define reg_mprj_io_27 (*(volatile uint32_t*)0x2600008c)
82#define reg_mprj_io_28 (*(volatile uint32_t*)0x26000090)
83#define reg_mprj_io_29 (*(volatile uint32_t*)0x26000094)
84#define reg_mprj_io_30 (*(volatile uint32_t*)0x26000098)
85#define reg_mprj_io_31 (*(volatile uint32_t*)0x2600009c)
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]86
Tim Edwardsba328902020-10-27 15:03:22 -0400[diff] [blame]87#define reg_mprj_io_32 (*(volatile uint32_t*)0x260000a0)
88#define reg_mprj_io_33 (*(volatile uint32_t*)0x260000a4)
89#define reg_mprj_io_34 (*(volatile uint32_t*)0x260000a8)
90#define reg_mprj_io_35 (*(volatile uint32_t*)0x260000ac)
91#define reg_mprj_io_36 (*(volatile uint32_t*)0x260000b0)
92#define reg_mprj_io_37 (*(volatile uint32_t*)0x260000b4)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]93
Tim Edwardsba328902020-10-27 15:03:22 -0400[diff] [blame]94// User Project Slaves (0x3000_0000)
shalan0d14e6e2020-08-31 16:50:48 +0200[diff] [blame]95#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
96
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]97// Flash Control SPI Configuration (2D00_0000)
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]98#define reg_spictrl (*(volatile uint32_t*)0x2d000000)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]99
Tim Edwardsba328902020-10-27 15:03:22 -0400[diff] [blame]100// Bit fields for Flash SPI control
101#define FLASH_BITBANG_IO0 0x00000001
102#define FLASH_BITBANG_IO1 0x00000002
103#define FLASH_BITBANG_CLK 0x00000010
104#define FLASH_BITBANG_CSB 0x00000020
105#define FLASH_BITBANG_OEB0 0x00000100
106#define FLASH_BITBANG_OEB1 0x00000200
107#define FLASH_ENABLE 0x80000000
108
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]109// Counter-Timer 0 Configuration
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]110#define reg_timer0_config (*(volatile uint32_t*)0x22000000)
111#define reg_timer0_value (*(volatile uint32_t*)0x22000004)
112#define reg_timer0_data (*(volatile uint32_t*)0x22000008)
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]113
114// Counter-Timer 1 Configuration
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]115#define reg_timer1_config (*(volatile uint32_t*)0x23000000)
116#define reg_timer1_value (*(volatile uint32_t*)0x23000004)
117#define reg_timer1_data (*(volatile uint32_t*)0x23000008)
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]118
Tim Edwardsba328902020-10-27 15:03:22 -0400[diff] [blame]119// Bit fields for Counter-timer configuration
120#define TIMER_ENABLE 0x01
121#define TIMER_ONESHOT 0x02
122#define TIMER_UPCOUNT 0x04
123#define TIMER_CHAIN 0x08
124#define TIMER_IRQ_ENABLE 0x10
125
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]126// SPI Master Configuration
Tim Edwards856b0922020-10-09 16:30:22 -0400[diff] [blame]127#define reg_spimaster_config (*(volatile uint32_t*)0x24000000)
128#define reg_spimaster_data (*(volatile uint32_t*)0x24000004)
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]129
Tim Edwardsba328902020-10-27 15:03:22 -0400[diff] [blame]130// Bit fields for SPI master configuration
131#define SPI_MASTER_DIV_MASK 0x00ff
132#define SPI_MASTER_MLB 0x0100
133#define SPI_MASTER_INV_CSB 0x0200
134#define SPI_MASTER_INV_CLK 0x0400
135#define SPI_MASTER_MODE_1 0x0800
136#define SPI_MASTER_STREAM 0x1000
137#define SPI_MASTER_ENABLE 0x2000
138#define SPI_MASTER_IRQ_ENABLE 0x4000
139#define SPI_HOUSEKEEPING_CONN 0x8000
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]140
Tim Edwardsba328902020-10-27 15:03:22 -0400[diff] [blame]141// System Area (0x2F00_0000)
142#define reg_power_good (*(volatile uint32_t*)0x2F000000)
143#define reg_clk_out_dest (*(volatile uint32_t*)0x2F000004)
144#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000008)
145#define reg_irq_source (*(volatile uint32_t*)0x2F00000C)
146
147// Bit fields for reg_power_good
148#define USER1_VCCD_POWER_GOOD 0x01
149#define USER2_VCCD_POWER_GOOD 0x02
150#define USER1_VDDA_POWER_GOOD 0x04
151#define USER2_VDDA_POWER_GOOD 0x08
152
153// Bit fields for reg_clk_out_dest
154#define CLOCK1_MONITOR 0x01
155#define CLOCK2_MONITOR 0x02
156
157// Bit fields for reg_irq_source
158#define IRQ7_SOURCE 0x01
159#define IRQ8_SOURCE 0x02
160
161// Individual bit fields for the GPIO pad control
162#define MGMT_ENABLE 0x0001
163#define OUTPUT_DISABLE 0x0002
164#define HOLD_OVERRIDE 0x0004
165#define INPUT_DISABLE 0x0008
166#define MODE_SELECT 0x0010
167#define ANALOG_ENABLE 0x0020
168#define ANALOG_SELECT 0x0040
169#define ANALOG_POLARITY 0x0080
170#define SLOW_SLEW_MODE 0x0100
171#define TRIPPOINT_SEL 0x0200
172#define DIGITAL_MODE_MASK 0x1c00
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]173
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]174// Useful GPIO mode values
175#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
176#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0803
177#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c03
Tim Edwardsf51dd082020-10-05 16:30:24 -0400[diff] [blame]178#define GPIO_MODE_MGMT_STD_OUTPUT 0x1809
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]179
180#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
181#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0802
182#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c02
Tim Edwardsf51dd082020-10-05 16:30:24 -0400[diff] [blame]183#define GPIO_MODE_USER_STD_OUTPUT 0x1808
Tim Edwards44bab472020-10-04 22:09:54 -0400[diff] [blame]184
shalanfd13eb52020-08-21 16:48:07 +0200[diff] [blame]185// --------------------------------------------------------
186#endif