Connected storage area to mgmt_core
- Added wishbone bridge in mgmt_soc to contain all logic needed for the core to interface
with the storage area
- Updated defs.h with the base addresses for the storage blocks
- Added R/W test for the mgmt blocks
diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h
index c9c0714..0aba014 100644
--- a/verilog/dv/caravel/defs.h
+++ b/verilog/dv/caravel/defs.h
@@ -12,8 +12,13 @@
extern uint32_t flashio_worker_begin;
extern uint32_t flashio_worker_end;
-// SYNTH_MEM (0x0100_0000)
-#define reg_synth_mem (*(volatile uint32_t*)0x01000000)
+// Storage area (MGMT: 0x0100_0000, User: 0x0200_0000)
+#define reg_mgmt_block0 (*(volatile uint32_t*)0x01000000)
+#define reg_mgmt_block1 (*(volatile uint32_t*)0x01100000)
+#define reg_user_block0 (*(volatile uint32_t*)0x02000000)
+#define reg_user_block1 (*(volatile uint32_t*)0x02100000)
+#define reg_user_block2 (*(volatile uint32_t*)0x02200000)
+#define reg_user_block3 (*(volatile uint32_t*)0x02300000)
// UART (0x2000_0000)
#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
