commit 14d35ac952caec3f6ff1a06b25a22cbef70d526d
author Manar <manarabdelatty@aucegypt.edu> Wed Oct 21 22:47:15 2020 +0200
committer Manar <manarabdelatty@aucegypt.edu> Wed Oct 21 22:47:15 2020 +0200
tree 08e7b35f37f5b7a919a3e3cc9e5192f449a2ec4c
parent 5f968550ba00cc2839093085ca89efa092cefb81

Added synthesized memory (4kb)

verilog/dv/caravel/defs.h

diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h
index abfcd44..20a426c 100644
--- a/verilog/dv/caravel/defs.h
+++ b/verilog/dv/caravel/defs.h
@@ -12,6 +12,9 @@
 extern uint32_t flashio_worker_begin;
 extern uint32_t flashio_worker_end;
 
+// SYNTH_MEM (0x0100_0000)
+#define reg_synth_mem (*(volatile uint32_t*)0x01000000)
+
 // UART (0x2000_0000)
 #define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
 #define reg_uart_data   (*(volatile uint32_t*)0x20000004)