Added synthesized memory (4kb)
diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h
index abfcd44..20a426c 100644
--- a/verilog/dv/caravel/defs.h
+++ b/verilog/dv/caravel/defs.h
@@ -12,6 +12,9 @@
extern uint32_t flashio_worker_begin;
extern uint32_t flashio_worker_end;
+// SYNTH_MEM (0x0100_0000)
+#define reg_synth_mem (*(volatile uint32_t*)0x01000000)
+
// UART (0x2000_0000)
#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
#define reg_uart_data (*(volatile uint32_t*)0x20000004)
diff --git a/verilog/dv/caravel/sections.lds b/verilog/dv/caravel/sections.lds
index 8482887..0e80064 100644
--- a/verilog/dv/caravel/sections.lds
+++ b/verilog/dv/caravel/sections.lds
@@ -1,6 +1,6 @@
MEMORY {
FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x400000 /* 4MB */
- RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x8000 /* 8192 words ( 32 KB) */
+ RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x1400 /* 1280 words (5 KB) */
}
SECTIONS {
