Corrected the counter/timer and made an enhancement to respond to a
disable/enable sequence as a counter reset. Generated testbenches
for both counter/timers.
diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h
index f777c39..68c2000 100644
--- a/verilog/dv/caravel/defs.h
+++ b/verilog/dv/caravel/defs.h
@@ -24,59 +24,65 @@
#define reg_gpio_pd (*(volatile uint32_t*)0x2100000c)
// Logic Analyzer (0x2200_0000)
-#define reg_la0_data (*(volatile uint32_t*)0x22000000)
-#define reg_la1_data (*(volatile uint32_t*)0x22000004)
-#define reg_la2_data (*(volatile uint32_t*)0x22000008)
-#define reg_la3_data (*(volatile uint32_t*)0x2200000c)
+#define reg_la0_data (*(volatile uint32_t*)0x25000000)
+#define reg_la1_data (*(volatile uint32_t*)0x25000004)
+#define reg_la2_data (*(volatile uint32_t*)0x25000008)
+#define reg_la3_data (*(volatile uint32_t*)0x2500000c)
-#define reg_la0_ena (*(volatile uint32_t*)0x22000010)
-#define reg_la1_ena (*(volatile uint32_t*)0x22000014)
-#define reg_la2_ena (*(volatile uint32_t*)0x22000018)
-#define reg_la3_ena (*(volatile uint32_t*)0x2200001c)
+#define reg_la0_ena (*(volatile uint32_t*)0x25000010)
+#define reg_la1_ena (*(volatile uint32_t*)0x25000014)
+#define reg_la2_ena (*(volatile uint32_t*)0x25000018)
+#define reg_la3_ena (*(volatile uint32_t*)0x2500001c)
// Mega Project Control (0x2300_0000)
-#define reg_mprj_datal (*(volatile uint32_t*)0x23000000)
-#define reg_mprj_datah (*(volatile uint32_t*)0x23000004)
-#define reg_mprj_xfer (*(volatile uint32_t*)0x23000008)
+#define reg_mprj_datal (*(volatile uint32_t*)0x26000000)
+#define reg_mprj_datah (*(volatile uint32_t*)0x26000004)
+#define reg_mprj_xfer (*(volatile uint32_t*)0x26000008)
-#define reg_mprj_io_0 (*(volatile uint32_t*)0x2300000c)
-#define reg_mprj_io_1 (*(volatile uint32_t*)0x23000010)
-#define reg_mprj_io_2 (*(volatile uint32_t*)0x23000014)
-#define reg_mprj_io_3 (*(volatile uint32_t*)0x23000018)
-#define reg_mprj_io_4 (*(volatile uint32_t*)0x2300001c)
-#define reg_mprj_io_5 (*(volatile uint32_t*)0x23000020)
-#define reg_mprj_io_6 (*(volatile uint32_t*)0x23000024)
+#define reg_mprj_io_0 (*(volatile uint32_t*)0x2600000c)
+#define reg_mprj_io_1 (*(volatile uint32_t*)0x26000010)
+#define reg_mprj_io_2 (*(volatile uint32_t*)0x26000014)
+#define reg_mprj_io_3 (*(volatile uint32_t*)0x26000018)
+#define reg_mprj_io_4 (*(volatile uint32_t*)0x2600001c)
+#define reg_mprj_io_5 (*(volatile uint32_t*)0x26000020)
+#define reg_mprj_io_6 (*(volatile uint32_t*)0x26000024)
-#define reg_mprj_io_7 (*(volatile uint32_t*)0x23000028)
-#define reg_mprj_io_8 (*(volatile uint32_t*)0x2300002c)
-#define reg_mprj_io_9 (*(volatile uint32_t*)0x23000030)
-#define reg_mprj_io_10 (*(volatile uint32_t*)0x23000034)
+#define reg_mprj_io_7 (*(volatile uint32_t*)0x26000028)
+#define reg_mprj_io_8 (*(volatile uint32_t*)0x2600002c)
+#define reg_mprj_io_9 (*(volatile uint32_t*)0x26000030)
+#define reg_mprj_io_10 (*(volatile uint32_t*)0x26000034)
-#define reg_mprj_io_11 (*(volatile uint32_t*)0x23000038)
-#define reg_mprj_io_12 (*(volatile uint32_t*)0x2300003c)
-#define reg_mprj_io_13 (*(volatile uint32_t*)0x23000040)
-#define reg_mprj_io_14 (*(volatile uint32_t*)0x23000044)
+#define reg_mprj_io_11 (*(volatile uint32_t*)0x26000038)
+#define reg_mprj_io_12 (*(volatile uint32_t*)0x2600003c)
+#define reg_mprj_io_13 (*(volatile uint32_t*)0x26000040)
+#define reg_mprj_io_14 (*(volatile uint32_t*)0x26000044)
-#define reg_mprj_io_15 (*(volatile uint32_t*)0x23000048)
-#define reg_mprj_io_16 (*(volatile uint32_t*)0x2300004c)
-#define reg_mprj_io_17 (*(volatile uint32_t*)0x23000050)
-#define reg_mprj_io_18 (*(volatile uint32_t*)0x23000054)
+#define reg_mprj_io_15 (*(volatile uint32_t*)0x26000048)
+#define reg_mprj_io_16 (*(volatile uint32_t*)0x2600004c)
+#define reg_mprj_io_17 (*(volatile uint32_t*)0x26000050)
+#define reg_mprj_io_18 (*(volatile uint32_t*)0x26000054)
-#define reg_mprj_io_19 (*(volatile uint32_t*)0x23000058)
-#define reg_mprj_io_20 (*(volatile uint32_t*)0x2300005c)
-#define reg_mprj_io_21 (*(volatile uint32_t*)0x23000060)
-#define reg_mprj_io_22 (*(volatile uint32_t*)0x23000064)
+#define reg_mprj_io_19 (*(volatile uint32_t*)0x26000058)
+#define reg_mprj_io_20 (*(volatile uint32_t*)0x2600005c)
+#define reg_mprj_io_21 (*(volatile uint32_t*)0x26000060)
+#define reg_mprj_io_22 (*(volatile uint32_t*)0x26000064)
-#define reg_mprj_io_23 (*(volatile uint32_t*)0x23000068)
-#define reg_mprj_io_24 (*(volatile uint32_t*)0x2300006c)
-#define reg_mprj_io_25 (*(volatile uint32_t*)0x23000070)
-#define reg_mprj_io_26 (*(volatile uint32_t*)0x23000074)
+#define reg_mprj_io_23 (*(volatile uint32_t*)0x26000068)
+#define reg_mprj_io_24 (*(volatile uint32_t*)0x2600006c)
+#define reg_mprj_io_25 (*(volatile uint32_t*)0x26000070)
+#define reg_mprj_io_26 (*(volatile uint32_t*)0x26000074)
-#define reg_mprj_io_27 (*(volatile uint32_t*)0x23000078)
-#define reg_mprj_io_28 (*(volatile uint32_t*)0x2300007c)
-#define reg_mprj_io_29 (*(volatile uint32_t*)0x23000080)
-#define reg_mprj_io_30 (*(volatile uint32_t*)0x23000084)
-#define reg_mprj_io_31 (*(volatile uint32_t*)0x23000088)
+#define reg_mprj_io_27 (*(volatile uint32_t*)0x26000078)
+#define reg_mprj_io_28 (*(volatile uint32_t*)0x2600007c)
+#define reg_mprj_io_29 (*(volatile uint32_t*)0x26000080)
+#define reg_mprj_io_30 (*(volatile uint32_t*)0x26000084)
+#define reg_mprj_io_31 (*(volatile uint32_t*)0x26000088)
+
+#define reg_mprj_io_32 (*(volatile uint32_t*)0x2600008c)
+#define reg_mprj_io_33 (*(volatile uint32_t*)0x26000090)
+#define reg_mprj_io_34 (*(volatile uint32_t*)0x26000094)
+#define reg_mprj_io_35 (*(volatile uint32_t*)0x26000098)
+#define reg_mprj_io_36 (*(volatile uint32_t*)0x2600009c)
// Mega Project Slaves (0x3000_0000)
#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
@@ -85,18 +91,18 @@
#define reg_spictrl (*(volatile uint32_t*)0x2d000000)
// Counter-Timer 0 Configuration
-#define reg_timer0_config (*(volatile uint32_t*)0x21100000)
-#define reg_timer0_value (*(volatile uint32_t*)0x21100004)
-#define reg_timer0_data (*(volatile uint32_t*)0x21100008)
+#define reg_timer0_config (*(volatile uint32_t*)0x22000000)
+#define reg_timer0_value (*(volatile uint32_t*)0x22000004)
+#define reg_timer0_data (*(volatile uint32_t*)0x22000008)
// Counter-Timer 1 Configuration
-#define reg_timer1_config (*(volatile uint32_t*)0x21200000)
-#define reg_timer1_value (*(volatile uint32_t*)0x21200004)
-#define reg_timer1_data (*(volatile uint32_t*)0x21200008)
+#define reg_timer1_config (*(volatile uint32_t*)0x23000000)
+#define reg_timer1_value (*(volatile uint32_t*)0x23000004)
+#define reg_timer1_data (*(volatile uint32_t*)0x23000008)
// SPI Master Configuration
-#define reg_spimaster_config (*(volatile uint32_t*)0x21300000)
-#define reg_spimaster_data (*(volatile uint32_t*)0x21300004)
+#define reg_spimaster_config (*(volatile uint32_t*)0x24000000)
+#define reg_spimaster_data (*(volatile uint32_t*)0x24000004)
// System Area (0x2F00_0000)
#define reg_pll_out_dest (*(volatile uint32_t*)0x2F00000c)
