Remove hand-built simple_por from the openlane dir

commit: c98236505c3a83925213f6f29533def100239611 [log] [tgz]
author: Ahmed Ghazy <ax3ghazy@aucegypt.edu> Sun Nov 29 20:10:43 2020 +0200
committer: Ahmed Ghazy <ax3ghazy@aucegypt.edu> Sun Nov 29 20:10:43 2020 +0200
tree: 697648900ade2c0f4dbad6b0ff2b6af63a3db289
parent: 740defbfb78892a0a0fd50a50364f7a7bede2c10 [diff]
diff --git a/openlane/simple_por/config.tcl b/openlane/simple_por/config.tcl
deleted file mode 100755
index 5a5d854..0000000
--- a/openlane/simple_por/config.tcl
+++ /dev/null

@@ -1,18 +0,0 @@
-# This is an analog design. It will be designed by hand.
-# This is a placeholder to get things going.
-set script_dir [file dirname [file normalize [info script]]]
-# User config
-set ::env(DESIGN_NAME) simple_por
-set ::env(STD_CELL_LIBRARY) sky130_fd_sc_hvl
-
-# Change if needed
-set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/simple_por.v
-set ::env(SYNTH_READ_BLACKBOX_LIB) 1
-
-# Fill this
-set ::env(CLOCK_TREE_SYNTH) 0
-
-set ::env(CELL_PAD) 8
-
-set ::env(FP_CORE_UTIL) 30
-set ::env(PL_TARGET_DENSITY) 0.5

diff --git a/openlane/simple_por/runs/simple_por/cmds.log b/openlane/simple_por/runs/simple_por/cmds.log
deleted file mode 100644
index 21bea90..0000000
--- a/openlane/simple_por/runs/simple_por/cmds.log
+++ /dev/null

@@ -1,76 +0,0 @@
-Wed Nov 11 03:14:10 UTC 2020 - Executing "/openLANE_flow/scripts/mergeLef.py -i /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/techlef/sky130_fd_sc_hvl.tlef /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lef/sky130_fd_sc_hvl.lef -o /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef |& tee >&@stdout"
-
-Wed Nov 11 03:14:10 UTC 2020 - Executing "/openLANE_flow/scripts/libtrim.pl { /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib  /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib} /home/xrex/usr/devel/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hvl/no_synth.cells > /project/openlane/simple_por/runs/simple_por/tmp/trimmed.lib"
-
-Wed Nov 11 03:14:10 UTC 2020 - Executing "yosys -c /openLANE_flow/scripts/synth.tcl -l /project/openlane/simple_por/runs/simple_por/logs/synthesis/yosys.log |& tee >&@stdout"
-
-Wed Nov 11 03:14:11 UTC 2020 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/project\/openlane\/simple_por\/runs\/simple_por\/results\/synthesis\/simple_por.synthesis.v/} /project/openlane/simple_por/runs/simple_por/config.tcl"
-
-Wed Nov 11 03:14:11 UTC 2020 - Executing "sed -i -e {s/\(set ::env(PREV_NETLIST)\).*/\1 0/} /project/openlane/simple_por/runs/simple_por/config.tcl"
-
-Wed Nov 11 03:14:11 UTC 2020 - Executing "sta /openLANE_flow/scripts/sta.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/synthesis/opensta.log"
-
-Wed Nov 11 03:14:11 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_floorplan.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/floorplan/verilog2def.openroad.log"
-
-Wed Nov 11 03:14:12 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_ioplacer.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/floorplan/ioPlacer.log"
-
-Wed Nov 11 03:14:12 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_replace.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/placement/replace.log"
-
-Wed Nov 11 03:14:13 UTC 2020 - Executing "/openLANE_flow/scripts/libtrim.pl /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ss_150C_1v65.lib /home/xrex/usr/devel/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hvl/no_synth.cells > /project/openlane/simple_por/runs/simple_por/tmp/opt.lib"
-
-Wed Nov 11 03:14:13 UTC 2020 - Executing "Psn /openLANE_flow/scripts/openPhySyn.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/placement/openphysyn.log"
-
-Wed Nov 11 03:14:13 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_write_verilog.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/write_verilog.log"
-
-Wed Nov 11 03:14:14 UTC 2020 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/project\/openlane\/simple_por\/runs\/simple_por\/results\/synthesis\/simple_por.synthesis_optimized.v/} /project/openlane/simple_por/runs/simple_por/config.tcl"
-
-Wed Nov 11 03:14:14 UTC 2020 - Executing "sed -i -e {s/\(set ::env(PREV_NETLIST)\).*/\1 \/project\/openlane\/simple_por\/runs\/simple_por\/results\/synthesis\/simple_por.synthesis.v/} /project/openlane/simple_por/runs/simple_por/config.tcl"
-
-Wed Nov 11 03:14:14 UTC 2020 - Executing "sta /openLANE_flow/scripts/sta.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/synthesis/opensta_post_openphysyn.log"
-
-Wed Nov 11 03:14:14 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_opendp.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/placement/opendp.log"
-
-Wed Nov 11 03:14:14 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/new_pdn.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/floorplan/pdn.log"
-
-Wed Nov 11 03:14:15 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_route.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/routing/fastroute.log"
-
-Wed Nov 11 03:14:15 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_route.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/routing/fastroute_post_antenna.log"
-
-Wed Nov 11 03:14:16 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_fill.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/routing/addspacers.log"
-
-Wed Nov 11 03:14:16 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_write_verilog.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/write_verilog.log"
-
-Wed Nov 11 03:14:17 UTC 2020 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/project\/openlane\/simple_por\/runs\/simple_por\/results\/synthesis\/simple_por.synthesis_preroute.v/} /project/openlane/simple_por/runs/simple_por/config.tcl"
-
-Wed Nov 11 03:14:17 UTC 2020 - Executing "sed -i -e {s/\(set ::env(PREV_NETLIST)\).*/\1 \/project\/openlane\/simple_por\/runs\/simple_por\/results\/synthesis\/simple_por.synthesis_optimized.v/} /project/openlane/simple_por/runs/simple_por/config.tcl"
-
-Wed Nov 11 03:14:17 UTC 2020 - Executing "envsubst < /openLANE_flow/scripts/tritonRoute.param > /project/openlane/simple_por/runs/simple_por/tmp/routing/tritonRoute.param"
-
-Wed Nov 11 03:14:17 UTC 2020 - Executing "TritonRoute /project/openlane/simple_por/runs/simple_por/tmp/routing/tritonRoute.param |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/routing/tritonRoute.log"
-
-Wed Nov 11 03:14:18 UTC 2020 - Executing "python3 /openLANE_flow/scripts/spef_extractor/main.py -l /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef -d /project/openlane/simple_por/runs/simple_por/results/routing/simple_por.def -mw PI -ec 1 |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/routing/spef_extraction.log"
-
-Wed Nov 11 03:14:18 UTC 2020 - Executing "sta /openLANE_flow/scripts/sta.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/synthesis/opensta_spef.log"
-
-Wed Nov 11 03:14:18 UTC 2020 - Executing "python3 /openLANE_flow/scripts/write_powered_def.py -d /project/openlane/simple_por/runs/simple_por/results/routing/simple_por.def -l /project/openlane/simple_por/runs/simple_por/tmp/merged.lef -v VPWR -g VGND -o /project/openlane/simple_por/runs/simple_por/tmp/routing/simple_por.powered.def |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/lvs/write_powered_verilog.log"
-
-Wed Nov 11 03:14:18 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_write_verilog.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/write_verilog.log"
-
-Wed Nov 11 03:14:19 UTC 2020 - Executing "yosys -c /openLANE_flow/scripts/yosys_rewrite_verilog.tcl -l /project/openlane/simple_por/runs/simple_por/logs/synthesis/yosys_rewrite_verilog.log"
-
-Wed Nov 11 03:14:19 UTC 2020 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/project\/openlane\/simple_por\/runs\/simple_por\/results\/lvs\/simple_por.lvs.powered.v/} /project/openlane/simple_por/runs/simple_por/config.tcl"
-
-Wed Nov 11 03:14:19 UTC 2020 - Executing "sed -i -e {s/\(set ::env(PREV_NETLIST)\).*/\1 \/project\/openlane\/simple_por\/runs\/simple_por\/results\/synthesis\/simple_por.synthesis_preroute.v/} /project/openlane/simple_por/runs/simple_por/config.tcl"
-
-Wed Nov 11 03:14:19 UTC 2020 - Executing "magic -noconsole -dnull -rcfile /home/xrex/usr/devel/pdks/sky130A/libs.tech/magic/sky130A.magicrc /openLANE_flow/scripts/magic.tcl </dev/null |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/magic/magic.log"
-
-Wed Nov 11 03:14:19 UTC 2020 - Executing "magic -noconsole -dnull -rcfile /home/xrex/usr/devel/pdks/sky130A/libs.tech/magic/sky130A.magicrc /project/openlane/simple_por/runs/simple_por/tmp/magic_spice.tcl </dev/null |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/magic/magic_spice.log"
-
-Wed Nov 11 03:14:19 UTC 2020 - Executing "magic -noconsole -dnull -rcfile /home/xrex/usr/devel/pdks/sky130A/libs.tech/magic/sky130A.magicrc /openLANE_flow/scripts/magic_drc.tcl </dev/null |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/magic/magic.drc.log"
-
-Wed Nov 11 03:14:20 UTC 2020 - Executing "netgen -batch lvs {/project/openlane/simple_por/runs/simple_por/results/magic/simple_por.spice simple_por} {/project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.powered.v simple_por} /home/xrex/usr/devel/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl /project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.log -json |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/lvs/lvs.log"
-
-Wed Nov 11 03:14:20 UTC 2020 - Executing "openroad -exit /openLANE_flow/scripts/openroad/or_antenna_check.tcl |& tee >&@stdout /project/openlane/simple_por/runs/simple_por/logs/routing/or_antenna.log"
-
-Wed Nov 11 03:14:20 UTC 2020 - Executing "python3 /openLANE_flow/report_generation_wrapper.py -d /project/openlane/simple_por -dn simple_por -t simple_por -o /project/openlane/simple_por/runs/simple_por/reports/final_summary_report.csv -r /project/openlane/simple_por/runs/simple_por"
-

diff --git a/openlane/simple_por/runs/simple_por/config.tcl b/openlane/simple_por/runs/simple_por/config.tcl
deleted file mode 100644
index f8bcacc..0000000
--- a/openlane/simple_por/runs/simple_por/config.tcl
+++ /dev/null

@@ -1,83 +0,0 @@
-# General config
-set ::env(PDK) "sky130A"
-set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hvl"
-set ::env(PDK_ROOT) "/home/xrex/usr/devel/pdks"
-set ::env(CELL_PAD) "8"
-set ::env(MERGED_LEF) "/project/openlane/simple_por/runs/simple_por/tmp/merged.lef"
-set ::env(MERGED_LEF_UNPADDED) "/project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef"
-set ::env(TRACKS_INFO_FILE) "/project/openlane/simple_por/runs/simple_por/tmp/tracks_copy.info"
-set ::env(TECH_LEF) "/home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/techlef/sky130_fd_sc_hvl.tlef"
-# Design config
-set ::env(CLOCK_PERIOD) "10"
-# Synthesis config
-set ::env(LIB_SYNTH) "/project/openlane/simple_por/runs/simple_por/tmp/trimmed.lib"
-set ::env(LIB_SYNTH_COMPLETE) " /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib  /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib"
-set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hvl__inv_16"
-set ::env(SYNTH_CAP_LOAD) "35.49"
-set ::env(SYNTH_MAX_FANOUT) "5"
-set ::env(SYNTH_NO_FLAT) "0"
-set ::env(SYNTH_MAX_TRAN) "[expr {0.1*10}]"
-set ::env(LIB_FASTEST) "/home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ff_n40C_5v50.lib"
-set ::env(LIB_SLOWEST) "/home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ss_150C_1v65.lib"
-set ::env(LIB_TYPICAL) " /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib  /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib"
-set ::env(SYNTH_SCRIPT) "/openLANE_flow/scripts/synth.tcl"
-set ::env(SYNTH_STRATEGY) "2"
-set ::env(CLOCK_BUFFER_FANOUT) "16"
-set ::env(BASE_SDC_FILE) "/openLANE_flow/scripts/base.sdc"
-# Floorplan config
-set ::env(FP_CORE_UTIL) "30"
-set ::env(FP_ASPECT_RATIO) "1"
-set ::env(FP_CORE_MARGIN) "0"
-set ::env(FP_IO_HMETAL) "4"
-set ::env(FP_IO_VMETAL) "3"
-set ::env(FP_ENDCAP_CELL) "sky130_fd_sc_hvl__decap_4"
-set ::env(FP_PDN_VOFFSET) "16.32"
-set ::env(FP_PDN_VPITCH) "153.6"
-set ::env(FP_PDN_HOFFSET) "16.65"
-set ::env(FP_PDN_HPITCH) "153.18"
-set ::env(FP_TAPCELL_DIST) "14"
-# Placement config
-set ::env(PL_TARGET_DENSITY) "0.5"
-set ::env(PL_TIME_DRIVEN) "0"
-set ::env(PL_LIB) " /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib  /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib"
-set ::env(PL_BASIC_PLACEMENT) "0"
-set ::env(PL_SKIP_INITIAL_PLACEMENT) "0"
-set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) "1"
-set ::env(PSN_ENABLE_RESIZING) "1"
-set ::env(PSN_ENABLE_PIN_SWAP) "1"
-set ::env(PL_RESIZER_OVERBUFFER) "0"
-# CTS config
-set ::env(CTS_TARGET_SKEW) "200"
-set ::env(CTS_ROOT_BUFFER) "sky130_fd_sc_hvl__buf_16"
-set ::env(CTS_TECH_DIR) "N/A"
-set ::env(CTS_TOLERANCE) "100"
-# Routing config
-set ::env(GLB_RT_MAXLAYER) "6"
-set ::env(GLB_RT_ADJUSTMENT) "0"
-set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
-set ::env(GLB_RT_L2_ADJUSTMENT) "0"
-set ::env(GLB_RT_MINLAYER) "1"
-set ::env(GLB_RT_MAXLAYER) "6"
-set ::env(GLB_RT_UNIDIRECTIONAL) "1"
-set ::env(GLB_RT_ALLOW_CONGESTION) "0"
-set ::env(GLB_RT_OVERFLOW_ITERS) "50"
-set ::env(GLB_RT_TILES) "15"
-set ::env(GLB_RT_ESTIMATE_PARASITICS) "0"
-set ::env(GLB_RT_MAX_DIODE_INS_ITERS) "1"
-set ::env(DIODE_PADDING) "2"
-set ::env(SPEF_WIRE_MODEL) "PI"
-set ::env(SPEF_EDGE_CAP_FACTOR) "1"
-# Flow control config
-set ::env(RUN_SIMPLE_CTS) "0"
-set ::env(RUN_ROUTING_DETAILED) "1"
-set ::env(CLOCK_TREE_SYNTH) "0"
-set ::env(LEC_ENABLE) "0"
-set ::env(FILL_INSERTION) "1"
-set ::env(DIODE_INSERTION_STRATEGY) "3"
-set ::env(CHECK_ASSIGN_STATEMENTS) "0"
-set ::env(CHECK_UNMAPPED_CELLS) "1"
-set ::env(USE_ARC_ANTENNA_CHECK) "1"
-set ::env(RUN_SPEF_EXTRACTION) "1"
-set ::env(CURRENT_DEF) /project/openlane/simple_por/runs/simple_por/results/routing/simple_por.def
-set ::env(CURRENT_NETLIST) /project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.powered.v
-set ::env(PREV_NETLIST) /project/openlane/simple_por/runs/simple_por/results/synthesis/simple_por.synthesis_preroute.v

diff --git a/openlane/simple_por/runs/simple_por/logs/cts/cts.log b/openlane/simple_por/runs/simple_por/logs/cts/cts.log
deleted file mode 100644
index 86ce643..0000000
--- a/openlane/simple_por/runs/simple_por/logs/cts/cts.log
+++ /dev/null

@@ -1 +0,0 @@
-SKIPPED!

diff --git a/openlane/simple_por/runs/simple_por/logs/floorplan/ioPlacer.log b/openlane/simple_por/runs/simple_por/logs/floorplan/ioPlacer.log
deleted file mode 100644
index f7999dd..0000000
--- a/openlane/simple_por/runs/simple_por/logs/floorplan/ioPlacer.log
+++ /dev/null

@@ -1,33 +0,0 @@
-OpenROAD 0.9.0 e582f2522b
-This program is licensed under the BSD-3 license. See the LICENSE file for details. 
-Components of this program may be licensed under more restrictive licenses which must be honored.
-Notice 0: Reading LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged.lef
-Notice 0:     Created 13 technology layers
-Notice 0:     Created 25 technology vias
-Notice 0:     Created 69 library cells
-Notice 0: Finished LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged.lef
-Notice 0: 
-Reading DEF file: /project/openlane/simple_por/runs/simple_por/tmp/floorplan/verilog2def_openroad.def
-Notice 0: Design: simple_por
-Notice 0:     Created 3 pins.
-Notice 0:     Created 3 components and 18 component-terminals.
-Notice 0:     Created 5 nets and 5 connections.
-Notice 0: Finished DEF file: /project/openlane/simple_por/runs/simple_por/tmp/floorplan/verilog2def_openroad.def
-#Macro blocks found: 0
-Warning: using the default boundaries offset (5 microns)
-Warning: using the default min distance between IO pins (2 tracks)
-WARNING: force pin spread option has no effect when using random pin placement
- > Running IO placement
- * Num of slots          90
- * Num of I/O            3
- * Num of I/O w/sink     1
- * Num of I/O w/o sink   2
- * Slots Per Section     200
- * Slots Increase Factor 0.01
- * Usage Per Section     0.8
- * Usage Increase Factor 0.01
- * Force Pin Spread      1
-
-WARNING: running random pin placement
-RandomMode Even
- > IO placement done.

diff --git a/openlane/simple_por/runs/simple_por/logs/floorplan/ioPlacer_runtime.txt b/openlane/simple_por/runs/simple_por/logs/floorplan/ioPlacer_runtime.txt
deleted file mode 100644
index d46012f..0000000
--- a/openlane/simple_por/runs/simple_por/logs/floorplan/ioPlacer_runtime.txt
+++ /dev/null

@@ -1 +0,0 @@
-0h0m0s405ms

diff --git a/openlane/simple_por/runs/simple_por/logs/floorplan/pdn.log b/openlane/simple_por/runs/simple_por/logs/floorplan/pdn.log
deleted file mode 100644
index fed244c..0000000
--- a/openlane/simple_por/runs/simple_por/logs/floorplan/pdn.log
+++ /dev/null

@@ -1,34 +0,0 @@
-OpenROAD 0.9.0 e582f2522b
-This program is licensed under the BSD-3 license. See the LICENSE file for details. 
-Components of this program may be licensed under more restrictive licenses which must be honored.
-Notice 0: Reading LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0:     Created 13 technology layers
-Notice 0:     Created 25 technology vias
-Notice 0:     Created 69 library cells
-Notice 0: Finished LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0: 
-Reading DEF file: /project/openlane/simple_por/runs/simple_por/results/placement/simple_por.placement.def
-Notice 0: Design: simple_por
-Notice 0:     Created 3 pins.
-Notice 0:     Created 3 components and 18 component-terminals.
-Notice 0:     Created 5 nets and 5 connections.
-Notice 0: Finished DEF file: /project/openlane/simple_por/runs/simple_por/results/placement/simple_por.placement.def
-[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
-[INFO] [PDNG-0016]   config: /home/xrex/usr/devel/pdks/sky130A/libs.tech/openlane/common_pdn.tcl
-[INFO] [PDNG-0008] Design Name is simple_por
-[INFO] [PDNG-0009] Reading technology data
-[INFO] [PDNG-0011] ****** INFO ******
-Type: stdcell, grid
-    Stdcell Rails
-      Layer: met1 -  width: 0.510  pitch: 4.070  offset: 0.000 
-    Straps
-      Layer: met4 -  width: 1.600  pitch: 4.320  offset: 2.160 
-      Layer: met5 -  width: 1.600  pitch: 4.070  offset: 2.035 
-    Connect: {met1 met4} {met4 met5}
-Type: macro, macro_1
-    Macro orientation: R0 R180 MX MY R90 R270 MXR90 MYR90
-    Straps
-    Connect: {met4_PIN_ver met5}
-[INFO] [PDNG-0012] **** END INFO ****
-[INFO] [PDNG-0013] Inserting stdcell grid - grid
-[INFO] [PDNG-0015] Writing to database

diff --git a/openlane/simple_por/runs/simple_por/logs/floorplan/pdn_runtime.txt b/openlane/simple_por/runs/simple_por/logs/floorplan/pdn_runtime.txt
deleted file mode 100644
index 249086c..0000000
--- a/openlane/simple_por/runs/simple_por/logs/floorplan/pdn_runtime.txt
+++ /dev/null

@@ -1 +0,0 @@
-0h0m0s425ms

diff --git a/openlane/simple_por/runs/simple_por/logs/floorplan/verilog2def.openroad.log b/openlane/simple_por/runs/simple_por/logs/floorplan/verilog2def.openroad.log
deleted file mode 100644
index d60996f..0000000
--- a/openlane/simple_por/runs/simple_por/logs/floorplan/verilog2def.openroad.log
+++ /dev/null

@@ -1,14 +0,0 @@
-OpenROAD 0.9.0 e582f2522b
-This program is licensed under the BSD-3 license. See the LICENSE file for details. 
-Components of this program may be licensed under more restrictive licenses which must be honored.
-Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib, line 35 default_operating_condition tt_025C_3v30 not found.
-Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib, line 31 default_operating_condition tt_025C_3v30_lv1v80 not found.
-Notice 0: Reading LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0:     Created 13 technology layers
-Notice 0:     Created 25 technology vias
-Notice 0:     Created 69 library cells
-Notice 0: Finished LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Info: Added 3 rows of 27 sites.
-[INFO] Extracting DIE_AREA and CORE_AREA from the floorplan
-[INFO] Floorplanned on a die area of 0.0 0.0 24.78 45.82 (microns). Saving to /project/openlane/simple_por/runs/simple_por/reports/floorplan/verilog2def.die_area.rpt.
-[INFO] Floorplanned on a core area of 5.76 16.28 18.72 28.49 (microns). Saving to /project/openlane/simple_por/runs/simple_por/reports/floorplan/verilog2def.core_area.rpt.

diff --git a/openlane/simple_por/runs/simple_por/logs/floorplan/verilog2def_openroad_runtime.txt b/openlane/simple_por/runs/simple_por/logs/floorplan/verilog2def_openroad_runtime.txt
deleted file mode 100644
index edd95ec..0000000
--- a/openlane/simple_por/runs/simple_por/logs/floorplan/verilog2def_openroad_runtime.txt
+++ /dev/null

@@ -1 +0,0 @@
-0h0m0s539ms

diff --git a/openlane/simple_por/runs/simple_por/logs/lvs/lvs.log b/openlane/simple_por/runs/simple_por/logs/lvs/lvs.log
deleted file mode 100644
index d87ea83..0000000
--- a/openlane/simple_por/runs/simple_por/logs/lvs/lvs.log
+++ /dev/null

@@ -1,50 +0,0 @@
-Netgen 1.5.157 compiled on Fri Oct  9 13:50:13 UTC 2020
-Warning: netgen command 'format' use fully-qualified name '::netgen::format'
-Warning: netgen command 'global' use fully-qualified name '::netgen::global'
-Generating JSON file result
-Reading netlist file /project/openlane/simple_por/runs/simple_por/results/magic/simple_por.spice
-Reading netlist file /project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.powered.v
-Warning:  A case-insensitive file has been read and so the	verilog file must be treated case-insensitive to match.
-Creating placeholder cell definition for module sky130_fd_sc_hvl__decap_4.
-Creating placeholder cell definition for module sky130_fd_sc_hvl__decap_8.
-Creating placeholder cell definition for module sky130_fd_sc_hvl__fill_2.
-Creating placeholder cell definition for module sky130_fd_sc_hvl__fill_1.
-Creating placeholder cell definition for module sky130_fd_sc_hvl__conb_1.
-Creating placeholder cell definition for module sky130_fd_sc_hvl__schmittbuf_1.
-Reading setup file /home/xrex/usr/devel/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl
-Comparison output logged to file /project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.log
-Logging to file "/project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.log" enabled
-Contents of circuit 1:  Circuit: 'sky130_fd_sc_hvl__schmittbuf_1'
-Circuit sky130_fd_sc_hvl__schmittbuf_1 contains 0 device instances.
-Circuit contains 0 nets, and 6 disconnected pins.
-Contents of circuit 2:  Circuit: 'sky130_fd_sc_hvl__schmittbuf_1'
-Circuit sky130_fd_sc_hvl__schmittbuf_1 contains 0 device instances.
-Circuit contains 0 nets.
-
-Circuit sky130_fd_sc_hvl__schmittbuf_1 contains no devices.
-Contents of circuit 1:  Circuit: 'sky130_fd_sc_hvl__conb_1'
-Circuit sky130_fd_sc_hvl__conb_1 contains 0 device instances.
-Circuit contains 0 nets, and 6 disconnected pins.
-Contents of circuit 2:  Circuit: 'sky130_fd_sc_hvl__conb_1'
-Circuit sky130_fd_sc_hvl__conb_1 contains 0 device instances.
-Circuit contains 0 nets.
-
-Circuit sky130_fd_sc_hvl__conb_1 contains no devices.
-Contents of circuit 1:  Circuit: 'simple_por'
-Circuit simple_por contains 3 device instances.
-  Class: sky130_fd_sc_hvl__schmittbuf_1 instances:   2
-  Class: sky130_fd_sc_hvl__conb_1 instances:   1
-Circuit contains 6 nets, and 2 disconnected pins.
-Contents of circuit 2:  Circuit: 'simple_por'
-Circuit simple_por contains 3 device instances.
-  Class: sky130_fd_sc_hvl__schmittbuf_1 instances:   2
-  Class: sky130_fd_sc_hvl__conb_1 instances:   1
-Circuit contains 5 nets, and 2 disconnected pins.
-
-Circuit 1 contains 3 devices, Circuit 2 contains 3 devices.
-Circuit 1 contains 5 nets,    Circuit 2 contains 5 nets.
-
-Netlists match uniquely.
-Result: Circuits match uniquely.
-Logging to file "/project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.log" disabled
-LVS Done.

diff --git a/openlane/simple_por/runs/simple_por/logs/lvs/write_powered_verilog.log b/openlane/simple_por/runs/simple_por/logs/lvs/write_powered_verilog.log
deleted file mode 100644
index 2cc36cc..0000000
--- a/openlane/simple_por/runs/simple_por/logs/lvs/write_powered_verilog.log
+++ /dev/null

@@ -1,19 +0,0 @@
-Notice 0: Reading LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged.lef
-Notice 0:     Created 13 technology layers
-Notice 0:     Created 25 technology vias
-Notice 0:     Created 69 library cells
-Notice 0: Finished LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged.lef
-Notice 0: 
-Reading DEF file: /project/openlane/simple_por/runs/simple_por/results/routing/simple_por.def
-Notice 0: Design: simple_por
-Notice 0:     Created 5 pins.
-Notice 0:     Created 16 components and 70 component-terminals.
-Notice 0:     Created 2 special nets and 0 connections.
-Notice 0:     Created 5 nets and 5 connections.
-Notice 0: Finished DEF file: /project/openlane/simple_por/runs/simple_por/results/routing/simple_por.def
-Top-level design name: simple_por
-Found port VPWR of type SIGNAL
-Found port VGND of type SIGNAL
-Power net:  VPWR
-Ground net: VGND
-Modified power connections of 16 cells (Remaining: 0 ).

diff --git a/openlane/simple_por/runs/simple_por/logs/magic/magic.drc b/openlane/simple_por/runs/simple_por/logs/magic/magic.drc
deleted file mode 100644
index 2a0de55..0000000
--- a/openlane/simple_por/runs/simple_por/logs/magic/magic.drc
+++ /dev/null

@@ -1,113 +0,0 @@
-simple_por
-----------------------------------------
-Poly resistor spacing to poly < 0.48um (poly.9)
-----------------------------------------
- 6.725 18.530 7.235 19.010
- 6.725 18.485 7.235 18.530
- 7.445 18.485 7.715 18.530
- 7.445 18.530 7.715 19.010
- 6.965 18.530 7.235 19.010
- 7.445 18.530 7.955 19.010
- 6.965 18.485 7.235 18.530
- 7.445 18.485 7.955 18.530
-----------------------------------------
-P-diffusion overlap of P-diffusion contact < 0.04um (licon.5a)
-----------------------------------------
- 5.690 24.835 5.730 25.005
- 5.690 23.835 5.730 24.005
-----------------------------------------
-Diffusion contact to rndiff < 0.06um ()
-----------------------------------------
- 7.965 27.795 7.985 27.855
- 8.025 27.665 8.045 27.795
- 8.780 25.005 8.800 25.065
- 8.840 24.835 8.860 25.005
- 8.780 24.005 8.800 24.065
- 8.840 23.835 8.860 24.005
- 8.025 21.045 8.045 21.215
- 6.630 27.725 6.690 27.955
- 7.965 27.795 7.985 27.855
- 5.690 24.835 5.750 25.065
- 8.780 25.005 8.800 25.065
- 5.690 23.835 5.750 24.065
- 8.780 24.005 8.800 24.065
- 6.630 20.945 6.690 21.175
-----------------------------------------
-Metal5 spacing < 1.6um (met5.2)
-----------------------------------------
- 2.780 24.755 15.740 24.965
- 2.780 23.800 6.510 24.755
- 6.510 23.800 7.690 24.755
- 7.690 23.800 10.830 24.755
- 10.830 23.800 12.010 24.755
- 12.010 23.800 15.740 24.755
- 2.780 25.610 4.350 26.565
- 4.350 25.610 5.530 26.565
- 5.530 25.610 8.670 26.565
- 8.670 25.610 9.850 26.565
- 9.850 25.610 12.990 26.565
- 12.990 25.610 14.170 26.565
- 14.170 25.610 15.740 26.565
- 2.780 25.400 15.740 25.610
- 2.780 22.720 15.740 22.930
- 2.780 21.765 4.350 22.720
- 4.350 21.765 5.530 22.720
- 5.530 21.765 8.670 22.720
- 8.670 21.765 9.850 22.720
- 9.850 21.765 12.990 22.720
- 12.990 21.765 14.170 22.720
- 14.170 21.765 15.740 22.720
- 2.780 23.575 6.510 24.530
- 6.510 23.575 7.690 24.530
- 7.690 23.575 10.830 24.530
- 10.830 23.575 12.010 24.530
- 12.010 23.575 15.740 24.530
- 2.780 23.365 15.740 23.575
- 2.780 20.685 15.740 20.895
- 2.780 19.730 6.510 20.685
- 6.510 19.730 7.690 20.685
- 7.690 19.730 10.830 20.685
- 10.830 19.730 12.010 20.685
- 12.010 19.730 15.740 20.685
- 2.780 21.540 4.350 22.495
- 4.350 21.540 5.530 22.495
- 5.530 21.540 8.670 22.495
- 8.670 21.540 9.850 22.495
- 9.850 21.540 12.990 22.495
- 12.990 21.540 14.170 22.495
- 14.170 21.540 15.740 22.495
- 2.780 21.330 15.740 21.540
- 2.780 18.650 15.740 18.860
- 2.780 17.695 4.350 18.650
- 4.350 17.695 5.530 18.650
- 5.530 17.695 8.670 18.650
- 8.670 17.695 9.850 18.650
- 9.850 17.695 12.990 18.650
- 12.990 17.695 14.170 18.650
- 14.170 17.695 15.740 18.650
- 2.780 19.505 6.510 20.460
- 6.510 19.505 7.690 20.460
- 7.690 19.505 10.830 20.460
- 10.830 19.505 12.010 20.460
- 12.010 19.505 15.740 20.460
- 2.780 19.295 15.740 19.505
-----------------------------------------
-MV Diffusion width < 0.29um (diff/tap.14)
-----------------------------------------
- 5.690 25.005 5.770 25.065
- 5.690 24.835 5.770 25.005
- 5.690 24.775 5.770 24.785
- 5.690 24.785 5.770 24.835
- 5.690 24.005 5.770 24.055
- 5.690 24.055 5.770 24.065
- 5.690 23.835 5.770 24.005
- 5.690 23.775 5.770 23.835
-----------------------------------------
-N-diffusion overlap of N-diffusion contact < 0.04um (licon.5a)
-----------------------------------------
- 6.630 27.725 6.670 27.895
- 6.630 20.945 6.670 21.115
-----------------------------------------
-[INFO]: COUNT: 90
-[INFO]: Should be divided by 3 or 4
-

diff --git a/openlane/simple_por/runs/simple_por/logs/magic/magic.drc.log b/openlane/simple_por/runs/simple_por/logs/magic/magic.drc.log
deleted file mode 100644
index 44be75f..0000000
--- a/openlane/simple_por/runs/simple_por/logs/magic/magic.drc.log
+++ /dev/null

@@ -1,39 +0,0 @@
-
-Magic 8.3 revision 64 - Compiled on Fri Oct  9 12:13:18 UTC 2020.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-Processing system .magicrc file
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130: scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/openLANE_flow/scripts/magic_drc.tcl" from command line.
-Warning: Calma reading is not undoable!  I hope that's OK.
-Library written using GDS-II Release 3.0
-Library name: simple_por
-Reading "sky130_fd_sc_hvl__decap_4".
-CIF file read warning: CIF style sky130: units rescaled by factor of 5 / 1
-Error while reading cell "sky130_fd_sc_hvl__decap_4" (byte position 2200): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hvl__decap_8".
-Error while reading cell "sky130_fd_sc_hvl__decap_8" (byte position 11712): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hvl__fill_1".
-Error while reading cell "sky130_fd_sc_hvl__fill_1" (byte position 13316): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hvl__fill_2".
-Error while reading cell "sky130_fd_sc_hvl__fill_2" (byte position 15752): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hvl__schmittbuf_1".
-Error while reading cell "sky130_fd_sc_hvl__schmittbuf_1" (byte position 24362): Unknown layer/datatype in boundary, layer=65 type=14
-Error while reading cell "sky130_fd_sc_hvl__schmittbuf_1" (byte position 28428): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "sky130_fd_sc_hvl__conb_1".
-Error while reading cell "sky130_fd_sc_hvl__conb_1" (byte position 31024): Unknown layer/datatype in boundary, layer=236 type=0
-Reading "simple_por".
-[INFO]: Loading simple_por
-
-DRC style is now "drc(full)"
-Loading DRC CIF style.
-[INFO]: COUNT: 90
-[INFO]: Should be divided by 3 or 4
-[INFO]: DRC Checking DONE (/project/openlane/simple_por/runs/simple_por/logs/magic/magic.drc)
-[INFO]: Saving mag view with DRC errors(/project/openlane/simple_por/runs/simple_por/results/magic/simple_por.drc.mag)
-[INFO]: Saved

diff --git a/openlane/simple_por/runs/simple_por/logs/magic/magic.log b/openlane/simple_por/runs/simple_por/logs/magic/magic.log
deleted file mode 100644
index 1853da7..0000000
--- a/openlane/simple_por/runs/simple_por/logs/magic/magic.log
+++ /dev/null

@@ -1,48 +0,0 @@
-
-Magic 8.3 revision 64 - Compiled on Fri Oct  9 12:13:18 UTC 2020.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-Processing system .magicrc file
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130: scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/openLANE_flow/scripts/magic.tcl" from command line.
-Reading LEF data from file /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/techlef/sky130_fd_sc_hvl.tlef.
-This action cannot be undone.
-LEF read, Line 64 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
-LEF read, Line 77 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
-LEF read, Line 98 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
-LEF read, Line 99 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
-LEF read, Line 111 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
-LEF read, Line 137 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
-LEF read, Line 138 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
-LEF read, Line 155 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
-LEF read, Line 174 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
-LEF read, Line 191 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
-LEF read, Line 209 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
-LEF read, Line 227 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
-LEF read, Line 246 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
-LEF read, Line 263 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
-LEF read: Processed 769 lines.
-Reading DEF data from file /project/openlane/simple_por/runs/simple_por/results/routing/simple_por.def.
-This action cannot be undone.
-  Processed 6 vias total.
-  Processed 16 subcell instances total.
-  Processed 5 pins total.
-  Processed 2 special nets total.
-  Processed 5 nets total.
-DEF read: Processed 209 lines.
-[INFO]: Zeroizing Origin
-[INFO]: Current Box Values: 0 0 4360 9164
-[INFO]: Saving .mag view With BBox Values: 0 0 4360 9164
-[INFO]: GDS Write Complete
-[INFO]: Writing abstract LEF
-Generating LEF output /project/openlane/simple_por/runs/simple_por/results/magic/simple_por.lef for cell simple_por:
-Diagnostic:  Write LEF header for cell simple_por
-Diagnostic:  Writing LEF output for cell simple_por
-Diagnostic:  Scale value is 0.005000
-[INFO]: LEF Write Complete
-[INFO]: MAGIC TAPEOUT STEP DONE

diff --git a/openlane/simple_por/runs/simple_por/logs/magic/magic_ext2spice.feedback.txt b/openlane/simple_por/runs/simple_por/logs/magic/magic_ext2spice.feedback.txt
deleted file mode 100644
index b5807cb..0000000
--- a/openlane/simple_por/runs/simple_por/logs/magic/magic_ext2spice.feedback.txt
+++ /dev/null

@@ -1,32 +0,0 @@
-box 1824 4053 1855 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 1889 4053 1951 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 1985 4053 1997 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 1536 4053 1567 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 1601 4053 1663 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 1697 4053 1728 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 1995 4053 2047 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 2081 4053 2143 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 2177 4053 2239 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 2273 4053 2304 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 2304 4053 2335 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 2369 4053 2431 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 2465 4053 2527 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 2561 4053 2592 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 3648 4053 3679 4087
-feedback add "Illegal overlap (types do not connect)" medium
-box 3713 4053 3744 4087
-feedback add "Illegal overlap (types do not connect)" medium

diff --git a/openlane/simple_por/runs/simple_por/logs/magic/magic_spice.log b/openlane/simple_por/runs/simple_por/logs/magic/magic_spice.log
deleted file mode 100644
index bbf61e4..0000000
--- a/openlane/simple_por/runs/simple_por/logs/magic/magic_spice.log
+++ /dev/null

@@ -1,48 +0,0 @@
-
-Magic 8.3 revision 64 - Compiled on Fri Oct  9 12:13:18 UTC 2020.
-Starting magic under Tcl interpreter
-Using the terminal as the console.
-Using NULL graphics device.
-Processing system .magicrc file
-Sourcing design .magicrc for technology sky130A ...
-2 Magic internal units = 1 Lambda
-Input style sky130: scaleFactor=2, multiplier=2
-Scaled tech values by 2 / 1 to match internal grid scaling
-Loading sky130A Device Generator Menu ...
-Loading "/project/openlane/simple_por/runs/simple_por/tmp/magic_spice.tcl" from command line.
-Reading LEF data from file /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/techlef/sky130_fd_sc_hvl.tlef.
-This action cannot be undone.
-LEF read, Line 64 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
-LEF read, Line 77 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
-LEF read, Line 98 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
-LEF read, Line 99 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
-LEF read, Line 111 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
-LEF read, Line 137 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
-LEF read, Line 138 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
-LEF read, Line 155 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
-LEF read, Line 174 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
-LEF read, Line 191 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
-LEF read, Line 209 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
-LEF read, Line 227 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
-LEF read, Line 246 (Message): Unknown keyword "MINWIDTH" in LEF file; ignoring.
-LEF read, Line 263 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
-LEF read: Processed 769 lines.
-Reading DEF data from file /project/openlane/simple_por/runs/simple_por/results/routing/simple_por.def.
-This action cannot be undone.
-  Processed 6 vias total.
-  Processed 16 subcell instances total.
-  Processed 5 pins total.
-  Processed 2 special nets total.
-  Processed 5 nets total.
-DEF read: Processed 209 lines.
-Extracting sky130_fd_sc_hvl__conb_1 into sky130_fd_sc_hvl__conb_1.ext:
-Extracting sky130_fd_sc_hvl__schmittbuf_1 into sky130_fd_sc_hvl__schmittbuf_1.ext:
-Extracting sky130_fd_sc_hvl__fill_2 into sky130_fd_sc_hvl__fill_2.ext:
-Extracting sky130_fd_sc_hvl__fill_1 into sky130_fd_sc_hvl__fill_1.ext:
-Extracting sky130_fd_sc_hvl__decap_8 into sky130_fd_sc_hvl__decap_8.ext:
-Extracting sky130_fd_sc_hvl__decap_4 into sky130_fd_sc_hvl__decap_4.ext:
-Extracting simple_por into simple_por.ext:
-simple_por: 16 fatal errors
-Total of 16 fatal errors.
-exttospice finished.
-Using technology "sky130A", version 20200927

diff --git a/openlane/simple_por/runs/simple_por/logs/placement/opendp.log b/openlane/simple_por/runs/simple_por/logs/placement/opendp.log
deleted file mode 100644
index 7566655..0000000
--- a/openlane/simple_por/runs/simple_por/logs/placement/opendp.log
+++ /dev/null

@@ -1,39 +0,0 @@
-OpenROAD 0.9.0 e582f2522b
-This program is licensed under the BSD-3 license. See the LICENSE file for details. 
-Components of this program may be licensed under more restrictive licenses which must be honored.
-Notice 0: Reading LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0:     Created 13 technology layers
-Notice 0:     Created 25 technology vias
-Notice 0:     Created 69 library cells
-Notice 0: Finished LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0: 
-Reading DEF file: /project/openlane/simple_por/runs/simple_por/tmp/placement/openphysyn.def
-Notice 0: Design: simple_por
-Notice 0:     Created 3 pins.
-Notice 0:     Created 3 components and 18 component-terminals.
-Notice 0:     Created 5 nets and 5 connections.
-Notice 0: Finished DEF file: /project/openlane/simple_por/runs/simple_por/tmp/placement/openphysyn.def
-Warning: could not find power special net
-Design Stats
---------------------------------
-total instances             3
-multi row instances         0
-fixed instances             0
-nets                        5
-design area             158.2 u^2
-fixed area                0.0 u^2
-movable area             52.7 u^2
-utilization                33 %
-utilization padded         63 %
-rows                        3
-row height                4.1 u
-
-Placement Analysis
---------------------------------
-total displacement        8.9 u
-average displacement      3.0 u
-max displacement          5.2 u
-original HPWL            28.4 u
-legalized HPWL           34.0 u
-delta HPWL                 20 %
-

diff --git a/openlane/simple_por/runs/simple_por/logs/placement/opendp_runtime.txt b/openlane/simple_por/runs/simple_por/logs/placement/opendp_runtime.txt
deleted file mode 100644
index b663908..0000000
--- a/openlane/simple_por/runs/simple_por/logs/placement/opendp_runtime.txt
+++ /dev/null

@@ -1 +0,0 @@
-0h0m0s416ms

diff --git a/openlane/simple_por/runs/simple_por/logs/placement/openphysyn.log b/openlane/simple_por/runs/simple_por/logs/placement/openphysyn.log
deleted file mode 100644
index ca72c8a..0000000
--- a/openlane/simple_por/runs/simple_por/logs/placement/openphysyn.log
+++ /dev/null

@@ -1,55 +0,0 @@
-[OpenPhySyn] [2020-11-11 03:14:13.320] [info] Loaded 6 transforms.
-[OpenPhySyn] [2020-11-11 03:14:13.697] [info] OpenPhySyn: 1.8.1
-Warning: /project/openlane/simple_por/runs/simple_por/tmp/opt.lib, line 36 default_operating_condition ss_150C_1v65 not found.
-Notice 0: Reading LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0:     Created 13 technology layers
-Notice 0:     Created 25 technology vias
-Notice 0:     Created 69 library cells
-Notice 0: Finished LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0: 
-Reading DEF file: /project/openlane/simple_por/runs/simple_por/tmp/placement/replace.def
-Notice 0: Design: simple_por
-Notice 0:     Created 3 pins.
-Notice 0:     Created 3 components and 18 component-terminals.
-Notice 0:     Created 5 nets and 5 connections.
-Notice 0: Finished DEF file: /project/openlane/simple_por/runs/simple_por/tmp/placement/replace.def
-Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
-=============== Initial Reports =============
-No paths found.
-Capacitance violations: 0
-Transition violations: 0
-wns 0.00
-tns 0.00
-Initial area: 527 um2
-OpenPhySyn timing repair:
-[OpenPhySyn] [2020-11-11 03:14:13.774] [info] Invoking repair_timing transform
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Buffer library: sky130_fd_sc_hvl__buf_16, sky130_fd_sc_hvl__buf_4, sky130_fd_sc_hvl__buf_32
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Inverter library: None
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Buffering: enabled
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Driver sizing: enabled
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Pin-swapping: enabled
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Mode: Timing-Driven
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Iteration 1
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] No more violations or cannot find more optimal buffer
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Runtime: 0s
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Buffers: 0
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Resize up: 0
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Resize down: 0
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Pin Swap: 0
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Buffered nets: 0
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Fanout violations: 0
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Transition violations: 0
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Capacitance violations: 0
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Slack gain: 0.0
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Initial area: 53
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] New area: 53
-[OpenPhySyn] [2020-11-11 03:14:13.784] [info] Finished repair_timing transform (0)
-Added/updated 0 cells
-=============== Final Reports =============
-No paths found.
-Capacitance violations: 0
-Transition violations: 0
-wns 0.00
-tns 0.00
-Final area: 527 um2
-Export optimized design

diff --git a/openlane/simple_por/runs/simple_por/logs/placement/openphysyn_runtime.txt b/openlane/simple_por/runs/simple_por/logs/placement/openphysyn_runtime.txt
deleted file mode 100644
index 177fdb9..0000000
--- a/openlane/simple_por/runs/simple_por/logs/placement/openphysyn_runtime.txt
+++ /dev/null

@@ -1 +0,0 @@
-0h0m1s245ms

diff --git a/openlane/simple_por/runs/simple_por/logs/placement/replace.log b/openlane/simple_por/runs/simple_por/logs/placement/replace.log
deleted file mode 100644
index 35662c8..0000000
--- a/openlane/simple_por/runs/simple_por/logs/placement/replace.log
+++ /dev/null

@@ -1,79 +0,0 @@
-OpenROAD 0.9.0 e582f2522b
-This program is licensed under the BSD-3 license. See the LICENSE file for details. 
-Components of this program may be licensed under more restrictive licenses which must be honored.
-Notice 0: Reading LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0:     Created 13 technology layers
-Notice 0:     Created 25 technology vias
-Notice 0:     Created 69 library cells
-Notice 0: Finished LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0: 
-Reading DEF file: /project/openlane/simple_por/runs/simple_por/tmp/floorplan/ioPlacer.def
-Notice 0: Design: simple_por
-Notice 0:     Created 3 pins.
-Notice 0:     Created 3 components and 18 component-terminals.
-Notice 0:     Created 5 nets and 5 connections.
-Notice 0: Finished DEF file: /project/openlane/simple_por/runs/simple_por/tmp/floorplan/ioPlacer.def
-[INFO] DBU = 1000
-[INFO] SiteSize = (480, 4070)
-[INFO] CoreAreaLxLy = (5760, 16280)
-[INFO] CoreAreaUxUy = (18720, 28490)
-[INFO] NumInstances = 3
-[INFO] NumPlaceInstances = 3
-[INFO] NumFixedInstances = 0
-[INFO] NumDummyInstances = 0
-[INFO] NumNets = 5
-[INFO] NumPins = 8
-[INFO] DieAreaLxLy = (0, 0)
-[INFO] DieAreaUxUy = (24780, 45820)
-[INFO] CoreAreaLxLy = (5760, 16280)
-[INFO] CoreAreaUxUy = (18720, 28490)
-[INFO] CoreArea = 158241600
-[INFO] NonPlaceInstsArea = 0
-[INFO] PlaceInstsArea = 52747200
-[INFO] Util(%) = 33.333336
-[INFO] StdInstsArea = 52747200
-[INFO] MacroInstsArea = 0
-[InitialPlace]  Iter: 1 CG Error: 3.45211e-09 HPWL: 80500
-[InitialPlace]  Iter: 2 CG Error: 9.08635e-08 HPWL: 39611
-[InitialPlace]  Iter: 3 CG Error: 9.08635e-08 HPWL: 39610
-[InitialPlace]  Iter: 4 CG Error: 9.08635e-08 HPWL: 39610
-[InitialPlace]  Iter: 5 CG Error: 9.08635e-08 HPWL: 39610
-[INFO] FillerInit: NumGCells = 4
-[INFO] FillerInit: NumGNets = 5
-[INFO] FillerInit: NumGPins = 8
-[INFO] TargetDensity = 0.500000
-[INFO] AveragePlaceInstArea = 17582400
-[INFO] IdealBinArea = 35164800
-[INFO] IdealBinCnt = 4
-[INFO] TotalBinArea = 158241600
-[INFO] BinCnt = (2, 2)
-[INFO] BinSize = (6480, 6105)
-[INFO] NumBins = 4
-[NesterovSolve] Iter: 1 overflow: 0.123104 HPWL: 28197
-[NesterovSolve] Iter: 10 overflow: 0.117056 HPWL: 28059
-[NesterovSolve] Iter: 20 overflow: 0.117068 HPWL: 28056
-[NesterovSolve] Iter: 30 overflow: 0.11715 HPWL: 28055
-[NesterovSolve] Iter: 40 overflow: 0.117132 HPWL: 28056
-[NesterovSolve] Iter: 50 overflow: 0.117098 HPWL: 28058
-[NesterovSolve] Iter: 60 overflow: 0.117065 HPWL: 28060
-[NesterovSolve] Iter: 70 overflow: 0.117047 HPWL: 28063
-[NesterovSolve] Iter: 80 overflow: 0.116944 HPWL: 28073
-[NesterovSolve] Iter: 90 overflow: 0.116874 HPWL: 28081
-[NesterovSolve] Iter: 100 overflow: 0.116704 HPWL: 28095
-[NesterovSolve] Iter: 110 overflow: 0.116516 HPWL: 28112
-[NesterovSolve] Iter: 120 overflow: 0.116273 HPWL: 28138
-[NesterovSolve] Iter: 130 overflow: 0.116012 HPWL: 28167
-[NesterovSolve] Iter: 140 overflow: 0.116073 HPWL: 28108
-[NesterovSolve] Iter: 150 overflow: 0.115767 HPWL: 28089
-[NesterovSolve] Iter: 160 overflow: 0.115124 HPWL: 28105
-[NesterovSolve] Iter: 170 overflow: 0.114174 HPWL: 28128
-[NesterovSolve] Iter: 180 overflow: 0.112855 HPWL: 28160
-[NesterovSolve] Iter: 190 overflow: 0.111004 HPWL: 28205
-[NesterovSolve] Iter: 200 overflow: 0.108432 HPWL: 28269
-[NesterovSolve] Iter: 210 overflow: 0.104974 HPWL: 28354
-[NesterovSolve] Iter: 220 overflow: 0.100488 HPWL: 28465
-[NesterovSolve] Finished with Overflow: 0.0999235
-Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ss_150C_1v65.lib, line 36 default_operating_condition ss_150C_1v65 not found.
-Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ff_n40C_5v50.lib, line 34 default_operating_condition ff_n40C_5v50 not found.
-create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
-Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable

diff --git a/openlane/simple_por/runs/simple_por/logs/placement/replace_runtime.txt b/openlane/simple_por/runs/simple_por/logs/placement/replace_runtime.txt
deleted file mode 100644
index 82857e0..0000000
--- a/openlane/simple_por/runs/simple_por/logs/placement/replace_runtime.txt
+++ /dev/null

@@ -1 +0,0 @@
-0h0m0s679ms

diff --git a/openlane/simple_por/runs/simple_por/logs/routing/addspacers.log b/openlane/simple_por/runs/simple_por/logs/routing/addspacers.log
deleted file mode 100644
index 4e0a484..0000000
--- a/openlane/simple_por/runs/simple_por/logs/routing/addspacers.log
+++ /dev/null

@@ -1,17 +0,0 @@
-OpenROAD 0.9.0 e582f2522b
-This program is licensed under the BSD-3 license. See the LICENSE file for details. 
-Components of this program may be licensed under more restrictive licenses which must be honored.
-Notice 0: Reading LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0:     Created 13 technology layers
-Notice 0:     Created 25 technology vias
-Notice 0:     Created 69 library cells
-Notice 0: Finished LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0: 
-Reading DEF file: /project/openlane/simple_por/runs/simple_por/tmp/routing/fastroute.def
-Notice 0: Design: simple_por
-Notice 0:     Created 5 pins.
-Notice 0:     Created 3 components and 18 component-terminals.
-Notice 0:     Created 2 special nets and 0 connections.
-Notice 0:     Created 5 nets and 5 connections.
-Notice 0: Finished DEF file: /project/openlane/simple_por/runs/simple_por/tmp/routing/fastroute.def
-Placed 13 filler instances.

diff --git a/openlane/simple_por/runs/simple_por/logs/routing/addspacers_runtime.txt b/openlane/simple_por/runs/simple_por/logs/routing/addspacers_runtime.txt
deleted file mode 100644
index b6eeda5..0000000
--- a/openlane/simple_por/runs/simple_por/logs/routing/addspacers_runtime.txt
+++ /dev/null

@@ -1 +0,0 @@
-0h0m0s409ms

diff --git a/openlane/simple_por/runs/simple_por/logs/routing/fastroute.log b/openlane/simple_por/runs/simple_por/logs/routing/fastroute.log
deleted file mode 100644
index 7084836..0000000
--- a/openlane/simple_por/runs/simple_por/logs/routing/fastroute.log
+++ /dev/null

@@ -1,187 +0,0 @@
-OpenROAD 0.9.0 e582f2522b
-This program is licensed under the BSD-3 license. See the LICENSE file for details. 
-Components of this program may be licensed under more restrictive licenses which must be honored.
-Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib, line 35 default_operating_condition tt_025C_3v30 not found.
-Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib, line 31 default_operating_condition tt_025C_3v30_lv1v80 not found.
-Notice 0: Reading LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0:     Created 13 technology layers
-Notice 0:     Created 25 technology vias
-Notice 0:     Created 69 library cells
-Notice 0: Finished LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0: 
-Reading DEF file: /project/openlane/simple_por/runs/simple_por/tmp/floorplan/pdn.def
-Notice 0: Design: simple_por
-Notice 0:     Created 5 pins.
-Notice 0:     Created 3 components and 18 component-terminals.
-Notice 0:     Created 2 special nets and 0 connections.
-Notice 0:     Created 5 nets and 5 connections.
-Notice 0: Finished DEF file: /project/openlane/simple_por/runs/simple_por/tmp/floorplan/pdn.def
-[PARAMS] Min routing layer: 2
-[PARAMS] Max routing layer: 6
-[PARAMS] Global adjustment: 0
-[PARAMS] Unidirectional routing: 1
-[PARAMS] Grid origin: (-1, -1)
-[INFO] #DB Obstructions: 0
-[INFO] #DB Obstacles: 90
-[INFO] #DB Macros: 0
-[INFO] Found 0 clock nets
-[INFO] Minimum degree: 2
-[INFO] Maximum degree: 2
-[INFO] Processing 76 obstacles in layer 1
-[INFO] Processing 16 obstacles in layer 2
-[INFO] Processing 5 obstacles in layer 5
-[INFO] Processing 5 obstacles in layer 6
-[INFO] Reducing resources of layer 1 by 99%
-[INFO] Reducing resources of layer 2 by 20%
-[INFO] Reducing resources of layer 3 by 20%
-[INFO] Reducing resources of layer 4 by 20%
-[INFO] Reducing resources of layer 5 by 10%
-[INFO] Reducing resources of layer 6 by 10%
-[INFO] WIRELEN : 2, WIRELEN1 : 0
-[INFO] NumSeg  : 2
-[INFO] NumShift: 0
-First L Route
-[INFO] WIRELEN : 2, WIRELEN1 : 2
-[INFO] NumSeg  : 2
-[INFO] NumShift: 0
-[Overflow Report] Total hCap    : 298
-[Overflow Report] Total vCap    : 326
-[Overflow Report] Total Usage   : 2
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] Num Overflow e: 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-Second L Route
-[Overflow Report] Total hCap    : 298
-[Overflow Report] Total vCap    : 326
-[Overflow Report] Total Usage   : 2
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] Num Overflow e: 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-First Z Route
-[Overflow Report] Total hCap    : 298
-[Overflow Report] Total vCap    : 326
-[Overflow Report] Total Usage   : 2
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] Num Overflow e: 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-[INFO] LV routing round 0, enlarge 10 
-[INFO] 10 threshold, 10 expand
-[Overflow Report] total Usage   : 2
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] Num Overflow e: 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-[INFO] LV routing round 1, enlarge 15 
-[INFO] 5 threshold, 15 expand
-[Overflow Report] total Usage   : 2
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] Num Overflow e: 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-[INFO] LV routing round 2, enlarge 20 
-[INFO] 1 threshold, 20 expand
-[Overflow Report] total Usage   : 2
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] Num Overflow e: 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-Usage checked
-Maze routing finished
-[INFO] P3 runtime: 0.000000 sec
-[INFO] Final 2D results: 
-[Overflow Report] total Usage   : 2
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] Num Overflow e: 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-Layer Assignment Begins
-Layer assignment finished
-[INFO] 2D + Layer Assignment Runtime: 0.000000 sec
-Post Processing Begins 
-Post Processsing finished
- Starting via filling
-[INFO] Via related to pin nodes 6
-[INFO] Via related stiner nodes 0
-Via filling finished
-
-Final usage/overflow report: 
-[INFO] Usage per layer: 
-    Layer 1 usage: 0
-    Layer 2 usage: 1
-    Layer 3 usage: 1
-    Layer 4 usage: 0
-    Layer 5 usage: 0
-    Layer 6 usage: 0
-
-[INFO] Capacity per layer: 
-    Layer 1 capacity: 0
-    Layer 2 capacity: 192
-    Layer 3 capacity: 220
-    Layer 4 capacity: 94
-    Layer 5 capacity: 106
-    Layer 6 capacity: 12
-
-[INFO] Use percentage per layer: 
-    Layer 1 use percentage: 0.0%
-    Layer 2 use percentage: 0.52%
-    Layer 3 use percentage: 0.45%
-    Layer 4 use percentage: 0.00%
-    Layer 5 use percentage: 0.00%
-    Layer 6 use percentage: 0.00%
-
-[INFO] Overflow per layer: 
-    Layer 1 overflow: 0
-    Layer 2 overflow: 0
-    Layer 3 overflow: 0
-    Layer 4 overflow: 0
-    Layer 5 overflow: 0
-    Layer 6 overflow: 0
-
-[Overflow Report] Total Usage   : 2
-[Overflow Report] Total Capacity: 624
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-[INFO] Final usage          : 2
-[INFO] Final number of vias : 6
-[INFO] Final usage 3D       : 20
-[INFO] Total wirelength: 50 um
-Repairing antennas...
-[WARNING]No OR_DEFAULT vias defined
-[INFO] #Antenna violations: 0
-[INFO] Num routed nets: 3

diff --git a/openlane/simple_por/runs/simple_por/logs/routing/fastroute_post_antenna.log b/openlane/simple_por/runs/simple_por/logs/routing/fastroute_post_antenna.log
deleted file mode 100644
index 9c7bd33..0000000
--- a/openlane/simple_por/runs/simple_por/logs/routing/fastroute_post_antenna.log
+++ /dev/null

@@ -1,184 +0,0 @@
-OpenROAD 0.9.0 e582f2522b
-This program is licensed under the BSD-3 license. See the LICENSE file for details. 
-Components of this program may be licensed under more restrictive licenses which must be honored.
-Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib, line 35 default_operating_condition tt_025C_3v30 not found.
-Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib, line 31 default_operating_condition tt_025C_3v30_lv1v80 not found.
-Notice 0: Reading LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0:     Created 13 technology layers
-Notice 0:     Created 25 technology vias
-Notice 0:     Created 69 library cells
-Notice 0: Finished LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0: 
-Reading DEF file: /project/openlane/simple_por/runs/simple_por/tmp/routing/fastroute.def
-Notice 0: Design: simple_por
-Notice 0:     Created 5 pins.
-Notice 0:     Created 3 components and 18 component-terminals.
-Notice 0:     Created 2 special nets and 0 connections.
-Notice 0:     Created 5 nets and 5 connections.
-Notice 0: Finished DEF file: /project/openlane/simple_por/runs/simple_por/tmp/routing/fastroute.def
-[PARAMS] Min routing layer: 2
-[PARAMS] Max routing layer: 6
-[PARAMS] Global adjustment: 0
-[PARAMS] Unidirectional routing: 1
-[PARAMS] Grid origin: (-1, -1)
-[INFO] #DB Obstructions: 0
-[INFO] #DB Obstacles: 90
-[INFO] #DB Macros: 0
-[INFO] Found 0 clock nets
-[INFO] Minimum degree: 2
-[INFO] Maximum degree: 2
-[INFO] Processing 76 obstacles in layer 1
-[INFO] Processing 16 obstacles in layer 2
-[INFO] Processing 5 obstacles in layer 5
-[INFO] Processing 5 obstacles in layer 6
-[INFO] Reducing resources of layer 1 by 99%
-[INFO] Reducing resources of layer 2 by 20%
-[INFO] Reducing resources of layer 3 by 20%
-[INFO] Reducing resources of layer 4 by 20%
-[INFO] Reducing resources of layer 5 by 10%
-[INFO] Reducing resources of layer 6 by 10%
-[INFO] WIRELEN : 2, WIRELEN1 : 0
-[INFO] NumSeg  : 2
-[INFO] NumShift: 0
-First L Route
-[INFO] WIRELEN : 2, WIRELEN1 : 2
-[INFO] NumSeg  : 2
-[INFO] NumShift: 0
-[Overflow Report] Total hCap    : 298
-[Overflow Report] Total vCap    : 326
-[Overflow Report] Total Usage   : 2
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] Num Overflow e: 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-Second L Route
-[Overflow Report] Total hCap    : 298
-[Overflow Report] Total vCap    : 326
-[Overflow Report] Total Usage   : 2
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] Num Overflow e: 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-First Z Route
-[Overflow Report] Total hCap    : 298
-[Overflow Report] Total vCap    : 326
-[Overflow Report] Total Usage   : 2
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] Num Overflow e: 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-[INFO] LV routing round 0, enlarge 10 
-[INFO] 10 threshold, 10 expand
-[Overflow Report] total Usage   : 2
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] Num Overflow e: 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-[INFO] LV routing round 1, enlarge 15 
-[INFO] 5 threshold, 15 expand
-[Overflow Report] total Usage   : 2
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] Num Overflow e: 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-[INFO] LV routing round 2, enlarge 20 
-[INFO] 1 threshold, 20 expand
-[Overflow Report] total Usage   : 2
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] Num Overflow e: 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-Usage checked
-Maze routing finished
-[INFO] P3 runtime: 0.000000 sec
-[INFO] Final 2D results: 
-[Overflow Report] total Usage   : 2
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] Num Overflow e: 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-Layer Assignment Begins
-Layer assignment finished
-[INFO] 2D + Layer Assignment Runtime: 0.000000 sec
-Post Processing Begins 
-Post Processsing finished
- Starting via filling
-[INFO] Via related to pin nodes 6
-[INFO] Via related stiner nodes 0
-Via filling finished
-
-Final usage/overflow report: 
-[INFO] Usage per layer: 
-    Layer 1 usage: 0
-    Layer 2 usage: 1
-    Layer 3 usage: 1
-    Layer 4 usage: 0
-    Layer 5 usage: 0
-    Layer 6 usage: 0
-
-[INFO] Capacity per layer: 
-    Layer 1 capacity: 0
-    Layer 2 capacity: 192
-    Layer 3 capacity: 220
-    Layer 4 capacity: 94
-    Layer 5 capacity: 106
-    Layer 6 capacity: 12
-
-[INFO] Use percentage per layer: 
-    Layer 1 use percentage: 0.0%
-    Layer 2 use percentage: 0.52%
-    Layer 3 use percentage: 0.45%
-    Layer 4 use percentage: 0.00%
-    Layer 5 use percentage: 0.00%
-    Layer 6 use percentage: 0.00%
-
-[INFO] Overflow per layer: 
-    Layer 1 overflow: 0
-    Layer 2 overflow: 0
-    Layer 3 overflow: 0
-    Layer 4 overflow: 0
-    Layer 5 overflow: 0
-    Layer 6 overflow: 0
-
-[Overflow Report] Total Usage   : 2
-[Overflow Report] Total Capacity: 624
-[Overflow Report] Max H Overflow: 0
-[Overflow Report] Max V Overflow: 0
-[Overflow Report] Max Overflow  : 0
-[Overflow Report] H   Overflow  : 0
-[Overflow Report] V   Overflow  : 0
-[Overflow Report] Final Overflow: 0
-
-[INFO] Final usage          : 2
-[INFO] Final number of vias : 6
-[INFO] Final usage 3D       : 20
-[INFO] Total wirelength: 50 um
-[INFO] Num routed nets: 3

diff --git a/openlane/simple_por/runs/simple_por/logs/routing/fastroute_runtime.txt b/openlane/simple_por/runs/simple_por/logs/routing/fastroute_runtime.txt
deleted file mode 100644
index 120137f..0000000
--- a/openlane/simple_por/runs/simple_por/logs/routing/fastroute_runtime.txt
+++ /dev/null

@@ -1 +0,0 @@
-0h0m1s141ms

diff --git a/openlane/simple_por/runs/simple_por/logs/routing/or_antenna.log b/openlane/simple_por/runs/simple_por/logs/routing/or_antenna.log
deleted file mode 100644
index 00f731e..0000000
--- a/openlane/simple_por/runs/simple_por/logs/routing/or_antenna.log
+++ /dev/null

@@ -1,19 +0,0 @@
-OpenROAD 0.9.0 e582f2522b
-This program is licensed under the BSD-3 license. See the LICENSE file for details. 
-Components of this program may be licensed under more restrictive licenses which must be honored.
-Notice 0: Reading LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0:     Created 13 technology layers
-Notice 0:     Created 25 technology vias
-Notice 0:     Created 69 library cells
-Notice 0: Finished LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0: 
-Reading DEF file: /project/openlane/simple_por/runs/simple_por/results/routing/simple_por.def
-Notice 0: Design: simple_por
-Notice 0:     Created 5 pins.
-Notice 0:     Created 16 components and 70 component-terminals.
-Notice 0:     Created 2 special nets and 0 connections.
-Notice 0:     Created 5 nets and 5 connections.
-Notice 0: Finished DEF file: /project/openlane/simple_por/runs/simple_por/results/routing/simple_por.def
-Number of pins violated: 0
-Number of nets violated: 0
-Total number of nets: 5

diff --git a/openlane/simple_por/runs/simple_por/logs/routing/spef_extraction.log b/openlane/simple_por/runs/simple_por/logs/routing/spef_extraction.log
deleted file mode 100644
index 6dae333..0000000
--- a/openlane/simple_por/runs/simple_por/logs/routing/spef_extraction.log
+++ /dev/null

@@ -1,12 +0,0 @@
-Start parsing LEF file...
-Parsing LEF file done.
-Start parsing DEF file...
-Parsing DEF file done.
-
-Parameters Used:
-Edge Capacitance Factor: 1.0
-Wire model: PI 
-
-RC Extraction is done
-Start writing SPEF file
-Writing SPEF is done

diff --git a/openlane/simple_por/runs/simple_por/logs/routing/tritonRoute.log b/openlane/simple_por/runs/simple_por/logs/routing/tritonRoute.log
deleted file mode 100644
index eec21b9..0000000
--- a/openlane/simple_por/runs/simple_por/logs/routing/tritonRoute.log
+++ /dev/null

@@ -1,500 +0,0 @@
-
-reading lef ...
-
-units:       1000
-#layers:     13
-#macros:     69
-#vias:       25
-#viarulegen: 25
-
-reading def ...
-
-design:      simple_por
-die area:    ( 0 0 ) ( 24780 45820 )
-trackPts:    12
-defvias:     4
-#components: 16
-#terminals:  5
-#snets:      2
-#nets:       5
-
-reading guide ...
-
-#guides:     10
-Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR...
-Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR...
-done initConstraintLayerIdx
-List of default vias:
-  Layer mcon
-    default via: L1M1_PR_MR
-  Layer via
-    default via: M1M2_PR
-  Layer via2
-    default via: via2_FR
-  Layer via3
-    default via: M3M4_PR_M
-  Layer via4
-    default via: via4_FR
-Writing reference output def...
-
-libcell analysis ...
-
-instance analysis ...
-#unique instances = 9
-
-init region query ...
-  complete FR_MASTERSLICE
-  complete FR_VIA
-  complete li1
-  complete mcon
-  complete met1
-  complete via
-  complete met2
-  complete via2
-  complete met3
-  complete via3
-  complete met4
-  complete via4
-  complete met5
-
-FR_MASTERSLICE shape region query size = 0
-FR_VIA shape region query size = 0
-li1 shape region query size = 150
-mcon shape region query size = 260
-met1 shape region query size = 78
-via shape region query size = 40
-met2 shape region query size = 22
-via2 shape region query size = 40
-met3 shape region query size = 21
-via3 shape region query size = 40
-met4 shape region query size = 28
-via4 shape region query size = 13
-met5 shape region query size = 20
-
-
-start pin access
-  complete 6 pins
-  complete 7 unique inst patterns
-  complete 3 groups
-Expt1 runtime (pin-level access point gen): 0.0124197
-Expt2 runtime (design-level access pattern gen): 0.00342962
-#scanned instances     = 16
-#unique  instances     = 9
-#stdCellGenAp          = 44
-#stdCellValidPlanarAp  = 0
-#stdCellValidViaAp     = 36
-#stdCellPinNoAp        = 0
-#stdCellPinCnt         = 5
-#instTermValidViaApCnt = 0
-#macroGenAp            = 0
-#macroValidPlanarAp    = 0
-#macroValidViaAp       = 0
-#macroNoAp             = 0
-
-complete pin access
-cpu time = 00:00:00, elapsed time = 00:00:00, memory = 6.60 (MB), peak = 6.93 (MB)
-
-post process guides ...
-GCELLGRID X -1 DO 6 STEP 7200 ;
-GCELLGRID Y -1 DO 3 STEP 7200 ;
-  complete FR_MASTERSLICE
-  complete FR_VIA
-  complete li1
-  complete mcon
-  complete met1
-  complete via
-  complete met2
-  complete via2
-  complete met3
-  complete via3
-  complete met4
-  complete via4
-  complete met5
-
-building cmap ... 
-
-init guide query ...
-  complete FR_MASTERSLICE (guide)
-  complete FR_VIA (guide)
-  complete li1 (guide)
-  complete mcon (guide)
-  complete met1 (guide)
-  complete via (guide)
-  complete met2 (guide)
-  complete via2 (guide)
-  complete met3 (guide)
-  complete via3 (guide)
-  complete met4 (guide)
-  complete via4 (guide)
-  complete met5 (guide)
-
-FR_MASTERSLICE guide region query size = 0
-FR_VIA guide region query size = 0
-li1 guide region query size = 4
-mcon guide region query size = 0
-met1 guide region query size = 3
-via guide region query size = 0
-met2 guide region query size = 2
-via2 guide region query size = 0
-met3 guide region query size = 0
-via3 guide region query size = 0
-met4 guide region query size = 0
-via4 guide region query size = 0
-met5 guide region query size = 0
-
-init gr pin query ...
-
-
-start track assignment
-Done with 6 vertical wires in 1 frboxes and 3 horizontal wires in 1 frboxes.
-Done with 1 vertical wires in 1 frboxes and 0 horizontal wires in 1 frboxes.
-
-complete track assignment
-cpu time = 00:00:00, elapsed time = 00:00:00, memory = 6.93 (MB), peak = 7.11 (MB)
-
-post processing ...
-
-start routing data preparation
-initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
-initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
-initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
-initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
-initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
-initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
-initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370)
-initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1)
-initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460)
-initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1)
-initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630)
-initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1)
-initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680)
-initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1)
-initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020)
-initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1)
-initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0)
-initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1)
-initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
-initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
-initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
-initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
-initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
-initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
-initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
-initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
-initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
-initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
-initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
-initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0)
-initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370)
-initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460)
-initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630)
-initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630)
-initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020)
-initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0)
-cpu time = 00:00:00, elapsed time = 00:00:00, memory = 7.15 (MB), peak = 7.15 (MB)
-
-start detail routing ...
-start 0th optimization iteration ...
-    completing 10% with 0 violations
-    elapsed time = 00:00:00, memory = 8.21 (MB)
-  number of violations = 0
-cpu time = 00:00:00, elapsed time = 00:00:00, memory = 8.20 (MB), peak = 371.90 (MB)
-total wire length = 30 um
-total wire length on LAYER li1 = 0 um
-total wire length on LAYER met1 = 9 um
-total wire length on LAYER met2 = 20 um
-total wire length on LAYER met3 = 0 um
-total wire length on LAYER met4 = 0 um
-total wire length on LAYER met5 = 0 um
-total number of vias = 10
-up-via summary (total 10):
-
----------------------
- FR_MASTERSLICE     0
-            li1     5
-           met1     5
-           met2     0
-           met3     0
-           met4     0
----------------------
-                   10
-
-
-start 1st optimization iteration ...
-    completing 10% with 0 violations
-    elapsed time = 00:00:00, memory = 9.75 (MB)
-    completing 20% with 0 violations
-    elapsed time = 00:00:00, memory = 9.84 (MB)
-  number of violations = 0
-cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.20 (MB), peak = 371.90 (MB)
-total wire length = 30 um
-total wire length on LAYER li1 = 0 um
-total wire length on LAYER met1 = 9 um
-total wire length on LAYER met2 = 20 um
-total wire length on LAYER met3 = 0 um
-total wire length on LAYER met4 = 0 um
-total wire length on LAYER met5 = 0 um
-total number of vias = 10
-up-via summary (total 10):
-
----------------------
- FR_MASTERSLICE     0
-            li1     5
-           met1     5
-           met2     0
-           met3     0
-           met4     0
----------------------
-                   10
-
-
-start 2nd optimization iteration ...
-    completing 10% with 0 violations
-    elapsed time = 00:00:00, memory = 14.20 (MB)
-    completing 20% with 0 violations
-    elapsed time = 00:00:00, memory = 14.20 (MB)
-    completing 30% with 0 violations
-    elapsed time = 00:00:00, memory = 14.20 (MB)
-    completing 40% with 0 violations
-    elapsed time = 00:00:00, memory = 14.20 (MB)
-  number of violations = 0
-cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.20 (MB), peak = 371.90 (MB)
-total wire length = 30 um
-total wire length on LAYER li1 = 0 um
-total wire length on LAYER met1 = 9 um
-total wire length on LAYER met2 = 20 um
-total wire length on LAYER met3 = 0 um
-total wire length on LAYER met4 = 0 um
-total wire length on LAYER met5 = 0 um
-total number of vias = 10
-up-via summary (total 10):
-
----------------------
- FR_MASTERSLICE     0
-            li1     5
-           met1     5
-           met2     0
-           met3     0
-           met4     0
----------------------
-                   10
-
-
-start 17th optimization iteration ...
-    completing 10% with 0 violations
-    elapsed time = 00:00:00, memory = 14.20 (MB)
-    completing 20% with 0 violations
-    elapsed time = 00:00:00, memory = 14.20 (MB)
-  number of violations = 0
-cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.20 (MB), peak = 371.90 (MB)
-total wire length = 30 um
-total wire length on LAYER li1 = 0 um
-total wire length on LAYER met1 = 9 um
-total wire length on LAYER met2 = 20 um
-total wire length on LAYER met3 = 0 um
-total wire length on LAYER met4 = 0 um
-total wire length on LAYER met5 = 0 um
-total number of vias = 10
-up-via summary (total 10):
-
----------------------
- FR_MASTERSLICE     0
-            li1     5
-           met1     5
-           met2     0
-           met3     0
-           met4     0
----------------------
-                   10
-
-
-start 25th optimization iteration ...
-    completing 10% with 0 violations
-    elapsed time = 00:00:00, memory = 14.46 (MB)
-    completing 20% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-  number of violations = 0
-cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.70 (MB), peak = 371.90 (MB)
-total wire length = 30 um
-total wire length on LAYER li1 = 0 um
-total wire length on LAYER met1 = 9 um
-total wire length on LAYER met2 = 20 um
-total wire length on LAYER met3 = 0 um
-total wire length on LAYER met4 = 0 um
-total wire length on LAYER met5 = 0 um
-total number of vias = 10
-up-via summary (total 10):
-
----------------------
- FR_MASTERSLICE     0
-            li1     5
-           met1     5
-           met2     0
-           met3     0
-           met4     0
----------------------
-                   10
-
-
-start 33rd optimization iteration ...
-    completing 10% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 20% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 30% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 40% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 50% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 60% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-  number of violations = 0
-cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.70 (MB), peak = 371.90 (MB)
-total wire length = 30 um
-total wire length on LAYER li1 = 0 um
-total wire length on LAYER met1 = 9 um
-total wire length on LAYER met2 = 20 um
-total wire length on LAYER met3 = 0 um
-total wire length on LAYER met4 = 0 um
-total wire length on LAYER met5 = 0 um
-total number of vias = 10
-up-via summary (total 10):
-
----------------------
- FR_MASTERSLICE     0
-            li1     5
-           met1     5
-           met2     0
-           met3     0
-           met4     0
----------------------
-                   10
-
-
-start 41st optimization iteration ...
-    completing 10% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 20% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 30% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 40% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 50% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 60% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-  number of violations = 0
-cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.70 (MB), peak = 371.90 (MB)
-total wire length = 30 um
-total wire length on LAYER li1 = 0 um
-total wire length on LAYER met1 = 9 um
-total wire length on LAYER met2 = 20 um
-total wire length on LAYER met3 = 0 um
-total wire length on LAYER met4 = 0 um
-total wire length on LAYER met5 = 0 um
-total number of vias = 10
-up-via summary (total 10):
-
----------------------
- FR_MASTERSLICE     0
-            li1     5
-           met1     5
-           met2     0
-           met3     0
-           met4     0
----------------------
-                   10
-
-
-start 49th optimization iteration ...
-    completing 10% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 20% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-  number of violations = 0
-cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.70 (MB), peak = 371.90 (MB)
-total wire length = 30 um
-total wire length on LAYER li1 = 0 um
-total wire length on LAYER met1 = 9 um
-total wire length on LAYER met2 = 20 um
-total wire length on LAYER met3 = 0 um
-total wire length on LAYER met4 = 0 um
-total wire length on LAYER met5 = 0 um
-total number of vias = 10
-up-via summary (total 10):
-
----------------------
- FR_MASTERSLICE     0
-            li1     5
-           met1     5
-           met2     0
-           met3     0
-           met4     0
----------------------
-                   10
-
-
-start 57th optimization iteration ...
-    completing 10% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 20% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 30% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 40% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 50% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-    completing 60% with 0 violations
-    elapsed time = 00:00:00, memory = 14.70 (MB)
-  number of violations = 0
-cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.70 (MB), peak = 371.90 (MB)
-total wire length = 30 um
-total wire length on LAYER li1 = 0 um
-total wire length on LAYER met1 = 9 um
-total wire length on LAYER met2 = 20 um
-total wire length on LAYER met3 = 0 um
-total wire length on LAYER met4 = 0 um
-total wire length on LAYER met5 = 0 um
-total number of vias = 10
-up-via summary (total 10):
-
----------------------
- FR_MASTERSLICE     0
-            li1     5
-           met1     5
-           met2     0
-           met3     0
-           met4     0
----------------------
-                   10
-
-
-complete detail routing
-total wire length = 30 um
-total wire length on LAYER li1 = 0 um
-total wire length on LAYER met1 = 9 um
-total wire length on LAYER met2 = 20 um
-total wire length on LAYER met3 = 0 um
-total wire length on LAYER met4 = 0 um
-total wire length on LAYER met5 = 0 um
-total number of vias = 10
-up-via summary (total 10):
-
----------------------
- FR_MASTERSLICE     0
-            li1     5
-           met1     5
-           met2     0
-           met3     0
-           met4     0
----------------------
-                   10
-
-cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.70 (MB), peak = 371.90 (MB)
-
-post processing ...
-
-Runtime taken (hrt): 0.95639

diff --git a/openlane/simple_por/runs/simple_por/logs/routing/tritonRoute_runtime.txt b/openlane/simple_por/runs/simple_por/logs/routing/tritonRoute_runtime.txt
deleted file mode 100644
index 6e6b95c..0000000
--- a/openlane/simple_por/runs/simple_por/logs/routing/tritonRoute_runtime.txt
+++ /dev/null

@@ -1 +0,0 @@
-0h0m0s961ms

diff --git a/openlane/simple_por/runs/simple_por/logs/synthesis/opensta.log b/openlane/simple_por/runs/simple_por/logs/synthesis/opensta.log
deleted file mode 100644
index 5b0c582..0000000
--- a/openlane/simple_por/runs/simple_por/logs/synthesis/opensta.log
+++ /dev/null

@@ -1,12 +0,0 @@
-OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
-License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
-
-This is free software, and you are free to change and redistribute it
-under certain conditions; type `show_copying' for details. 
-This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
-Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ff_n40C_5v50.lib, line 34 default_operating_condition ff_n40C_5v50 not found.
-Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ss_150C_1v65.lib, line 36 default_operating_condition ss_150C_1v65 not found.
-create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
-Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
-tns 0.00
-wns 0.00

diff --git a/openlane/simple_por/runs/simple_por/logs/synthesis/opensta_post_openphysyn.log b/openlane/simple_por/runs/simple_por/logs/synthesis/opensta_post_openphysyn.log
deleted file mode 100644
index 5b0c582..0000000
--- a/openlane/simple_por/runs/simple_por/logs/synthesis/opensta_post_openphysyn.log
+++ /dev/null

@@ -1,12 +0,0 @@
-OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
-License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
-
-This is free software, and you are free to change and redistribute it
-under certain conditions; type `show_copying' for details. 
-This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
-Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ff_n40C_5v50.lib, line 34 default_operating_condition ff_n40C_5v50 not found.
-Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ss_150C_1v65.lib, line 36 default_operating_condition ss_150C_1v65 not found.
-create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
-Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
-tns 0.00
-wns 0.00

diff --git a/openlane/simple_por/runs/simple_por/logs/synthesis/opensta_spef.log b/openlane/simple_por/runs/simple_por/logs/synthesis/opensta_spef.log
deleted file mode 100644
index c85d542..0000000
--- a/openlane/simple_por/runs/simple_por/logs/synthesis/opensta_spef.log
+++ /dev/null

@@ -1,14 +0,0 @@
-OpenSTA 2.2.0 0d73b5b65a Copyright (c) 2019, Parallax Software, Inc.
-License GPLv3: GNU GPL version 3 <http://gnu.org/licenses/gpl.html>
-
-This is free software, and you are free to change and redistribute it
-under certain conditions; type `show_copying' for details. 
-This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'.
-Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ff_n40C_5v50.lib, line 34 default_operating_condition ff_n40C_5v50 not found.
-Warning: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__ss_150C_1v65.lib, line 36 default_operating_condition ss_150C_1v65 not found.
-Warning: /project/openlane/simple_por/runs/simple_por/results/synthesis/simple_por.synthesis_preroute.v, line 18 module sky130_fd_sc_hvl__fill_2 not found.  Creating black box for FILLER_0_4.
-Warning: /project/openlane/simple_por/runs/simple_por/results/synthesis/simple_por.synthesis_preroute.v, line 19 module sky130_fd_sc_hvl__fill_1 not found.  Creating black box for FILLER_0_6.
-create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
-Error: base.sdc, 1 can't read "::env(CLOCK_PORT)": no such variable
-tns 0.00
-wns 0.00

diff --git a/openlane/simple_por/runs/simple_por/logs/synthesis/yosys.log b/openlane/simple_por/runs/simple_por/logs/synthesis/yosys.log
deleted file mode 100644
index b2765c3..0000000
--- a/openlane/simple_por/runs/simple_por/logs/synthesis/yosys.log
+++ /dev/null

@@ -1,644 +0,0 @@
-
- /----------------------------------------------------------------------------\
- |                                                                            |
- |  yosys -- Yosys Open SYnthesis Suite                                       |
- |                                                                            |
- |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |
- |                                                                            |
- |  Permission to use, copy, modify, and/or distribute this software for any  |
- |  purpose with or without fee is hereby granted, provided that the above    |
- |  copyright notice and this permission notice appear in all copies.         |
- |                                                                            |
- |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
- |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
- |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
- |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
- |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
- |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
- |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
- |                                                                            |
- \----------------------------------------------------------------------------/
-
- Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
-
-[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
-[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
-[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
-[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
-[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
-
-1. Executing Liberty frontend.
-Imported 57 cell types from liberty file.
-
-2. Executing Liberty frontend.
-Imported 8 cell types from liberty file.
-
-3. Executing Verilog-2005 frontend: /project/openlane/simple_por/../../verilog/rtl/simple_por.v
-Parsing SystemVerilog input from `/project/openlane/simple_por/../../verilog/rtl/simple_por.v' to AST representation.
-Generating RTLIL representation for module `\simple_por'.
-Successfully finished Verilog frontend.
-
-4. Generating Graphviz representation of design.
-Writing dot description to `/project/openlane/simple_por/runs/simple_por/tmp/synthesis/hierarchy.dot'.
-Dumping module simple_por to page 1.
-
-5. Executing HIERARCHY pass (managing design hierarchy).
-
-5.1. Analyzing design hierarchy..
-Top module:  \simple_por
-
-5.2. Analyzing design hierarchy..
-Top module:  \simple_por
-Removed 0 unused modules.
-
-6. Executing SYNTH pass.
-
-6.1. Executing HIERARCHY pass (managing design hierarchy).
-
-6.1.1. Analyzing design hierarchy..
-Top module:  \simple_por
-
-6.1.2. Analyzing design hierarchy..
-Top module:  \simple_por
-Removed 0 unused modules.
-
-6.2. Executing PROC pass (convert processes to netlists).
-
-6.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
-Cleaned up 0 empty switches.
-
-6.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
-Removed a total of 0 dead cases.
-
-6.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
-Removed 0 redundant assignments.
-Promoted 3 assignments to connections.
-
-6.2.4. Executing PROC_INIT pass (extract init attributes).
-Found init rule in `\simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:0$3'.
-  Set init value: \inode = 1'0
-
-6.2.5. Executing PROC_ARST pass (detect async resets in processes).
-
-6.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
-Creating decoders for process `\simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:0$3'.
-Creating decoders for process `\simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:26$2'.
-Creating decoders for process `\simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:23$1'.
-
-6.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).
-
-6.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
-Creating register for signal `\simple_por.\inode' using process `\simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:26$2'.
-  created $dff cell `$procdff$4' with negative edge clock.
-Creating register for signal `\simple_por.\inode' using process `\simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:23$1'.
-  created $dff cell `$procdff$5' with positive edge clock.
-
-6.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
-Removing empty process `simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:0$3'.
-Removing empty process `simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:26$2'.
-Removing empty process `simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:23$1'.
-Cleaned up 0 empty switches.
-
-6.3. Executing FLATTEN pass (flatten design).
-
-6.4. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-6.5. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-Removed 0 unused cells and 3 unused wires.
-<suppressed ~1 debug messages>
-
-6.6. Executing CHECK pass (checking for obvious problems).
-checking module simple_por..
-Warning: multiple conflicting drivers for simple_por.\inode:
-    port Q[0] of cell $procdff$4 ($dff)
-    port Q[0] of cell $procdff$5 ($dff)
-found and reported 1 problems.
-
-6.7. Executing OPT pass (performing simple optimizations).
-
-6.7.1. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-6.7.2. Executing OPT_MERGE pass (detect identical cells).
-Finding identical cells in module `\simple_por'.
-Removed a total of 0 cells.
-
-6.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
-Running muxtree optimizer on module \simple_por..
-  Creating internal representation of mux trees.
-  No muxes found in this module.
-Removed 0 multiplexer ports.
-
-6.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
-  Optimizing cells in module \simple_por.
-Performed a total of 0 changes.
-
-6.7.5. Executing OPT_MERGE pass (detect identical cells).
-Finding identical cells in module `\simple_por'.
-Removed a total of 0 cells.
-
-6.7.6. Executing OPT_DFF pass (perform DFF optimizations).
-Setting constant 0-bit at position 0 on $procdff$4 ($dff) from module simple_por.
-
-6.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-Warning: Driver-driver conflict for \inode between cell $procdff$5.Q and constant 1'0 in simple_por: Resolved using constant.
-Removed 1 unused cells and 0 unused wires.
-<suppressed ~1 debug messages>
-
-6.7.8. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-6.7.9. Rerunning OPT passes. (Maybe there is more to do..)
-
-6.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
-Running muxtree optimizer on module \simple_por..
-  Creating internal representation of mux trees.
-  No muxes found in this module.
-Removed 0 multiplexer ports.
-
-6.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
-  Optimizing cells in module \simple_por.
-Performed a total of 0 changes.
-
-6.7.12. Executing OPT_MERGE pass (detect identical cells).
-Finding identical cells in module `\simple_por'.
-Removed a total of 0 cells.
-
-6.7.13. Executing OPT_DFF pass (perform DFF optimizations).
-
-6.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-
-6.7.15. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-6.7.16. Finished OPT passes. (There is nothing left to do.)
-
-6.8. Executing FSM pass (extract and optimize FSM).
-
-6.8.1. Executing FSM_DETECT pass (finding FSMs in design).
-
-6.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
-
-6.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
-
-6.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-
-6.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
-
-6.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
-
-6.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
-
-6.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
-
-6.9. Executing OPT pass (performing simple optimizations).
-
-6.9.1. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-6.9.2. Executing OPT_MERGE pass (detect identical cells).
-Finding identical cells in module `\simple_por'.
-Removed a total of 0 cells.
-
-6.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
-Running muxtree optimizer on module \simple_por..
-  Creating internal representation of mux trees.
-  No muxes found in this module.
-Removed 0 multiplexer ports.
-
-6.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
-  Optimizing cells in module \simple_por.
-Performed a total of 0 changes.
-
-6.9.5. Executing OPT_MERGE pass (detect identical cells).
-Finding identical cells in module `\simple_por'.
-Removed a total of 0 cells.
-
-6.9.6. Executing OPT_DFF pass (perform DFF optimizations).
-
-6.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-
-6.9.8. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-6.9.9. Finished OPT passes. (There is nothing left to do.)
-
-6.10. Executing WREDUCE pass (reducing word size of cells).
-
-6.11. Executing PEEPOPT pass (run peephole optimizers).
-
-6.12. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-
-6.13. Executing ALUMACC pass (create $alu and $macc cells).
-Extracting $alu and $macc cells in module simple_por:
-  created 0 $alu and 0 $macc cells.
-
-6.14. Executing SHARE pass (SAT-based resource sharing).
-
-6.15. Executing OPT pass (performing simple optimizations).
-
-6.15.1. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-6.15.2. Executing OPT_MERGE pass (detect identical cells).
-Finding identical cells in module `\simple_por'.
-Removed a total of 0 cells.
-
-6.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
-Running muxtree optimizer on module \simple_por..
-  Creating internal representation of mux trees.
-  No muxes found in this module.
-Removed 0 multiplexer ports.
-
-6.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
-  Optimizing cells in module \simple_por.
-Performed a total of 0 changes.
-
-6.15.5. Executing OPT_MERGE pass (detect identical cells).
-Finding identical cells in module `\simple_por'.
-Removed a total of 0 cells.
-
-6.15.6. Executing OPT_DFF pass (perform DFF optimizations).
-
-6.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-
-6.15.8. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-6.15.9. Finished OPT passes. (There is nothing left to do.)
-
-6.16. Executing MEMORY pass.
-
-6.16.1. Executing OPT_MEM pass (optimize memories).
-Performed a total of 0 transformations.
-
-6.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
-
-6.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-
-6.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
-
-6.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-
-6.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).
-
-6.17. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-
-6.18. Executing OPT pass (performing simple optimizations).
-
-6.18.1. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-6.18.2. Executing OPT_MERGE pass (detect identical cells).
-Finding identical cells in module `\simple_por'.
-Removed a total of 0 cells.
-
-6.18.3. Executing OPT_DFF pass (perform DFF optimizations).
-
-6.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-
-6.18.5. Finished fast OPT passes.
-
-6.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
-
-6.20. Executing OPT pass (performing simple optimizations).
-
-6.20.1. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-6.20.2. Executing OPT_MERGE pass (detect identical cells).
-Finding identical cells in module `\simple_por'.
-Removed a total of 0 cells.
-
-6.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
-Running muxtree optimizer on module \simple_por..
-  Creating internal representation of mux trees.
-  No muxes found in this module.
-Removed 0 multiplexer ports.
-
-6.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
-  Optimizing cells in module \simple_por.
-Performed a total of 0 changes.
-
-6.20.5. Executing OPT_MERGE pass (detect identical cells).
-Finding identical cells in module `\simple_por'.
-Removed a total of 0 cells.
-
-6.20.6. Executing OPT_SHARE pass.
-
-6.20.7. Executing OPT_DFF pass (perform DFF optimizations).
-
-6.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-
-6.20.9. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-6.20.10. Finished OPT passes. (There is nothing left to do.)
-
-6.21. Executing TECHMAP pass (map to technology primitives).
-
-6.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
-Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
-Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
-Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
-Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
-Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
-Generating RTLIL representation for module `\_90_simplemap_various'.
-Generating RTLIL representation for module `\_90_simplemap_registers'.
-Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
-Generating RTLIL representation for module `\_90_shift_shiftx'.
-Generating RTLIL representation for module `\_90_fa'.
-Generating RTLIL representation for module `\_90_lcu'.
-Generating RTLIL representation for module `\_90_alu'.
-Generating RTLIL representation for module `\_90_macc'.
-Generating RTLIL representation for module `\_90_alumacc'.
-Generating RTLIL representation for module `\$__div_mod_u'.
-Generating RTLIL representation for module `\$__div_mod_trunc'.
-Generating RTLIL representation for module `\_90_div'.
-Generating RTLIL representation for module `\_90_mod'.
-Generating RTLIL representation for module `\$__div_mod_floor'.
-Generating RTLIL representation for module `\_90_divfloor'.
-Generating RTLIL representation for module `\_90_modfloor'.
-Generating RTLIL representation for module `\_90_pow'.
-Generating RTLIL representation for module `\_90_pmux'.
-Generating RTLIL representation for module `\_90_lut'.
-Successfully finished Verilog frontend.
-
-6.21.2. Continuing TECHMAP pass.
-No more expansions possible.
-<suppressed ~67 debug messages>
-
-6.22. Executing OPT pass (performing simple optimizations).
-
-6.22.1. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-6.22.2. Executing OPT_MERGE pass (detect identical cells).
-Finding identical cells in module `\simple_por'.
-Removed a total of 0 cells.
-
-6.22.3. Executing OPT_DFF pass (perform DFF optimizations).
-
-6.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-
-6.22.5. Finished fast OPT passes.
-
-6.23. Executing ABC pass (technology mapping using ABC).
-
-6.23.1. Extracting gate netlist of module `\simple_por' to `<abc-temp-dir>/input.blif'..
-Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
-Don't call ABC as there is nothing to map.
-Removing temp directory.
-
-6.24. Executing OPT pass (performing simple optimizations).
-
-6.24.1. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-6.24.2. Executing OPT_MERGE pass (detect identical cells).
-Finding identical cells in module `\simple_por'.
-Removed a total of 0 cells.
-
-6.24.3. Executing OPT_DFF pass (perform DFF optimizations).
-
-6.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-
-6.24.5. Finished fast OPT passes.
-
-6.25. Executing HIERARCHY pass (managing design hierarchy).
-
-6.25.1. Analyzing design hierarchy..
-Top module:  \simple_por
-
-6.25.2. Analyzing design hierarchy..
-Top module:  \simple_por
-Removed 0 unused modules.
-
-6.26. Printing statistics.
-
-=== simple_por ===
-
-   Number of wires:                  5
-   Number of wire bits:              5
-   Number of public wires:           5
-   Number of public wire bits:       5
-   Number of memories:               0
-   Number of memory bits:            0
-   Number of processes:              0
-   Number of cells:                  2
-     sky130_fd_sc_hvl__schmittbuf_1      2
-
-6.27. Executing CHECK pass (checking for obvious problems).
-checking module simple_por..
-found and reported 0 problems.
-
-7. Executing SHARE pass (SAT-based resource sharing).
-
-8. Executing OPT pass (performing simple optimizations).
-
-8.1. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-8.2. Executing OPT_MERGE pass (detect identical cells).
-Finding identical cells in module `\simple_por'.
-Removed a total of 0 cells.
-
-8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
-Running muxtree optimizer on module \simple_por..
-  Creating internal representation of mux trees.
-  No muxes found in this module.
-Removed 0 multiplexer ports.
-
-8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
-  Optimizing cells in module \simple_por.
-Performed a total of 0 changes.
-
-8.5. Executing OPT_MERGE pass (detect identical cells).
-Finding identical cells in module `\simple_por'.
-Removed a total of 0 cells.
-
-8.6. Executing OPT_DFF pass (perform DFF optimizations).
-
-8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-
-8.8. Executing OPT_EXPR pass (perform const folding).
-Optimizing module simple_por.
-
-8.9. Finished OPT passes. (There is nothing left to do.)
-
-9. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-Removed 0 unused cells and 1 unused wires.
-<suppressed ~1 debug messages>
-
-10. Printing statistics.
-
-=== simple_por ===
-
-   Number of wires:                  4
-   Number of wire bits:              4
-   Number of public wires:           4
-   Number of public wire bits:       4
-   Number of memories:               0
-   Number of memory bits:            0
-   Number of processes:              0
-   Number of cells:                  2
-     sky130_fd_sc_hvl__schmittbuf_1      2
-
-11. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
-  cell sky130_fd_sc_hvl__dfxtp_1 (noninv, pins=3, area=48.84) is a direct match for cell type $_DFF_P_.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
-  cell sky130_fd_sc_hvl__dfrtp_1 (noninv, pins=4, area=62.52) is a direct match for cell type $_DFF_PN0_.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
-  cell sky130_fd_sc_hvl__dfstp_1 (noninv, pins=4, area=60.56) is a direct match for cell type $_DFF_PN1_.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
-Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
-  final dff cell mappings:
-    unmapped dff cell: $_DFF_N_
-    \sky130_fd_sc_hvl__dfxtp_1 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
-    unmapped dff cell: $_DFF_NN0_
-    unmapped dff cell: $_DFF_NN1_
-    unmapped dff cell: $_DFF_NP0_
-    unmapped dff cell: $_DFF_NP1_
-    \sky130_fd_sc_hvl__dfrtp_1 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
-    \sky130_fd_sc_hvl__dfstp_1 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
-    unmapped dff cell: $_DFF_PP0_
-    unmapped dff cell: $_DFF_PP1_
-    unmapped dff cell: $_DFFSR_NNN_
-    unmapped dff cell: $_DFFSR_NNP_
-    unmapped dff cell: $_DFFSR_NPN_
-    unmapped dff cell: $_DFFSR_NPP_
-    unmapped dff cell: $_DFFSR_PNN_
-    unmapped dff cell: $_DFFSR_PNP_
-    unmapped dff cell: $_DFFSR_PPN_
-    unmapped dff cell: $_DFFSR_PPP_
-
-11.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
-Mapping DFF cells in module `\simple_por':
-
-12. Printing statistics.
-
-=== simple_por ===
-
-   Number of wires:                  4
-   Number of wire bits:              4
-   Number of public wires:           4
-   Number of public wire bits:       4
-   Number of memories:               0
-   Number of memory bits:            0
-   Number of processes:              0
-   Number of cells:                  2
-     sky130_fd_sc_hvl__schmittbuf_1      2
-
-13. Executing ABC pass (technology mapping using ABC).
-
-13.1. Extracting gate netlist of module `\simple_por' to `/tmp/yosys-abc-hrVmdg/input.blif'..
-Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
-Don't call ABC as there is nothing to map.
-Removing temp directory.
-
-14. Executing SETUNDEF pass (replace undef values with defined constants).
-
-15. Executing HILOMAP pass (mapping to constant drivers).
-
-16. Executing SPLITNETS pass (splitting up multi-bit signals).
-
-17. Executing OPT_CLEAN pass (remove unused cells and wires).
-Finding unused cells or wires in module \simple_por..
-
-18. Executing INSBUF pass (insert buffer cells for connected wires).
-
-19. Executing CHECK pass (checking for obvious problems).
-checking module simple_por..
-found and reported 0 problems.
-
-20. Printing statistics.
-
-=== simple_por ===
-
-   Number of wires:                  5
-   Number of wire bits:              5
-   Number of public wires:           4
-   Number of public wire bits:       4
-   Number of memories:               0
-   Number of memory bits:            0
-   Number of processes:              0
-   Number of cells:                  3
-     sky130_fd_sc_hvl__conb_1        1
-     sky130_fd_sc_hvl__schmittbuf_1      2
-
-   Chip area for module '\simple_por': 52.747200
-
-21. Executing Verilog backend.
-Dumping module `\simple_por'.
-
-Warnings: 8 unique messages, 56 total
-End of script. Logfile hash: bc23914c66, CPU: user 0.44s system 0.01s, MEM: 22.57 MB peak
-Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
-Time spent: 28% 4x read_liberty (0 sec), 27% 1x dfflibmap (0 sec), ...

diff --git a/openlane/simple_por/runs/simple_por/logs/synthesis/yosys_rewrite_verilog.log b/openlane/simple_por/runs/simple_por/logs/synthesis/yosys_rewrite_verilog.log
deleted file mode 100644
index fe3117d..0000000
--- a/openlane/simple_por/runs/simple_por/logs/synthesis/yosys_rewrite_verilog.log
+++ /dev/null

@@ -1,43 +0,0 @@
-
- /----------------------------------------------------------------------------\
- |                                                                            |
- |  yosys -- Yosys Open SYnthesis Suite                                       |
- |                                                                            |
- |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |
- |                                                                            |
- |  Permission to use, copy, modify, and/or distribute this software for any  |
- |  purpose with or without fee is hereby granted, provided that the above    |
- |  copyright notice and this permission notice appear in all copies.         |
- |                                                                            |
- |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
- |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
- |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
- |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
- |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
- |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
- |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
- |                                                                            |
- \----------------------------------------------------------------------------/
-
- Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
-
-[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
-[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
-[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
-[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
-[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
-
-1. Executing Verilog-2005 frontend: /project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.powered.v
-Parsing Verilog input from `/project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.powered.v' to AST representation.
-Generating RTLIL representation for module `\simple_por'.
-/project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.powered.v:12: Warning: Identifier `\_0_' is implicitly declared.
-/project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.powered.v:18: Warning: Identifier `\mid' is implicitly declared.
-Successfully finished Verilog frontend.
-
-2. Executing Verilog backend.
-Dumping module `\simple_por'.
-
-Warnings: 2 unique messages, 2 total
-End of script. Logfile hash: b41ccc5405, CPU: user 0.02s system 0.00s, MEM: 7.59 MB peak
-Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
-Time spent: 79% 2x write_verilog (0 sec), 20% 2x read_verilog (0 sec)

diff --git a/openlane/simple_por/runs/simple_por/logs/synthesis/yosys_runtime.txt b/openlane/simple_por/runs/simple_por/logs/synthesis/yosys_runtime.txt
deleted file mode 100644
index 0b9c936..0000000
--- a/openlane/simple_por/runs/simple_por/logs/synthesis/yosys_runtime.txt
+++ /dev/null

@@ -1 +0,0 @@
-0h0m0s463ms

diff --git a/openlane/simple_por/runs/simple_por/logs/write_verilog.log b/openlane/simple_por/runs/simple_por/logs/write_verilog.log
deleted file mode 100644
index c18aab0..0000000
--- a/openlane/simple_por/runs/simple_por/logs/write_verilog.log
+++ /dev/null

@@ -1,16 +0,0 @@
-OpenROAD 0.9.0 e582f2522b
-This program is licensed under the BSD-3 license. See the LICENSE file for details. 
-Components of this program may be licensed under more restrictive licenses which must be honored.
-Notice 0: Reading LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0:     Created 13 technology layers
-Notice 0:     Created 25 technology vias
-Notice 0:     Created 69 library cells
-Notice 0: Finished LEF file:  /project/openlane/simple_por/runs/simple_por/tmp/merged_unpadded.lef
-Notice 0: 
-Reading DEF file: /project/openlane/simple_por/runs/simple_por/tmp/routing/simple_por.powered.def
-Notice 0: Design: simple_por
-Notice 0:     Created 5 pins.
-Notice 0:     Created 16 components and 70 component-terminals.
-Notice 0:     Created 2 special nets and 0 connections.
-Notice 0:     Created 7 nets and 69 connections.
-Notice 0: Finished DEF file: /project/openlane/simple_por/runs/simple_por/tmp/routing/simple_por.powered.def

diff --git a/openlane/simple_por/runs/simple_por/reports/final_summary_report.csv b/openlane/simple_por/runs/simple_por/reports/final_summary_report.csv
deleted file mode 100644
index 506e699..0000000
--- a/openlane/simple_por/runs/simple_por/reports/final_summary_report.csv
+++ /dev/null

@@ -1,2 +0,0 @@
-,design,design_name,config,runtime,DIEAREA_mm^2,CellPer_mm^2,(Cell/mm^2)/Core_Util,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/simple_por,simple_por,simple_por,0h0m9s,0.00108,2777.777777777778,9259.25925925926,-1,371.9,3,0,0,0,0,0,0,23,0,0,30,10,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,28465,5,5,4,4,0,0,0,3,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,2,5,30,1,153.6,153.18,0.5,0,sky130_fd_sc_hvl,8,3

diff --git a/openlane/simple_por/runs/simple_por/reports/floorplan/verilog2def.core_area.rpt b/openlane/simple_por/runs/simple_por/reports/floorplan/verilog2def.core_area.rpt
deleted file mode 100644
index 3ff9cf7..0000000
--- a/openlane/simple_por/runs/simple_por/reports/floorplan/verilog2def.core_area.rpt
+++ /dev/null

@@ -1 +0,0 @@
-5.76 16.28 18.72 28.49

diff --git a/openlane/simple_por/runs/simple_por/reports/floorplan/verilog2def.die_area.rpt b/openlane/simple_por/runs/simple_por/reports/floorplan/verilog2def.die_area.rpt
deleted file mode 100644
index ef57a1b..0000000
--- a/openlane/simple_por/runs/simple_por/reports/floorplan/verilog2def.die_area.rpt
+++ /dev/null

@@ -1 +0,0 @@
-0.0 0.0 24.78 45.82

diff --git a/openlane/simple_por/runs/simple_por/reports/placement/openphysyn_allchecks.rpt b/openlane/simple_por/runs/simple_por/reports/placement/openphysyn_allchecks.rpt
deleted file mode 100644
index 804fb12..0000000
--- a/openlane/simple_por/runs/simple_por/reports/placement/openphysyn_allchecks.rpt
+++ /dev/null

@@ -1 +0,0 @@
-No paths found.

diff --git a/openlane/simple_por/runs/simple_por/reports/placement/openphysyn_tns.rpt b/openlane/simple_por/runs/simple_por/reports/placement/openphysyn_tns.rpt
deleted file mode 100644
index 53df237..0000000
--- a/openlane/simple_por/runs/simple_por/reports/placement/openphysyn_tns.rpt
+++ /dev/null

@@ -1 +0,0 @@
-tns 0.00

diff --git a/openlane/simple_por/runs/simple_por/reports/placement/openphysyn_violators.rpt b/openlane/simple_por/runs/simple_por/reports/placement/openphysyn_violators.rpt
deleted file mode 100644
index e69de29..0000000
--- a/openlane/simple_por/runs/simple_por/reports/placement/openphysyn_violators.rpt
+++ /dev/null


diff --git a/openlane/simple_por/runs/simple_por/reports/placement/openphysyn_wns.rpt b/openlane/simple_por/runs/simple_por/reports/placement/openphysyn_wns.rpt
deleted file mode 100644
index 3196164..0000000
--- a/openlane/simple_por/runs/simple_por/reports/placement/openphysyn_wns.rpt
+++ /dev/null

@@ -1 +0,0 @@
-wns 0.00

diff --git a/openlane/simple_por/runs/simple_por/reports/placement/replace.min_max.rpt b/openlane/simple_por/runs/simple_por/reports/placement/replace.min_max.rpt
deleted file mode 100644
index 804fb12..0000000
--- a/openlane/simple_por/runs/simple_por/reports/placement/replace.min_max.rpt
+++ /dev/null

@@ -1 +0,0 @@
-No paths found.

diff --git a/openlane/simple_por/runs/simple_por/reports/placement/replace.rpt b/openlane/simple_por/runs/simple_por/reports/placement/replace.rpt
deleted file mode 100644
index 804fb12..0000000
--- a/openlane/simple_por/runs/simple_por/reports/placement/replace.rpt
+++ /dev/null

@@ -1 +0,0 @@
-No paths found.

diff --git a/openlane/simple_por/runs/simple_por/reports/placement/replace.timing.rpt b/openlane/simple_por/runs/simple_por/reports/placement/replace.timing.rpt
deleted file mode 100644
index 804fb12..0000000
--- a/openlane/simple_por/runs/simple_por/reports/placement/replace.timing.rpt
+++ /dev/null

@@ -1 +0,0 @@
-No paths found.

diff --git a/openlane/simple_por/runs/simple_por/reports/placement/replace_tns.rpt b/openlane/simple_por/runs/simple_por/reports/placement/replace_tns.rpt
deleted file mode 100644
index 53df237..0000000
--- a/openlane/simple_por/runs/simple_por/reports/placement/replace_tns.rpt
+++ /dev/null

@@ -1 +0,0 @@
-tns 0.00

diff --git a/openlane/simple_por/runs/simple_por/reports/placement/replace_wns.rpt b/openlane/simple_por/runs/simple_por/reports/placement/replace_wns.rpt
deleted file mode 100644
index 3196164..0000000
--- a/openlane/simple_por/runs/simple_por/reports/placement/replace_wns.rpt
+++ /dev/null

@@ -1 +0,0 @@
-wns 0.00

diff --git a/openlane/simple_por/runs/simple_por/reports/routing/antenna.rpt b/openlane/simple_por/runs/simple_por/reports/routing/antenna.rpt
deleted file mode 100644
index d156fbc..0000000
--- a/openlane/simple_por/runs/simple_por/reports/routing/antenna.rpt
+++ /dev/null

@@ -1,69 +0,0 @@
-Warning - class CORE ANTENNACELL is not found. This msg can be ignored if not in the antenna-avoid flow
-
-Net - porb_h
-  No sinks on this net
-
-Net - vdd3v3
-
-Net - vss
-
-Net - _0_
-  hystbuf1  (sky130_fd_sc_hvl__schmittbuf_1)  A
-[1]  met2:
-  PAR:    0.41  Ratio:    0.00       (Area)
-  PAR:    2.08  Ratio:  400.00       (S.Area)
-  CAR:    0.49  Ratio:    0.00       (C.Area)
-  CAR:    2.55  Ratio:    0.00       (C.S.Area)
-
-[1]  met1:
-  PAR:    0.07  Ratio:    0.00       (Area)
-  PAR:    0.45  Ratio:  400.00       (S.Area)
-  CAR:    0.09  Ratio:    0.00       (C.Area)
-  CAR:    0.47  Ratio:    0.00       (C.S.Area)
-
-[1]  li1:
-  PAR:    0.01  Ratio:    0.00       (Area)
-  PAR:    0.01  Ratio:   75.00       (S.Area)
-  CAR:    0.01  Ratio:    0.00       (C.Area)
-  CAR:    0.01  Ratio:    0.00       (C.S.Area)
-
-[1]  M1M2_PR:
-  PAR:    0.02  Ratio:    6.00       (Area)
-  CAR:    0.04  Ratio:    0.00       (C.Area)
-
-[1]  L1M1_PR_MR:
-  PAR:    0.02  Ratio:    3.00       (Area)
-  CAR:    0.02  Ratio:    0.00       (C.Area)
-
-
-Net - mid
-  hystbuf2  (sky130_fd_sc_hvl__schmittbuf_1)  A
-[1]  met2:
-  PAR:    0.41  Ratio:    0.00       (Area)
-  PAR:    2.08  Ratio: 2838.50       (S.Area)
-  CAR:    0.44  Ratio:    0.00       (C.Area)
-  CAR:    2.18  Ratio:    0.00       (C.S.Area)
-
-[1]  met1:
-  PAR:    0.02  Ratio:    0.00       (Area)
-  PAR:    0.08  Ratio:  400.00       (S.Area)
-  CAR:    0.03  Ratio:    0.00       (C.Area)
-  CAR:    0.10  Ratio:    0.00       (C.S.Area)
-
-[1]  li1:
-  PAR:    0.01  Ratio:    0.00       (Area)
-  PAR:    0.01  Ratio:   75.00       (S.Area)
-  CAR:    0.01  Ratio:    0.00       (C.Area)
-  CAR:    0.01  Ratio:    0.00       (C.S.Area)
-
-[1]  M1M2_PR:
-  PAR:    0.02  Ratio:    6.00       (Area)
-  CAR:    0.04  Ratio:    0.00       (C.Area)
-
-[1]  L1M1_PR_MR:
-  PAR:    0.02  Ratio:    3.00       (Area)
-  CAR:    0.02  Ratio:    0.00       (C.Area)
-
-Number of pins violated: 0
-Number of nets violated: 0
-Total number of unspecial nets: 5

diff --git a/openlane/simple_por/runs/simple_por/reports/routing/tritonRoute.drc b/openlane/simple_por/runs/simple_por/reports/routing/tritonRoute.drc
deleted file mode 100644
index e69de29..0000000
--- a/openlane/simple_por/runs/simple_por/reports/routing/tritonRoute.drc
+++ /dev/null


diff --git a/openlane/simple_por/runs/simple_por/reports/runtime.txt b/openlane/simple_por/runs/simple_por/reports/runtime.txt
deleted file mode 100644
index afae173..0000000
--- a/openlane/simple_por/runs/simple_por/reports/runtime.txt
+++ /dev/null

@@ -1 +0,0 @@
-Routing completed for simple_por/11-11_03-14 in 0h0m9s

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta.min_max.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta.min_max.rpt
deleted file mode 100644
index 804fb12..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta.min_max.rpt
+++ /dev/null

@@ -1 +0,0 @@
-No paths found.

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta.rpt
deleted file mode 100644
index 804fb12..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta.rpt
+++ /dev/null

@@ -1 +0,0 @@
-No paths found.

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta.timing.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta.timing.rpt
deleted file mode 100644
index 804fb12..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta.timing.rpt
+++ /dev/null

@@ -1 +0,0 @@
-No paths found.

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn.min_max.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn.min_max.rpt
deleted file mode 100644
index 804fb12..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn.min_max.rpt
+++ /dev/null

@@ -1 +0,0 @@
-No paths found.

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn.rpt
deleted file mode 100644
index 804fb12..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn.rpt
+++ /dev/null

@@ -1 +0,0 @@
-No paths found.

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn.timing.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn.timing.rpt
deleted file mode 100644
index 804fb12..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn.timing.rpt
+++ /dev/null

@@ -1 +0,0 @@
-No paths found.

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn_tns.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn_tns.rpt
deleted file mode 100644
index 53df237..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn_tns.rpt
+++ /dev/null

@@ -1 +0,0 @@
-tns 0.00

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn_wns.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn_wns.rpt
deleted file mode 100644
index 3196164..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_post_openphysyn_wns.rpt
+++ /dev/null

@@ -1 +0,0 @@
-wns 0.00

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef.min_max.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef.min_max.rpt
deleted file mode 100644
index 804fb12..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef.min_max.rpt
+++ /dev/null

@@ -1 +0,0 @@
-No paths found.

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef.rpt
deleted file mode 100644
index 804fb12..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef.rpt
+++ /dev/null

@@ -1 +0,0 @@
-No paths found.

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef.timing.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef.timing.rpt
deleted file mode 100644
index 804fb12..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef.timing.rpt
+++ /dev/null

@@ -1 +0,0 @@
-No paths found.

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef_tns.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef_tns.rpt
deleted file mode 100644
index 53df237..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef_tns.rpt
+++ /dev/null

@@ -1 +0,0 @@
-tns 0.00

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef_wns.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef_wns.rpt
deleted file mode 100644
index 3196164..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_spef_wns.rpt
+++ /dev/null

@@ -1 +0,0 @@
-wns 0.00

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_tns.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_tns.rpt
deleted file mode 100644
index 53df237..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_tns.rpt
+++ /dev/null

@@ -1 +0,0 @@
-tns 0.00

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_wns.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_wns.rpt
deleted file mode 100644
index 3196164..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/opensta_wns.rpt
+++ /dev/null

@@ -1 +0,0 @@
-wns 0.00

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/yosys_2.chk.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/yosys_2.chk.rpt
deleted file mode 100644
index 36f18a4..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/yosys_2.chk.rpt
+++ /dev/null

@@ -1,4 +0,0 @@
-
-19. Executing CHECK pass (checking for obvious problems).
-checking module simple_por..
-found and reported 0 problems.

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/yosys_2.stat.rpt b/openlane/simple_por/runs/simple_por/reports/synthesis/yosys_2.stat.rpt
deleted file mode 100644
index 364a9ea..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/yosys_2.stat.rpt
+++ /dev/null

@@ -1,18 +0,0 @@
-
-20. Printing statistics.
-
-=== simple_por ===
-
-   Number of wires:                  5
-   Number of wire bits:              5
-   Number of public wires:           4
-   Number of public wire bits:       4
-   Number of memories:               0
-   Number of memory bits:            0
-   Number of processes:              0
-   Number of cells:                  3
-     sky130_fd_sc_hvl__conb_1        1
-     sky130_fd_sc_hvl__schmittbuf_1      2
-
-   Chip area for module '\simple_por': 52.747200
-

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/yosys_dff.stat b/openlane/simple_por/runs/simple_por/reports/synthesis/yosys_dff.stat
deleted file mode 100644
index f580948..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/yosys_dff.stat
+++ /dev/null

@@ -1,15 +0,0 @@
-
-12. Printing statistics.
-
-=== simple_por ===
-
-   Number of wires:                  4
-   Number of wire bits:              4
-   Number of public wires:           4
-   Number of public wire bits:       4
-   Number of memories:               0
-   Number of memory bits:            0
-   Number of processes:              0
-   Number of cells:                  2
-     sky130_fd_sc_hvl__schmittbuf_1      2
-

diff --git a/openlane/simple_por/runs/simple_por/reports/synthesis/yosys_pre.stat b/openlane/simple_por/runs/simple_por/reports/synthesis/yosys_pre.stat
deleted file mode 100644
index 6aed169..0000000
--- a/openlane/simple_por/runs/simple_por/reports/synthesis/yosys_pre.stat
+++ /dev/null

@@ -1,15 +0,0 @@
-
-10. Printing statistics.
-
-=== simple_por ===
-
-   Number of wires:                  4
-   Number of wire bits:              4
-   Number of public wires:           4
-   Number of public wire bits:       4
-   Number of memories:               0
-   Number of memory bits:            0
-   Number of processes:              0
-   Number of cells:                  2
-     sky130_fd_sc_hvl__schmittbuf_1      2
-

diff --git a/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.json b/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.json
deleted file mode 100644
index 8033210..0000000
--- a/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.json
+++ /dev/null

@@ -1,72 +0,0 @@
-[
-  {
-   "pins": [
-      [
-        "A",
-        "X",
-        "VGND",
-        "VNB",
-        "VPB",
-        "VPWR"
-      ], [
-        "A",
-        "X",
-        "VGND",
-        "VNB",
-        "VPB",
-        "VPWR"
-      ]
-   ]
-  },
-  {
-   "pins": [
-      [
-        "LO",
-        "VGND",
-        "VNB",
-        "VPB",
-        "VPWR"
-      ], [
-        "LO",
-        "VGND",
-        "VNB",
-        "VPB",
-        "VPWR"
-      ]
-   ]
-  },
-  {
-   "name": [
-      "simple_por",
-      "simple_por"
-   ],
-   "devices": [
-       [
-         ["sky130_fd_sc_hvl__schmittbuf_1", 2],
-         ["sky130_fd_sc_hvl__conb_1", 1 ]
-       ], [
-         ["sky130_fd_sc_hvl__schmittbuf_1", 2 ],
-         ["sky130_fd_sc_hvl__conb_1", 1 ]
-       ]
-   ],
-   "nets": [
-    5,
-    5
-   ],
-   "badnets": [
-   ],
-   "badelements": [
-   ],
-   "pins": [
-      [
-        "porb_h",
-        "VGND",
-        "VPWR"
-      ], [
-        "porb_h",
-        "VGND",
-        "VPWR"
-      ]
-   ]
-  }
-]

diff --git a/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.log b/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.log
deleted file mode 100644
index 1cfe1f1..0000000
--- a/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.log
+++ /dev/null

@@ -1,69 +0,0 @@
-
-Cell sky130_fd_sc_hvl__schmittbuf_1 disconnected node: A
-Cell sky130_fd_sc_hvl__schmittbuf_1 disconnected node: X
-Cell sky130_fd_sc_hvl__schmittbuf_1 disconnected node: VGND
-Cell sky130_fd_sc_hvl__schmittbuf_1 disconnected node: VNB
-Cell sky130_fd_sc_hvl__schmittbuf_1 disconnected node: VPB
-Cell sky130_fd_sc_hvl__schmittbuf_1 disconnected node: VPWR
-Warning: Equate pins:  cell sky130_fd_sc_hvl__schmittbuf_1 has no definition, treated as a black box.
-
-Subcircuit pins:
-Circuit 1: sky130_fd_sc_hvl__schmittbuf_1  |Circuit 2: sky130_fd_sc_hvl__schmittbuf_1  
--------------------------------------------|-------------------------------------------
-A                                          |A                                          
-X                                          |X                                          
-VGND                                       |VGND                                       
-VNB                                        |VNB                                        
-VPB                                        |VPB                                        
-VPWR                                       |VPWR                                       
----------------------------------------------------------------------------------------
-Cell pin lists are equivalent.
-Device classes sky130_fd_sc_hvl__schmittbuf_1 and sky130_fd_sc_hvl__schmittbuf_1 are equivalent.
-
-Cell sky130_fd_sc_hvl__conb_1 disconnected node: HI
-Cell sky130_fd_sc_hvl__conb_1 disconnected node: LO
-Cell sky130_fd_sc_hvl__conb_1 disconnected node: VGND
-Cell sky130_fd_sc_hvl__conb_1 disconnected node: VNB
-Cell sky130_fd_sc_hvl__conb_1 disconnected node: VPB
-Cell sky130_fd_sc_hvl__conb_1 disconnected node: VPWR
-Warning: Equate pins:  cell sky130_fd_sc_hvl__conb_1 has no definition, treated as a black box.
-
-Subcircuit pins:
-Circuit 1: sky130_fd_sc_hvl__conb_1        |Circuit 2: sky130_fd_sc_hvl__conb_1        
--------------------------------------------|-------------------------------------------
-LO                                         |LO                                         
-VGND                                       |VGND                                       
-VNB                                        |VNB                                        
-VPB                                        |VPB                                        
-VPWR                                       |VPWR                                       
----------------------------------------------------------------------------------------
-Cell pin lists are equivalent.
-Device classes sky130_fd_sc_hvl__conb_1 and sky130_fd_sc_hvl__conb_1 are equivalent.
-
-Cell simple_por disconnected node: vdd3v3
-Cell simple_por disconnected node: vss
-
-Cell simple_por disconnected node: vdd3v3
-Cell simple_por disconnected node: vss
-
-Subcircuit summary:
-Circuit 1: simple_por                      |Circuit 2: simple_por                      
--------------------------------------------|-------------------------------------------
-sky130_fd_sc_hvl__schmittbuf_1 (2)         |sky130_fd_sc_hvl__schmittbuf_1 (2)         
-sky130_fd_sc_hvl__conb_1 (1)               |sky130_fd_sc_hvl__conb_1 (1)               
-Number of devices: 3                       |Number of devices: 3                       
-Number of nets: 5                          |Number of nets: 5                          
----------------------------------------------------------------------------------------
-Circuits match uniquely.
-Netlists match uniquely.
-
-Subcircuit pins:
-Circuit 1: simple_por                      |Circuit 2: simple_por                      
--------------------------------------------|-------------------------------------------
-porb_h                                     |porb_h                                     
-VGND                                       |VGND                                       
-VPWR                                       |VPWR                                       
----------------------------------------------------------------------------------------
-Cell pin lists are equivalent.
-Device classes simple_por and simple_por are equivalent.
-Circuits match uniquely.

diff --git a/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.powered.v b/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.powered.v
deleted file mode 100644
index bf90099..0000000
--- a/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.powered.v
+++ /dev/null

@@ -1,112 +0,0 @@
-/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
-
-module simple_por(porb_h, vdd3v3, vss, VPWR, VGND);
-  input VGND;
-  input VPWR;
-  wire _0_;
-  wire mid;
-  output porb_h;
-  input vdd3v3;
-  input vss;
-  sky130_fd_sc_hvl__decap_4 FILLER_0_0 (
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hvl__decap_8 FILLER_0_12 (
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hvl__decap_4 FILLER_0_20 (
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hvl__fill_2 FILLER_0_24 (
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hvl__fill_1 FILLER_0_26 (
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hvl__fill_2 FILLER_0_4 (
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hvl__fill_1 FILLER_0_6 (
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hvl__decap_4 FILLER_1_0 (
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hvl__decap_8 FILLER_1_15 (
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hvl__decap_4 FILLER_1_23 (
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hvl__decap_4 FILLER_2_0 (
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hvl__decap_8 FILLER_2_15 (
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hvl__decap_4 FILLER_2_23 (
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hvl__conb_1 _1_ (
-    .LO(_0_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR)
-  );
-  sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
-    .A(_0_),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR),
-    .X(mid)
-  );
-  sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
-    .A(mid),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR),
-    .X(porb_h)
-  );
-endmodule

diff --git a/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs_parsed.log b/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs_parsed.log
deleted file mode 100644
index 0a843e5..0000000
--- a/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs_parsed.log
+++ /dev/null

@@ -1,3 +0,0 @@
-LVS reports no net, device, pin, or property mismatches.
-
-Total errors = 0

diff --git a/openlane/simple_por/runs/simple_por/results/magic/.magicrc b/openlane/simple_por/runs/simple_por/results/magic/.magicrc
deleted file mode 100644
index 9d2bba1..0000000
--- a/openlane/simple_por/runs/simple_por/results/magic/.magicrc
+++ /dev/null

@@ -1,75 +0,0 @@
-puts stdout "Sourcing design .magicrc for technology sky130A ..."
-
-# Put grid on 0.005 pitch.  This is important, as some commands don't
-# rescale the grid automatically (such as lef read?).
-
-set scalefac [tech lambda]
-if {[lindex $scalefac 1] < 2} {
-    scalegrid 1 2
-}
-
-# drc off
-drc euclidean on
-
-# Allow override of PDK path from environment variable PDKPATH
-if {[catch {set PDKPATH $env(PDKPATH)}]} {
-    set PDKPATH "/home/xrex/usr/devel/pdks/sky130A"
-}
-
-# loading technology
-tech load $PDKPATH/libs.tech/magic/current/sky130A.tech
-
-# load device generator
-source $PDKPATH/libs.tech/magic/current/sky130A.tcl
-
-# load bind keys (optional)
-# source $PDKPATH/libs.tech/magic/current/sky130A-BindKeys
-
-# set units to lambda grid 
-snap lambda
-
-# set sky130 standard power, ground, and substrate names
-set VDD VPWR
-set GND VGND
-set SUB VSUBS
-
-# Allow override of type of magic library views used, "mag" or "maglef",
-# from environment variable MAGTYPE
-
-if {[catch {set MAGTYPE $env(MAGTYPE)}]} {
-   set MAGTYPE maglef
-}
-
-# add path to reference cells
-if {[file isdir ${PDKPATH}/libs.ref/${MAGTYPE}]} {
-    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_pr
-    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_io
-    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hd
-    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hdll
-    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hs
-    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_hvl
-    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_lp
-    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ls
-    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_fd_sc_ms
-    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc
-    addpath ${PDKPATH}/libs.ref/${MAGTYPE}/sky130_osu_sc_t18
-} else {
-    addpath ${PDKPATH}/libs.ref/sky130_fd_pr/${MAGTYPE}
-    addpath ${PDKPATH}/libs.ref/sky130_fd_io/${MAGTYPE}
-    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hd/${MAGTYPE}
-    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hdll/${MAGTYPE}
-    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hs/${MAGTYPE}
-    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_hvl/${MAGTYPE}
-    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_lp/${MAGTYPE}
-    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ls/${MAGTYPE}
-    addpath ${PDKPATH}/libs.ref/sky130_fd_sc_ms/${MAGTYPE}
-    addpath ${PDKPATH}/libs.ref/sky130_osu_sc/${MAGTYPE}
-    addpath ${PDKPATH}/libs.ref/sky130_osu_sc_t18/${MAGTYPE}
-}
-
-# add path to GDS cells
-
-# add path to IP from catalog.  This procedure defined in the PDK script.
-catch {magic::query_mylib_ip}
-# add path to local IP from user design space.  Defined in the PDK script.
-catch {magic::query_my_projects}

diff --git a/openlane/simple_por/runs/simple_por/results/magic/simple_por.drc.mag b/openlane/simple_por/runs/simple_por/results/magic/simple_por.drc.mag
deleted file mode 100644
index 0af4f0a..0000000
--- a/openlane/simple_por/runs/simple_por/results/magic/simple_por.drc.mag
+++ /dev/null

@@ -1,953 +0,0 @@
-magic
-tech sky130A
-magscale 1 2
-timestamp 1605064460
-<< checkpaint >>
-rect -3932 -3932 8292 13096
-<< viali >>
-rect 1931 5496 1965 5530
-rect 1547 5274 1581 5308
-rect 1931 4682 1965 4716
-rect 1547 4460 1581 4494
-rect 1451 3868 1485 3902
-<< metal1 >>
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-rect 556 5672 1298 5724
-rect 1350 5672 1362 5724
-rect 1414 5672 1426 5724
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-rect 556 5647 3148 5672
-rect 764 5487 770 5539
-rect 822 5527 828 5539
-rect 1919 5530 1977 5536
-rect 1919 5527 1931 5530
-rect 822 5499 1931 5527
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-rect 1965 5496 1977 5530
-rect 1919 5490 1977 5496
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-rect 556 3282 3148 3307
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-rect 1846 3230 1858 3282
-rect 1910 3230 1922 3282
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-rect 2710 3230 2722 3282
-rect 2774 3230 2786 3282
-rect 2838 3230 3148 3282
-rect 556 3205 3148 3230
-<< via1 >>
-rect 1298 5672 1350 5724
-rect 1362 5672 1414 5724
-rect 1426 5672 1478 5724
-rect 1490 5672 1542 5724
-rect 2162 5672 2214 5724
-rect 2226 5672 2278 5724
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-rect 1547 5274 1581 5308
-rect 1581 5274 1590 5308
-rect 1538 5265 1590 5274
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-rect 1058 4858 1110 4910
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-rect 1922 4858 1974 4910
-rect 2594 4858 2646 4910
-rect 2658 4858 2710 4910
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-rect 1538 4673 1590 4725
-rect 1634 4451 1686 4503
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-rect 1922 3230 1974 3282
-rect 2594 3230 2646 3282
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-<< metal2 >>
-rect 768 8364 824 9164
-rect 782 5545 810 8364
-rect 1272 5726 1568 5749
-rect 1328 5724 1352 5726
-rect 1408 5724 1432 5726
-rect 1488 5724 1512 5726
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-rect 1920 4856 1944 4858
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-rect 1272 4098 1568 4121
-rect 1328 4096 1352 4098
-rect 1408 4096 1432 4098
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-rect 2352 4042 2376 4044
-rect 2136 4019 2432 4042
-rect 1634 3911 1686 3917
-rect 1634 3853 1686 3859
-rect 840 3284 1136 3307
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-rect 976 3282 1000 3284
-rect 1056 3282 1080 3284
-rect 918 3230 920 3282
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-rect 1056 3230 1058 3282
-rect 896 3228 920 3230
-rect 976 3228 1000 3230
-rect 1056 3228 1080 3230
-rect 840 3205 1136 3228
-rect 1704 3284 2000 3307
-rect 1760 3282 1784 3284
-rect 1840 3282 1864 3284
-rect 1920 3282 1944 3284
-rect 1782 3230 1784 3282
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-rect 1760 3228 1784 3230
-rect 1840 3228 1864 3230
-rect 1920 3228 1944 3230
-rect 1704 3205 2000 3228
-rect 2568 3284 2864 3307
-rect 2624 3282 2648 3284
-rect 2704 3282 2728 3284
-rect 2784 3282 2808 3284
-rect 2646 3230 2648 3282
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-rect 2784 3230 2786 3282
-rect 2624 3228 2648 3230
-rect 2704 3228 2728 3230
-rect 2784 3228 2808 3230
-rect 2568 3205 2864 3228
-rect 0 0 56 800
-<< via2 >>
-rect 1272 5724 1328 5726
-rect 1352 5724 1408 5726
-rect 1432 5724 1488 5726
-rect 1512 5724 1568 5726
-rect 1272 5672 1298 5724
-rect 1298 5672 1328 5724
-rect 1352 5672 1362 5724
-rect 1362 5672 1408 5724
-rect 1432 5672 1478 5724
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-rect 1432 5670 1488 5672
-rect 1512 5670 1568 5672
-rect 2136 5724 2192 5726
-rect 2216 5724 2272 5726
-rect 2296 5724 2352 5726
-rect 2376 5724 2432 5726
-rect 2136 5672 2162 5724
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-rect 2216 5672 2226 5724
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-rect 2296 5672 2342 5724
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-rect 2136 5670 2192 5672
-rect 2216 5670 2272 5672
-rect 2296 5670 2352 5672
-rect 2376 5670 2432 5672
-rect 840 4910 896 4912
-rect 920 4910 976 4912
-rect 1000 4910 1056 4912
-rect 1080 4910 1136 4912
-rect 840 4858 866 4910
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-rect 920 4858 930 4910
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-rect 1110 4858 1136 4910
-rect 840 4856 896 4858
-rect 920 4856 976 4858
-rect 1000 4856 1056 4858
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-rect 1704 4910 1760 4912
-rect 1784 4910 1840 4912
-rect 1864 4910 1920 4912
-rect 1944 4910 2000 4912
-rect 1704 4858 1730 4910
-rect 1730 4858 1760 4910
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-rect 1864 4858 1910 4910
-rect 1910 4858 1920 4910
-rect 1944 4858 1974 4910
-rect 1974 4858 2000 4910
-rect 1704 4856 1760 4858
-rect 1784 4856 1840 4858
-rect 1864 4856 1920 4858
-rect 1944 4856 2000 4858
-rect 2568 4910 2624 4912
-rect 2648 4910 2704 4912
-rect 2728 4910 2784 4912
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-rect 2838 4858 2864 4910
-rect 2568 4856 2624 4858
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-rect 1272 4096 1328 4098
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-rect 866 3230 896 3282
-rect 920 3230 930 3282
-rect 930 3230 976 3282
-rect 1000 3230 1046 3282
-rect 1046 3230 1056 3282
-rect 1080 3230 1110 3282
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-rect 1000 3228 1056 3230
-rect 1080 3228 1136 3230
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-rect 1944 3282 2000 3284
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-rect 1730 3230 1760 3282
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-rect 1910 3230 1920 3282
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-rect 1864 3228 1920 3230
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-rect 2838 3230 2864 3282
-rect 2568 3228 2624 3230
-rect 2648 3228 2704 3230
-rect 2728 3228 2784 3230
-rect 2808 3228 2864 3230
-<< metal3 >>
-rect 1260 5730 1580 5731
-rect 1260 5666 1268 5730
-rect 1332 5666 1348 5730
-rect 1412 5666 1428 5730
-rect 1492 5666 1508 5730
-rect 1572 5666 1580 5730
-rect 1260 5665 1580 5666
-rect 2124 5730 2444 5731
-rect 2124 5666 2132 5730
-rect 2196 5666 2212 5730
-rect 2276 5666 2292 5730
-rect 2356 5666 2372 5730
-rect 2436 5666 2444 5730
-rect 2124 5665 2444 5666
-rect 828 4916 1148 4917
-rect 828 4852 836 4916
-rect 900 4852 916 4916
-rect 980 4852 996 4916
-rect 1060 4852 1076 4916
-rect 1140 4852 1148 4916
-rect 828 4851 1148 4852
-rect 1692 4916 2012 4917
-rect 1692 4852 1700 4916
-rect 1764 4852 1780 4916
-rect 1844 4852 1860 4916
-rect 1924 4852 1940 4916
-rect 2004 4852 2012 4916
-rect 1692 4851 2012 4852
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-rect 2556 4852 2564 4916
-rect 2628 4852 2644 4916
-rect 2708 4852 2724 4916
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-rect 2868 4852 2876 4916
-rect 2556 4851 2876 4852
-rect 1260 4102 1580 4103
-rect 1260 4038 1268 4102
-rect 1332 4038 1348 4102
-rect 1412 4038 1428 4102
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-rect 1572 4038 1580 4102
-rect 1260 4037 1580 4038
-rect 2124 4102 2444 4103
-rect 2124 4038 2132 4102
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-rect 2276 4038 2292 4102
-rect 2356 4038 2372 4102
-rect 2436 4038 2444 4102
-rect 2124 4037 2444 4038
-rect 3560 3862 4360 3982
-rect 828 3288 1148 3289
-rect 828 3224 836 3288
-rect 900 3224 916 3288
-rect 980 3224 996 3288
-rect 1060 3224 1076 3288
-rect 1140 3224 1148 3288
-rect 828 3223 1148 3224
-rect 1692 3288 2012 3289
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-rect 1764 3224 1780 3288
-rect 1844 3224 1860 3288
-rect 1924 3224 1940 3288
-rect 2004 3224 2012 3288
-rect 1692 3223 2012 3224
-rect 2556 3288 2876 3289
-rect 2556 3224 2564 3288
-rect 2628 3224 2644 3288
-rect 2708 3224 2724 3288
-rect 2788 3224 2804 3288
-rect 2868 3224 2876 3288
-rect 2556 3223 2876 3224
-<< via3 >>
-rect 1268 5726 1332 5730
-rect 1268 5670 1272 5726
-rect 1272 5670 1328 5726
-rect 1328 5670 1332 5726
-rect 1268 5666 1332 5670
-rect 1348 5726 1412 5730
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-rect 1352 5670 1408 5726
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-rect 1348 5666 1412 5670
-rect 1428 5726 1492 5730
-rect 1428 5670 1432 5726
-rect 1432 5670 1488 5726
-rect 1488 5670 1492 5726
-rect 1428 5666 1492 5670
-rect 1508 5726 1572 5730
-rect 1508 5670 1512 5726
-rect 1512 5670 1568 5726
-rect 1568 5670 1572 5726
-rect 1508 5666 1572 5670
-rect 2132 5726 2196 5730
-rect 2132 5670 2136 5726
-rect 2136 5670 2192 5726
-rect 2192 5670 2196 5726
-rect 2132 5666 2196 5670
-rect 2212 5726 2276 5730
-rect 2212 5670 2216 5726
-rect 2216 5670 2272 5726
-rect 2272 5670 2276 5726
-rect 2212 5666 2276 5670
-rect 2292 5726 2356 5730
-rect 2292 5670 2296 5726
-rect 2296 5670 2352 5726
-rect 2352 5670 2356 5726
-rect 2292 5666 2356 5670
-rect 2372 5726 2436 5730
-rect 2372 5670 2376 5726
-rect 2376 5670 2432 5726
-rect 2432 5670 2436 5726
-rect 2372 5666 2436 5670
-rect 836 4912 900 4916
-rect 836 4856 840 4912
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-rect 836 4852 900 4856
-rect 916 4912 980 4916
-rect 916 4856 920 4912
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-rect 916 4852 980 4856
-rect 996 4912 1060 4916
-rect 996 4856 1000 4912
-rect 1000 4856 1056 4912
-rect 1056 4856 1060 4912
-rect 996 4852 1060 4856
-rect 1076 4912 1140 4916
-rect 1076 4856 1080 4912
-rect 1080 4856 1136 4912
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-rect 1076 4852 1140 4856
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-rect 1700 4856 1704 4912
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-rect 1700 4852 1764 4856
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-rect 2644 4852 2708 4856
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-rect 2724 4852 2788 4856
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-rect 2804 4852 2868 4856
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-rect 1704 3228 1760 3284
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-rect 1700 3224 1764 3228
-rect 1780 3284 1844 3288
-rect 1780 3228 1784 3284
-rect 1784 3228 1840 3284
-rect 1840 3228 1844 3284
-rect 1780 3224 1844 3228
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-rect 1860 3228 1864 3284
-rect 1864 3228 1920 3284
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-rect 1860 3224 1924 3228
-rect 1940 3284 2004 3288
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-rect 1944 3228 2000 3284
-rect 2000 3228 2004 3284
-rect 1940 3224 2004 3228
-rect 2564 3284 2628 3288
-rect 2564 3228 2568 3284
-rect 2568 3228 2624 3284
-rect 2624 3228 2628 3284
-rect 2564 3224 2628 3228
-rect 2644 3284 2708 3288
-rect 2644 3228 2648 3284
-rect 2648 3228 2704 3284
-rect 2704 3228 2708 3284
-rect 2644 3224 2708 3228
-rect 2724 3284 2788 3288
-rect 2724 3228 2728 3284
-rect 2728 3228 2784 3284
-rect 2784 3228 2788 3284
-rect 2724 3224 2788 3228
-rect 2804 3284 2868 3288
-rect 2804 3228 2808 3284
-rect 2808 3228 2864 3284
-rect 2864 3228 2868 3284
-rect 2804 3224 2868 3228
-<< metal4 >>
-rect 828 5358 1148 5749
-rect 828 5122 870 5358
-rect 1106 5122 1148 5358
-rect 828 4916 1148 5122
-rect 828 4852 836 4916
-rect 900 4852 916 4916
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-rect 828 4544 1148 4852
-rect 828 4308 870 4544
-rect 1106 4308 1148 4544
-rect 828 3730 1148 4308
-rect 828 3494 870 3730
-rect 1106 3494 1148 3730
-rect 828 3288 1148 3494
-rect 828 3224 836 3288
-rect 900 3224 916 3288
-rect 980 3224 996 3288
-rect 1060 3224 1076 3288
-rect 1140 3224 1148 3288
-rect 828 3205 1148 3224
-rect 1260 5730 1580 5749
-rect 1260 5666 1268 5730
-rect 1332 5666 1348 5730
-rect 1412 5666 1428 5730
-rect 1492 5666 1508 5730
-rect 1572 5666 1580 5730
-rect 1260 4951 1580 5666
-rect 1260 4715 1302 4951
-rect 1538 4715 1580 4951
-rect 1260 4137 1580 4715
-rect 1260 4102 1302 4137
-rect 1538 4102 1580 4137
-rect 1260 4038 1268 4102
-rect 1572 4038 1580 4102
-rect 1260 3901 1302 4038
-rect 1538 3901 1580 4038
-rect 1260 3205 1580 3901
-rect 1692 5358 2012 5749
-rect 1692 5122 1734 5358
-rect 1970 5122 2012 5358
-rect 1692 4916 2012 5122
-rect 1692 4852 1700 4916
-rect 1764 4852 1780 4916
-rect 1844 4852 1860 4916
-rect 1924 4852 1940 4916
-rect 2004 4852 2012 4916
-rect 1692 4544 2012 4852
-rect 1692 4308 1734 4544
-rect 1970 4308 2012 4544
-rect 1692 3730 2012 4308
-rect 1692 3494 1734 3730
-rect 1970 3494 2012 3730
-rect 1692 3288 2012 3494
-rect 1692 3224 1700 3288
-rect 1764 3224 1780 3288
-rect 1844 3224 1860 3288
-rect 1924 3224 1940 3288
-rect 2004 3224 2012 3288
-rect 1692 3205 2012 3224
-rect 2124 5730 2444 5749
-rect 2124 5666 2132 5730
-rect 2196 5666 2212 5730
-rect 2276 5666 2292 5730
-rect 2356 5666 2372 5730
-rect 2436 5666 2444 5730
-rect 2124 4951 2444 5666
-rect 2124 4715 2166 4951
-rect 2402 4715 2444 4951
-rect 2124 4137 2444 4715
-rect 2124 4102 2166 4137
-rect 2402 4102 2444 4137
-rect 2124 4038 2132 4102
-rect 2436 4038 2444 4102
-rect 2124 3901 2166 4038
-rect 2402 3901 2444 4038
-rect 2124 3205 2444 3901
-rect 2556 5358 2876 5749
-rect 2556 5122 2598 5358
-rect 2834 5122 2876 5358
-rect 2556 4916 2876 5122
-rect 2556 4852 2564 4916
-rect 2628 4852 2644 4916
-rect 2708 4852 2724 4916
-rect 2788 4852 2804 4916
-rect 2868 4852 2876 4916
-rect 2556 4544 2876 4852
-rect 2556 4308 2598 4544
-rect 2834 4308 2876 4544
-rect 2556 3730 2876 4308
-rect 2556 3494 2598 3730
-rect 2834 3494 2876 3730
-rect 2556 3288 2876 3494
-rect 2556 3224 2564 3288
-rect 2628 3224 2644 3288
-rect 2708 3224 2724 3288
-rect 2788 3224 2804 3288
-rect 2868 3224 2876 3288
-rect 2556 3205 2876 3224
-<< via4 >>
-rect 870 5122 1106 5358
-rect 870 4308 1106 4544
-rect 870 3494 1106 3730
-rect 1302 4715 1538 4951
-rect 1302 4102 1538 4137
-rect 1302 4038 1332 4102
-rect 1332 4038 1348 4102
-rect 1348 4038 1412 4102
-rect 1412 4038 1428 4102
-rect 1428 4038 1492 4102
-rect 1492 4038 1508 4102
-rect 1508 4038 1538 4102
-rect 1302 3901 1538 4038
-rect 1734 5122 1970 5358
-rect 1734 4308 1970 4544
-rect 1734 3494 1970 3730
-rect 2166 4715 2402 4951
-rect 2166 4102 2402 4137
-rect 2166 4038 2196 4102
-rect 2196 4038 2212 4102
-rect 2212 4038 2276 4102
-rect 2276 4038 2292 4102
-rect 2292 4038 2356 4102
-rect 2356 4038 2372 4102
-rect 2372 4038 2402 4102
-rect 2166 3901 2402 4038
-rect 2598 5122 2834 5358
-rect 2598 4308 2834 4544
-rect 2598 3494 2834 3730
-<< metal5 >>
-rect 556 5358 3148 5400
-rect 556 5122 870 5358
-rect 1106 5122 1734 5358
-rect 1970 5122 2598 5358
-rect 2834 5122 3148 5358
-rect 556 5080 3148 5122
-rect 556 4951 3148 4993
-rect 556 4715 1302 4951
-rect 1538 4715 2166 4951
-rect 2402 4715 3148 4951
-rect 556 4673 3148 4715
-rect 556 4544 3148 4586
-rect 556 4308 870 4544
-rect 1106 4308 1734 4544
-rect 1970 4308 2598 4544
-rect 2834 4308 3148 4544
-rect 556 4266 3148 4308
-rect 556 4137 3148 4179
-rect 556 3901 1302 4137
-rect 1538 3901 2166 4137
-rect 2402 3901 3148 4137
-rect 556 3859 3148 3901
-rect 556 3730 3148 3772
-rect 556 3494 870 3730
-rect 1106 3494 1734 3730
-rect 1970 3494 2598 3730
-rect 2834 3494 3148 3730
-rect 556 3452 3148 3494
-use sky130_fd_sc_hvl__decap_4  FILLER_1_0
-timestamp 1605064460
-transform 1 0 556 0 1 4070
-box -66 -23 450 897
-use sky130_fd_sc_hvl__decap_8  FILLER_0_12
-timestamp 1605064460
-transform 1 0 1708 0 -1 4070
-box -66 -23 834 897
-use sky130_fd_sc_hvl__fill_1  FILLER_0_6
-timestamp 1605064460
-transform 1 0 1132 0 -1 4070
-box -66 -23 162 897
-use sky130_fd_sc_hvl__fill_2  FILLER_0_4
-timestamp 1605064460
-transform 1 0 940 0 -1 4070
-box -66 -23 258 897
-use sky130_fd_sc_hvl__decap_4  FILLER_0_0
-timestamp 1605064460
-transform 1 0 556 0 -1 4070
-box -66 -23 450 897
-use sky130_fd_sc_hvl__schmittbuf_1  hystbuf1
-timestamp 1605064460
-transform 1 0 940 0 1 4070
-box -66 -23 1122 897
-use sky130_fd_sc_hvl__conb_1  _1_
-timestamp 1605064460
-transform 1 0 1228 0 -1 4070
-box -66 -23 546 897
-use sky130_fd_sc_hvl__decap_4  FILLER_1_23
-timestamp 1605064460
-transform 1 0 2764 0 1 4070
-box -66 -23 450 897
-use sky130_fd_sc_hvl__decap_8  FILLER_1_15
-timestamp 1605064460
-transform 1 0 1996 0 1 4070
-box -66 -23 834 897
-use sky130_fd_sc_hvl__fill_2  FILLER_0_24
-timestamp 1605064460
-transform 1 0 2860 0 -1 4070
-box -66 -23 258 897
-use sky130_fd_sc_hvl__decap_4  FILLER_0_20
-timestamp 1605064460
-transform 1 0 2476 0 -1 4070
-box -66 -23 450 897
-use sky130_fd_sc_hvl__fill_1  FILLER_0_26
-timestamp 1605064460
-transform 1 0 3052 0 -1 4070
-box -66 -23 162 897
-use sky130_fd_sc_hvl__decap_4  FILLER_2_0
-timestamp 1605064460
-transform 1 0 556 0 -1 5698
-box -66 -23 450 897
-use sky130_fd_sc_hvl__schmittbuf_1  hystbuf2
-timestamp 1605064460
-transform 1 0 940 0 -1 5698
-box -66 -23 1122 897
-use sky130_fd_sc_hvl__decap_4  FILLER_2_23
-timestamp 1605064460
-transform 1 0 2764 0 -1 5698
-box -66 -23 450 897
-use sky130_fd_sc_hvl__decap_8  FILLER_2_15
-timestamp 1605064460
-transform 1 0 1996 0 -1 5698
-box -66 -23 834 897
-<< labels >>
-rlabel metal2 s 768 8364 824 9164 4 porb_h
-port 1 nsew
-rlabel metal2 s 0 0 56 800 4 vdd3v3
-port 2 nsew
-rlabel metal3 s 3560 3862 4360 3982 4 vss
-port 3 nsew
-rlabel metal5 s 556 3452 3148 3772 4 VPWR
-port 4 nsew
-rlabel metal5 s 556 3859 3148 4179 4 VGND
-port 5 nsew
-<< properties >>
-string FIXED_BBOX 0 0 4360 9164
-<< end >>

diff --git a/openlane/simple_por/runs/simple_por/results/magic/simple_por.ext b/openlane/simple_por/runs/simple_por/results/magic/simple_por.ext
deleted file mode 100644
index 262f923..0000000
--- a/openlane/simple_por/runs/simple_por/results/magic/simple_por.ext
+++ /dev/null

@@ -1,166 +0,0 @@
-timestamp 1605064459
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-use sky130_fd_sc_hvl__decap_4 FILLER_2_23 1 0 3360 0 -1 5698
-use sky130_fd_sc_hvl__decap_8 FILLER_2_15 1 0 2592 0 -1 5698
-use sky130_fd_sc_hvl__decap_4 FILLER_2_0 1 0 1152 0 -1 5698
-use sky130_fd_sc_hvl__decap_4 FILLER_1_23 1 0 3360 0 1 4070
-use sky130_fd_sc_hvl__decap_8 FILLER_1_15 1 0 2592 0 1 4070
-use sky130_fd_sc_hvl__decap_4 FILLER_1_0 1 0 1152 0 1 4070
-use sky130_fd_sc_hvl__fill_1 FILLER_0_26 1 0 3648 0 -1 4070
-use sky130_fd_sc_hvl__fill_2 FILLER_0_24 1 0 3456 0 -1 4070
-use sky130_fd_sc_hvl__decap_4 FILLER_0_20 1 0 3072 0 -1 4070
-use sky130_fd_sc_hvl__decap_8 FILLER_0_12 1 0 2304 0 -1 4070
-use sky130_fd_sc_hvl__fill_1 FILLER_0_6 1 0 1728 0 -1 4070
-use sky130_fd_sc_hvl__fill_2 FILLER_0_4 1 0 1536 0 -1 4070
-use sky130_fd_sc_hvl__decap_4 FILLER_0_0 1 0 1152 0 -1 4070
-use sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 1 0 1536 0 -1 5698
-use sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 1 0 1536 0 1 4070
-use sky130_fd_sc_hvl__conb_1 _1_ 1 0 1824 0 -1 4070
-port "vss" 2 4156 3862 4956 3982 m3
-port "vdd3v3" 1 596 0 652 800 m2
-port "VPWR" 3 1152 3452 3744 3772 m5
-port "VGND" 4 1152 3859 3744 4179 m5
-port "porb_h" 0 1364 8364 1420 9164 m2
-node "vss" 0 0 4156 3862 m3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "vdd3v3" 0 0 596 0 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "VPWR" 0 0 1152 3452 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "VGND" 0 0 1152 3859 m5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_2047_3868#" 0 0 2047 3868 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_2143_5274#" 0 0 2143 5274 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "porb_h" 0 0 1364 8364 m2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_23/li_0_n17#" "FILLER_2_15/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_23/VPWR" "FILLER_2_23/VPB" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_23/VPB" "FILLER_2_15/VPWR"
-merge "FILLER_2_15/VPWR" "FILLER_2_15/VPB"
-merge "FILLER_2_15/VPB" "FILLER_1_23/VPWR"
-merge "FILLER_1_23/VPWR" "FILLER_1_23/VPB"
-merge "FILLER_1_23/VPB" "FILLER_1_15/VPWR"
-merge "FILLER_1_15/VPWR" "FILLER_1_15/VPB"
-merge "FILLER_1_15/VPB" "FILLER_2_0/VPWR"
-merge "FILLER_2_0/VPWR" "FILLER_2_0/VPB"
-merge "FILLER_2_0/VPB" "hystbuf2/VPWR"
-merge "hystbuf2/VPWR" "hystbuf2/VPB"
-merge "hystbuf2/VPB" "FILLER_1_0/VPWR"
-merge "FILLER_1_0/VPWR" "FILLER_1_0/VPB"
-merge "FILLER_1_0/VPB" "hystbuf1/VPWR"
-merge "hystbuf1/VPWR" "hystbuf1/VPB"
-merge "hystbuf1/VPB" "FILLER_0_26/VPWR"
-merge "FILLER_0_26/VPWR" "FILLER_0_26/VPB"
-merge "FILLER_0_26/VPB" "FILLER_0_24/VPWR"
-merge "FILLER_0_24/VPWR" "FILLER_0_24/VPB"
-merge "FILLER_0_24/VPB" "FILLER_0_20/VPWR"
-merge "FILLER_0_20/VPWR" "FILLER_0_20/VPB"
-merge "FILLER_0_20/VPB" "FILLER_0_12/VPWR"
-merge "FILLER_0_12/VPWR" "FILLER_0_12/VPB"
-merge "FILLER_0_12/VPB" "FILLER_0_6/VPWR"
-merge "FILLER_0_6/VPWR" "FILLER_0_6/VPB"
-merge "FILLER_0_6/VPB" "FILLER_0_4/VPWR"
-merge "FILLER_0_4/VPWR" "FILLER_0_4/VPB"
-merge "FILLER_0_4/VPB" "FILLER_0_0/VPWR"
-merge "FILLER_0_0/VPWR" "FILLER_0_0/VPB"
-merge "FILLER_0_0/VPB" "_1_/VPWR"
-merge "_1_/VPWR" "_1_/VPB"
-merge "_1_/VPB" "VPWR"
-merge "FILLER_2_23/VNB" "FILLER_2_15/VNB" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_15/VNB" "FILLER_2_0/VNB"
-merge "FILLER_2_0/VNB" "FILLER_2_23/VGND"
-merge "FILLER_2_23/VGND" "FILLER_2_15/VGND"
-merge "FILLER_2_15/VGND" "FILLER_2_0/VGND"
-merge "FILLER_2_0/VGND" "hystbuf2/VGND"
-merge "hystbuf2/VGND" "hystbuf2/VNB"
-merge "hystbuf2/VNB" "FILLER_0_26/VGND"
-merge "FILLER_0_26/VGND" "FILLER_0_26/VNB"
-merge "FILLER_0_26/VNB" "FILLER_0_24/VGND"
-merge "FILLER_0_24/VGND" "FILLER_0_24/VNB"
-merge "FILLER_0_24/VNB" "FILLER_1_23/VGND"
-merge "FILLER_1_23/VGND" "FILLER_1_23/VNB"
-merge "FILLER_1_23/VNB" "FILLER_1_15/VGND"
-merge "FILLER_1_15/VGND" "FILLER_1_15/VNB"
-merge "FILLER_1_15/VNB" "FILLER_0_20/VGND"
-merge "FILLER_0_20/VGND" "FILLER_0_20/VNB"
-merge "FILLER_0_20/VNB" "FILLER_0_12/VGND"
-merge "FILLER_0_12/VGND" "FILLER_0_12/VNB"
-merge "FILLER_0_12/VNB" "FILLER_1_0/VGND"
-merge "FILLER_1_0/VGND" "FILLER_1_0/VNB"
-merge "FILLER_1_0/VNB" "FILLER_0_6/VGND"
-merge "FILLER_0_6/VGND" "FILLER_0_6/VNB"
-merge "FILLER_0_6/VNB" "FILLER_0_4/VGND"
-merge "FILLER_0_4/VGND" "FILLER_0_4/VNB"
-merge "FILLER_0_4/VNB" "FILLER_0_0/VGND"
-merge "FILLER_0_0/VGND" "FILLER_0_0/VNB"
-merge "FILLER_0_0/VNB" "hystbuf1/VGND"
-merge "hystbuf1/VGND" "hystbuf1/VNB"
-merge "hystbuf1/VNB" "_1_/VGND"
-merge "_1_/VGND" "_1_/VNB"
-merge "_1_/VNB" "VGND"
-merge "FILLER_2_15/li_353_797#" "FILLER_1_15/li_353_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "hystbuf2/X" "porb_h" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_23/VSUBS" "FILLER_2_15/VSUBS" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_15/VSUBS" "FILLER_2_0/VSUBS"
-merge "FILLER_2_0/VSUBS" "hystbuf2/VSUBS"
-merge "hystbuf2/VSUBS" "FILLER_0_26/VSUBS"
-merge "FILLER_0_26/VSUBS" "FILLER_0_24/VSUBS"
-merge "FILLER_0_24/VSUBS" "FILLER_1_23/VSUBS"
-merge "FILLER_1_23/VSUBS" "FILLER_1_15/VSUBS"
-merge "FILLER_1_15/VSUBS" "FILLER_0_20/VSUBS"
-merge "FILLER_0_20/VSUBS" "FILLER_0_12/VSUBS"
-merge "FILLER_0_12/VSUBS" "FILLER_1_0/VSUBS"
-merge "FILLER_1_0/VSUBS" "FILLER_0_6/VSUBS"
-merge "FILLER_0_6/VSUBS" "FILLER_0_4/VSUBS"
-merge "FILLER_0_4/VSUBS" "FILLER_0_0/VSUBS"
-merge "FILLER_0_0/VSUBS" "hystbuf1/VSUBS"
-merge "hystbuf1/VSUBS" "_1_/VSUBS"
-merge "_1_/VSUBS" "VSUBS"
-merge "FILLER_1_23/li_257_n17#" "FILLER_0_24/li_161_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_15/li_545_797#" "FILLER_1_15/li_545_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_23/li_65_797#" "FILLER_1_23/li_65_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_15/li_545_n17#" "FILLER_0_20/li_65_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "hystbuf2/A" "hystbuf1/X" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "hystbuf1/X" "li_2143_5274#"
-merge "FILLER_2_0/li_0_797#" "FILLER_1_0/li_0_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "hystbuf1/A" "_1_/LO" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "_1_/LO" "li_2047_3868#"
-merge "FILLER_2_23/li_257_797#" "FILLER_1_23/li_257_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_23/li_65_n17#" "FILLER_0_24/li_0_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_0_24/li_0_n17#" "FILLER_0_20/li_353_n17#"
-merge "FILLER_1_15/li_641_n17#" "FILLER_0_20/li_161_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_0/li_0_n17#" "FILLER_0_0/li_0_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_0/li_257_797#" "FILLER_1_0/li_257_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_0/li_161_797#" "FILLER_1_0/li_161_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_0_20/li_0_797#" "FILLER_0_12/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_0_4/li_0_797#" "FILLER_0_0/li_353_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_0/li_161_n17#" "FILLER_0_0/li_161_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_15/li_449_n17#" "FILLER_0_20/li_0_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_0_20/li_0_n17#" "FILLER_0_12/li_737_n17#"
-merge "FILLER_2_15/li_641_797#" "FILLER_1_15/li_641_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_0/li_353_n17#" "FILLER_0_4/li_0_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_0_4/li_0_n17#" "FILLER_0_0/li_353_n17#"
-merge "FILLER_1_15/li_0_n17#" "FILLER_0_12/li_257_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_15/li_161_797#" "FILLER_1_15/li_161_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_23/li_353_797#" "FILLER_1_23/li_353_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_0_12/li_0_797#" "_1_/li_449_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_15/li_353_n17#" "FILLER_0_12/li_641_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_0_24/li_0_797#" "FILLER_0_20/li_353_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_15/li_449_797#" "FILLER_1_15/li_449_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_15/li_0_797#" "FILLER_1_15/li_0_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_23/li_161_n17#" "FILLER_0_24/li_65_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_0/li_65_n17#" "FILLER_0_0/li_65_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_15/li_257_n17#" "FILLER_0_12/li_545_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_23/li_0_n17#" "FILLER_1_15/li_737_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_15/li_737_n17#" "FILLER_0_20/li_257_n17#"
-merge "FILLER_2_23/li_161_797#" "FILLER_1_23/li_161_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_15/li_161_n17#" "FILLER_0_12/li_449_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_0/li_257_n17#" "FILLER_0_0/li_257_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_23/li_0_797#" "FILLER_2_15/li_737_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_15/li_737_797#" "FILLER_1_23/li_0_797#"
-merge "FILLER_1_23/li_0_797#" "FILLER_1_15/li_737_797#"
-merge "FILLER_2_15/li_65_797#" "FILLER_1_15/li_65_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_0/li_353_797#" "FILLER_1_0/li_353_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_0/li_65_797#" "FILLER_1_0/li_65_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_2_15/li_257_797#" "FILLER_1_15/li_257_797#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-merge "FILLER_1_15/li_65_n17#" "FILLER_0_12/li_353_n17#" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

diff --git a/openlane/simple_por/runs/simple_por/results/magic/simple_por.gds b/openlane/simple_por/runs/simple_por/results/magic/simple_por.gds
deleted file mode 100644
index ce432ec..0000000
--- a/openlane/simple_por/runs/simple_por/results/magic/simple_por.gds
+++ /dev/null
Binary files differ

diff --git a/openlane/simple_por/runs/simple_por/results/magic/simple_por.lef b/openlane/simple_por/runs/simple_por/results/magic/simple_por.lef
deleted file mode 100644
index 7c61a2d..0000000
--- a/openlane/simple_por/runs/simple_por/results/magic/simple_por.lef
+++ /dev/null

@@ -1,64 +0,0 @@
-VERSION 5.7 ;
-  NOWIREEXTENSIONATPIN ON ;
-  DIVIDERCHAR "/" ;
-  BUSBITCHARS "[]" ;
-MACRO simple_por
-  CLASS BLOCK ;
-  FOREIGN simple_por ;
-  ORIGIN 0.000 0.000 ;
-  SIZE 21.800 BY 45.820 ;
-  PIN porb_h
-    DIRECTION OUTPUT TRISTATE ;
-    PORT
-      LAYER met2 ;
-        RECT 3.840 41.820 4.120 45.820 ;
-    END
-  END porb_h
-  PIN vdd3v3
-    DIRECTION INPUT ;
-    PORT
-      LAYER met2 ;
-        RECT 0.000 0.000 0.280 4.000 ;
-    END
-  END vdd3v3
-  PIN vss
-    DIRECTION INPUT ;
-    PORT
-      LAYER met3 ;
-        RECT 17.800 19.310 21.800 19.910 ;
-    END
-  END vss
-  PIN VPWR
-    DIRECTION INPUT ;
-    USE POWER ;
-    PORT
-      LAYER met5 ;
-        RECT 2.780 17.260 15.740 18.860 ;
-    END
-  END VPWR
-  PIN VGND
-    DIRECTION INPUT ;
-    USE GROUND ;
-    PORT
-      LAYER met5 ;
-        RECT 2.780 19.295 15.740 20.895 ;
-    END
-  END VGND
-  OBS
-      LAYER li1 ;
-        RECT 2.780 16.195 15.740 28.575 ;
-      LAYER met1 ;
-        RECT 2.780 16.025 15.740 28.745 ;
-      LAYER met2 ;
-        RECT 4.400 41.540 14.320 41.820 ;
-        RECT 3.850 16.025 14.320 41.540 ;
-      LAYER met3 ;
-        RECT 4.140 16.115 14.380 28.655 ;
-      LAYER met4 ;
-        RECT 4.140 16.025 14.380 28.745 ;
-      LAYER met5 ;
-        RECT 2.780 22.495 15.740 27.000 ;
-  END
-END simple_por
-END LIBRARY
-

diff --git a/openlane/simple_por/runs/simple_por/results/magic/simple_por.mag b/openlane/simple_por/runs/simple_por/results/magic/simple_por.mag
deleted file mode 100644
index 2c8ff09..0000000
--- a/openlane/simple_por/runs/simple_por/results/magic/simple_por.mag
+++ /dev/null

@@ -1,951 +0,0 @@
-magic
-tech sky130A
-magscale 1 2
-timestamp 1605064459
-<< viali >>
-rect 1931 5496 1965 5530
-rect 1547 5274 1581 5308
-rect 1931 4682 1965 4716
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-<< metal1 >>
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-rect 1046 3230 1058 3282
-rect 1110 3230 1730 3282
-rect 1782 3230 1794 3282
-rect 1846 3230 1858 3282
-rect 1910 3230 1922 3282
-rect 1974 3230 2594 3282
-rect 2646 3230 2658 3282
-rect 2710 3230 2722 3282
-rect 2774 3230 2786 3282
-rect 2838 3230 3148 3282
-rect 556 3205 3148 3230
-<< via1 >>
-rect 1298 5672 1350 5724
-rect 1362 5672 1414 5724
-rect 1426 5672 1478 5724
-rect 1490 5672 1542 5724
-rect 2162 5672 2214 5724
-rect 2226 5672 2278 5724
-rect 2290 5672 2342 5724
-rect 2354 5672 2406 5724
-rect 770 5487 822 5539
-rect 1538 5308 1590 5317
-rect 1538 5274 1547 5308
-rect 1547 5274 1581 5308
-rect 1581 5274 1590 5308
-rect 1538 5265 1590 5274
-rect 866 4858 918 4910
-rect 930 4858 982 4910
-rect 994 4858 1046 4910
-rect 1058 4858 1110 4910
-rect 1730 4858 1782 4910
-rect 1794 4858 1846 4910
-rect 1858 4858 1910 4910
-rect 1922 4858 1974 4910
-rect 2594 4858 2646 4910
-rect 2658 4858 2710 4910
-rect 2722 4858 2774 4910
-rect 2786 4858 2838 4910
-rect 1538 4673 1590 4725
-rect 1634 4451 1686 4503
-rect 1298 4044 1350 4096
-rect 1362 4044 1414 4096
-rect 1426 4044 1478 4096
-rect 1490 4044 1542 4096
-rect 2162 4044 2214 4096
-rect 2226 4044 2278 4096
-rect 2290 4044 2342 4096
-rect 2354 4044 2406 4096
-rect 1634 3859 1686 3911
-rect 866 3230 918 3282
-rect 930 3230 982 3282
-rect 994 3230 1046 3282
-rect 1058 3230 1110 3282
-rect 1730 3230 1782 3282
-rect 1794 3230 1846 3282
-rect 1858 3230 1910 3282
-rect 1922 3230 1974 3282
-rect 2594 3230 2646 3282
-rect 2658 3230 2710 3282
-rect 2722 3230 2774 3282
-rect 2786 3230 2838 3282
-<< metal2 >>
-rect 768 8364 824 9164
-rect 782 5545 810 8364
-rect 1272 5726 1568 5749
-rect 1328 5724 1352 5726
-rect 1408 5724 1432 5726
-rect 1488 5724 1512 5726
-rect 1350 5672 1352 5724
-rect 1414 5672 1426 5724
-rect 1488 5672 1490 5724
-rect 1328 5670 1352 5672
-rect 1408 5670 1432 5672
-rect 1488 5670 1512 5672
-rect 1272 5647 1568 5670
-rect 2136 5726 2432 5749
-rect 2192 5724 2216 5726
-rect 2272 5724 2296 5726
-rect 2352 5724 2376 5726
-rect 2214 5672 2216 5724
-rect 2278 5672 2290 5724
-rect 2352 5672 2354 5724
-rect 2192 5670 2216 5672
-rect 2272 5670 2296 5672
-rect 2352 5670 2376 5672
-rect 2136 5647 2432 5670
-rect 770 5539 822 5545
-rect 770 5481 822 5487
-rect 1538 5317 1590 5323
-rect 1538 5259 1590 5265
-rect 840 4912 1136 4935
-rect 896 4910 920 4912
-rect 976 4910 1000 4912
-rect 1056 4910 1080 4912
-rect 918 4858 920 4910
-rect 982 4858 994 4910
-rect 1056 4858 1058 4910
-rect 896 4856 920 4858
-rect 976 4856 1000 4858
-rect 1056 4856 1080 4858
-rect 840 4833 1136 4856
-rect 1550 4731 1578 5259
-rect 1704 4912 2000 4935
-rect 1760 4910 1784 4912
-rect 1840 4910 1864 4912
-rect 1920 4910 1944 4912
-rect 1782 4858 1784 4910
-rect 1846 4858 1858 4910
-rect 1920 4858 1922 4910
-rect 1760 4856 1784 4858
-rect 1840 4856 1864 4858
-rect 1920 4856 1944 4858
-rect 1704 4833 2000 4856
-rect 2568 4912 2864 4935
-rect 2624 4910 2648 4912
-rect 2704 4910 2728 4912
-rect 2784 4910 2808 4912
-rect 2646 4858 2648 4910
-rect 2710 4858 2722 4910
-rect 2784 4858 2786 4910
-rect 2624 4856 2648 4858
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-rect 1538 4725 1590 4731
-rect 1538 4667 1590 4673
-rect 1634 4503 1686 4509
-rect 1634 4445 1686 4451
-rect 1272 4098 1568 4121
-rect 1328 4096 1352 4098
-rect 1408 4096 1432 4098
-rect 1488 4096 1512 4098
-rect 1350 4044 1352 4096
-rect 1414 4044 1426 4096
-rect 1488 4044 1490 4096
-rect 1328 4042 1352 4044
-rect 1408 4042 1432 4044
-rect 1488 4042 1512 4044
-rect 1272 4019 1568 4042
-rect 1646 3917 1674 4445
-rect 2136 4098 2432 4121
-rect 2192 4096 2216 4098
-rect 2272 4096 2296 4098
-rect 2352 4096 2376 4098
-rect 2214 4044 2216 4096
-rect 2278 4044 2290 4096
-rect 2352 4044 2354 4096
-rect 2192 4042 2216 4044
-rect 2272 4042 2296 4044
-rect 2352 4042 2376 4044
-rect 2136 4019 2432 4042
-rect 1634 3911 1686 3917
-rect 1634 3853 1686 3859
-rect 840 3284 1136 3307
-rect 896 3282 920 3284
-rect 976 3282 1000 3284
-rect 1056 3282 1080 3284
-rect 918 3230 920 3282
-rect 982 3230 994 3282
-rect 1056 3230 1058 3282
-rect 896 3228 920 3230
-rect 976 3228 1000 3230
-rect 1056 3228 1080 3230
-rect 840 3205 1136 3228
-rect 1704 3284 2000 3307
-rect 1760 3282 1784 3284
-rect 1840 3282 1864 3284
-rect 1920 3282 1944 3284
-rect 1782 3230 1784 3282
-rect 1846 3230 1858 3282
-rect 1920 3230 1922 3282
-rect 1760 3228 1784 3230
-rect 1840 3228 1864 3230
-rect 1920 3228 1944 3230
-rect 1704 3205 2000 3228
-rect 2568 3284 2864 3307
-rect 2624 3282 2648 3284
-rect 2704 3282 2728 3284
-rect 2784 3282 2808 3284
-rect 2646 3230 2648 3282
-rect 2710 3230 2722 3282
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-rect 2624 3228 2648 3230
-rect 2704 3228 2728 3230
-rect 2784 3228 2808 3230
-rect 2568 3205 2864 3228
-rect 0 0 56 800
-<< via2 >>
-rect 1272 5724 1328 5726
-rect 1352 5724 1408 5726
-rect 1432 5724 1488 5726
-rect 1512 5724 1568 5726
-rect 1272 5672 1298 5724
-rect 1298 5672 1328 5724
-rect 1352 5672 1362 5724
-rect 1362 5672 1408 5724
-rect 1432 5672 1478 5724
-rect 1478 5672 1488 5724
-rect 1512 5672 1542 5724
-rect 1542 5672 1568 5724
-rect 1272 5670 1328 5672
-rect 1352 5670 1408 5672
-rect 1432 5670 1488 5672
-rect 1512 5670 1568 5672
-rect 2136 5724 2192 5726
-rect 2216 5724 2272 5726
-rect 2296 5724 2352 5726
-rect 2376 5724 2432 5726
-rect 2136 5672 2162 5724
-rect 2162 5672 2192 5724
-rect 2216 5672 2226 5724
-rect 2226 5672 2272 5724
-rect 2296 5672 2342 5724
-rect 2342 5672 2352 5724
-rect 2376 5672 2406 5724
-rect 2406 5672 2432 5724
-rect 2136 5670 2192 5672
-rect 2216 5670 2272 5672
-rect 2296 5670 2352 5672
-rect 2376 5670 2432 5672
-rect 840 4910 896 4912
-rect 920 4910 976 4912
-rect 1000 4910 1056 4912
-rect 1080 4910 1136 4912
-rect 840 4858 866 4910
-rect 866 4858 896 4910
-rect 920 4858 930 4910
-rect 930 4858 976 4910
-rect 1000 4858 1046 4910
-rect 1046 4858 1056 4910
-rect 1080 4858 1110 4910
-rect 1110 4858 1136 4910
-rect 840 4856 896 4858
-rect 920 4856 976 4858
-rect 1000 4856 1056 4858
-rect 1080 4856 1136 4858
-rect 1704 4910 1760 4912
-rect 1784 4910 1840 4912
-rect 1864 4910 1920 4912
-rect 1944 4910 2000 4912
-rect 1704 4858 1730 4910
-rect 1730 4858 1760 4910
-rect 1784 4858 1794 4910
-rect 1794 4858 1840 4910
-rect 1864 4858 1910 4910
-rect 1910 4858 1920 4910
-rect 1944 4858 1974 4910
-rect 1974 4858 2000 4910
-rect 1704 4856 1760 4858
-rect 1784 4856 1840 4858
-rect 1864 4856 1920 4858
-rect 1944 4856 2000 4858
-rect 2568 4910 2624 4912
-rect 2648 4910 2704 4912
-rect 2728 4910 2784 4912
-rect 2808 4910 2864 4912
-rect 2568 4858 2594 4910
-rect 2594 4858 2624 4910
-rect 2648 4858 2658 4910
-rect 2658 4858 2704 4910
-rect 2728 4858 2774 4910
-rect 2774 4858 2784 4910
-rect 2808 4858 2838 4910
-rect 2838 4858 2864 4910
-rect 2568 4856 2624 4858
-rect 2648 4856 2704 4858
-rect 2728 4856 2784 4858
-rect 2808 4856 2864 4858
-rect 1272 4096 1328 4098
-rect 1352 4096 1408 4098
-rect 1432 4096 1488 4098
-rect 1512 4096 1568 4098
-rect 1272 4044 1298 4096
-rect 1298 4044 1328 4096
-rect 1352 4044 1362 4096
-rect 1362 4044 1408 4096
-rect 1432 4044 1478 4096
-rect 1478 4044 1488 4096
-rect 1512 4044 1542 4096
-rect 1542 4044 1568 4096
-rect 1272 4042 1328 4044
-rect 1352 4042 1408 4044
-rect 1432 4042 1488 4044
-rect 1512 4042 1568 4044
-rect 2136 4096 2192 4098
-rect 2216 4096 2272 4098
-rect 2296 4096 2352 4098
-rect 2376 4096 2432 4098
-rect 2136 4044 2162 4096
-rect 2162 4044 2192 4096
-rect 2216 4044 2226 4096
-rect 2226 4044 2272 4096
-rect 2296 4044 2342 4096
-rect 2342 4044 2352 4096
-rect 2376 4044 2406 4096
-rect 2406 4044 2432 4096
-rect 2136 4042 2192 4044
-rect 2216 4042 2272 4044
-rect 2296 4042 2352 4044
-rect 2376 4042 2432 4044
-rect 840 3282 896 3284
-rect 920 3282 976 3284
-rect 1000 3282 1056 3284
-rect 1080 3282 1136 3284
-rect 840 3230 866 3282
-rect 866 3230 896 3282
-rect 920 3230 930 3282
-rect 930 3230 976 3282
-rect 1000 3230 1046 3282
-rect 1046 3230 1056 3282
-rect 1080 3230 1110 3282
-rect 1110 3230 1136 3282
-rect 840 3228 896 3230
-rect 920 3228 976 3230
-rect 1000 3228 1056 3230
-rect 1080 3228 1136 3230
-rect 1704 3282 1760 3284
-rect 1784 3282 1840 3284
-rect 1864 3282 1920 3284
-rect 1944 3282 2000 3284
-rect 1704 3230 1730 3282
-rect 1730 3230 1760 3282
-rect 1784 3230 1794 3282
-rect 1794 3230 1840 3282
-rect 1864 3230 1910 3282
-rect 1910 3230 1920 3282
-rect 1944 3230 1974 3282
-rect 1974 3230 2000 3282
-rect 1704 3228 1760 3230
-rect 1784 3228 1840 3230
-rect 1864 3228 1920 3230
-rect 1944 3228 2000 3230
-rect 2568 3282 2624 3284
-rect 2648 3282 2704 3284
-rect 2728 3282 2784 3284
-rect 2808 3282 2864 3284
-rect 2568 3230 2594 3282
-rect 2594 3230 2624 3282
-rect 2648 3230 2658 3282
-rect 2658 3230 2704 3282
-rect 2728 3230 2774 3282
-rect 2774 3230 2784 3282
-rect 2808 3230 2838 3282
-rect 2838 3230 2864 3282
-rect 2568 3228 2624 3230
-rect 2648 3228 2704 3230
-rect 2728 3228 2784 3230
-rect 2808 3228 2864 3230
-<< metal3 >>
-rect 1260 5730 1580 5731
-rect 1260 5666 1268 5730
-rect 1332 5666 1348 5730
-rect 1412 5666 1428 5730
-rect 1492 5666 1508 5730
-rect 1572 5666 1580 5730
-rect 1260 5665 1580 5666
-rect 2124 5730 2444 5731
-rect 2124 5666 2132 5730
-rect 2196 5666 2212 5730
-rect 2276 5666 2292 5730
-rect 2356 5666 2372 5730
-rect 2436 5666 2444 5730
-rect 2124 5665 2444 5666
-rect 828 4916 1148 4917
-rect 828 4852 836 4916
-rect 900 4852 916 4916
-rect 980 4852 996 4916
-rect 1060 4852 1076 4916
-rect 1140 4852 1148 4916
-rect 828 4851 1148 4852
-rect 1692 4916 2012 4917
-rect 1692 4852 1700 4916
-rect 1764 4852 1780 4916
-rect 1844 4852 1860 4916
-rect 1924 4852 1940 4916
-rect 2004 4852 2012 4916
-rect 1692 4851 2012 4852
-rect 2556 4916 2876 4917
-rect 2556 4852 2564 4916
-rect 2628 4852 2644 4916
-rect 2708 4852 2724 4916
-rect 2788 4852 2804 4916
-rect 2868 4852 2876 4916
-rect 2556 4851 2876 4852
-rect 1260 4102 1580 4103
-rect 1260 4038 1268 4102
-rect 1332 4038 1348 4102
-rect 1412 4038 1428 4102
-rect 1492 4038 1508 4102
-rect 1572 4038 1580 4102
-rect 1260 4037 1580 4038
-rect 2124 4102 2444 4103
-rect 2124 4038 2132 4102
-rect 2196 4038 2212 4102
-rect 2276 4038 2292 4102
-rect 2356 4038 2372 4102
-rect 2436 4038 2444 4102
-rect 2124 4037 2444 4038
-rect 3560 3862 4360 3982
-rect 828 3288 1148 3289
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-rect 900 3224 916 3288
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-rect 1140 3224 1148 3288
-rect 828 3223 1148 3224
-rect 1692 3288 2012 3289
-rect 1692 3224 1700 3288
-rect 1764 3224 1780 3288
-rect 1844 3224 1860 3288
-rect 1924 3224 1940 3288
-rect 2004 3224 2012 3288
-rect 1692 3223 2012 3224
-rect 2556 3288 2876 3289
-rect 2556 3224 2564 3288
-rect 2628 3224 2644 3288
-rect 2708 3224 2724 3288
-rect 2788 3224 2804 3288
-rect 2868 3224 2876 3288
-rect 2556 3223 2876 3224
-<< via3 >>
-rect 1268 5726 1332 5730
-rect 1268 5670 1272 5726
-rect 1272 5670 1328 5726
-rect 1328 5670 1332 5726
-rect 1268 5666 1332 5670
-rect 1348 5726 1412 5730
-rect 1348 5670 1352 5726
-rect 1352 5670 1408 5726
-rect 1408 5670 1412 5726
-rect 1348 5666 1412 5670
-rect 1428 5726 1492 5730
-rect 1428 5670 1432 5726
-rect 1432 5670 1488 5726
-rect 1488 5670 1492 5726
-rect 1428 5666 1492 5670
-rect 1508 5726 1572 5730
-rect 1508 5670 1512 5726
-rect 1512 5670 1568 5726
-rect 1568 5670 1572 5726
-rect 1508 5666 1572 5670
-rect 2132 5726 2196 5730
-rect 2132 5670 2136 5726
-rect 2136 5670 2192 5726
-rect 2192 5670 2196 5726
-rect 2132 5666 2196 5670
-rect 2212 5726 2276 5730
-rect 2212 5670 2216 5726
-rect 2216 5670 2272 5726
-rect 2272 5670 2276 5726
-rect 2212 5666 2276 5670
-rect 2292 5726 2356 5730
-rect 2292 5670 2296 5726
-rect 2296 5670 2352 5726
-rect 2352 5670 2356 5726
-rect 2292 5666 2356 5670
-rect 2372 5726 2436 5730
-rect 2372 5670 2376 5726
-rect 2376 5670 2432 5726
-rect 2432 5670 2436 5726
-rect 2372 5666 2436 5670
-rect 836 4912 900 4916
-rect 836 4856 840 4912
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-rect 836 4852 900 4856
-rect 916 4912 980 4916
-rect 916 4856 920 4912
-rect 920 4856 976 4912
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-rect 996 4912 1060 4916
-rect 996 4856 1000 4912
-rect 1000 4856 1056 4912
-rect 1056 4856 1060 4912
-rect 996 4852 1060 4856
-rect 1076 4912 1140 4916
-rect 1076 4856 1080 4912
-rect 1080 4856 1136 4912
-rect 1136 4856 1140 4912
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-rect 1700 4912 1764 4916
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-rect 1780 4912 1844 4916
-rect 1780 4856 1784 4912
-rect 1784 4856 1840 4912
-rect 1840 4856 1844 4912
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-rect 1860 4912 1924 4916
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-rect 1940 4912 2004 4916
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-rect 2564 4912 2628 4916
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-rect 2644 4912 2708 4916
-rect 2644 4856 2648 4912
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-rect 2724 4912 2788 4916
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-rect 2804 4912 2868 4916
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-rect 1268 4098 1332 4102
-rect 1268 4042 1272 4098
-rect 1272 4042 1328 4098
-rect 1328 4042 1332 4098
-rect 1268 4038 1332 4042
-rect 1348 4098 1412 4102
-rect 1348 4042 1352 4098
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-rect 1408 4042 1412 4098
-rect 1348 4038 1412 4042
-rect 1428 4098 1492 4102
-rect 1428 4042 1432 4098
-rect 1432 4042 1488 4098
-rect 1488 4042 1492 4098
-rect 1428 4038 1492 4042
-rect 1508 4098 1572 4102
-rect 1508 4042 1512 4098
-rect 1512 4042 1568 4098
-rect 1568 4042 1572 4098
-rect 1508 4038 1572 4042
-rect 2132 4098 2196 4102
-rect 2132 4042 2136 4098
-rect 2136 4042 2192 4098
-rect 2192 4042 2196 4098
-rect 2132 4038 2196 4042
-rect 2212 4098 2276 4102
-rect 2212 4042 2216 4098
-rect 2216 4042 2272 4098
-rect 2272 4042 2276 4098
-rect 2212 4038 2276 4042
-rect 2292 4098 2356 4102
-rect 2292 4042 2296 4098
-rect 2296 4042 2352 4098
-rect 2352 4042 2356 4098
-rect 2292 4038 2356 4042
-rect 2372 4098 2436 4102
-rect 2372 4042 2376 4098
-rect 2376 4042 2432 4098
-rect 2432 4042 2436 4098
-rect 2372 4038 2436 4042
-rect 836 3284 900 3288
-rect 836 3228 840 3284
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-rect 836 3224 900 3228
-rect 916 3284 980 3288
-rect 916 3228 920 3284
-rect 920 3228 976 3284
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-rect 916 3224 980 3228
-rect 996 3284 1060 3288
-rect 996 3228 1000 3284
-rect 1000 3228 1056 3284
-rect 1056 3228 1060 3284
-rect 996 3224 1060 3228
-rect 1076 3284 1140 3288
-rect 1076 3228 1080 3284
-rect 1080 3228 1136 3284
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-rect 1076 3224 1140 3228
-rect 1700 3284 1764 3288
-rect 1700 3228 1704 3284
-rect 1704 3228 1760 3284
-rect 1760 3228 1764 3284
-rect 1700 3224 1764 3228
-rect 1780 3284 1844 3288
-rect 1780 3228 1784 3284
-rect 1784 3228 1840 3284
-rect 1840 3228 1844 3284
-rect 1780 3224 1844 3228
-rect 1860 3284 1924 3288
-rect 1860 3228 1864 3284
-rect 1864 3228 1920 3284
-rect 1920 3228 1924 3284
-rect 1860 3224 1924 3228
-rect 1940 3284 2004 3288
-rect 1940 3228 1944 3284
-rect 1944 3228 2000 3284
-rect 2000 3228 2004 3284
-rect 1940 3224 2004 3228
-rect 2564 3284 2628 3288
-rect 2564 3228 2568 3284
-rect 2568 3228 2624 3284
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-rect 2644 3284 2708 3288
-rect 2644 3228 2648 3284
-rect 2648 3228 2704 3284
-rect 2704 3228 2708 3284
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-rect 2724 3284 2788 3288
-rect 2724 3228 2728 3284
-rect 2728 3228 2784 3284
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-rect 2724 3224 2788 3228
-rect 2804 3284 2868 3288
-rect 2804 3228 2808 3284
-rect 2808 3228 2864 3284
-rect 2864 3228 2868 3284
-rect 2804 3224 2868 3228
-<< metal4 >>
-rect 828 5358 1148 5749
-rect 828 5122 870 5358
-rect 1106 5122 1148 5358
-rect 828 4916 1148 5122
-rect 828 4852 836 4916
-rect 900 4852 916 4916
-rect 980 4852 996 4916
-rect 1060 4852 1076 4916
-rect 1140 4852 1148 4916
-rect 828 4544 1148 4852
-rect 828 4308 870 4544
-rect 1106 4308 1148 4544
-rect 828 3730 1148 4308
-rect 828 3494 870 3730
-rect 1106 3494 1148 3730
-rect 828 3288 1148 3494
-rect 828 3224 836 3288
-rect 900 3224 916 3288
-rect 980 3224 996 3288
-rect 1060 3224 1076 3288
-rect 1140 3224 1148 3288
-rect 828 3205 1148 3224
-rect 1260 5730 1580 5749
-rect 1260 5666 1268 5730
-rect 1332 5666 1348 5730
-rect 1412 5666 1428 5730
-rect 1492 5666 1508 5730
-rect 1572 5666 1580 5730
-rect 1260 4951 1580 5666
-rect 1260 4715 1302 4951
-rect 1538 4715 1580 4951
-rect 1260 4137 1580 4715
-rect 1260 4102 1302 4137
-rect 1538 4102 1580 4137
-rect 1260 4038 1268 4102
-rect 1572 4038 1580 4102
-rect 1260 3901 1302 4038
-rect 1538 3901 1580 4038
-rect 1260 3205 1580 3901
-rect 1692 5358 2012 5749
-rect 1692 5122 1734 5358
-rect 1970 5122 2012 5358
-rect 1692 4916 2012 5122
-rect 1692 4852 1700 4916
-rect 1764 4852 1780 4916
-rect 1844 4852 1860 4916
-rect 1924 4852 1940 4916
-rect 2004 4852 2012 4916
-rect 1692 4544 2012 4852
-rect 1692 4308 1734 4544
-rect 1970 4308 2012 4544
-rect 1692 3730 2012 4308
-rect 1692 3494 1734 3730
-rect 1970 3494 2012 3730
-rect 1692 3288 2012 3494
-rect 1692 3224 1700 3288
-rect 1764 3224 1780 3288
-rect 1844 3224 1860 3288
-rect 1924 3224 1940 3288
-rect 2004 3224 2012 3288
-rect 1692 3205 2012 3224
-rect 2124 5730 2444 5749
-rect 2124 5666 2132 5730
-rect 2196 5666 2212 5730
-rect 2276 5666 2292 5730
-rect 2356 5666 2372 5730
-rect 2436 5666 2444 5730
-rect 2124 4951 2444 5666
-rect 2124 4715 2166 4951
-rect 2402 4715 2444 4951
-rect 2124 4137 2444 4715
-rect 2124 4102 2166 4137
-rect 2402 4102 2444 4137
-rect 2124 4038 2132 4102
-rect 2436 4038 2444 4102
-rect 2124 3901 2166 4038
-rect 2402 3901 2444 4038
-rect 2124 3205 2444 3901
-rect 2556 5358 2876 5749
-rect 2556 5122 2598 5358
-rect 2834 5122 2876 5358
-rect 2556 4916 2876 5122
-rect 2556 4852 2564 4916
-rect 2628 4852 2644 4916
-rect 2708 4852 2724 4916
-rect 2788 4852 2804 4916
-rect 2868 4852 2876 4916
-rect 2556 4544 2876 4852
-rect 2556 4308 2598 4544
-rect 2834 4308 2876 4544
-rect 2556 3730 2876 4308
-rect 2556 3494 2598 3730
-rect 2834 3494 2876 3730
-rect 2556 3288 2876 3494
-rect 2556 3224 2564 3288
-rect 2628 3224 2644 3288
-rect 2708 3224 2724 3288
-rect 2788 3224 2804 3288
-rect 2868 3224 2876 3288
-rect 2556 3205 2876 3224
-<< via4 >>
-rect 870 5122 1106 5358
-rect 870 4308 1106 4544
-rect 870 3494 1106 3730
-rect 1302 4715 1538 4951
-rect 1302 4102 1538 4137
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-rect 1734 3494 1970 3730
-rect 2166 4715 2402 4951
-rect 2166 4102 2402 4137
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-rect 2276 4038 2292 4102
-rect 2292 4038 2356 4102
-rect 2356 4038 2372 4102
-rect 2372 4038 2402 4102
-rect 2166 3901 2402 4038
-rect 2598 5122 2834 5358
-rect 2598 4308 2834 4544
-rect 2598 3494 2834 3730
-<< metal5 >>
-rect 556 5358 3148 5400
-rect 556 5122 870 5358
-rect 1106 5122 1734 5358
-rect 1970 5122 2598 5358
-rect 2834 5122 3148 5358
-rect 556 5080 3148 5122
-rect 556 4951 3148 4993
-rect 556 4715 1302 4951
-rect 1538 4715 2166 4951
-rect 2402 4715 3148 4951
-rect 556 4673 3148 4715
-rect 556 4544 3148 4586
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-rect 1106 4308 1734 4544
-rect 1970 4308 2598 4544
-rect 2834 4308 3148 4544
-rect 556 4266 3148 4308
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-rect 556 3901 1302 4137
-rect 1538 3901 2166 4137
-rect 2402 3901 3148 4137
-rect 556 3859 3148 3901
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-rect 556 3494 870 3730
-rect 1106 3494 1734 3730
-rect 1970 3494 2598 3730
-rect 2834 3494 3148 3730
-rect 556 3452 3148 3494
-use sky130_fd_sc_hvl__conb_1  _1_ /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag
-timestamp 1604489734
-transform 1 0 1228 0 -1 4070
-box -66 -23 546 897
-use sky130_fd_sc_hvl__schmittbuf_1  hystbuf1 /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag
-timestamp 1604489734
-transform 1 0 940 0 1 4070
-box -66 -23 1122 897
-use sky130_fd_sc_hvl__decap_4  FILLER_0_0 /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag
-timestamp 1604489734
-transform 1 0 556 0 -1 4070
-box -66 -23 450 897
-use sky130_fd_sc_hvl__fill_2  FILLER_0_4 /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag
-timestamp 1604489734
-transform 1 0 940 0 -1 4070
-box -66 -23 258 897
-use sky130_fd_sc_hvl__fill_1  FILLER_0_6 /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag
-timestamp 1604489734
-transform 1 0 1132 0 -1 4070
-box -66 -23 162 897
-use sky130_fd_sc_hvl__decap_8  FILLER_0_12 /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/mag
-timestamp 1604489734
-transform 1 0 1708 0 -1 4070
-box -66 -23 834 897
-use sky130_fd_sc_hvl__decap_4  FILLER_1_0
-timestamp 1604489734
-transform 1 0 556 0 1 4070
-box -66 -23 450 897
-use sky130_fd_sc_hvl__decap_4  FILLER_0_20
-timestamp 1604489734
-transform 1 0 2476 0 -1 4070
-box -66 -23 450 897
-use sky130_fd_sc_hvl__fill_2  FILLER_0_24
-timestamp 1604489734
-transform 1 0 2860 0 -1 4070
-box -66 -23 258 897
-use sky130_fd_sc_hvl__decap_8  FILLER_1_15
-timestamp 1604489734
-transform 1 0 1996 0 1 4070
-box -66 -23 834 897
-use sky130_fd_sc_hvl__decap_4  FILLER_1_23
-timestamp 1604489734
-transform 1 0 2764 0 1 4070
-box -66 -23 450 897
-use sky130_fd_sc_hvl__fill_1  FILLER_0_26
-timestamp 1604489734
-transform 1 0 3052 0 -1 4070
-box -66 -23 162 897
-use sky130_fd_sc_hvl__schmittbuf_1  hystbuf2
-timestamp 1604489734
-transform 1 0 940 0 -1 5698
-box -66 -23 1122 897
-use sky130_fd_sc_hvl__decap_4  FILLER_2_0
-timestamp 1604489734
-transform 1 0 556 0 -1 5698
-box -66 -23 450 897
-use sky130_fd_sc_hvl__decap_8  FILLER_2_15
-timestamp 1604489734
-transform 1 0 1996 0 -1 5698
-box -66 -23 834 897
-use sky130_fd_sc_hvl__decap_4  FILLER_2_23
-timestamp 1604489734
-transform 1 0 2764 0 -1 5698
-box -66 -23 450 897
-<< labels >>
-rlabel metal2 s 768 8364 824 9164 6 porb_h
-port 0 nsew default tristate
-rlabel metal2 s 0 0 56 800 6 vdd3v3
-port 1 nsew default input
-rlabel metal3 s 3560 3862 4360 3982 6 vss
-port 2 nsew default input
-rlabel metal5 s 556 3452 3148 3772 6 VPWR
-port 3 nsew default input
-rlabel metal5 s 556 3859 3148 4179 6 VGND
-port 4 nsew default input
-<< properties >>
-string FIXED_BBOX 0 0 4360 9164
-<< end >>

diff --git a/openlane/simple_por/runs/simple_por/results/magic/simple_por.spice b/openlane/simple_por/runs/simple_por/results/magic/simple_por.spice
deleted file mode 100644
index fd80ca3..0000000
--- a/openlane/simple_por/runs/simple_por/results/magic/simple_por.spice
+++ /dev/null

@@ -1,45 +0,0 @@
-* NGSPICE file created from simple_por.ext - technology: sky130A
-
-* Black-box entry subcircuit for sky130_fd_sc_hvl__fill_2 abstract view
-.subckt sky130_fd_sc_hvl__fill_2 VGND VNB VPB VPWR
-.ends
-
-* Black-box entry subcircuit for sky130_fd_sc_hvl__fill_1 abstract view
-.subckt sky130_fd_sc_hvl__fill_1 VGND VNB VPB VPWR
-.ends
-
-* Black-box entry subcircuit for sky130_fd_sc_hvl__decap_4 abstract view
-.subckt sky130_fd_sc_hvl__decap_4 VGND VNB VPB VPWR
-.ends
-
-* Black-box entry subcircuit for sky130_fd_sc_hvl__schmittbuf_1 abstract view
-.subckt sky130_fd_sc_hvl__schmittbuf_1 A X VGND VNB VPB VPWR
-.ends
-
-* Black-box entry subcircuit for sky130_fd_sc_hvl__decap_8 abstract view
-.subckt sky130_fd_sc_hvl__decap_8 VGND VNB VPB VPWR
-.ends
-
-* Black-box entry subcircuit for sky130_fd_sc_hvl__conb_1 abstract view
-.subckt sky130_fd_sc_hvl__conb_1 HI LO VGND VNB VPB VPWR
-.ends
-
-.subckt simple_por porb_h vdd3v3 vss VPWR VGND
-XFILLER_0_24 VGND VGND VPWR VPWR sky130_fd_sc_hvl__fill_2
-XFILLER_0_26 VGND VGND VPWR VPWR sky130_fd_sc_hvl__fill_1
-XFILLER_1_0 VGND VGND VPWR VPWR sky130_fd_sc_hvl__decap_4
-Xhystbuf1 _1_/LO hystbuf1/X VGND VGND VPWR VPWR sky130_fd_sc_hvl__schmittbuf_1
-Xhystbuf2 hystbuf1/X porb_h VGND VGND VPWR VPWR sky130_fd_sc_hvl__schmittbuf_1
-XFILLER_1_23 VGND VGND VPWR VPWR sky130_fd_sc_hvl__decap_4
-XFILLER_1_15 VGND VGND VPWR VPWR sky130_fd_sc_hvl__decap_8
-XFILLER_2_0 VGND VGND VPWR VPWR sky130_fd_sc_hvl__decap_4
-X_1_ _1_/HI _1_/LO VGND VGND VPWR VPWR sky130_fd_sc_hvl__conb_1
-XFILLER_0_0 VGND VGND VPWR VPWR sky130_fd_sc_hvl__decap_4
-XFILLER_2_23 VGND VGND VPWR VPWR sky130_fd_sc_hvl__decap_4
-XFILLER_0_4 VGND VGND VPWR VPWR sky130_fd_sc_hvl__fill_2
-XFILLER_2_15 VGND VGND VPWR VPWR sky130_fd_sc_hvl__decap_8
-XFILLER_0_6 VGND VGND VPWR VPWR sky130_fd_sc_hvl__fill_1
-XFILLER_0_20 VGND VGND VPWR VPWR sky130_fd_sc_hvl__decap_4
-XFILLER_0_12 VGND VGND VPWR VPWR sky130_fd_sc_hvl__decap_8
-.ends
-

diff --git a/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__conb_1.ext b/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__conb_1.ext
deleted file mode 100644
index fd6d4e0..0000000
--- a/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__conb_1.ext
+++ /dev/null

@@ -1,46 +0,0 @@
-timestamp 1604489738
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-abstract
-port "VNB" 4 0 -23 480 23 m1
-port "VGND" 3 0 51 480 125 m1
-port "LO" 2 207 100 273 300 li
-port "LO" 2 207 300 359 353 li
-port "LO" 2 306 353 359 635 li
-port "LO" 2 306 635 422 763 li
-port "HI" 1 58 86 173 214 li
-port "HI" 1 123 214 173 387 li
-port "HI" 1 123 387 265 437 li
-port "HI" 1 215 437 265 706 li
-port "VPWR" 6 0 689 480 763 m1
-port "VPB" 5 0 791 480 837 m1
-node "li_449_n17#" 0 0 449 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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-node "VNB" 0 0 0 -23 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_0_n17#" 0 0 0 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "VGND" 0 0 0 51 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_307_57#" 0 0 307 57 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "LO" 0 0 306 635 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-equiv "LO" "LO"
-equiv "LO" "LO"
-equiv "LO" "LO"
-node "HI" 0 0 215 437 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-equiv "HI" "HI"
-equiv "HI" "HI"
-equiv "HI" "HI"
-node "VPWR" 0 0 0 689 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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-substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

diff --git a/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__decap_4.ext b/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__decap_4.ext
deleted file mode 100644
index 02d7cbd..0000000
--- a/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__decap_4.ext
+++ /dev/null

@@ -1,28 +0,0 @@
-timestamp 1604489738
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-abstract
-port "VNB" 2 0 -23 384 23 m1
-port "VGND" 1 0 51 384 125 m1
-port "VPWR" 4 0 689 384 763 m1
-port "VPB" 3 0 791 384 837 m1
-node "li_353_n17#" 0 0 353 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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-node "VNB" 0 0 0 -23 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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-node "li_65_797#" 0 0 65 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "VPB" 0 0 0 791 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_0_797#" 0 0 0 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

diff --git a/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__decap_8.ext b/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__decap_8.ext
deleted file mode 100644
index a2ca5e2..0000000
--- a/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__decap_8.ext
+++ /dev/null

@@ -1,36 +0,0 @@
-timestamp 1604489738
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-abstract
-port "VNB" 2 0 -23 768 23 m1
-port "VGND" 1 0 51 768 125 m1
-port "VPWR" 4 0 689 768 763 m1
-port "VPB" 3 0 791 768 837 m1
-node "li_737_n17#" 0 0 737 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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-node "VNB" 0 0 0 -23 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_0_n17#" 0 0 0 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "VGND" 0 0 0 51 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_115_72#" 0 0 115 72 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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-node "li_545_797#" 0 0 545 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_449_797#" 0 0 449 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_353_797#" 0 0 353 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_257_797#" 0 0 257 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_161_797#" 0 0 161 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_65_797#" 0 0 65 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "VPB" 0 0 0 791 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_0_797#" 0 0 0 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

diff --git a/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__fill_1.ext b/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__fill_1.ext
deleted file mode 100644
index 582fd18..0000000
--- a/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__fill_1.ext
+++ /dev/null

@@ -1,24 +0,0 @@
-timestamp 1604489738
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-abstract
-port "VGND" 1 0 51 96 125 m1
-port "VPWR" 4 0 689 96 763 m1
-port "VNB" 2 0 -23 96 23 m1
-port "VNB" 2 0 -17 96 17 li
-port "VNB" 2 31 -17 65 17 v0
-port "VPB" 3 0 791 96 837 m1
-port "VPB" 3 0 797 96 831 li
-port "VPB" 3 31 797 65 831 v0
-node "VGND" 0 0 0 51 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "VPWR" 0 0 0 689 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "VNB" 0 0 31 -17 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-equiv "VNB" "VNB"
-equiv "VNB" "VNB"
-node "VPB" 0 0 31 797 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-equiv "VPB" "VPB"
-equiv "VPB" "VPB"
-substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

diff --git a/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__fill_2.ext b/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__fill_2.ext
deleted file mode 100644
index 659ab81..0000000
--- a/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__fill_2.ext
+++ /dev/null

@@ -1,22 +0,0 @@
-timestamp 1604489738
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-abstract
-port "VGND" 1 0 51 192 125 m1
-port "VPWR" 4 0 689 192 763 m1
-port "VNB" 2 0 -23 192 23 m1
-port "VPB" 3 0 791 192 837 m1
-node "VGND" 0 0 0 51 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "VPWR" 0 0 0 689 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_161_n17#" 0 0 161 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_65_n17#" 0 0 65 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "VNB" 0 0 0 -23 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_0_n17#" 0 0 0 -17 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_161_797#" 0 0 161 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_65_797#" 0 0 65 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "VPB" 0 0 0 791 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_0_797#" 0 0 0 797 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

diff --git a/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__schmittbuf_1.ext b/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__schmittbuf_1.ext
deleted file mode 100644
index f625a29..0000000
--- a/openlane/simple_por/runs/simple_por/results/magic/sky130_fd_sc_hvl__schmittbuf_1.ext
+++ /dev/null

@@ -1,75 +0,0 @@
-timestamp 1604489738
-version 8.3
-tech sky130A
-style ngspice()
-scale 1000 1 500000
-resistclasses 2200000 3050000 1700000 3050000 120000 197000 114000 191000 120000 197000 114000 191000 48200 319800 2000000 48200 48200 12200 125 125 47 47 29 5
-abstract
-port "VNB" 4 0 -23 1056 23 m1
-port "VNB" 4 0 -17 1056 17 li
-port "VNB" 4 31 -17 65 17 v0
-port "VNB" 4 127 -17 161 17 v0
-port "VNB" 4 223 -17 257 17 v0
-port "VNB" 4 319 -17 353 17 v0
-port "VNB" 4 415 -17 449 17 v0
-port "VNB" 4 511 -17 545 17 v0
-port "VNB" 4 607 -17 641 17 v0
-port "VNB" 4 703 -17 737 17 v0
-port "VNB" 4 799 -17 833 17 v0
-port "VNB" 4 895 -17 929 17 v0
-port "VNB" 4 991 -17 1025 17 v0
-port "X" 2 972 103 1039 743 li
-port "VGND" 3 0 51 1056 125 m1
-port "A" 1 403 371 661 430 li
-port "VPWR" 6 0 689 1056 763 m1
-port "VPB" 5 0 791 1056 837 m1
-port "VPB" 5 0 797 1056 831 li
-port "VPB" 5 31 797 65 831 v0
-port "VPB" 5 127 797 161 831 v0
-port "VPB" 5 223 797 257 831 v0
-port "VPB" 5 319 797 353 831 v0
-port "VPB" 5 415 797 449 831 v0
-port "VPB" 5 511 797 545 831 v0
-port "VPB" 5 607 797 641 831 v0
-port "VPB" 5 703 797 737 831 v0
-port "VPB" 5 799 797 833 831 v0
-port "VPB" 5 895 797 929 831 v0
-port "VPB" 5 991 797 1025 831 v0
-node "VNB" 0 0 991 -17 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-equiv "VNB" "VNB"
-equiv "VNB" "VNB"
-equiv "VNB" "VNB"
-equiv "VNB" "VNB"
-equiv "VNB" "VNB"
-equiv "VNB" "VNB"
-equiv "VNB" "VNB"
-equiv "VNB" "VNB"
-equiv "VNB" "VNB"
-equiv "VNB" "VNB"
-equiv "VNB" "VNB"
-equiv "VNB" "VNB"
-node "X" 0 0 972 103 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "VGND" 0 0 0 51 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_624_75#" 0 0 624 75 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_212_195#" 0 0 212 195 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "A" 0 0 403 371 li 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_209_331#" 0 0 209 331 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_86_433#" 0 0 86 433 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_240_459#" 0 0 240 459 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "VPWR" 0 0 0 689 m1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_626_681#" 0 0 626 681 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "li_17_361#" 0 0 17 361 obsli 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-node "VPB" 0 0 991 797 v0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-equiv "VPB" "VPB"
-equiv "VPB" "VPB"
-equiv "VPB" "VPB"
-equiv "VPB" "VPB"
-equiv "VPB" "VPB"
-equiv "VPB" "VPB"
-equiv "VPB" "VPB"
-equiv "VPB" "VPB"
-equiv "VPB" "VPB"
-equiv "VPB" "VPB"
-equiv "VPB" "VPB"
-equiv "VPB" "VPB"
-substrate "VSUBS" 0 0 -1073741817 -1073741817 space 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

diff --git a/openlane/simple_por/runs/simple_por/results/placement/simple_por.placement.def b/openlane/simple_por/runs/simple_por/results/placement/simple_por.placement.def
deleted file mode 100644
index b9cf8da..0000000
--- a/openlane/simple_por/runs/simple_por/results/placement/simple_por.placement.def
+++ /dev/null

@@ -1,39 +0,0 @@
-VERSION 5.8 ;
-DIVIDERCHAR "/" ;
-BUSBITCHARS "[]" ;
-DESIGN simple_por ;
-UNITS DISTANCE MICRONS 1000 ;
-DIEAREA ( 0 0 ) ( 24780 45820 ) ;
-ROW ROW_0 unithv 5760 16280 FS DO 27 BY 1 STEP 480 0 ;
-ROW ROW_1 unithv 5760 20350 N DO 27 BY 1 STEP 480 0 ;
-ROW ROW_2 unithv 5760 24420 FS DO 27 BY 1 STEP 480 0 ;
-TRACKS X 240 DO 52 STEP 480 LAYER li1 ;
-TRACKS Y 240 DO 95 STEP 480 LAYER li1 ;
-TRACKS X 185 DO 67 STEP 370 LAYER met1 ;
-TRACKS Y 185 DO 124 STEP 370 LAYER met1 ;
-TRACKS X 240 DO 52 STEP 480 LAYER met2 ;
-TRACKS Y 240 DO 95 STEP 480 LAYER met2 ;
-TRACKS X 370 DO 33 STEP 740 LAYER met3 ;
-TRACKS Y 370 DO 62 STEP 740 LAYER met3 ;
-TRACKS X 480 DO 26 STEP 960 LAYER met4 ;
-TRACKS Y 480 DO 48 STEP 960 LAYER met4 ;
-TRACKS X 1665 DO 7 STEP 3330 LAYER met5 ;
-TRACKS Y 1665 DO 14 STEP 3330 LAYER met5 ;
-COMPONENTS 3 ;
-    - _1_ sky130_fd_sc_hvl__conb_1 + PLACED ( 9120 16280 ) FS ;
-    - hystbuf1 sky130_fd_sc_hvl__schmittbuf_1 + PLACED ( 7680 20350 ) N ;
-    - hystbuf2 sky130_fd_sc_hvl__schmittbuf_1 + PLACED ( 7680 24420 ) FS ;
-END COMPONENTS
-PINS 3 ;
-    - porb_h + NET porb_h + DIRECTION OUTPUT + USE SIGNAL + PLACED ( 6960 43820 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
-    - vdd3v3 + NET vdd3v3 + DIRECTION INPUT + USE SIGNAL + PLACED ( 3120 2000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
-    - vss + NET vss + DIRECTION INPUT + USE SIGNAL + PLACED ( 22780 19610 ) N + LAYER met3 ( -2000 -300 ) ( 2000 300 ) ;
-END PINS
-NETS 5 ;
-    - porb_h ( PIN porb_h ) ( hystbuf2 X ) + USE SIGNAL ;
-    - vdd3v3 ( PIN vdd3v3 ) + USE SIGNAL ;
-    - vss ( PIN vss ) + USE SIGNAL ;
-    - _0_ ( hystbuf1 A ) ( _1_ LO ) + USE SIGNAL ;
-    - mid ( hystbuf2 A ) ( hystbuf1 X ) + USE SIGNAL ;
-END NETS
-END DESIGN

diff --git a/openlane/simple_por/runs/simple_por/results/routing/simple_por.def b/openlane/simple_por/runs/simple_por/results/routing/simple_por.def
deleted file mode 100644
index 6b2240c..0000000
--- a/openlane/simple_por/runs/simple_por/results/routing/simple_por.def
+++ /dev/null

@@ -1,209 +0,0 @@
-VERSION 5.8 ;
-DIVIDERCHAR "/" ;
-BUSBITCHARS "[]" ;
-DESIGN simple_por ;
-UNITS DISTANCE MICRONS 1000 ;
-
-DIEAREA ( 0 0 ) ( 24780 45820 ) ;
-
-ROW ROW_0 unithv 5760 16280 FS DO 27 BY 1 STEP 480 0
- ;
-ROW ROW_1 unithv 5760 20350 N DO 27 BY 1 STEP 480 0
- ;
-ROW ROW_2 unithv 5760 24420 FS DO 27 BY 1 STEP 480 0
- ;
-TRACKS X 240 DO 52 STEP 480 LAYER li1 ;
-TRACKS Y 240 DO 95 STEP 480 LAYER li1 ;
-TRACKS X 185 DO 67 STEP 370 LAYER met1 ;
-TRACKS Y 185 DO 124 STEP 370 LAYER met1 ;
-TRACKS X 240 DO 52 STEP 480 LAYER met2 ;
-TRACKS Y 240 DO 95 STEP 480 LAYER met2 ;
-TRACKS X 370 DO 33 STEP 740 LAYER met3 ;
-TRACKS Y 370 DO 62 STEP 740 LAYER met3 ;
-TRACKS X 480 DO 26 STEP 960 LAYER met4 ;
-TRACKS Y 480 DO 48 STEP 960 LAYER met4 ;
-TRACKS X 1665 DO 7 STEP 3330 LAYER met5 ;
-TRACKS Y 1665 DO 14 STEP 3330 LAYER met5 ;
-
-VIAS 6 ;
-- via2_FR 
-+ RECT met2 ( -140 -185 ) ( 140 185 ) 
-+ RECT via2 ( -100 -100 ) ( 100 100 ) 
-+ RECT met3 ( -165 -165 ) ( 165 165 ) 
- 
- ;
-- via4_FR 
-+ RECT met4 ( -590 -590 ) ( 590 590 ) 
-+ RECT via4 ( -400 -400 ) ( 400 400 ) 
-+ RECT met5 ( -710 -710 ) ( 710 710 ) 
- 
- ;
-- via_1600x510 
- 
-+ VIARULE M1M2_PR
-  + CUTSIZE 150 150
-  + LAYERS met1 via met2
-  + CUTSPACING 170 170
-  + ENCLOSURE 245 180 55 180
-  + ROWCOL 1 4
- ;
-- via2_1600x510 
- 
-+ VIARULE M2M3_PR
-  + CUTSIZE 200 200
-  + LAYERS met2 via2 met3
-  + CUTSPACING 200 200
-  + ENCLOSURE 40 155 100 65
-  + ROWCOL 1 4
- ;
-- via3_1600x510 
- 
-+ VIARULE M3M4_PR
-  + CUTSIZE 200 200
-  + LAYERS met3 via3 met4
-  + CUTSPACING 200 200
-  + ENCLOSURE 100 60 100 155
-  + ROWCOL 1 4
- ;
-- via4_1600x1600 
- 
-+ VIARULE M4M5_PR
-  + CUTSIZE 800 800
-  + LAYERS met4 via4 met5
-  + CUTSPACING 800 800
-  + ENCLOSURE 400 400 400 400
- ;
-END VIAS
-
-COMPONENTS 16 ;
-- _1_ sky130_fd_sc_hvl__conb_1 + PLACED ( 9120 16280 ) FS ;
-- hystbuf1 sky130_fd_sc_hvl__schmittbuf_1 + PLACED ( 7680 20350 ) N ;
-- hystbuf2 sky130_fd_sc_hvl__schmittbuf_1 + PLACED ( 7680 24420 ) FS ;
-- FILLER_0_0 sky130_fd_sc_hvl__decap_4 + PLACED ( 5760 16280 ) FS ;
-- FILLER_0_4 sky130_fd_sc_hvl__fill_2 + PLACED ( 7680 16280 ) FS ;
-- FILLER_0_6 sky130_fd_sc_hvl__fill_1 + PLACED ( 8640 16280 ) FS ;
-- FILLER_0_12 sky130_fd_sc_hvl__decap_8 + PLACED ( 11520 16280 ) FS ;
-- FILLER_0_20 sky130_fd_sc_hvl__decap_4 + PLACED ( 15360 16280 ) FS ;
-- FILLER_0_24 sky130_fd_sc_hvl__fill_2 + PLACED ( 17280 16280 ) FS ;
-- FILLER_0_26 sky130_fd_sc_hvl__fill_1 + PLACED ( 18240 16280 ) FS ;
-- FILLER_1_0 sky130_fd_sc_hvl__decap_4 + PLACED ( 5760 20350 ) N ;
-- FILLER_1_15 sky130_fd_sc_hvl__decap_8 + PLACED ( 12960 20350 ) N ;
-- FILLER_1_23 sky130_fd_sc_hvl__decap_4 + PLACED ( 16800 20350 ) N ;
-- FILLER_2_0 sky130_fd_sc_hvl__decap_4 + PLACED ( 5760 24420 ) FS ;
-- FILLER_2_15 sky130_fd_sc_hvl__decap_8 + PLACED ( 12960 24420 ) FS ;
-- FILLER_2_23 sky130_fd_sc_hvl__decap_4 + PLACED ( 16800 24420 ) FS ;
-END COMPONENTS
-
-PINS 5 ;
-- porb_h + NET porb_h + DIRECTION OUTPUT + USE SIGNAL 
-  + LAYER met2 ( -140 -2000 ) ( 140 2000 )
-  + PLACED ( 6960 43820 ) N ;
-- vdd3v3 + NET vdd3v3 + DIRECTION INPUT + USE SIGNAL 
-  + LAYER met2 ( -140 -2000 ) ( 140 2000 )
-  + PLACED ( 3120 2000 ) N ;
-- vss + NET vss + DIRECTION INPUT + USE SIGNAL 
-  + LAYER met3 ( -2000 -300 ) ( 2000 300 )
-  + PLACED ( 22780 19610 ) N ;
-- VPWR + NET VPWR + DIRECTION INPUT + USE SIGNAL 
-  + LAYER met5 ( -6480 -800 ) ( 6480 800 )
-  + FIXED ( 12240 18060 ) N + SPECIAL ;
-- VGND + NET VGND + DIRECTION INPUT + USE SIGNAL 
-  + LAYER met5 ( -6480 -800 ) ( 6480 800 )
-  + FIXED ( 12240 20095 ) N + SPECIAL ;
-END PINS
-
-SPECIALNETS 2 ;
-- VPWR ( PIN VPWR ) 
-  + ROUTED met4 0 + SHAPE STRIPE ( 16560 26200 ) via4_1600x1600 
-    NEW met4 0 + SHAPE STRIPE ( 12240 26200 ) via4_1600x1600 
-    NEW met4 0 + SHAPE STRIPE ( 7920 26200 ) via4_1600x1600 
-    NEW met4 0 + SHAPE STRIPE ( 16560 22130 ) via4_1600x1600 
-    NEW met4 0 + SHAPE STRIPE ( 12240 22130 ) via4_1600x1600 
-    NEW met4 0 + SHAPE STRIPE ( 7920 22130 ) via4_1600x1600 
-    NEW met4 0 + SHAPE STRIPE ( 16560 18060 ) via4_1600x1600 
-    NEW met4 0 + SHAPE STRIPE ( 12240 18060 ) via4_1600x1600 
-    NEW met4 0 + SHAPE STRIPE ( 7920 18060 ) via4_1600x1600 
-    NEW met3 0 + SHAPE STRIPE ( 16560 24420 ) via3_1600x510 
-    NEW met2 0 + SHAPE STRIPE ( 16560 24420 ) via2_1600x510 
-    NEW met1 0 + SHAPE STRIPE ( 16560 24420 ) via_1600x510 
-    NEW met3 0 + SHAPE STRIPE ( 12240 24420 ) via3_1600x510 
-    NEW met2 0 + SHAPE STRIPE ( 12240 24420 ) via2_1600x510 
-    NEW met1 0 + SHAPE STRIPE ( 12240 24420 ) via_1600x510 
-    NEW met3 0 + SHAPE STRIPE ( 7920 24420 ) via3_1600x510 
-    NEW met2 0 + SHAPE STRIPE ( 7920 24420 ) via2_1600x510 
-    NEW met1 0 + SHAPE STRIPE ( 7920 24420 ) via_1600x510 
-    NEW met3 0 + SHAPE STRIPE ( 16560 16280 ) via3_1600x510 
-    NEW met2 0 + SHAPE STRIPE ( 16560 16280 ) via2_1600x510 
-    NEW met1 0 + SHAPE STRIPE ( 16560 16280 ) via_1600x510 
-    NEW met3 0 + SHAPE STRIPE ( 12240 16280 ) via3_1600x510 
-    NEW met2 0 + SHAPE STRIPE ( 12240 16280 ) via2_1600x510 
-    NEW met1 0 + SHAPE STRIPE ( 12240 16280 ) via_1600x510 
-    NEW met3 0 + SHAPE STRIPE ( 7920 16280 ) via3_1600x510 
-    NEW met2 0 + SHAPE STRIPE ( 7920 16280 ) via2_1600x510 
-    NEW met1 0 + SHAPE STRIPE ( 7920 16280 ) via_1600x510 
-    NEW met5 1600 + SHAPE STRIPE ( 5760 26200 ) ( 18720 26200 ) 
-    NEW met5 1600 + SHAPE STRIPE ( 5760 22130 ) ( 18720 22130 ) 
-    NEW met5 1600 + SHAPE STRIPE ( 5760 18060 ) ( 18720 18060 ) 
-    NEW met4 1600 + SHAPE STRIPE ( 16560 16025 ) ( 16560 28745 ) 
-    NEW met4 1600 + SHAPE STRIPE ( 12240 16025 ) ( 12240 28745 ) 
-    NEW met4 1600 + SHAPE STRIPE ( 7920 16025 ) ( 7920 28745 ) 
-    NEW met1 510 + SHAPE FOLLOWPIN ( 5760 24420 ) ( 18720 24420 ) 
-    NEW met1 510 + SHAPE FOLLOWPIN ( 5760 16280 ) ( 18720 16280 ) 
-  + USE POWER ;
-- VGND ( PIN VGND ) 
-  + ROUTED met4 0 + SHAPE STRIPE ( 14400 24165 ) via4_1600x1600 
-    NEW met4 0 + SHAPE STRIPE ( 10080 24165 ) via4_1600x1600 
-    NEW met4 0 + SHAPE STRIPE ( 14400 20095 ) via4_1600x1600 
-    NEW met4 0 + SHAPE STRIPE ( 10080 20095 ) via4_1600x1600 
-    NEW met3 0 + SHAPE STRIPE ( 14400 28490 ) via3_1600x510 
-    NEW met2 0 + SHAPE STRIPE ( 14400 28490 ) via2_1600x510 
-    NEW met1 0 + SHAPE STRIPE ( 14400 28490 ) via_1600x510 
-    NEW met3 0 + SHAPE STRIPE ( 10080 28490 ) via3_1600x510 
-    NEW met2 0 + SHAPE STRIPE ( 10080 28490 ) via2_1600x510 
-    NEW met1 0 + SHAPE STRIPE ( 10080 28490 ) via_1600x510 
-    NEW met3 0 + SHAPE STRIPE ( 14400 20350 ) via3_1600x510 
-    NEW met2 0 + SHAPE STRIPE ( 14400 20350 ) via2_1600x510 
-    NEW met1 0 + SHAPE STRIPE ( 14400 20350 ) via_1600x510 
-    NEW met3 0 + SHAPE STRIPE ( 10080 20350 ) via3_1600x510 
-    NEW met2 0 + SHAPE STRIPE ( 10080 20350 ) via2_1600x510 
-    NEW met1 0 + SHAPE STRIPE ( 10080 20350 ) via_1600x510 
-    NEW met5 1600 + SHAPE STRIPE ( 5760 24165 ) ( 18720 24165 ) 
-    NEW met5 1600 + SHAPE STRIPE ( 5760 20095 ) ( 18720 20095 ) 
-    NEW met4 1600 + SHAPE STRIPE ( 14400 16025 ) ( 14400 28745 ) 
-    NEW met4 1600 + SHAPE STRIPE ( 10080 16025 ) ( 10080 28745 ) 
-    NEW met1 510 + SHAPE FOLLOWPIN ( 5760 28490 ) ( 18720 28490 ) 
-    NEW met1 510 + SHAPE FOLLOWPIN ( 5760 20350 ) ( 18720 20350 ) 
-  + USE GROUND ;
-END SPECIALNETS
-
-NETS 5 ;
-- porb_h ( PIN porb_h ) ( hystbuf2 X ) 
-  + ROUTED met1 ( 6960 27565 ) ( 12720 27565 )
-    NEW met2 ( 6960 27565 ) ( 6960 42550 0 )
-    NEW li1 ( 12720 27565 ) L1M1_PR_MR
-    NEW met1 ( 6960 27565 ) M1M2_PR
-+ USE SIGNAL ;
-- vdd3v3 ( PIN vdd3v3 ) 
-+ USE SIGNAL ;
-- vss ( PIN vss ) 
-+ USE SIGNAL ;
-- _0_ ( hystbuf1 A ) ( _1_ LO ) 
-  + ROUTED met1 ( 10320 19425 ) ( 11280 19425 )
-    NEW met2 ( 11280 19425 ) ( 11280 22385 )
-    NEW met1 ( 10800 22385 ) ( 11280 22385 )
-    NEW li1 ( 10320 19425 ) L1M1_PR_MR
-    NEW met1 ( 11280 19425 ) M1M2_PR
-    NEW met1 ( 11280 22385 ) M1M2_PR
-    NEW li1 ( 10800 22385 ) L1M1_PR_MR
-+ USE SIGNAL ;
-- mid ( hystbuf2 A ) ( hystbuf1 X ) 
-  + ROUTED met1 ( 10800 23495 ) ( 12720 23495 )
-    NEW met2 ( 10800 23495 ) ( 10800 26455 )
-    NEW li1 ( 12720 23495 ) L1M1_PR_MR
-    NEW met1 ( 10800 23495 ) M1M2_PR
-    NEW li1 ( 10800 26455 ) L1M1_PR_MR
-    NEW met1 ( 10800 26455 ) M1M2_PR
-    NEW met1 ( 10800 26455 ) RECT ( -355 -70 0 70 )
-+ USE SIGNAL ;
-END NETS
-END DESIGN

diff --git a/openlane/simple_por/runs/simple_por/results/routing/simple_por.def.ref b/openlane/simple_por/runs/simple_por/results/routing/simple_por.def.ref
deleted file mode 100644
index ea8b874..0000000
--- a/openlane/simple_por/runs/simple_por/results/routing/simple_por.def.ref
+++ /dev/null

@@ -1,132 +0,0 @@
-VERSION 5.8 ;
-DIVIDERCHAR "/" ;
-BUSBITCHARS "[]" ;
-DESIGN simple_por ;
-UNITS DISTANCE MICRONS 1000 ;
-DIEAREA ( 0 0 ) ( 24780 45820 ) ;
-ROW ROW_0 unithv 5760 16280 FS DO 27 BY 1 STEP 480 0 ;
-ROW ROW_1 unithv 5760 20350 N DO 27 BY 1 STEP 480 0 ;
-ROW ROW_2 unithv 5760 24420 FS DO 27 BY 1 STEP 480 0 ;
-TRACKS X 240 DO 52 STEP 480 LAYER li1 ;
-TRACKS Y 240 DO 95 STEP 480 LAYER li1 ;
-TRACKS X 185 DO 67 STEP 370 LAYER met1 ;
-TRACKS Y 185 DO 124 STEP 370 LAYER met1 ;
-TRACKS X 240 DO 52 STEP 480 LAYER met2 ;
-TRACKS Y 240 DO 95 STEP 480 LAYER met2 ;
-TRACKS X 370 DO 33 STEP 740 LAYER met3 ;
-TRACKS Y 370 DO 62 STEP 740 LAYER met3 ;
-TRACKS X 480 DO 26 STEP 960 LAYER met4 ;
-TRACKS Y 480 DO 48 STEP 960 LAYER met4 ;
-TRACKS X 1665 DO 7 STEP 3330 LAYER met5 ;
-TRACKS Y 1665 DO 14 STEP 3330 LAYER met5 ;
-
-VIAS 6 ;
-- via2_FR
-  + RECT met2 ( -140 -185 ) ( 140 185 )
-  + RECT via2 ( -100 -100 ) ( 100 100 )
-  + RECT met3 ( -165 -165 ) ( 165 165 )
-  ;
-- via4_FR
-  + RECT met4 ( -590 -590 ) ( 590 590 )
-  + RECT via4 ( -400 -400 ) ( 400 400 )
-  + RECT met5 ( -710 -710 ) ( 710 710 )
-  ;
-    - via_1600x510 + VIARULE M1M2_PR + CUTSIZE 150 150  + LAYERS met1 via met2  + CUTSPACING 170 170  + ENCLOSURE 245 180 55 180  + ROWCOL 1 4  ;
-    - via2_1600x510 + VIARULE M2M3_PR + CUTSIZE 200 200  + LAYERS met2 via2 met3  + CUTSPACING 200 200  + ENCLOSURE 40 155 100 65  + ROWCOL 1 4  ;
-    - via3_1600x510 + VIARULE M3M4_PR + CUTSIZE 200 200  + LAYERS met3 via3 met4  + CUTSPACING 200 200  + ENCLOSURE 100 60 100 155  + ROWCOL 1 4  ;
-    - via4_1600x1600 + VIARULE M4M5_PR + CUTSIZE 800 800  + LAYERS met4 via4 met5  + CUTSPACING 800 800  + ENCLOSURE 400 400 400 400  ;
-END VIAS
-COMPONENTS 16 ;
-    - _1_ sky130_fd_sc_hvl__conb_1 + PLACED ( 9120 16280 ) FS ;
-    - hystbuf1 sky130_fd_sc_hvl__schmittbuf_1 + PLACED ( 7680 20350 ) N ;
-    - hystbuf2 sky130_fd_sc_hvl__schmittbuf_1 + PLACED ( 7680 24420 ) FS ;
-    - FILLER_0_0 sky130_fd_sc_hvl__decap_4 + PLACED ( 5760 16280 ) FS ;
-    - FILLER_0_4 sky130_fd_sc_hvl__fill_2 + PLACED ( 7680 16280 ) FS ;
-    - FILLER_0_6 sky130_fd_sc_hvl__fill_1 + PLACED ( 8640 16280 ) FS ;
-    - FILLER_0_12 sky130_fd_sc_hvl__decap_8 + PLACED ( 11520 16280 ) FS ;
-    - FILLER_0_20 sky130_fd_sc_hvl__decap_4 + PLACED ( 15360 16280 ) FS ;
-    - FILLER_0_24 sky130_fd_sc_hvl__fill_2 + PLACED ( 17280 16280 ) FS ;
-    - FILLER_0_26 sky130_fd_sc_hvl__fill_1 + PLACED ( 18240 16280 ) FS ;
-    - FILLER_1_0 sky130_fd_sc_hvl__decap_4 + PLACED ( 5760 20350 ) N ;
-    - FILLER_1_15 sky130_fd_sc_hvl__decap_8 + PLACED ( 12960 20350 ) N ;
-    - FILLER_1_23 sky130_fd_sc_hvl__decap_4 + PLACED ( 16800 20350 ) N ;
-    - FILLER_2_0 sky130_fd_sc_hvl__decap_4 + PLACED ( 5760 24420 ) FS ;
-    - FILLER_2_15 sky130_fd_sc_hvl__decap_8 + PLACED ( 12960 24420 ) FS ;
-    - FILLER_2_23 sky130_fd_sc_hvl__decap_4 + PLACED ( 16800 24420 ) FS ;
-END COMPONENTS
-PINS 5 ;
-    - porb_h + NET porb_h + DIRECTION OUTPUT + USE SIGNAL + PLACED ( 6960 43820 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
-    - vdd3v3 + NET vdd3v3 + DIRECTION INPUT + USE SIGNAL + PLACED ( 3120 2000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
-    - vss + NET vss + DIRECTION INPUT + USE SIGNAL + PLACED ( 22780 19610 ) N + LAYER met3 ( -2000 -300 ) ( 2000 300 ) ;
-    - VPWR + NET VPWR + SPECIAL + DIRECTION INPUT + USE SIGNAL + FIXED ( 12240 18060 ) N + LAYER met5 ( -6480 -800 ) ( 6480 800 ) ;
-    - VGND + NET VGND + SPECIAL + DIRECTION INPUT + USE SIGNAL + FIXED ( 12240 20095 ) N + LAYER met5 ( -6480 -800 ) ( 6480 800 ) ;
-END PINS
-SPECIALNETS 2 ;
-    - VPWR ( PIN VPWR ) + USE POWER
-      + ROUTED met4 0 + SHAPE STRIPE ( 16560 26200 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 12240 26200 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 7920 26200 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 16560 22130 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 12240 22130 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 7920 22130 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 16560 18060 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 12240 18060 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 7920 18060 ) via4_1600x1600
-      NEW met3 0 + SHAPE STRIPE ( 16560 24420 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 16560 24420 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 16560 24420 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 12240 24420 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 12240 24420 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 12240 24420 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 7920 24420 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 7920 24420 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 7920 24420 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 16560 16280 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 16560 16280 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 16560 16280 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 12240 16280 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 12240 16280 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 12240 16280 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 7920 16280 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 7920 16280 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 7920 16280 ) via_1600x510
-      NEW met5 1600 + SHAPE STRIPE ( 5760 26200 ) ( 18720 26200 )
-      NEW met5 1600 + SHAPE STRIPE ( 5760 22130 ) ( 18720 22130 )
-      NEW met5 1600 + SHAPE STRIPE ( 5760 18060 ) ( 18720 18060 )
-      NEW met4 1600 + SHAPE STRIPE ( 16560 16025 ) ( 16560 28745 )
-      NEW met4 1600 + SHAPE STRIPE ( 12240 16025 ) ( 12240 28745 )
-      NEW met4 1600 + SHAPE STRIPE ( 7920 16025 ) ( 7920 28745 )
-      NEW met1 510 + SHAPE FOLLOWPIN ( 5760 24420 ) ( 18720 24420 )
-      NEW met1 510 + SHAPE FOLLOWPIN ( 5760 16280 ) ( 18720 16280 ) ;
-    - VGND ( PIN VGND ) + USE GROUND
-      + ROUTED met4 0 + SHAPE STRIPE ( 14400 24165 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 10080 24165 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 14400 20095 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 10080 20095 ) via4_1600x1600
-      NEW met3 0 + SHAPE STRIPE ( 14400 28490 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 14400 28490 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 14400 28490 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 10080 28490 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 10080 28490 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 10080 28490 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 14400 20350 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 14400 20350 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 14400 20350 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 10080 20350 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 10080 20350 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 10080 20350 ) via_1600x510
-      NEW met5 1600 + SHAPE STRIPE ( 5760 24165 ) ( 18720 24165 )
-      NEW met5 1600 + SHAPE STRIPE ( 5760 20095 ) ( 18720 20095 )
-      NEW met4 1600 + SHAPE STRIPE ( 14400 16025 ) ( 14400 28745 )
-      NEW met4 1600 + SHAPE STRIPE ( 10080 16025 ) ( 10080 28745 )
-      NEW met1 510 + SHAPE FOLLOWPIN ( 5760 28490 ) ( 18720 28490 )
-      NEW met1 510 + SHAPE FOLLOWPIN ( 5760 20350 ) ( 18720 20350 ) ;
-END SPECIALNETS
-NETS 5 ;
-    - porb_h ( PIN porb_h ) ( hystbuf2 X ) + USE SIGNAL ;
-    - vdd3v3 ( PIN vdd3v3 ) + USE SIGNAL ;
-    - vss ( PIN vss ) + USE SIGNAL ;
-    - _0_ ( hystbuf1 A ) ( _1_ LO ) + USE SIGNAL ;
-    - mid ( hystbuf2 A ) ( hystbuf1 X ) + USE SIGNAL ;
-END NETS
-END DESIGN

diff --git a/openlane/simple_por/runs/simple_por/results/routing/simple_por.spef b/openlane/simple_por/runs/simple_por/results/routing/simple_por.spef
deleted file mode 100644
index 4a901d4..0000000
--- a/openlane/simple_por/runs/simple_por/results/routing/simple_por.spef
+++ /dev/null

@@ -1,93 +0,0 @@
-*SPEF "IEEE 1481-1998"
-*DESIGN "simple_por"
-*DATE "Wed Nov 11 03:14:18 2020"
-*VENDOR "AUC CSCE Department"
-*PROGRAM "SPEF Extractor"
-*VERSION "1.0"
-*DESIGN_FLOW "PIN_CAP NONE"
-*DIVIDER /
-*DELIMITER :
-*BUS_DELIMITER []
-*T_UNIT 1.00000 NS
-*C_UNIT 1.00000 PF
-*R_UNIT 1.00000 OHM
-*L_UNIT 1.00000 HENRY
-
-
-*NAME_MAP
-*0 porb_h
-*1 vdd3v3
-*2 vss
-*3 _0_
-*4 mid
-
-*D_NET *0 0.00167723130293
-*CONN
-*P porb_h O
-*I hystbuf2:X O
-*CAP
-0 *0:1 0.00024973915087999997
-1 hystbuf2:X 0.00024973915087999997
-2 *0:2 0.000588876500585
-3 *0:3 0.000588876500585
-*RES
-0 *0:1 hystbuf2:X 5.142857142857142
-1 *0:2 *0:3 13.379464285714285
-2 hystbuf2:X hystbuf2:X 0
-3 *0:1 *0:2 0
-*END
-
-*D_NET *1 0
-*CONN
-*P vdd3v3 I
-*CAP
-*RES
-*END
-
-*D_NET *2 0
-*CONN
-*P vss I
-*CAP
-*RES
-*END
-
-*D_NET *3 0.00038587409456000005
-*CONN
-*I hystbuf1:A I
-*I _1_:LO O
-*CAP
-4 _1_:LO 4.635600848e-05
-5 *3:1 4.635600848e-05
-6 *3:2 0.00012056334456000002
-7 *3:3 0.00012056334456000002
-8 hystbuf1:A 2.601769424e-05
-9 *3:4 2.601769424e-05
-*RES
-4 _1_:LO *3:1 0.857142857142857
-5 *3:2 *3:3 2.642857142857143
-6 hystbuf1:A *3:4 0.4285714285714285
-7 _1_:LO _1_:LO 0
-8 *3:1 *3:2 0
-9 *3:4 *3:3 0
-10 hystbuf1:A hystbuf1:A 0
-*END
-
-*D_NET *4 0.00041519196304
-*CONN
-*I hystbuf2:A I
-*I hystbuf1:X O
-*CAP
-10 *4:1 8.703263695999999e-05
-11 hystbuf1:X 8.703263695999999e-05
-12 *4:2 0.00012056334456000002
-13 *4:3 0.00012056334456000002
-14 hystbuf2:A 0.0
-*RES
-11 *4:1 hystbuf1:X 1.714285714285714
-12 *4:2 *4:3 2.642857142857143
-13 hystbuf1:X hystbuf1:X 0
-14 *4:1 *4:2 0
-15 hystbuf2:A hystbuf2:A 0
-16 hystbuf2:A *4:3 0
-*END
-

diff --git a/openlane/simple_por/runs/simple_por/results/synthesis/simple_por.synthesis.v b/openlane/simple_por/runs/simple_por/results/synthesis/simple_por.synthesis.v
deleted file mode 100644
index 3fa044b..0000000
--- a/openlane/simple_por/runs/simple_por/results/synthesis/simple_por.synthesis.v
+++ /dev/null

@@ -1,20 +0,0 @@
-/* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */
-
-module simple_por(vdd3v3, vss, porb_h);
-  wire _0_;
-  wire mid;
-  output porb_h;
-  input vdd3v3;
-  input vss;
-  sky130_fd_sc_hvl__conb_1 _1_ (
-    .LO(_0_)
-  );
-  sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
-    .A(_0_),
-    .X(mid)
-  );
-  sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
-    .A(mid),
-    .X(porb_h)
-  );
-endmodule

diff --git a/openlane/simple_por/runs/simple_por/results/synthesis/simple_por.synthesis_optimized.v b/openlane/simple_por/runs/simple_por/results/synthesis/simple_por.synthesis_optimized.v
deleted file mode 100644
index 51960d4..0000000
--- a/openlane/simple_por/runs/simple_por/results/synthesis/simple_por.synthesis_optimized.v
+++ /dev/null

@@ -1,13 +0,0 @@
-module simple_por (porb_h,
-    vdd3v3,
-    vss);
- output porb_h;
- input vdd3v3;
- input vss;
-
- sky130_fd_sc_hvl__conb_1 _1_ (.LO(_0_));
- sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (.A(_0_),
-    .X(mid));
- sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (.A(mid),
-    .X(porb_h));
-endmodule

diff --git a/openlane/simple_por/runs/simple_por/results/synthesis/simple_por.synthesis_preroute.v b/openlane/simple_por/runs/simple_por/results/synthesis/simple_por.synthesis_preroute.v
deleted file mode 100644
index 88e6fdb..0000000
--- a/openlane/simple_por/runs/simple_por/results/synthesis/simple_por.synthesis_preroute.v
+++ /dev/null

@@ -1,30 +0,0 @@
-module simple_por (porb_h,
-    vdd3v3,
-    vss,
-    VPWR,
-    VGND);
- output porb_h;
- input vdd3v3;
- input vss;
- input VPWR;
- input VGND;
-
- sky130_fd_sc_hvl__conb_1 _1_ (.LO(_0_));
- sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (.A(_0_),
-    .X(mid));
- sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (.A(mid),
-    .X(porb_h));
- sky130_fd_sc_hvl__decap_4 FILLER_0_0 ();
- sky130_fd_sc_hvl__fill_2 FILLER_0_4 ();
- sky130_fd_sc_hvl__fill_1 FILLER_0_6 ();
- sky130_fd_sc_hvl__decap_8 FILLER_0_12 ();
- sky130_fd_sc_hvl__decap_4 FILLER_0_20 ();
- sky130_fd_sc_hvl__fill_2 FILLER_0_24 ();
- sky130_fd_sc_hvl__fill_1 FILLER_0_26 ();
- sky130_fd_sc_hvl__decap_4 FILLER_1_0 ();
- sky130_fd_sc_hvl__decap_8 FILLER_1_15 ();
- sky130_fd_sc_hvl__decap_4 FILLER_1_23 ();
- sky130_fd_sc_hvl__decap_4 FILLER_2_0 ();
- sky130_fd_sc_hvl__decap_8 FILLER_2_15 ();
- sky130_fd_sc_hvl__decap_4 FILLER_2_23 ();
-endmodule

diff --git a/openlane/simple_por/runs/simple_por/tmp/floorplan/ioPlacer.def b/openlane/simple_por/runs/simple_por/tmp/floorplan/ioPlacer.def
deleted file mode 100644
index 1f88bcf..0000000
--- a/openlane/simple_por/runs/simple_por/tmp/floorplan/ioPlacer.def
+++ /dev/null

@@ -1,39 +0,0 @@
-VERSION 5.8 ;
-DIVIDERCHAR "/" ;
-BUSBITCHARS "[]" ;
-DESIGN simple_por ;
-UNITS DISTANCE MICRONS 1000 ;
-DIEAREA ( 0 0 ) ( 24780 45820 ) ;
-ROW ROW_0 unithv 5760 16280 FS DO 27 BY 1 STEP 480 0 ;
-ROW ROW_1 unithv 5760 20350 N DO 27 BY 1 STEP 480 0 ;
-ROW ROW_2 unithv 5760 24420 FS DO 27 BY 1 STEP 480 0 ;
-TRACKS X 240 DO 52 STEP 480 LAYER li1 ;
-TRACKS Y 240 DO 95 STEP 480 LAYER li1 ;
-TRACKS X 185 DO 67 STEP 370 LAYER met1 ;
-TRACKS Y 185 DO 124 STEP 370 LAYER met1 ;
-TRACKS X 240 DO 52 STEP 480 LAYER met2 ;
-TRACKS Y 240 DO 95 STEP 480 LAYER met2 ;
-TRACKS X 370 DO 33 STEP 740 LAYER met3 ;
-TRACKS Y 370 DO 62 STEP 740 LAYER met3 ;
-TRACKS X 480 DO 26 STEP 960 LAYER met4 ;
-TRACKS Y 480 DO 48 STEP 960 LAYER met4 ;
-TRACKS X 1665 DO 7 STEP 3330 LAYER met5 ;
-TRACKS Y 1665 DO 14 STEP 3330 LAYER met5 ;
-COMPONENTS 3 ;
-    - _1_ sky130_fd_sc_hvl__conb_1 ;
-    - hystbuf1 sky130_fd_sc_hvl__schmittbuf_1 ;
-    - hystbuf2 sky130_fd_sc_hvl__schmittbuf_1 ;
-END COMPONENTS
-PINS 3 ;
-    - porb_h + NET porb_h + DIRECTION OUTPUT + USE SIGNAL + PLACED ( 6960 43820 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
-    - vdd3v3 + NET vdd3v3 + DIRECTION INPUT + USE SIGNAL + PLACED ( 3120 2000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
-    - vss + NET vss + DIRECTION INPUT + USE SIGNAL + PLACED ( 22780 19610 ) N + LAYER met3 ( -2000 -300 ) ( 2000 300 ) ;
-END PINS
-NETS 5 ;
-    - porb_h ( PIN porb_h ) ( hystbuf2 X ) + USE SIGNAL ;
-    - vdd3v3 ( PIN vdd3v3 ) + USE SIGNAL ;
-    - vss ( PIN vss ) + USE SIGNAL ;
-    - _0_ ( hystbuf1 A ) ( _1_ LO ) + USE SIGNAL ;
-    - mid ( hystbuf2 A ) ( hystbuf1 X ) + USE SIGNAL ;
-END NETS
-END DESIGN

diff --git a/openlane/simple_por/runs/simple_por/tmp/floorplan/pdn.def b/openlane/simple_por/runs/simple_por/tmp/floorplan/pdn.def
deleted file mode 100644
index f579432..0000000
--- a/openlane/simple_por/runs/simple_por/tmp/floorplan/pdn.def
+++ /dev/null

@@ -1,108 +0,0 @@
-VERSION 5.8 ;
-DIVIDERCHAR "/" ;
-BUSBITCHARS "[]" ;
-DESIGN simple_por ;
-UNITS DISTANCE MICRONS 1000 ;
-DIEAREA ( 0 0 ) ( 24780 45820 ) ;
-ROW ROW_0 unithv 5760 16280 FS DO 27 BY 1 STEP 480 0 ;
-ROW ROW_1 unithv 5760 20350 N DO 27 BY 1 STEP 480 0 ;
-ROW ROW_2 unithv 5760 24420 FS DO 27 BY 1 STEP 480 0 ;
-TRACKS X 240 DO 52 STEP 480 LAYER li1 ;
-TRACKS Y 240 DO 95 STEP 480 LAYER li1 ;
-TRACKS X 185 DO 67 STEP 370 LAYER met1 ;
-TRACKS Y 185 DO 124 STEP 370 LAYER met1 ;
-TRACKS X 240 DO 52 STEP 480 LAYER met2 ;
-TRACKS Y 240 DO 95 STEP 480 LAYER met2 ;
-TRACKS X 370 DO 33 STEP 740 LAYER met3 ;
-TRACKS Y 370 DO 62 STEP 740 LAYER met3 ;
-TRACKS X 480 DO 26 STEP 960 LAYER met4 ;
-TRACKS Y 480 DO 48 STEP 960 LAYER met4 ;
-TRACKS X 1665 DO 7 STEP 3330 LAYER met5 ;
-TRACKS Y 1665 DO 14 STEP 3330 LAYER met5 ;
-VIAS 4 ;
-    - via_1600x510 + VIARULE M1M2_PR + CUTSIZE 150 150  + LAYERS met1 via met2  + CUTSPACING 170 170  + ENCLOSURE 245 180 55 180  + ROWCOL 1 4  ;
-    - via2_1600x510 + VIARULE M2M3_PR + CUTSIZE 200 200  + LAYERS met2 via2 met3  + CUTSPACING 200 200  + ENCLOSURE 40 155 100 65  + ROWCOL 1 4  ;
-    - via3_1600x510 + VIARULE M3M4_PR + CUTSIZE 200 200  + LAYERS met3 via3 met4  + CUTSPACING 200 200  + ENCLOSURE 100 60 100 155  + ROWCOL 1 4  ;
-    - via4_1600x1600 + VIARULE M4M5_PR + CUTSIZE 800 800  + LAYERS met4 via4 met5  + CUTSPACING 800 800  + ENCLOSURE 400 400 400 400  ;
-END VIAS
-COMPONENTS 3 ;
-    - _1_ sky130_fd_sc_hvl__conb_1 + PLACED ( 9120 16280 ) FS ;
-    - hystbuf1 sky130_fd_sc_hvl__schmittbuf_1 + PLACED ( 7680 20350 ) N ;
-    - hystbuf2 sky130_fd_sc_hvl__schmittbuf_1 + PLACED ( 7680 24420 ) FS ;
-END COMPONENTS
-PINS 5 ;
-    - porb_h + NET porb_h + DIRECTION OUTPUT + USE SIGNAL + PLACED ( 6960 43820 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
-    - vdd3v3 + NET vdd3v3 + DIRECTION INPUT + USE SIGNAL + PLACED ( 3120 2000 ) N + LAYER met2 ( -140 -2000 ) ( 140 2000 ) ;
-    - vss + NET vss + DIRECTION INPUT + USE SIGNAL + PLACED ( 22780 19610 ) N + LAYER met3 ( -2000 -300 ) ( 2000 300 ) ;
-    - VPWR + NET VPWR + DIRECTION INPUT + USE SIGNAL + FIXED ( 12240 18060 ) N + LAYER met5 ( -6480 -800 ) ( 6480 800 ) ;
-    - VGND + NET VGND + DIRECTION INPUT + USE SIGNAL + FIXED ( 12240 20095 ) N + LAYER met5 ( -6480 -800 ) ( 6480 800 ) ;
-END PINS
-SPECIALNETS 2 ;
-    - VPWR ( PIN VPWR ) + USE POWER
-      + ROUTED met4 0 + SHAPE STRIPE ( 16560 26200 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 12240 26200 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 7920 26200 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 16560 22130 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 12240 22130 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 7920 22130 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 16560 18060 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 12240 18060 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 7920 18060 ) via4_1600x1600
-      NEW met3 0 + SHAPE STRIPE ( 16560 24420 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 16560 24420 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 16560 24420 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 12240 24420 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 12240 24420 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 12240 24420 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 7920 24420 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 7920 24420 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 7920 24420 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 16560 16280 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 16560 16280 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 16560 16280 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 12240 16280 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 12240 16280 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 12240 16280 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 7920 16280 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 7920 16280 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 7920 16280 ) via_1600x510
-      NEW met5 1600 + SHAPE STRIPE ( 5760 26200 ) ( 18720 26200 )
-      NEW met5 1600 + SHAPE STRIPE ( 5760 22130 ) ( 18720 22130 )
-      NEW met5 1600 + SHAPE STRIPE ( 5760 18060 ) ( 18720 18060 )
-      NEW met4 1600 + SHAPE STRIPE ( 16560 16025 ) ( 16560 28745 )
-      NEW met4 1600 + SHAPE STRIPE ( 12240 16025 ) ( 12240 28745 )
-      NEW met4 1600 + SHAPE STRIPE ( 7920 16025 ) ( 7920 28745 )
-      NEW met1 510 + SHAPE FOLLOWPIN ( 5760 24420 ) ( 18720 24420 )
-      NEW met1 510 + SHAPE FOLLOWPIN ( 5760 16280 ) ( 18720 16280 ) ;
-    - VGND ( PIN VGND ) + USE GROUND
-      + ROUTED met4 0 + SHAPE STRIPE ( 14400 24165 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 10080 24165 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 14400 20095 ) via4_1600x1600
-      NEW met4 0 + SHAPE STRIPE ( 10080 20095 ) via4_1600x1600
-      NEW met3 0 + SHAPE STRIPE ( 14400 28490 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 14400 28490 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 14400 28490 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 10080 28490 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 10080 28490 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 10080 28490 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 14400 20350 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 14400 20350 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 14400 20350 ) via_1600x510
-      NEW met3 0 + SHAPE STRIPE ( 10080 20350 ) via3_1600x510
-      NEW met2 0 + SHAPE STRIPE ( 10080 20350 ) via2_1600x510
-      NEW met1 0 + SHAPE STRIPE ( 10080 20350 ) via_1600x510
-      NEW met5 1600 + SHAPE STRIPE ( 5760 24165 ) ( 18720 24165 )
-      NEW met5 1600 + SHAPE STRIPE ( 5760 20095 ) ( 18720 20095 )
-      NEW met4 1600 + SHAPE STRIPE ( 14400 16025 ) ( 14400 28745 )
-      NEW met4 1600 + SHAPE STRIPE ( 10080 16025 ) ( 10080 28745 )
-      NEW met1 510 + SHAPE FOLLOWPIN ( 5760 28490 ) ( 18720 28490 )
-      NEW met1 510 + SHAPE FOLLOWPIN ( 5760 20350 ) ( 18720 20350 ) ;
-END SPECIALNETS
-NETS 5 ;
-    - porb_h ( PIN porb_h ) ( hystbuf2 X ) + USE SIGNAL ;
-    - vdd3v3 ( PIN vdd3v3 ) + USE SIGNAL ;
-    - vss ( PIN vss ) + USE SIGNAL ;
-    - _0_ ( hystbuf1 A ) ( _1_ LO ) + USE SIGNAL ;
-    - mid ( hystbuf2 A ) ( hystbuf1 X ) + USE SIGNAL ;
-END NETS
-END DESIGN

diff --git a/openlane/simple_por/runs/simple_por/tmp/floorplan/verilog2def_openroad.def b/openlane/simple_por/runs/simple_por/tmp/floorplan/verilog2def_openroad.def
deleted file mode 100644
index e8416a9..0000000
--- a/openlane/simple_por/runs/simple_por/tmp/floorplan/verilog2def_openroad.def
+++ /dev/null

@@ -1,39 +0,0 @@
-VERSION 5.8 ;
-DIVIDERCHAR "/" ;
-BUSBITCHARS "[]" ;
-DESIGN simple_por ;
-UNITS DISTANCE MICRONS 1000 ;
-DIEAREA ( 0 0 ) ( 24780 45820 ) ;
-ROW ROW_0 unithv 5760 16280 FS DO 27 BY 1 STEP 480 0 ;
-ROW ROW_1 unithv 5760 20350 N DO 27 BY 1 STEP 480 0 ;
-ROW ROW_2 unithv 5760 24420 FS DO 27 BY 1 STEP 480 0 ;
-TRACKS X 240 DO 52 STEP 480 LAYER li1 ;
-TRACKS Y 240 DO 95 STEP 480 LAYER li1 ;
-TRACKS X 185 DO 67 STEP 370 LAYER met1 ;
-TRACKS Y 185 DO 124 STEP 370 LAYER met1 ;
-TRACKS X 240 DO 52 STEP 480 LAYER met2 ;
-TRACKS Y 240 DO 95 STEP 480 LAYER met2 ;
-TRACKS X 370 DO 33 STEP 740 LAYER met3 ;
-TRACKS Y 370 DO 62 STEP 740 LAYER met3 ;
-TRACKS X 480 DO 26 STEP 960 LAYER met4 ;
-TRACKS Y 480 DO 48 STEP 960 LAYER met4 ;
-TRACKS X 1665 DO 7 STEP 3330 LAYER met5 ;
-TRACKS Y 1665 DO 14 STEP 3330 LAYER met5 ;
-COMPONENTS 3 ;
-    - _1_ sky130_fd_sc_hvl__conb_1 ;
-    - hystbuf1 sky130_fd_sc_hvl__schmittbuf_1 ;
-    - hystbuf2 sky130_fd_sc_hvl__schmittbuf_1 ;
-END COMPONENTS
-PINS 3 ;
-    - porb_h + NET porb_h + DIRECTION OUTPUT + USE SIGNAL ;
-    - vdd3v3 + NET vdd3v3 + DIRECTION INPUT + USE SIGNAL ;
-    - vss + NET vss + DIRECTION INPUT + USE SIGNAL ;
-END PINS
-NETS 5 ;
-    - _0_ ( hystbuf1 A ) ( _1_ LO ) + USE SIGNAL ;
-    - mid ( hystbuf2 A ) ( hystbuf1 X ) + USE SIGNAL ;
-    - porb_h ( PIN porb_h ) ( hystbuf2 X ) + USE SIGNAL ;
-    - vdd3v3 ( PIN vdd3v3 ) + USE SIGNAL ;
-    - vss ( PIN vss ) + USE SIGNAL ;
-END NETS
-END DESIGN

diff --git a/openlane/simple_por/runs/simple_por/tmp/magic_spice.tcl b/openlane/simple_por/runs/simple_por/tmp/magic_spice.tcl
deleted file mode 100644
index 9a5f4a1..0000000
--- a/openlane/simple_por/runs/simple_por/tmp/magic_spice.tcl
+++ /dev/null

@@ -1,24 +0,0 @@
-
-lef read /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_sc_hvl/techlef/sky130_fd_sc_hvl.tlef
-if {  [info exist ::env(EXTRA_LEFS)] } {
-	set lefs_in $::env(EXTRA_LEFS)
-	foreach lef_file $lefs_in {
-		lef read $lef_file
-	}
-}
-def read /project/openlane/simple_por/runs/simple_por/results/routing/simple_por.def
-load simple_por -dereference
-cd /project/openlane/simple_por/runs/simple_por/results/magic/
-extract do local
-extract no capacitance
-extract no coupling
-extract no resistance
-extract no adjust
-# extract warn all
-extract
-
-ext2spice lvs
-ext2spice simple_por.ext
-feedback save /project/openlane/simple_por/runs/simple_por/logs/magic/magic_ext2spice.feedback.txt
-# exec cp simple_por.spice /project/openlane/simple_por/runs/simple_por/results/magic/simple_por.spice
-

diff --git a/openlane/simple_por/runs/simple_por/tmp/merged.lef b/openlane/simple_por/runs/simple_por/tmp/merged.lef
deleted file mode 100644
index 448e6e4..0000000
--- a/openlane/simple_por/runs/simple_por/tmp/merged.lef
+++ /dev/null

@@ -1,12841 +0,0 @@
-# Copyright 2020 The SkyWater PDK Authors
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     https://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#
-# SPDX-License-Identifier: Apache-2.0
-
-VERSION 5.7 ;
-
-BUSBITCHARS "[]" ;
-DIVIDERCHAR "/" ;
-
-UNITS
-  TIME NANOSECONDS 1 ;
-  CAPACITANCE PICOFARADS 1 ;
-  RESISTANCE OHMS 1 ;
-  DATABASE MICRONS 1000 ;
-END UNITS
-
-MANUFACTURINGGRID 0.005 ;
-
-PROPERTYDEFINITIONS
-  LAYER LEF58_TYPE STRING ;
-END PROPERTYDEFINITIONS
-
-# High voltage, single height
-SITE unithv
-  SYMMETRY Y ;
-  CLASS CORE ;
-  SIZE 0.48 BY 4.07 ;
-END unithv
-
-# High voltage, double height
-SITE unithvdbl
-  SYMMETRY Y ;
-  CLASS CORE ;
-  SIZE 0.48 BY 8.14 ;
-END unithvdbl
-
-LAYER nwell
-  TYPE MASTERSLICE ;
-  PROPERTY LEF58_TYPE "TYPE NWELL ;" ;
-END nwell
-
-LAYER pwell
-  TYPE MASTERSLICE ;
-  PROPERTY LEF58_TYPE "TYPE NWELL ;" ;
-END pwell
-
-LAYER li1
-  TYPE ROUTING ;
-  DIRECTION VERTICAL ;
-
-  PITCH 0.48 ;
-  MINWIDTH 0.17 ;
-
-  WIDTH 0.17 ;          # LI 1
-  # SPACING  0.17 ;     # LI 2
-  SPACINGTABLE
-     PARALLELRUNLENGTH 0
-     WIDTH 0 0.17 ;
-  AREA 0.0561 ;         # LI 6
-  THICKNESS 0.1 ;
-  EDGECAPACITANCE 40.697E-6 ;
-  CAPACITANCE CPERSQDIST 36.9866E-6 ;
-  RESISTANCE RPERSQ 12.2 ;
-
-  ANTENNADIFFSIDEAREARATIO PWL ( ( 0 75 ) ( 0.0125 75 ) ( 0.0225 85.125 ) ( 22.5 10200 ) ) ;
-END li1
-
-LAYER mcon
-  TYPE CUT ;
-
-  WIDTH 0.17 ;                # Mcon 1
-  SPACING 0.19 ;              # Mcon 2
-  ENCLOSURE BELOW 0 0 ;       # Mcon 4
-  ENCLOSURE ABOVE 0.03 0.06 ; # Met1 4 / Met1 5
-
-  ANTENNADIFFAREARATIO PWL ( ( 0 3 ) ( 0.0125 3 ) ( 0.0225 3.405 ) ( 22.5 408 ) ) ;
-  DCCURRENTDENSITY AVERAGE 0.36 ; # mA per via Iavg_max at Tj = 90oC
-
-END mcon
-
-LAYER met1
-  TYPE ROUTING ;
-  DIRECTION HORIZONTAL ;
-
-  PITCH 0.37 ;
-  MINENCLOSEDAREA 0.14 ;
-  MINWIDTH 0.14 ;
-
-  WIDTH 0.14 ;                     # Met1 1
-  # SPACING 0.14 ;                 # Met1 2
-  # SPACING 0.28 RANGE 3.001 100 ; # Met1 3b
-  SPACINGTABLE
-     PARALLELRUNLENGTH 0
-     WIDTH 0 0.14
-     WIDTH 3 0.28 ;
-  AREA 0.083 ;                     # Met1 6
-  THICKNESS 0.35 ;
-
-  ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
-
-  EDGECAPACITANCE 40.567E-6 ;
-  CAPACITANCE CPERSQDIST 25.7784E-6 ;
-  DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC
-  ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC
-
-  RESISTANCE RPERSQ 0.125 ;
-END met1
-
-LAYER via
-  TYPE CUT ;
-  WIDTH 0.15 ;                  # Via 1a
-  SPACING 0.17 ;                # Via 2
-  ENCLOSURE BELOW 0.055 0.085 ; # Via 4a / Via 5a
-  ENCLOSURE ABOVE 0.055 0.085 ; # Met2 4 / Met2 5
-
-  ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
-  DCCURRENTDENSITY AVERAGE 0.29 ; # mA per via Iavg_max at Tj = 90oC
-END via
-
-LAYER met2
-  TYPE ROUTING ;
-  DIRECTION VERTICAL ;
-
-  PITCH 0.48 ;
-  MINENCLOSEDAREA 0.14 ;
-  MINWIDTH 0.14 ;
-
-  WIDTH 0.14 ;                        # Met2 1
-  # SPACING  0.14 ;                   # Met2 2
-  # SPACING  0.28 RANGE 3.001 100 ;   # Met2 3b
-  SPACINGTABLE
-     PARALLELRUNLENGTH 0
-     WIDTH 0 0.14
-     WIDTH 3 0.28 ;
-  AREA 0.0676 ;                       # Met2 6
-  THICKNESS 0.35 ;
-
-  EDGECAPACITANCE 37.759E-6 ;
-  CAPACITANCE CPERSQDIST 16.9423E-6 ;
-  RESISTANCE RPERSQ 0.125 ;
-  DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC
-  ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC
-  ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
-END met2
-
-# ******** Layer via2, type routing, number 44 **************
-LAYER via2
-  TYPE CUT ;
-  WIDTH 0.2 ;                   # Via2 1
-  SPACING 0.2 ;                 # Via2 2
-  ENCLOSURE BELOW 0.04 0.085 ;  # Via2 4
-  ENCLOSURE ABOVE 0.065 0.065 ; # Met3 4
-  ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
-  DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC
-END via2
-
-LAYER met3
-  TYPE ROUTING ;
-  DIRECTION HORIZONTAL ;
-
-  PITCH 0.74 ;
-  MINWIDTH 0.3 ;
-
-  WIDTH 0.3 ;              # Met3 1
-  # SPACING 0.3 ;          # Met3 2
-  SPACINGTABLE
-     PARALLELRUNLENGTH 0
-     WIDTH 0 0.3
-     WIDTH 3 0.4 ;
-  AREA 0.24 ;              # Met3 6
-  THICKNESS 0.8 ;
-
-  EDGECAPACITANCE 40.989E-6 ;
-  CAPACITANCE CPERSQDIST 12.3729E-6 ;
-  RESISTANCE RPERSQ 0.047 ;
-  DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC
-  ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC
-
-  ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
-END met3
-
-LAYER via3
-  TYPE CUT ;
-  WIDTH 0.2 ;                   # Via3 1
-  SPACING 0.2 ;                 # Via3 2
-  ENCLOSURE BELOW 0.06 0.09 ;   # Via3 4 / Via3 5
-  ENCLOSURE ABOVE 0.065 0.065 ; # Met4 3
-  ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
-  DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC
-END via3
-
-LAYER met4
-  TYPE ROUTING ;
-  DIRECTION VERTICAL ;
-
-  PITCH 0.96 ;
-  MINWIDTH 0.3 ;
-
-  WIDTH 0.3 ;             # Met4 1
-  # SPACING  0.3 ;             # Met4 2
-  SPACINGTABLE
-     PARALLELRUNLENGTH 0
-     WIDTH 0 0.3
-     WIDTH 3 0.4 ;
-  AREA 0.24 ;              # Met4 4a
-
-  THICKNESS 0.8 ;
-
-  EDGECAPACITANCE 36.676E-6 ;
-  CAPACITANCE CPERSQDIST 8.41537E-6 ;
-  RESISTANCE RPERSQ 0.047 ;
-  DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC
-  ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC
-
-  ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
-END met4
-
-LAYER via4
-  TYPE CUT ;
-
-  WIDTH 0.8 ;                 # Via4 1
-  SPACING 0.8 ;               # Via4 2
-  ENCLOSURE BELOW 0.19 0.19 ; # Via4 4
-  ENCLOSURE ABOVE 0.31 0.31 ; # Met5 3
-  ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
-  DCCURRENTDENSITY AVERAGE 2.49 ; # mA per via Iavg_max at Tj = 90oC
-END via4
-
-LAYER met5
-  TYPE ROUTING ;
-  DIRECTION HORIZONTAL ;
-
-  PITCH 3.33 ;
-  MINWIDTH 1.6 ;
-
-  WIDTH 1.6 ;            # Met5 1
-  #SPACING  1.6 ;        # Met5 2
-  SPACINGTABLE
-     PARALLELRUNLENGTH 0
-     WIDTH 0 1.6 ;
-  AREA 4 ;               # Met5 4
-
-  THICKNESS 1.2 ;
-
-  EDGECAPACITANCE 38.851E-6 ;
-  CAPACITANCE CPERSQDIST 6.32063E-6 ;
-  RESISTANCE RPERSQ 0.0285 ;
-  DCCURRENTDENSITY AVERAGE 10.17 ; # mA/um Iavg_max at Tj = 90oC
-  ACCURRENTDENSITY RMS 22.34 ; # mA/um Irms_max at Tj = 90oC
-
-  ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
-END met5
-
-
-### Routing via cells section   ###
-# Plus via rule, metals are along the prefered direction
-VIA L1M1_PR DEFAULT
-  LAYER mcon ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  LAYER li1 ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  LAYER met1 ;
-  RECT -0.145 -0.115 0.145 0.115 ;
-END L1M1_PR
-
-VIARULE L1M1_PR GENERATE
-  LAYER li1 ;
-  ENCLOSURE 0 0 ;
-  LAYER met1 ;
-  ENCLOSURE 0.06 0.03 ;
-  LAYER mcon ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  SPACING 0.36 BY 0.36 ;
-END L1M1_PR
-
-# Plus via rule, metals are along the non prefered direction
-VIA L1M1_PR_R DEFAULT
-  LAYER mcon ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  LAYER li1 ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  LAYER met1 ;
-  RECT -0.115 -0.145 0.115 0.145 ;
-END L1M1_PR_R
-
-VIARULE L1M1_PR_R GENERATE
-  LAYER li1 ;
-  ENCLOSURE 0 0 ;
-  LAYER met1 ;
-  ENCLOSURE 0.03 0.06 ;
-  LAYER mcon ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  SPACING 0.36 BY 0.36 ;
-END L1M1_PR_R
-
-# Minus via rule, lower layer metal is along prefered direction
-VIA L1M1_PR_M DEFAULT
-  LAYER mcon ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  LAYER li1 ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  LAYER met1 ;
-  RECT -0.115 -0.145 0.115 0.145 ;
-END L1M1_PR_M
-
-VIARULE L1M1_PR_M GENERATE
-  LAYER li1 ;
-  ENCLOSURE 0 0 ;
-  LAYER met1 ;
-  ENCLOSURE 0.03 0.06 ;
-  LAYER mcon ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  SPACING 0.36 BY 0.36 ;
-END L1M1_PR_M
-
-# Minus via rule, upper layer metal is along prefered direction
-VIA L1M1_PR_MR DEFAULT
-  LAYER mcon ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  LAYER li1 ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  LAYER met1 ;
-  RECT -0.145 -0.115 0.145 0.115 ;
-END L1M1_PR_MR
-
-VIARULE L1M1_PR_MR GENERATE
-  LAYER li1 ;
-  ENCLOSURE 0 0 ;
-  LAYER met1 ;
-  ENCLOSURE 0.06 0.03 ;
-  LAYER mcon ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  SPACING 0.36 BY 0.36 ;
-END L1M1_PR_MR
-
-# Centered via rule, we really do not want to use it
-VIA L1M1_PR_C DEFAULT
-  LAYER mcon ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  LAYER li1 ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  LAYER met1 ;
-  RECT -0.145 -0.145 0.145 0.145 ;
-END L1M1_PR_C
-
-VIARULE L1M1_PR_C GENERATE
-  LAYER li1 ;
-  ENCLOSURE 0 0 ;
-  LAYER met1 ;
-  ENCLOSURE 0.06 0.06 ;
-  LAYER mcon ;
-  RECT -0.085 -0.085 0.085 0.085 ;
-  SPACING 0.36 BY 0.36 ;
-END L1M1_PR_C
-
-# Plus via rule, metals are along the prefered direction
-VIA M1M2_PR DEFAULT
-  LAYER via ;
-  RECT -0.075 -0.075 0.075 0.075 ;
-  LAYER met1 ;
-  RECT -0.16 -0.13 0.16 0.13 ;
-  LAYER met2 ;
-  RECT -0.13 -0.16 0.13 0.16 ;
-END M1M2_PR
-
-VIARULE M1M2_PR GENERATE
-  LAYER met1 ;
-  ENCLOSURE 0.085 0.055 ;
-  LAYER met2 ;
-  ENCLOSURE 0.055 0.085 ;
-  LAYER via ;
-  RECT -0.075 -0.075 0.075 0.075 ;
-  SPACING 0.32 BY 0.32 ;
-END M1M2_PR
-
-# Plus via rule, metals are along the non prefered direction
-VIA M1M2_PR_R DEFAULT
-  LAYER via ;
-  RECT -0.075 -0.075 0.075 0.075 ;
-  LAYER met1 ;
-  RECT -0.13 -0.16 0.13 0.16 ;
-  LAYER met2 ;
-  RECT -0.16 -0.13 0.16 0.13 ;
-END M1M2_PR_R
-
-VIARULE M1M2_PR_R GENERATE
-  LAYER met1 ;
-  ENCLOSURE 0.055 0.085 ;
-  LAYER met2 ;
-  ENCLOSURE 0.085 0.055 ;
-  LAYER via ;
-  RECT -0.075 -0.075 0.075 0.075 ;
-  SPACING 0.32 BY 0.32 ;
-END M1M2_PR_R
-
-# Minus via rule, lower layer metal is along prefered direction
-VIA M1M2_PR_M DEFAULT
-  LAYER via ;
-  RECT -0.075 -0.075 0.075 0.075 ;
-  LAYER met1 ;
-  RECT -0.16 -0.13 0.16 0.13 ;
-  LAYER met2 ;
-  RECT -0.16 -0.13 0.16 0.13 ;
-END M1M2_PR_M
-
-VIARULE M1M2_PR_M GENERATE
-  LAYER met1 ;
-  ENCLOSURE 0.085 0.055 ;
-  LAYER met2 ;
-  ENCLOSURE 0.085 0.055 ;
-  LAYER via ;
-  RECT -0.075 -0.075 0.075 0.075 ;
-  SPACING 0.32 BY 0.32 ;
-END M1M2_PR_M
-
-# Minus via rule, upper layer metal is along prefered direction
-VIA M1M2_PR_MR DEFAULT
-  LAYER via ;
-  RECT -0.075 -0.075 0.075 0.075 ;
-  LAYER met1 ;
-  RECT -0.13 -0.16 0.13 0.16 ;
-  LAYER met2 ;
-  RECT -0.13 -0.16 0.13 0.16 ;
-END M1M2_PR_MR
-
-VIARULE M1M2_PR_MR GENERATE
-  LAYER met1 ;
-  ENCLOSURE 0.055 0.085 ;
-  LAYER met2 ;
-  ENCLOSURE 0.055 0.085 ;
-  LAYER via ;
-  RECT -0.075 -0.075 0.075 0.075 ;
-  SPACING 0.32 BY 0.32 ;
-END M1M2_PR_MR
-
-# Centered via rule, we really do not want to use it
-VIA M1M2_PR_C DEFAULT
-  LAYER via ;
-  RECT -0.075 -0.075 0.075 0.075 ;
-  LAYER met1 ;
-  RECT -0.16 -0.16 0.16 0.16 ;
-  LAYER met2 ;
-  RECT -0.16 -0.16 0.16 0.16 ;
-END M1M2_PR_C
-
-VIARULE M1M2_PR_C GENERATE
-  LAYER met1 ;
-  ENCLOSURE 0.085 0.085 ;
-  LAYER met2 ;
-  ENCLOSURE 0.085 0.085 ;
-  LAYER via ;
-  RECT -0.075 -0.075 0.075 0.075 ;
-  SPACING 0.32 BY 0.32 ;
-END M1M2_PR_C
-
-# Plus via rule, metals are along the prefered direction
-VIA M2M3_PR DEFAULT
-  LAYER via2 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  LAYER met2 ;
-  RECT -0.14 -0.185 0.14 0.185 ;
-  LAYER met3 ;
-  RECT -0.165 -0.165 0.165 0.165 ;
-END M2M3_PR
-
-VIARULE M2M3_PR GENERATE
-  LAYER met2 ;
-  ENCLOSURE 0.04 0.085 ;
-  LAYER met3 ;
-  ENCLOSURE 0.065 0.065 ;
-  LAYER via2 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  SPACING 0.4 BY 0.4 ;
-END M2M3_PR
-
-# Plus via rule, metals are along the non prefered direction
-VIA M2M3_PR_R DEFAULT
-  LAYER via2 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  LAYER met2 ;
-  RECT -0.185 -0.14 0.185 0.14 ;
-  LAYER met3 ;
-  RECT -0.165 -0.165 0.165 0.165 ;
-END M2M3_PR_R
-
-VIARULE M2M3_PR_R GENERATE
-  LAYER met2 ;
-  ENCLOSURE 0.085 0.04 ;
-  LAYER met3 ;
-  ENCLOSURE 0.065 0.065 ;
-  LAYER via2 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  SPACING 0.4 BY 0.4 ;
-END M2M3_PR_R
-
-# Minus via rule, lower layer metal is along prefered direction
-VIA M2M3_PR_M DEFAULT
-  LAYER via2 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  LAYER met2 ;
-  RECT -0.14 -0.185 0.14 0.185 ;
-  LAYER met3 ;
-  RECT -0.165 -0.165 0.165 0.165 ;
-END M2M3_PR_M
-
-VIARULE M2M3_PR_M GENERATE
-  LAYER met2 ;
-  ENCLOSURE 0.04 0.085 ;
-  LAYER met3 ;
-  ENCLOSURE 0.065 0.065 ;
-  LAYER via2 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  SPACING 0.4 BY 0.4 ;
-END M2M3_PR_M
-
-# Minus via rule, upper layer metal is along prefered direction
-VIA M2M3_PR_MR DEFAULT
-  LAYER via2 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  LAYER met2 ;
-  RECT -0.185 -0.14 0.185 0.14 ;
-  LAYER met3 ;
-  RECT -0.165 -0.165 0.165 0.165 ;
-END M2M3_PR_MR
-
-VIARULE M2M3_PR_MR GENERATE
-  LAYER met2 ;
-  ENCLOSURE 0.085 0.04 ;
-  LAYER met3 ;
-  ENCLOSURE 0.065 0.065 ;
-  LAYER via2 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  SPACING 0.4 BY 0.4 ;
-END M2M3_PR_MR
-
-# Centered via rule, we really do not want to use it
-VIA M2M3_PR_C DEFAULT
-  LAYER via2 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  LAYER met2 ;
-  RECT -0.185 -0.185 0.185 0.185 ;
-  LAYER met3 ;
-  RECT -0.165 -0.165 0.165 0.165 ;
-END M2M3_PR_C
-
-VIARULE M2M3_PR_C GENERATE
-  LAYER met2 ;
-  ENCLOSURE 0.085 0.085 ;
-  LAYER met3 ;
-  ENCLOSURE 0.065 0.065 ;
-  LAYER via2 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  SPACING 0.4 BY 0.4 ;
-END M2M3_PR_C
-
-# Plus via rule, metals are along the prefered direction
-VIA M3M4_PR DEFAULT
-  LAYER via3 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  LAYER met3 ;
-  RECT -0.19 -0.16 0.19 0.16 ;
-  LAYER met4 ;
-  RECT -0.165 -0.165 0.165 0.165 ;
-END M3M4_PR
-
-VIARULE M3M4_PR GENERATE
-  LAYER met3 ;
-  ENCLOSURE 0.09 0.06 ;
-  LAYER met4 ;
-  ENCLOSURE 0.065 0.065 ;
-  LAYER via3 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  SPACING 0.4 BY 0.4 ;
-END M3M4_PR
-
-# Plus via rule, metals are along the non prefered direction
-VIA M3M4_PR_R DEFAULT
-  LAYER via3 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  LAYER met3 ;
-  RECT -0.16 -0.19 0.16 0.19 ;
-  LAYER met4 ;
-  RECT -0.165 -0.165 0.165 0.165 ;
-END M3M4_PR_R
-
-VIARULE M3M4_PR_R GENERATE
-  LAYER met3 ;
-  ENCLOSURE 0.06 0.09 ;
-  LAYER met4 ;
-  ENCLOSURE 0.065 0.065 ;
-  LAYER via3 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  SPACING 0.4 BY 0.4 ;
-END M3M4_PR_R
-
-# Minus via rule, lower layer metal is along prefered direction
-VIA M3M4_PR_M DEFAULT
-  LAYER via3 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  LAYER met3 ;
-  RECT -0.19 -0.16 0.19 0.16 ;
-  LAYER met4 ;
-  RECT -0.165 -0.165 0.165 0.165 ;
-END M3M4_PR_M
-
-VIARULE M3M4_PR_M GENERATE
-  LAYER met3 ;
-  ENCLOSURE 0.09 0.06 ;
-  LAYER met4 ;
-  ENCLOSURE 0.065 0.065 ;
-  LAYER via3 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  SPACING 0.4 BY 0.4 ;
-END M3M4_PR_M
-
-# Minus via rule, upper layer metal is along prefered direction
-VIA M3M4_PR_MR DEFAULT
-  LAYER via3 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  LAYER met3 ;
-  RECT -0.16 -0.19 0.16 0.19 ;
-  LAYER met4 ;
-  RECT -0.165 -0.165 0.165 0.165 ;
-END M3M4_PR_MR
-
-VIARULE M3M4_PR_MR GENERATE
-  LAYER met3 ;
-  ENCLOSURE 0.06 0.09 ;
-  LAYER met4 ;
-  ENCLOSURE 0.065 0.065 ;
-  LAYER via3 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  SPACING 0.4 BY 0.4 ;
-END M3M4_PR_MR
-
-# Centered via rule, we really do not want to use it
-VIA M3M4_PR_C DEFAULT
-  LAYER via3 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  LAYER met3 ;
-  RECT -0.19 -0.19 0.19 0.19 ;
-  LAYER met4 ;
-  RECT -0.165 -0.165 0.165 0.165 ;
-END M3M4_PR_C
-
-VIARULE M3M4_PR_C GENERATE
-  LAYER met3 ;
-  ENCLOSURE 0.09 0.09 ;
-  LAYER met4 ;
-  ENCLOSURE 0.065 0.065 ;
-  LAYER via3 ;
-  RECT -0.1 -0.1 0.1 0.1 ;
-  SPACING 0.4 BY 0.4 ;
-END M3M4_PR_C
-
-# Plus via rule, metals are along the prefered direction
-VIA M4M5_PR DEFAULT
-  LAYER via4 ;
-  RECT -0.4 -0.4 0.4 0.4 ;
-  LAYER met4 ;
-  RECT -0.59 -0.59 0.59 0.59 ;
-  LAYER met5 ;
-  RECT -0.71 -0.71 0.71 0.71 ;
-END M4M5_PR
-
-VIARULE M4M5_PR GENERATE
-  LAYER met4 ;
-  ENCLOSURE 0.19 0.19 ;
-  LAYER met5 ;
-  ENCLOSURE 0.31 0.31 ;
-  LAYER via4 ;
-  RECT -0.4 -0.4 0.4 0.4 ;
-  SPACING 1.6 BY 1.6 ;
-END M4M5_PR
-
-# Plus via rule, metals are along the non prefered direction
-VIA M4M5_PR_R DEFAULT
-  LAYER via4 ;
-  RECT -0.4 -0.4 0.4 0.4 ;
-  LAYER met4 ;
-  RECT -0.59 -0.59 0.59 0.59 ;
-  LAYER met5 ;
-  RECT -0.71 -0.71 0.71 0.71 ;
-END M4M5_PR_R
-
-VIARULE M4M5_PR_R GENERATE
-  LAYER met4 ;
-  ENCLOSURE 0.19 0.19 ;
-  LAYER met5 ;
-  ENCLOSURE 0.31 0.31 ;
-  LAYER via4 ;
-  RECT -0.4 -0.4 0.4 0.4 ;
-  SPACING 1.6 BY 1.6 ;
-END M4M5_PR_R
-
-# Minus via rule, lower layer metal is along prefered direction
-VIA M4M5_PR_M DEFAULT
-  LAYER via4 ;
-  RECT -0.4 -0.4 0.4 0.4 ;
-  LAYER met4 ;
-  RECT -0.59 -0.59 0.59 0.59 ;
-  LAYER met5 ;
-  RECT -0.71 -0.71 0.71 0.71 ;
-END M4M5_PR_M
-
-VIARULE M4M5_PR_M GENERATE
-  LAYER met4 ;
-  ENCLOSURE 0.19 0.19 ;
-  LAYER met5 ;
-  ENCLOSURE 0.31 0.31 ;
-  LAYER via4 ;
-  RECT -0.4 -0.4 0.4 0.4 ;
-  SPACING 1.6 BY 1.6 ;
-END M4M5_PR_M
-
-# Minus via rule, upper layer metal is along prefered direction
-VIA M4M5_PR_MR DEFAULT
-  LAYER via4 ;
-  RECT -0.4 -0.4 0.4 0.4 ;
-  LAYER met4 ;
-  RECT -0.59 -0.59 0.59 0.59 ;
-  LAYER met5 ;
-  RECT -0.71 -0.71 0.71 0.71 ;
-END M4M5_PR_MR
-
-VIARULE M4M5_PR_MR GENERATE
-  LAYER met4 ;
-  ENCLOSURE 0.19 0.19 ;
-  LAYER met5 ;
-  ENCLOSURE 0.31 0.31 ;
-  LAYER via4 ;
-  RECT -0.4 -0.4 0.4 0.4 ;
-  SPACING 1.6 BY 1.6 ;
-END M4M5_PR_MR
-
-# Centered via rule, we really do not want to use it
-VIA M4M5_PR_C DEFAULT
-  LAYER via4 ;
-  RECT -0.4 -0.4 0.4 0.4 ;
-  LAYER met4 ;
-  RECT -0.59 -0.59 0.59 0.59 ;
-  LAYER met5 ;
-  RECT -0.71 -0.71 0.71 0.71 ;
-END M4M5_PR_C
-
-VIARULE M4M5_PR_C GENERATE
-  LAYER met4 ;
-  ENCLOSURE 0.19 0.19 ;
-  LAYER met5 ;
-  ENCLOSURE 0.31 0.31 ;
-  LAYER via4 ;
-  RECT -0.4 -0.4 0.4 0.4 ;
-  SPACING 1.6 BY 1.6 ;
-END M4M5_PR_C
-###  end of single via cells   ###
-
-
-MACRO sky130_fd_sc_hvl__dfsbp_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__dfsbp_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  17.76000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN D
-    ANTENNAGATEAREA  0.420000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 2.525000 1.515000 2.875000 2.145000 ;
-    END
-  END D
-  PIN Q
-    ANTENNADIFFAREA  0.498750 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 17.300000 0.495000 17.635000 1.325000 ;
-        RECT 17.300000 2.355000 17.635000 3.435000 ;
-        RECT 17.405000 1.325000 17.635000 2.355000 ;
-    END
-  END Q
-  PIN Q_N
-    ANTENNADIFFAREA  0.641250 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 15.015000 0.495000 15.375000 3.755000 ;
-    END
-  END Q_N
-  PIN SET_B
-    ANTENNAGATEAREA  0.840000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT  6.985000 1.155000 10.330000 1.325000 ;
-        RECT 10.160000 1.325000 10.330000 1.605000 ;
-        RECT 10.160000 1.605000 10.885000 1.775000 ;
-        RECT 10.715000 1.775000 10.885000 1.975000 ;
-        RECT 10.715000 1.975000 12.830000 2.145000 ;
-        RECT 12.150000 1.555000 12.830000 1.975000 ;
-    END
-  END SET_B
-  PIN CLK
-    ANTENNAGATEAREA  0.585000 ;
-    DIRECTION INPUT ;
-    USE CLOCK ;
-    PORT
-      LAYER li1 ;
-        RECT 0.560000 1.550000 0.890000 2.520000 ;
-    END
-  END CLK
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 17.760000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 17.760000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 17.760000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 17.760000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT  0.000000 -0.085000 17.760000 0.085000 ;
-      RECT  0.000000  3.985000 17.760000 4.155000 ;
-      RECT  0.110000  0.540000  0.360000 1.200000 ;
-      RECT  0.110000  1.200000  1.590000 1.370000 ;
-      RECT  0.110000  1.370000  0.380000 3.450000 ;
-      RECT  0.540000  0.365000  1.490000 1.020000 ;
-      RECT  0.650000  2.700000  1.240000 3.705000 ;
-      RECT  1.260000  1.370000  1.590000 1.870000 ;
-      RECT  1.420000  1.870000  1.590000 3.630000 ;
-      RECT  1.420000  3.630000  2.290000 3.800000 ;
-      RECT  1.670000  0.540000  2.000000 1.000000 ;
-      RECT  1.770000  1.000000  2.000000 1.165000 ;
-      RECT  1.770000  1.165000  2.820000 1.335000 ;
-      RECT  1.770000  1.335000  1.940000 3.450000 ;
-      RECT  2.120000  2.325000  3.025000 2.495000 ;
-      RECT  2.120000  2.495000  2.290000 3.630000 ;
-      RECT  2.220000  0.365000  2.470000 0.985000 ;
-      RECT  2.470000  2.675000  2.675000 3.705000 ;
-      RECT  2.650000  0.265000  4.460000 0.435000 ;
-      RECT  2.650000  0.435000  2.820000 1.165000 ;
-      RECT  2.855000  2.495000  3.025000 3.355000 ;
-      RECT  2.855000  3.355000  5.500000 3.525000 ;
-      RECT  3.000000  0.615000  3.375000 1.005000 ;
-      RECT  3.205000  1.005000  3.375000 2.675000 ;
-      RECT  3.205000  2.675000  3.545000 3.175000 ;
-      RECT  3.555000  1.105000  3.725000 2.225000 ;
-      RECT  3.555000  2.225000  4.800000 2.395000 ;
-      RECT  3.725000  2.395000  3.895000 3.355000 ;
-      RECT  3.780000  0.615000  4.110000 0.925000 ;
-      RECT  3.905000  0.925000  4.075000 1.855000 ;
-      RECT  3.905000  1.855000  8.060000 2.025000 ;
-      RECT  4.075000  2.675000  4.405000 3.005000 ;
-      RECT  4.075000  3.005000  5.150000 3.175000 ;
-      RECT  4.255000  1.105000  4.585000 1.505000 ;
-      RECT  4.255000  1.505000  9.470000 1.675000 ;
-      RECT  4.290000  0.435000  4.460000 1.105000 ;
-      RECT  4.585000  2.395000  4.800000 2.555000 ;
-      RECT  4.650000  0.365000  5.600000 0.905000 ;
-      RECT  4.945000  1.085000  6.150000 1.325000 ;
-      RECT  4.980000  2.025000  5.150000 3.005000 ;
-      RECT  5.330000  2.205000  7.025000 2.375000 ;
-      RECT  5.330000  2.555000  6.595000 2.725000 ;
-      RECT  5.330000  2.725000  5.500000 3.355000 ;
-      RECT  5.680000  2.905000  6.245000 3.705000 ;
-      RECT  5.820000  0.515000  6.150000 1.085000 ;
-      RECT  6.425000  2.725000  6.595000 3.355000 ;
-      RECT  6.425000  3.355000  7.675000 3.525000 ;
-      RECT  6.775000  2.375000  7.025000 3.175000 ;
-      RECT  6.785000  0.365000  7.735000 0.975000 ;
-      RECT  7.505000  2.545000  9.120000 2.715000 ;
-      RECT  7.505000  2.715000  7.675000 3.355000 ;
-      RECT  7.730000  2.025000  8.060000 2.365000 ;
-      RECT  7.855000  2.895000  8.805000 3.705000 ;
-      RECT  8.185000  0.375000 11.110000 0.545000 ;
-      RECT  8.185000  0.545000  8.515000 0.975000 ;
-      RECT  8.755000  0.725000 10.680000 0.975000 ;
-      RECT  8.870000  1.885000  9.120000 2.545000 ;
-      RECT  9.300000  1.675000  9.470000 2.305000 ;
-      RECT  9.300000  2.305000 10.185000 2.475000 ;
-      RECT  9.345000  2.675000  9.675000 3.585000 ;
-      RECT  9.345000  3.585000 10.535000 3.755000 ;
-      RECT  9.650000  1.505000  9.980000 1.955000 ;
-      RECT  9.650000  1.955000 10.535000 2.125000 ;
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-      RECT 10.715000 -0.085000 10.885000 0.085000 ;
-      RECT 10.715000  3.985000 10.885000 4.155000 ;
-      RECT 10.875000  3.505000 11.045000 3.675000 ;
-      RECT 11.160000  0.395000 11.330000 0.565000 ;
-      RECT 11.195000 -0.085000 11.365000 0.085000 ;
-      RECT 11.195000  3.985000 11.365000 4.155000 ;
-      RECT 11.235000  3.505000 11.405000 3.675000 ;
-      RECT 11.520000  0.395000 11.690000 0.565000 ;
-      RECT 11.675000 -0.085000 11.845000 0.085000 ;
-      RECT 11.675000  3.985000 11.845000 4.155000 ;
-      RECT 11.880000  0.395000 12.050000 0.565000 ;
-      RECT 12.155000 -0.085000 12.325000 0.085000 ;
-      RECT 12.155000  3.985000 12.325000 4.155000 ;
-      RECT 12.270000  3.505000 12.440000 3.675000 ;
-      RECT 12.630000  3.505000 12.800000 3.675000 ;
-      RECT 12.635000 -0.085000 12.805000 0.085000 ;
-      RECT 12.635000  3.985000 12.805000 4.155000 ;
-      RECT 12.990000  3.505000 13.160000 3.675000 ;
-      RECT 13.115000 -0.085000 13.285000 0.085000 ;
-      RECT 13.115000  3.985000 13.285000 4.155000 ;
-      RECT 13.595000 -0.085000 13.765000 0.085000 ;
-      RECT 13.595000  3.985000 13.765000 4.155000 ;
-      RECT 13.765000  0.395000 13.935000 0.565000 ;
-      RECT 13.800000  3.505000 13.970000 3.675000 ;
-      RECT 14.075000 -0.085000 14.245000 0.085000 ;
-      RECT 14.075000  3.985000 14.245000 4.155000 ;
-      RECT 14.125000  0.395000 14.295000 0.565000 ;
-      RECT 14.160000  3.505000 14.330000 3.675000 ;
-      RECT 14.485000  0.395000 14.655000 0.565000 ;
-      RECT 14.520000  3.505000 14.690000 3.675000 ;
-      RECT 14.555000 -0.085000 14.725000 0.085000 ;
-      RECT 14.555000  3.985000 14.725000 4.155000 ;
-      RECT 15.035000 -0.085000 15.205000 0.085000 ;
-      RECT 15.035000  3.985000 15.205000 4.155000 ;
-    LAYER met1 ;
-      RECT 2.015000 1.920000 2.305000 1.965000 ;
-      RECT 2.015000 1.965000 9.985000 2.105000 ;
-      RECT 2.015000 2.105000 2.305000 2.150000 ;
-      RECT 4.415000 1.920000 4.705000 1.965000 ;
-      RECT 4.415000 2.105000 4.705000 2.150000 ;
-      RECT 9.695000 1.920000 9.985000 1.965000 ;
-      RECT 9.695000 2.105000 9.985000 2.150000 ;
-  END
-END sky130_fd_sc_hvl__dfrtp_1
-MACRO sky130_fd_sc_hvl__diode_2
-  CLASS CORE ANTENNACELL ;
-  FOREIGN sky130_fd_sc_hvl__diode_2 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  0.960000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN DIODE
-    ANTENNADIFFAREA  0.607200 ;
-    ANTENNAGATEAREA  0.607200 ;
-    DIRECTION INPUT ;
-    PORT
-      LAYER li1 ;
-        RECT 0.105000 0.515000 0.855000 3.280000 ;
-    END
-  END DIODE
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 0.960000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 0.960000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 0.960000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 0.960000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT 0.000000 -0.085000 0.960000 0.085000 ;
-      RECT 0.000000  3.985000 0.960000 4.155000 ;
-    LAYER mcon ;
-      RECT 0.155000 -0.085000 0.325000 0.085000 ;
-      RECT 0.155000  3.985000 0.325000 4.155000 ;
-      RECT 0.635000 -0.085000 0.805000 0.085000 ;
-      RECT 0.635000  3.985000 0.805000 4.155000 ;
-  END
-END sky130_fd_sc_hvl__diode_2
-MACRO sky130_fd_sc_hvl__lsbufhv2lv_simple_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__lsbufhv2lv_simple_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  8.640000 BY  8.140000 ;
-  SYMMETRY X Y ;
-  SITE unithvdbl ;
-  PIN A
-    ANTENNAGATEAREA  0.585000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 4.355000 1.465000 4.685000 3.260000 ;
-    END
-  END A
-  PIN X
-    ANTENNADIFFAREA  0.626250 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 2.995000 0.495000 3.255000 2.175000 ;
-        RECT 2.995000 2.175000 3.440000 3.755000 ;
-    END
-  END X
-  PIN LVPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.070000 3.020000 8.570000 3.305000 ;
-    END
-  END LVPWR
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 7.515000 8.640000 7.885000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 8.025000 8.640000 8.255000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 8.640000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 4.325000 8.640000 4.695000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT 0.000000 -0.085000 8.640000 0.085000 ;
-      RECT 0.000000  3.985000 0.800000 4.155000 ;
-      RECT 0.000000  8.055000 8.640000 8.225000 ;
-      RECT 3.130000  3.955000 5.095000 4.525000 ;
-      RECT 3.435000  0.365000 4.685000 0.935000 ;
-      RECT 3.565000  1.115000 5.115000 1.285000 ;
-      RECT 3.565000  1.285000 3.895000 1.745000 ;
-      RECT 3.620000  2.175000 4.175000 3.955000 ;
-      RECT 4.865000  0.495000 5.115000 1.115000 ;
-      RECT 4.865000  1.285000 5.115000 3.005000 ;
-      RECT 7.425000  3.985000 8.640000 4.155000 ;
-    LAYER mcon ;
-      RECT 0.155000 -0.085000 0.325000 0.085000 ;
-      RECT 0.155000  3.985000 0.325000 4.155000 ;
-      RECT 0.155000  8.055000 0.325000 8.225000 ;
-      RECT 0.635000 -0.085000 0.805000 0.085000 ;
-      RECT 0.635000  8.055000 0.805000 8.225000 ;
-      RECT 1.115000 -0.085000 1.285000 0.085000 ;
-      RECT 1.115000  8.055000 1.285000 8.225000 ;
-      RECT 1.595000 -0.085000 1.765000 0.085000 ;
-      RECT 1.595000  8.055000 1.765000 8.225000 ;
-      RECT 2.075000 -0.085000 2.245000 0.085000 ;
-      RECT 2.075000  8.055000 2.245000 8.225000 ;
-      RECT 2.555000 -0.085000 2.725000 0.085000 ;
-      RECT 2.555000  8.055000 2.725000 8.225000 ;
-      RECT 3.035000 -0.085000 3.205000 0.085000 ;
-      RECT 3.035000  8.055000 3.205000 8.225000 ;
-      RECT 3.435000  0.395000 3.605000 0.565000 ;
-      RECT 3.515000 -0.085000 3.685000 0.085000 ;
-      RECT 3.515000  8.055000 3.685000 8.225000 ;
-      RECT 3.630000  3.075000 3.800000 3.245000 ;
-      RECT 3.795000  0.395000 3.965000 0.565000 ;
-      RECT 3.990000  3.075000 4.160000 3.245000 ;
-      RECT 3.995000 -0.085000 4.165000 0.085000 ;
-      RECT 3.995000  8.055000 4.165000 8.225000 ;
-      RECT 4.155000  0.395000 4.325000 0.565000 ;
-      RECT 4.475000 -0.085000 4.645000 0.085000 ;
-      RECT 4.475000  8.055000 4.645000 8.225000 ;
-      RECT 4.515000  0.395000 4.685000 0.565000 ;
-      RECT 4.955000 -0.085000 5.125000 0.085000 ;
-      RECT 4.955000  8.055000 5.125000 8.225000 ;
-      RECT 5.435000 -0.085000 5.605000 0.085000 ;
-      RECT 5.435000  8.055000 5.605000 8.225000 ;
-      RECT 5.915000 -0.085000 6.085000 0.085000 ;
-      RECT 5.915000  8.055000 6.085000 8.225000 ;
-      RECT 6.395000 -0.085000 6.565000 0.085000 ;
-      RECT 6.395000  8.055000 6.565000 8.225000 ;
-      RECT 6.875000 -0.085000 7.045000 0.085000 ;
-      RECT 6.875000  8.055000 7.045000 8.225000 ;
-      RECT 7.355000 -0.085000 7.525000 0.085000 ;
-      RECT 7.355000  8.055000 7.525000 8.225000 ;
-      RECT 7.835000 -0.085000 8.005000 0.085000 ;
-      RECT 7.835000  3.985000 8.005000 4.155000 ;
-      RECT 7.835000  8.055000 8.005000 8.225000 ;
-      RECT 8.315000 -0.085000 8.485000 0.085000 ;
-      RECT 8.315000  3.985000 8.485000 4.155000 ;
-      RECT 8.315000  8.055000 8.485000 8.225000 ;
-    LAYER met1 ;
-      RECT 0.000000 -0.115000 8.640000 0.115000 ;
-      RECT 0.000000  0.255000 8.640000 0.625000 ;
-      RECT 0.000000  3.445000 8.640000 3.815000 ;
-  END
-END sky130_fd_sc_hvl__lsbufhv2lv_simple_1
-MACRO sky130_fd_sc_hvl__nor2_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__nor2_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  2.400000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN A
-    ANTENNAGATEAREA  1.125000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 0.125000 1.775000 1.315000 2.120000 ;
-    END
-  END A
-  PIN B
-    ANTENNAGATEAREA  1.125000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 1.495000 1.775000 1.825000 2.120000 ;
-    END
-  END B
-  PIN Y
-    ANTENNADIFFAREA  0.637500 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 1.200000 0.495000 1.530000 1.425000 ;
-        RECT 1.200000 1.425000 2.275000 1.595000 ;
-        RECT 2.020000 1.595000 2.275000 3.755000 ;
-    END
-  END Y
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 2.400000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 2.400000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 2.400000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 2.400000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT 0.000000 -0.085000 2.400000 0.085000 ;
-      RECT 0.000000  3.985000 2.400000 4.155000 ;
-      RECT 0.090000  0.365000 1.020000 1.325000 ;
-      RECT 0.090000  2.300000 1.760000 3.755000 ;
-      RECT 1.720000  0.365000 2.310000 1.245000 ;
-    LAYER mcon ;
-      RECT 0.110000  0.395000 0.280000 0.565000 ;
-      RECT 0.120000  3.505000 0.290000 3.675000 ;
-      RECT 0.155000 -0.085000 0.325000 0.085000 ;
-      RECT 0.155000  3.985000 0.325000 4.155000 ;
-      RECT 0.470000  0.395000 0.640000 0.565000 ;
-      RECT 0.480000  3.505000 0.650000 3.675000 ;
-      RECT 0.635000 -0.085000 0.805000 0.085000 ;
-      RECT 0.635000  3.985000 0.805000 4.155000 ;
-      RECT 0.830000  0.395000 1.000000 0.565000 ;
-      RECT 0.840000  3.505000 1.010000 3.675000 ;
-      RECT 1.115000 -0.085000 1.285000 0.085000 ;
-      RECT 1.115000  3.985000 1.285000 4.155000 ;
-      RECT 1.200000  3.505000 1.370000 3.675000 ;
-      RECT 1.560000  3.505000 1.730000 3.675000 ;
-      RECT 1.595000 -0.085000 1.765000 0.085000 ;
-      RECT 1.595000  3.985000 1.765000 4.155000 ;
-      RECT 1.750000  0.395000 1.920000 0.565000 ;
-      RECT 2.075000 -0.085000 2.245000 0.085000 ;
-      RECT 2.075000  3.985000 2.245000 4.155000 ;
-      RECT 2.110000  0.395000 2.280000 0.565000 ;
-  END
-END sky130_fd_sc_hvl__nor2_1
-MACRO sky130_fd_sc_hvl__conb_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__conb_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  2.400000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN HI
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 0.290000 0.430000 0.865000 1.070000 ;
-        RECT 0.615000 1.070000 0.865000 1.935000 ;
-        RECT 0.615000 1.935000 1.325000 2.185000 ;
-        RECT 1.075000 2.185000 1.325000 3.530000 ;
-    END
-  END HI
-  PIN LO
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 1.035000 0.500000 1.365000 1.500000 ;
-        RECT 1.035000 1.500000 1.795000 1.765000 ;
-        RECT 1.530000 1.765000 1.795000 3.175000 ;
-        RECT 1.530000 3.175000 2.110000 3.815000 ;
-    END
-  END LO
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 2.400000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 2.400000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 2.400000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 2.400000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT 0.000000 -0.085000 2.400000 0.085000 ;
-      RECT 0.000000  3.985000 2.400000 4.155000 ;
-      RECT 0.215000  3.175000 0.620000 3.445000 ;
-      RECT 0.215000  3.445000 0.865000 3.785000 ;
-      RECT 1.535000  0.285000 2.185000 0.625000 ;
-      RECT 1.780000  0.625000 2.185000 1.070000 ;
-    LAYER mcon ;
-      RECT 0.155000 -0.085000 0.325000 0.085000 ;
-      RECT 0.155000  3.985000 0.325000 4.155000 ;
-      RECT 0.275000  3.505000 0.445000 3.675000 ;
-      RECT 0.635000 -0.085000 0.805000 0.085000 ;
-      RECT 0.635000  3.505000 0.805000 3.675000 ;
-      RECT 0.635000  3.985000 0.805000 4.155000 ;
-      RECT 1.115000 -0.085000 1.285000 0.085000 ;
-      RECT 1.115000  3.985000 1.285000 4.155000 ;
-      RECT 1.595000 -0.085000 1.765000 0.085000 ;
-      RECT 1.595000  0.395000 1.765000 0.565000 ;
-      RECT 1.595000  3.985000 1.765000 4.155000 ;
-      RECT 1.955000  0.395000 2.125000 0.565000 ;
-      RECT 2.075000 -0.085000 2.245000 0.085000 ;
-      RECT 2.075000  3.985000 2.245000 4.155000 ;
-  END
-END sky130_fd_sc_hvl__conb_1
-MACRO sky130_fd_sc_hvl__dfxtp_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__dfxtp_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  12.00000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN D
-    ANTENNAGATEAREA  0.420000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 1.595000 1.555000 2.470000 1.750000 ;
-    END
-  END D
-  PIN Q
-    ANTENNADIFFAREA  0.596250 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 11.560000 2.185000 11.890000 3.735000 ;
-        RECT 11.640000 0.685000 11.890000 2.185000 ;
-    END
-  END Q
-  PIN CLK
-    ANTENNAGATEAREA  0.585000 ;
-    DIRECTION INPUT ;
-    USE CLOCK ;
-    PORT
-      LAYER li1 ;
-        RECT 0.540000 1.905000 0.870000 2.575000 ;
-    END
-  END CLK
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 12.000000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 12.000000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 12.000000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 12.000000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT  0.000000 -0.085000 12.000000 0.085000 ;
-      RECT  0.000000  3.985000 12.000000 4.155000 ;
-      RECT  0.110000  0.595000  0.380000 1.555000 ;
-      RECT  0.110000  1.555000  1.415000 1.725000 ;
-      RECT  0.110000  1.725000  0.360000 3.565000 ;
-      RECT  0.540000  2.755000  1.490000 3.705000 ;
-      RECT  0.560000  0.365000  1.510000 1.095000 ;
-      RECT  1.165000  1.725000  1.415000 1.930000 ;
-      RECT  1.165000  1.930000  2.820000 2.225000 ;
-      RECT  1.670000  2.445000  2.820000 2.615000 ;
-      RECT  1.670000  2.615000  2.000000 3.565000 ;
-      RECT  1.690000  0.595000  2.020000 1.205000 ;
-      RECT  1.690000  1.205000  3.115000 1.375000 ;
-      RECT  2.200000  0.365000  2.765000 1.025000 ;
-      RECT  2.220000  2.795000  2.470000 3.705000 ;
-      RECT  2.650000  1.760000  3.685000 1.930000 ;
-      RECT  2.650000  2.615000  2.820000 3.305000 ;
-      RECT  2.650000  3.305000  3.680000 3.475000 ;
-      RECT  2.945000  0.265000  5.055000 0.435000 ;
-      RECT  2.945000  0.435000  3.115000 1.205000 ;
-      RECT  3.000000  2.110000  4.035000 2.280000 ;
-      RECT  3.000000  2.280000  3.330000 3.125000 ;
-      RECT  3.295000  0.615000  4.035000 1.025000 ;
-      RECT  3.430000  1.205000  3.685000 1.760000 ;
-      RECT  3.510000  2.460000  3.840000 3.135000 ;
-      RECT  3.510000  3.135000  7.655000 3.305000 ;
-      RECT  3.865000  1.025000  4.035000 2.110000 ;
-      RECT  4.055000  2.675000  4.385000 2.955000 ;
-      RECT  4.215000  0.615000  4.545000 1.525000 ;
-      RECT  4.215000  1.525000  6.345000 1.695000 ;
-      RECT  4.215000  1.695000  4.385000 2.675000 ;
-      RECT  4.565000  1.885000  4.890000 2.385000 ;
-      RECT  4.565000  2.385000  6.955000 2.555000 ;
-      RECT  4.725000  0.435000  5.055000 1.175000 ;
-      RECT  4.725000  1.175000  6.555000 1.345000 ;
-      RECT  5.070000  3.485000  6.020000 3.735000 ;
-      RECT  5.255000  0.365000  6.205000 0.995000 ;
-      RECT  5.435000  1.875000  7.305000 2.045000 ;
-      RECT  5.435000  2.045000  5.765000 2.205000 ;
-      RECT  6.385000  0.265000  7.450000 0.435000 ;
-      RECT  6.385000  0.435000  6.555000 1.175000 ;
-      RECT  6.470000  2.755000  7.305000 2.955000 ;
-      RECT  6.705000  2.225000  6.955000 2.385000 ;
-      RECT  6.735000  0.615000  7.065000 1.875000 ;
-      RECT  7.135000  2.045000  7.305000 2.755000 ;
-      RECT  7.280000  0.435000  7.450000 1.125000 ;
-      RECT  7.280000  1.125000  7.655000 1.445000 ;
-      RECT  7.485000  1.445000  7.655000 2.225000 ;
-      RECT  7.485000  2.225000  8.250000 2.515000 ;
-      RECT  7.485000  2.515000  7.655000 3.135000 ;
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-      RECT  7.630000  0.855000  8.600000 0.945000 ;
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-      RECT  8.430000  2.445000  8.600000 2.695000 ;
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-      RECT 10.215000  2.005000 10.545000 3.735000 ;
-      RECT 10.690000  0.365000 11.280000 1.495000 ;
-      RECT 10.725000  2.195000 11.315000 3.735000 ;
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-      RECT  0.155000  3.985000  0.325000 4.155000 ;
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-      RECT  0.590000  0.395000  0.760000 0.565000 ;
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-      RECT  0.635000  3.985000  0.805000 4.155000 ;
-      RECT  0.930000  3.505000  1.100000 3.675000 ;
-      RECT  0.950000  0.395000  1.120000 0.565000 ;
-      RECT  1.115000 -0.085000  1.285000 0.085000 ;
-      RECT  1.115000  3.985000  1.285000 4.155000 ;
-      RECT  1.290000  3.505000  1.460000 3.675000 ;
-      RECT  1.310000  0.395000  1.480000 0.565000 ;
-      RECT  1.595000 -0.085000  1.765000 0.085000 ;
-      RECT  1.595000  3.985000  1.765000 4.155000 ;
-      RECT  2.075000 -0.085000  2.245000 0.085000 ;
-      RECT  2.075000  3.985000  2.245000 4.155000 ;
-      RECT  2.215000  0.395000  2.385000 0.565000 ;
-      RECT  2.250000  3.505000  2.420000 3.675000 ;
-      RECT  2.555000 -0.085000  2.725000 0.085000 ;
-      RECT  2.555000  3.985000  2.725000 4.155000 ;
-      RECT  2.575000  0.395000  2.745000 0.565000 ;
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-      RECT  3.035000  3.985000  3.205000 4.155000 ;
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-      RECT  3.995000  3.985000  4.165000 4.155000 ;
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-      RECT  9.530000  0.395000  9.700000 0.565000 ;
-      RECT  9.565000  3.505000  9.735000 3.675000 ;
-      RECT  9.755000 -0.085000  9.925000 0.085000 ;
-      RECT  9.755000  3.985000  9.925000 4.155000 ;
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-      RECT 10.235000  3.985000 10.405000 4.155000 ;
-      RECT 10.715000 -0.085000 10.885000 0.085000 ;
-      RECT 10.715000  3.985000 10.885000 4.155000 ;
-      RECT 10.720000  0.395000 10.890000 0.565000 ;
-      RECT 10.755000  3.505000 10.925000 3.675000 ;
-      RECT 11.080000  0.395000 11.250000 0.565000 ;
-      RECT 11.115000  3.505000 11.285000 3.675000 ;
-      RECT 11.195000 -0.085000 11.365000 0.085000 ;
-      RECT 11.195000  3.985000 11.365000 4.155000 ;
-      RECT 11.675000 -0.085000 11.845000 0.085000 ;
-      RECT 11.675000  3.985000 11.845000 4.155000 ;
-  END
-END sky130_fd_sc_hvl__dfxtp_1
-MACRO sky130_fd_sc_hvl__decap_4
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__decap_4 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  1.920000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 1.920000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 1.920000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 1.920000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 1.920000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT 0.000000 -0.085000 1.920000 0.085000 ;
-      RECT 0.000000  3.985000 1.920000 4.155000 ;
-      RECT 0.170000  0.365000 1.780000 0.845000 ;
-      RECT 0.250000  2.685000 1.700000 3.755000 ;
-      RECT 0.475000  0.845000 1.780000 1.250000 ;
-      RECT 0.475000  1.250000 0.805000 2.030000 ;
-      RECT 1.015000  1.700000 1.345000 2.685000 ;
-    LAYER mcon ;
-      RECT 0.155000 -0.085000 0.325000 0.085000 ;
-      RECT 0.155000  3.985000 0.325000 4.155000 ;
-      RECT 0.215000  0.395000 0.385000 0.565000 ;
-      RECT 0.495000  3.560000 0.665000 3.730000 ;
-      RECT 0.635000 -0.085000 0.805000 0.085000 ;
-      RECT 0.635000  3.985000 0.805000 4.155000 ;
-      RECT 0.655000  0.395000 0.825000 0.565000 ;
-      RECT 0.860000  3.560000 1.030000 3.730000 ;
-      RECT 1.095000  0.395000 1.265000 0.565000 ;
-      RECT 1.115000 -0.085000 1.285000 0.085000 ;
-      RECT 1.115000  3.985000 1.285000 4.155000 ;
-      RECT 1.300000  3.560000 1.470000 3.730000 ;
-      RECT 1.510000  0.395000 1.680000 0.565000 ;
-      RECT 1.595000 -0.085000 1.765000 0.085000 ;
-      RECT 1.595000  3.985000 1.765000 4.155000 ;
-  END
-END sky130_fd_sc_hvl__decap_4
-MACRO sky130_fd_sc_hvl__decap_8
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__decap_8 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  3.840000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 3.840000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 3.840000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 3.840000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 3.840000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT 0.000000 -0.085000 3.840000 0.085000 ;
-      RECT 0.000000  3.985000 3.840000 4.155000 ;
-      RECT 0.500000  2.680000 3.240000 3.750000 ;
-      RECT 0.575000  0.360000 3.305000 1.360000 ;
-      RECT 0.735000  1.360000 1.065000 2.025000 ;
-      RECT 1.470000  1.695000 1.800000 2.680000 ;
-      RECT 2.015000  1.360000 2.345000 2.025000 ;
-      RECT 2.750000  1.695000 3.080000 2.680000 ;
-    LAYER mcon ;
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-      RECT 0.635000 -0.085000 0.805000 0.085000 ;
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-      RECT 3.515000  3.985000 3.685000 4.155000 ;
-  END
-END sky130_fd_sc_hvl__decap_8
-MACRO sky130_fd_sc_hvl__o22a_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__o22a_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  5.280000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN A1
-    ANTENNAGATEAREA  1.125000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 1.420000 1.775000 2.150000 2.055000 ;
-        RECT 1.980000 1.400000 2.775000 1.570000 ;
-        RECT 1.980000 1.570000 2.150000 1.775000 ;
-        RECT 2.605000 1.230000 4.880000 1.400000 ;
-        RECT 3.035000 1.210000 3.710000 1.230000 ;
-        RECT 4.550000 1.400000 4.880000 2.015000 ;
-    END
-  END A1
-  PIN A2
-    ANTENNAGATEAREA  1.125000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 3.485000 1.580000 4.195000 1.910000 ;
-    END
-  END A2
-  PIN B1
-    ANTENNAGATEAREA  1.125000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 2.330000 1.750000 2.755000 2.120000 ;
-    END
-  END B1
-  PIN B2
-    ANTENNAGATEAREA  1.125000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 2.955000 1.580000 3.250000 2.120000 ;
-    END
-  END B2
-  PIN X
-    ANTENNADIFFAREA  0.641250 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 0.125000 0.495000 0.380000 3.755000 ;
-    END
-  END X
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 5.280000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 5.280000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 5.280000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 5.280000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT 0.000000 -0.085000 5.280000 0.085000 ;
-      RECT 0.000000  3.985000 5.280000 4.155000 ;
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-      RECT 2.255000  0.880000 2.855000 1.050000 ;
-      RECT 2.525000  0.615000 2.855000 0.880000 ;
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-      RECT 3.430000  2.175000 3.680000 2.300000 ;
-      RECT 3.430000  2.470000 3.680000 3.755000 ;
-      RECT 3.860000  2.195000 5.170000 3.735000 ;
-      RECT 3.890000  0.365000 5.190000 1.050000 ;
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-      RECT 0.155000  3.985000 0.325000 4.155000 ;
-      RECT 0.560000  0.395000 0.730000 0.565000 ;
-      RECT 0.560000  3.505000 0.730000 3.675000 ;
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-      RECT 0.920000  3.505000 1.090000 3.675000 ;
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-      RECT 1.115000  3.985000 1.285000 4.155000 ;
-      RECT 1.280000  0.395000 1.450000 0.565000 ;
-      RECT 1.280000  3.505000 1.450000 3.675000 ;
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-      RECT 1.595000  3.985000 1.765000 4.155000 ;
-      RECT 1.640000  3.505000 1.810000 3.675000 ;
-      RECT 2.000000  3.505000 2.170000 3.675000 ;
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-      RECT 2.075000  3.985000 2.245000 4.155000 ;
-      RECT 2.360000  3.505000 2.530000 3.675000 ;
-      RECT 2.555000 -0.085000 2.725000 0.085000 ;
-      RECT 2.555000  3.985000 2.725000 4.155000 ;
-      RECT 2.720000  3.505000 2.890000 3.675000 ;
-      RECT 3.035000 -0.085000 3.205000 0.085000 ;
-      RECT 3.035000  3.985000 3.205000 4.155000 ;
-      RECT 3.080000  3.505000 3.250000 3.675000 ;
-      RECT 3.515000 -0.085000 3.685000 0.085000 ;
-      RECT 3.515000  3.985000 3.685000 4.155000 ;
-      RECT 3.890000  3.505000 4.060000 3.675000 ;
-      RECT 3.915000  0.395000 4.085000 0.565000 ;
-      RECT 3.995000 -0.085000 4.165000 0.085000 ;
-      RECT 3.995000  3.985000 4.165000 4.155000 ;
-      RECT 4.250000  3.505000 4.420000 3.675000 ;
-      RECT 4.275000  0.395000 4.445000 0.565000 ;
-      RECT 4.475000 -0.085000 4.645000 0.085000 ;
-      RECT 4.475000  3.985000 4.645000 4.155000 ;
-      RECT 4.610000  3.505000 4.780000 3.675000 ;
-      RECT 4.635000  0.395000 4.805000 0.565000 ;
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-      RECT 4.955000  3.985000 5.125000 4.155000 ;
-      RECT 4.970000  3.505000 5.140000 3.675000 ;
-      RECT 4.995000  0.395000 5.165000 0.565000 ;
-  END
-END sky130_fd_sc_hvl__o22a_1
-MACRO sky130_fd_sc_hvl__sdfsbp_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__sdfsbp_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  20.16000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN D
-    ANTENNAGATEAREA  0.420000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 1.975000 1.845000 2.305000 2.355000 ;
-    END
-  END D
-  PIN Q
-    ANTENNADIFFAREA  0.498750 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 19.700000 0.495000 20.035000 1.325000 ;
-        RECT 19.700000 2.355000 20.035000 3.435000 ;
-        RECT 19.805000 1.325000 20.035000 2.355000 ;
-    END
-  END Q
-  PIN Q_N
-    ANTENNADIFFAREA  0.611250 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 17.405000 0.495000 17.785000 3.735000 ;
-    END
-  END Q_N
-  PIN SCD
-    ANTENNAGATEAREA  0.420000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 3.485000 0.810000 3.690000 2.150000 ;
-    END
-  END SCD
-  PIN SCE
-    ANTENNAGATEAREA  0.840000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 0.605000 1.495000 2.955000 1.665000 ;
-        RECT 0.605000 1.665000 1.795000 2.165000 ;
-        RECT 2.680000 1.095000 2.955000 1.495000 ;
-        RECT 2.680000 1.665000 2.955000 1.765000 ;
-    END
-  END SCE
-  PIN SET_B
-    ANTENNAGATEAREA  0.840000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 10.205000 1.210000 12.355000 1.380000 ;
-        RECT 12.185000 0.265000 14.170000 0.435000 ;
-        RECT 12.185000 0.435000 12.355000 1.210000 ;
-        RECT 14.000000 0.435000 14.170000 1.425000 ;
-        RECT 14.000000 1.425000 14.845000 1.645000 ;
-    END
-  END SET_B
-  PIN CLK
-    ANTENNAGATEAREA  0.585000 ;
-    DIRECTION INPUT ;
-    USE CLOCK ;
-    PORT
-      LAYER li1 ;
-        RECT 4.380000 1.180000 4.710000 2.150000 ;
-    END
-  END CLK
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 20.160000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
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-      RECT 12.295000  2.175000 13.245000 3.755000 ;
-      RECT 12.315000  0.365000 13.265000 1.485000 ;
-    LAYER mcon ;
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-      RECT  0.600000  3.505000  0.770000 3.675000 ;
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-      RECT  2.470000  3.505000  2.640000 3.675000 ;
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-      RECT  4.475000  3.985000  4.645000 4.155000 ;
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-      RECT 10.235000  3.985000 10.405000 4.155000 ;
-      RECT 10.715000 -0.085000 10.885000 0.085000 ;
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-      RECT 11.675000 -0.085000 11.845000 0.085000 ;
-      RECT 11.675000  3.985000 11.845000 4.155000 ;
-      RECT 12.155000 -0.085000 12.325000 0.085000 ;
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-      RECT 12.325000  3.505000 12.495000 3.675000 ;
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-      RECT 12.635000 -0.085000 12.805000 0.085000 ;
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-      RECT 12.705000  0.395000 12.875000 0.565000 ;
-      RECT 13.045000  3.505000 13.215000 3.675000 ;
-      RECT 13.065000  0.395000 13.235000 0.565000 ;
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-      RECT 13.115000  3.985000 13.285000 4.155000 ;
-      RECT 13.595000 -0.085000 13.765000 0.085000 ;
-      RECT 13.595000  3.985000 13.765000 4.155000 ;
-  END
-END sky130_fd_sc_hvl__dfxbp_1
-MACRO sky130_fd_sc_hvl__dlclkp_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__dlclkp_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  10.08000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN GATE
-    ANTENNAGATEAREA  0.585000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 0.610000 1.385000 0.940000 2.200000 ;
-    END
-  END GATE
-  PIN GCLK
-    ANTENNADIFFAREA  0.596250 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 9.630000 0.515000 9.995000 1.215000 ;
-        RECT 9.630000 1.895000 9.995000 3.735000 ;
-        RECT 9.725000 1.215000 9.995000 1.895000 ;
-    END
-  END GCLK
-  PIN CLK
-    ANTENNAGATEAREA  1.170000 ;
-    DIRECTION INPUT ;
-    USE CLOCK ;
-    PORT
-      LAYER li1 ;
-        RECT 3.360000 1.465000 3.690000 1.975000 ;
-        RECT 8.235000 3.125000 8.600000 3.445000 ;
-        RECT 8.350000 1.725000 8.680000 2.025000 ;
-        RECT 8.350000 2.025000 8.600000 3.125000 ;
-    END
-  END CLK
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 10.080000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 10.080000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 10.080000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 10.080000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
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-      RECT 0.110000  2.200000  0.440000 3.445000 ;
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-      RECT 0.110000  3.555000  3.330000 3.815000 ;
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-      RECT 3.860000  3.005000  5.175000 3.215000 ;
-      RECT 4.095000  0.255000  4.660000 0.535000 ;
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-      RECT 4.375000  1.195000  6.490000 1.365000 ;
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-      RECT 4.375000  2.330000  4.660000 2.660000 ;
-      RECT 4.715000  1.615000  5.305000 1.945000 ;
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-      RECT 9.260000  0.425000 9.430000 0.595000 ;
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-      RECT 9.755000 -0.085000 9.925000 0.085000 ;
-      RECT 9.755000  3.985000 9.925000 4.155000 ;
-  END
-END sky130_fd_sc_hvl__dlclkp_1
-MACRO sky130_fd_sc_hvl__lsbufhv2hv_lh_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__lsbufhv2hv_lh_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  10.56000 BY  8.140000 ;
-  SYMMETRY X Y ;
-  SITE unithvdbl ;
-  PIN A
-    ANTENNAGATEAREA  0.750000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 2.495000 1.530000 2.805000 2.200000 ;
-    END
-  END A
-  PIN X
-    ANTENNADIFFAREA  0.596250 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 10.120000 4.405000 10.450000 7.625000 ;
-    END
-  END X
-  PIN LOWHVPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.070000 3.020000 10.490000 3.305000 ;
-    END
-  END LOWHVPWR
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 7.515000 10.560000 7.885000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 8.025000 10.560000 8.255000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 10.560000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 4.325000 10.560000 4.695000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT 0.000000 -0.085000 10.560000 0.085000 ;
-      RECT 0.000000  3.985000  0.800000 4.155000 ;
-      RECT 0.000000  8.055000 10.560000 8.225000 ;
-      RECT 3.090000  0.685000  3.420000 1.745000 ;
-      RECT 3.090000  1.745000  4.845000 1.995000 ;
-      RECT 3.090000  1.995000  3.420000 5.165000 ;
-      RECT 3.090000  5.165000  5.660000 5.495000 ;
-      RECT 3.300000  6.085000  3.890000 7.715000 ;
-      RECT 3.300000  7.715000  7.010000 7.885000 ;
-      RECT 3.590000  3.355000  4.780000 4.025000 ;
-      RECT 3.740000  0.255000  9.540000 0.425000 ;
-      RECT 3.740000  0.425000  4.330000 1.475000 ;
-      RECT 3.740000  2.325000  4.330000 3.355000 ;
-      RECT 4.210000  5.665000  7.930000 5.995000 ;
-      RECT 4.210000  5.995000  4.540000 7.545000 ;
-      RECT 4.650000  0.685000  4.980000 1.145000 ;
-      RECT 4.650000  1.145000  5.660000 1.475000 ;
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-      RECT 5.830000  0.425000  6.420000 1.975000 ;
-      RECT 6.420000  6.165000  7.010000 7.715000 ;
-      RECT 6.740000  0.595000  7.070000 2.145000 ;
-      RECT 6.740000  2.145000  8.630000 2.475000 ;
-      RECT 7.375000  3.605000  8.045000 3.935000 ;
-      RECT 7.390000  0.425000  7.980000 1.975000 ;
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-  CLASS CORE ;
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-  CLASS CORE ;
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-      RECT 14.555000  3.985000 14.725000 4.155000 ;
-  END
-END sky130_fd_sc_hvl__dfstp_1
-MACRO sky130_fd_sc_hvl__probec_p_8
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__probec_p_8 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  9.600000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN A
-    ANTENNAGATEAREA  3.375000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 0.635000 1.580000 2.245000 1.815000 ;
-    END
-  END A
-  PIN X
-    ANTENNADIFFAREA  2.520000 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met4 ;
-        RECT 2.410000 1.445000 3.590000 2.625000 ;
-        RECT 5.010000 1.445000 6.190000 2.625000 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT 2.290000  1.235000 6.310000 2.835000 ;
-        RECT 4.710000 -0.365000 6.310000 1.235000 ;
-        RECT 4.710000  2.835000 6.310000 4.435000 ;
-    END
-  END X
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met5 ;
-        RECT 7.910000 -0.365000 10.410000 1.235000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 9.600000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 9.600000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met5 ;
-        RECT 7.910000 2.835000 10.410000 4.435000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
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-      RECT 1.695000  3.475000 1.865000 3.645000 ;
-      RECT 1.755000  0.380000 1.925000 0.550000 ;
-      RECT 2.075000 -0.085000 2.245000 0.085000 ;
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-      RECT 7.945000  3.475000 8.115000 3.645000 ;
-      RECT 7.955000  0.380000 8.125000 0.550000 ;
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-      RECT 9.640000 0.265000 9.960000 0.585000 ;
-      RECT 9.640000 3.485000 9.960000 3.805000 ;
-  END
-END sky130_fd_sc_hvl__probec_p_8
-MACRO sky130_fd_sc_hvl__a21o_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__a21o_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  4.320000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN A1
-    ANTENNAGATEAREA  1.125000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 2.805000 1.505000 3.715000 1.835000 ;
-    END
-  END A1
-  PIN A2
-    ANTENNAGATEAREA  1.125000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 3.895000 1.505000 4.195000 1.835000 ;
-    END
-  END A2
-  PIN B1
-    ANTENNAGATEAREA  1.125000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 1.085000 1.505000 2.275000 1.750000 ;
-    END
-  END B1
-  PIN X
-    ANTENNADIFFAREA  0.611250 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 0.110000 0.495000 0.460000 1.325000 ;
-        RECT 0.110000 1.325000 0.360000 3.735000 ;
-    END
-  END X
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 4.320000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 4.320000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 4.320000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 4.320000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
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-      RECT 3.995000  3.985000 4.165000 4.155000 ;
-  END
-END sky130_fd_sc_hvl__a21o_1
-MACRO sky130_fd_sc_hvl__xor2_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__xor2_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  5.280000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN A
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-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 2.045000 1.775000 3.235000 2.150000 ;
-    END
-  END A
-  PIN B
-    ANTENNAGATEAREA  2.250000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
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-        RECT 1.340000 1.595000 1.510000 1.775000 ;
-        RECT 3.415000 1.595000 3.715000 1.835000 ;
-    END
-  END B
-  PIN X
-    ANTENNADIFFAREA  0.637500 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 3.850000 0.495000 4.370000 1.325000 ;
-        RECT 3.965000 1.325000 4.370000 2.425000 ;
-    END
-  END X
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 5.280000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 5.280000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
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-    END
-  END VPB
-  PIN VPWR
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-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 5.280000 3.815000 ;
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-  END VPWR
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-      RECT  9.695000  3.080000  9.865000 3.250000 ;
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-      RECT 11.195000  8.055000 11.365000 8.225000 ;
-      RECT 11.675000 -0.085000 11.845000 0.085000 ;
-      RECT 11.675000  8.055000 11.845000 8.225000 ;
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-      RECT 12.155000  8.055000 12.325000 8.225000 ;
-      RECT 12.635000 -0.085000 12.805000 0.085000 ;
-      RECT 12.635000  8.055000 12.805000 8.225000 ;
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-      RECT 13.115000  8.055000 13.285000 8.225000 ;
-      RECT 13.595000 -0.085000 13.765000 0.085000 ;
-      RECT 13.595000  8.055000 13.765000 8.225000 ;
-    LAYER met1 ;
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-      RECT 0.000000  0.255000 13.920000 0.625000 ;
-      RECT 0.000000  3.445000 13.920000 3.815000 ;
-  END
-END sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1
-MACRO sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  11.04000 BY  8.140000 ;
-  SYMMETRY X Y ;
-  SITE unithvdbl ;
-  PIN A
-    ANTENNAGATEAREA  0.252000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 2.495000 1.530000 2.805000 2.200000 ;
-    END
-  END A
-  PIN X
-    ANTENNADIFFAREA  0.596250 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 10.600000 4.405000 10.930000 6.055000 ;
-        RECT 10.600000 6.725000 10.930000 7.625000 ;
-        RECT 10.690000 6.055000 10.930000 6.725000 ;
-    END
-  END X
-  PIN LVPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.070000 3.020000 10.970000 3.305000 ;
-    END
-  END LVPWR
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 7.515000 11.040000 7.885000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 8.025000 11.040000 8.255000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 11.040000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 4.325000 11.040000 4.695000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
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-      RECT  0.000000  8.055000 11.040000 8.225000 ;
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-      RECT  2.885000  3.055000  3.175000 5.495000 ;
-      RECT  2.975000  0.735000  3.265000 1.745000 ;
-      RECT  2.975000  1.745000  4.310000 1.995000 ;
-      RECT  2.975000  1.995000  3.265000 2.765000 ;
-      RECT  3.095000  0.335000  4.045000 0.565000 ;
-      RECT  3.145000  6.165000  3.735000 7.715000 ;
-      RECT  3.145000  7.715000  5.295000 7.885000 ;
-      RECT  3.345000  3.225000  4.115000 4.200000 ;
-      RECT  3.435000  0.565000  3.705000 1.575000 ;
-      RECT  3.435000  2.165000  3.705000 3.075000 ;
-      RECT  3.435000  3.075000  4.115000 3.225000 ;
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-      RECT  4.055000  5.995000  4.385000 7.545000 ;
-      RECT  4.480000  1.575000  4.810000 2.145000 ;
-      RECT  4.480000  2.145000  5.790000 2.165000 ;
-      RECT  4.705000  6.165000  5.295000 7.715000 ;
-      RECT  5.050000  0.255000  7.200000 0.425000 ;
-      RECT  5.050000  0.425000  5.640000 1.975000 ;
-      RECT  5.960000  0.595000  6.290000 2.145000 ;
-      RECT  5.960000  2.145000  7.850000 2.325000 ;
-      RECT  6.565000  2.795000  6.895000 4.405000 ;
-      RECT  6.565000  4.405000  7.025000 4.735000 ;
-      RECT  6.610000  0.425000  7.200000 1.975000 ;
-      RECT  6.695000  4.735000  7.025000 5.665000 ;
-      RECT  6.695000  5.995000  7.025000 6.285000 ;
-      RECT  6.695000  6.285000  8.815000 6.615000 ;
-      RECT  7.095000  2.495000  9.835000 2.705000 ;
-      RECT  7.095000  2.705000  7.765000 4.215000 ;
-      RECT  7.390000  4.405000  7.980000 5.945000 ;
-      RECT  7.520000  0.255000  9.410000 0.425000 ;
-      RECT  7.520000  0.425000  7.850000 2.145000 ;
-      RECT  7.955000  2.875000  8.545000 3.705000 ;
-      RECT  8.170000  0.595000  8.760000 2.495000 ;
-      RECT  8.235000  3.985000 11.040000 4.155000 ;
-      RECT  8.300000  4.405000  8.630000 6.285000 ;
-      RECT  8.535000  6.615000  8.815000 6.955000 ;
-      RECT  8.915000  2.705000  9.835000 3.465000 ;
-      RECT  8.995000  4.405000  9.325000 6.225000 ;
-      RECT  8.995000  6.225000 10.520000 6.555000 ;
-      RECT  8.995000  6.555000  9.325000 7.625000 ;
-      RECT  9.080000  0.425000  9.410000 2.055000 ;
-      RECT  9.690000  4.405000 10.280000 5.945000 ;
-      RECT  9.690000  6.835000 10.280000 7.745000 ;
-      RECT 10.125000  2.795000 10.715000 3.705000 ;
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-      RECT  0.155000  3.985000  0.325000 4.155000 ;
-      RECT  0.155000  8.055000  0.325000 8.225000 ;
-      RECT  0.635000 -0.085000  0.805000 0.085000 ;
-      RECT  0.635000  8.055000  0.805000 8.225000 ;
-      RECT  1.115000 -0.085000  1.285000 0.085000 ;
-      RECT  1.115000  8.055000  1.285000 8.225000 ;
-      RECT  1.595000 -0.085000  1.765000 0.085000 ;
-      RECT  1.595000  8.055000  1.765000 8.225000 ;
-      RECT  2.075000 -0.085000  2.245000 0.085000 ;
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-      RECT  2.555000 -0.085000  2.725000 0.085000 ;
-      RECT  2.555000  8.055000  2.725000 8.225000 ;
-      RECT  3.035000 -0.085000  3.205000 0.085000 ;
-      RECT  3.035000  8.055000  3.205000 8.225000 ;
-      RECT  3.125000  0.365000  3.295000 0.535000 ;
-      RECT  3.175000  7.545000  3.345000 7.715000 ;
-      RECT  3.485000  0.425000  3.655000 0.595000 ;
-      RECT  3.485000  3.050000  3.655000 3.220000 ;
-      RECT  3.515000 -0.085000  3.685000 0.085000 ;
-      RECT  3.515000  8.055000  3.685000 8.225000 ;
-      RECT  3.535000  7.545000  3.705000 7.715000 ;
-      RECT  3.845000  0.365000  4.015000 0.535000 ;
-      RECT  3.845000  3.105000  4.015000 3.275000 ;
-      RECT  3.995000 -0.085000  4.165000 0.085000 ;
-      RECT  3.995000  8.055000  4.165000 8.225000 ;
-      RECT  4.475000 -0.085000  4.645000 0.085000 ;
-      RECT  4.475000  8.055000  4.645000 8.225000 ;
-      RECT  4.735000  7.545000  4.905000 7.715000 ;
-      RECT  4.955000 -0.085000  5.125000 0.085000 ;
-      RECT  4.955000  8.055000  5.125000 8.225000 ;
-      RECT  5.080000  0.425000  5.250000 0.595000 ;
-      RECT  5.095000  7.545000  5.265000 7.715000 ;
-      RECT  5.435000 -0.085000  5.605000 0.085000 ;
-      RECT  5.435000  8.055000  5.605000 8.225000 ;
-      RECT  5.440000  0.425000  5.610000 0.595000 ;
-      RECT  5.915000 -0.085000  6.085000 0.085000 ;
-      RECT  5.915000  8.055000  6.085000 8.225000 ;
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-      RECT  6.395000  8.055000  6.565000 8.225000 ;
-      RECT  6.640000  0.425000  6.810000 0.595000 ;
-      RECT  6.875000 -0.085000  7.045000 0.085000 ;
-      RECT  6.875000  8.055000  7.045000 8.225000 ;
-      RECT  7.000000  0.425000  7.170000 0.595000 ;
-      RECT  7.355000 -0.085000  7.525000 0.085000 ;
-      RECT  7.355000  8.055000  7.525000 8.225000 ;
-      RECT  7.420000  4.495000  7.590000 4.665000 ;
-      RECT  7.780000  4.495000  7.950000 4.665000 ;
-      RECT  7.835000 -0.085000  8.005000 0.085000 ;
-      RECT  7.835000  8.055000  8.005000 8.225000 ;
-      RECT  7.985000  3.475000  8.155000 3.645000 ;
-      RECT  8.315000 -0.085000  8.485000 0.085000 ;
-      RECT  8.315000  3.985000  8.485000 4.155000 ;
-      RECT  8.315000  8.055000  8.485000 8.225000 ;
-      RECT  8.345000  3.475000  8.515000 3.645000 ;
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-      RECT  9.275000  8.055000  9.445000 8.225000 ;
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-      RECT  9.720000  7.545000  9.890000 7.715000 ;
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-      RECT  9.755000  3.985000  9.925000 4.155000 ;
-      RECT  9.755000  8.055000  9.925000 8.225000 ;
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-      RECT 0.000000  3.445000 11.040000 3.815000 ;
-  END
-END sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1
-MACRO sky130_fd_sc_hvl__and3_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__and3_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  3.840000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN A
-    ANTENNAGATEAREA  0.420000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 0.605000 0.810000 0.935000 1.645000 ;
-    END
-  END A
-  PIN B
-    ANTENNAGATEAREA  0.420000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 0.605000 2.175000 1.565000 2.490000 ;
-    END
-  END B
-  PIN C
-    ANTENNAGATEAREA  0.420000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 1.115000 0.810000 2.255000 1.645000 ;
-    END
-  END C
-  PIN X
-    ANTENNADIFFAREA  0.626250 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 3.365000 2.175000 3.715000 3.755000 ;
-        RECT 3.410000 0.495000 3.715000 2.175000 ;
-    END
-  END X
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 3.840000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 3.840000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 3.840000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 3.840000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
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-      RECT 0.000000  3.985000 3.840000 4.155000 ;
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-      RECT 0.560000  2.670000 1.510000 3.705000 ;
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-      RECT 2.200000  2.175000 3.150000 3.755000 ;
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-      RECT 2.555000  3.985000 2.725000 4.155000 ;
-      RECT 2.590000  3.505000 2.760000 3.675000 ;
-      RECT 2.950000  3.505000 3.120000 3.675000 ;
-      RECT 3.015000  0.395000 3.185000 0.565000 ;
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-      RECT 3.515000 -0.085000 3.685000 0.085000 ;
-      RECT 3.515000  3.985000 3.685000 4.155000 ;
-  END
-END sky130_fd_sc_hvl__and3_1
-MACRO sky130_fd_sc_hvl__lsbufhv2lv_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__lsbufhv2lv_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  8.160000 BY  8.140000 ;
-  SYMMETRY X Y ;
-  SITE unithvdbl ;
-  PIN A
-    ANTENNAGATEAREA  0.420000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 0.630000 4.870000 1.300000 5.200000 ;
-    END
-  END A
-  PIN X
-    ANTENNADIFFAREA  0.492900 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 3.485000 0.735000 3.960000 3.245000 ;
-    END
-  END X
-  PIN LVPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.070000 3.020000 8.090000 3.305000 ;
-    END
-  END LVPWR
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 7.515000 8.160000 7.885000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 8.025000 8.160000 8.255000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 8.160000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 4.325000 8.160000 4.695000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
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-      RECT 0.170000  1.565000 1.750000 1.895000 ;
-      RECT 0.170000  6.220000 1.750000 6.575000 ;
-      RECT 0.170000  6.575000 0.420000 7.060000 ;
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-      RECT 4.130000  3.075000 4.750000 3.415000 ;
-      RECT 4.130000  4.085000 4.400000 5.415000 ;
-      RECT 4.570000  2.085000 4.820000 2.655000 ;
-      RECT 4.570000  2.655000 5.170000 2.905000 ;
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-        RECT 10.905000 0.435000 11.075000 0.960000 ;
-        RECT 10.905000 0.960000 11.840000 1.130000 ;
-        RECT 11.510000 1.130000 11.840000 1.350000 ;
-    END
-  END RESET_B
-  PIN CLK
-    ANTENNAGATEAREA  0.585000 ;
-    DIRECTION INPUT ;
-    USE CLOCK ;
-    PORT
-      LAYER li1 ;
-        RECT 0.595000 1.175000 0.925000 1.720000 ;
-    END
-  END CLK
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 16.800000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 16.800000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 16.800000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 16.800000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT  0.000000 -0.085000 16.800000 0.085000 ;
-      RECT  0.000000  3.985000 16.800000 4.155000 ;
-      RECT  0.165000  0.495000  0.495000 0.995000 ;
-      RECT  0.165000  0.995000  0.415000 2.275000 ;
-      RECT  0.165000  2.275000  1.835000 2.445000 ;
-      RECT  0.165000  2.445000  0.415000 3.455000 ;
-      RECT  0.595000  2.625000  1.485000 3.705000 ;
-      RECT  0.675000  0.365000  1.625000 0.995000 ;
-      RECT  1.505000  1.900000  1.835000 2.275000 ;
-      RECT  1.665000  2.445000  1.835000 3.635000 ;
-      RECT  1.665000  3.635000  3.205000 3.805000 ;
-      RECT  1.805000  0.495000  2.185000 0.995000 ;
-      RECT  2.015000  0.995000  2.185000 1.550000 ;
-      RECT  2.015000  1.550000  2.275000 3.455000 ;
-      RECT  2.365000  0.365000  3.315000 1.325000 ;
-      RECT  2.525000  2.300000  4.515000 2.470000 ;
-      RECT  2.525000  2.470000  2.855000 3.420000 ;
-      RECT  3.035000  2.650000  3.905000 2.820000 ;
-      RECT  3.035000  2.820000  3.205000 3.635000 ;
-      RECT  3.385000  3.000000  3.555000 3.705000 ;
-      RECT  3.735000  2.820000  3.905000 3.600000 ;
-      RECT  3.735000  3.600000  5.565000 3.770000 ;
-      RECT  4.085000  3.000000  4.515000 3.420000 ;
-      RECT  4.345000  0.825000  4.655000 1.325000 ;
-      RECT  4.345000  1.325000  4.515000 2.300000 ;
-      RECT  4.345000  2.470000  4.515000 3.000000 ;
-      RECT  4.695000  1.505000  5.925000 1.780000 ;
-      RECT  4.695000  1.780000  4.865000 2.820000 ;
-      RECT  4.865000  3.000000  5.215000 3.420000 ;
-      RECT  5.045000  2.200000  6.275000 2.370000 ;
-      RECT  5.045000  2.370000  5.215000 3.000000 ;
-      RECT  5.270000  0.825000  5.600000 1.155000 ;
-      RECT  5.270000  1.155000  6.275000 1.325000 ;
-      RECT  5.395000  2.550000  5.650000 2.875000 ;
-      RECT  5.395000  2.875000  7.035000 3.045000 ;
-      RECT  5.395000  3.045000  5.565000 3.600000 ;
-      RECT  5.595000  1.780000  5.925000 2.020000 ;
-      RECT  5.745000  3.225000  6.685000 3.705000 ;
-      RECT  6.105000  1.325000  6.275000 1.475000 ;
-      RECT  6.105000  1.475000  8.165000 1.645000 ;
-      RECT  6.105000  1.645000  6.275000 2.200000 ;
-      RECT  6.105000  2.370000  6.275000 2.525000 ;
-      RECT  6.105000  2.525000  7.385000 2.695000 ;
-      RECT  6.455000  1.825000  6.785000 2.175000 ;
-      RECT  6.455000  2.175000  9.025000 2.345000 ;
-      RECT  6.865000  3.045000  7.035000 3.635000 ;
-      RECT  6.865000  3.635000  7.735000 3.805000 ;
-      RECT  7.215000  0.365000  8.165000 0.945000 ;
-      RECT  7.215000  2.695000  7.385000 3.455000 ;
-      RECT  7.565000  2.700000  9.375000 2.870000 ;
-      RECT  7.565000  2.870000  7.735000 3.635000 ;
-      RECT  7.915000  3.050000  8.865000 3.705000 ;
-      RECT  8.695000  0.615000  9.025000 2.175000 ;
-      RECT  8.695000  2.345000  9.025000 2.520000 ;
-      RECT  9.205000  1.230000 10.375000 1.400000 ;
-      RECT  9.205000  1.400000  9.375000 2.700000 ;
-      RECT  9.555000  2.270000 10.410000 2.440000 ;
-      RECT  9.555000  2.440000  9.805000 3.350000 ;
-      RECT  9.580000  0.615000 10.725000 0.785000 ;
-      RECT  9.580000  0.785000  9.910000 0.995000 ;
-      RECT  9.725000  1.580000 10.060000 2.090000 ;
-      RECT 10.090000  1.070000 10.375000 1.230000 ;
-      RECT 10.240000  2.000000 12.530000 2.170000 ;
-      RECT 10.240000  2.170000 10.410000 2.270000 ;
-      RECT 10.555000  0.785000 10.725000 2.000000 ;
-      RECT 10.590000  2.350000 11.540000 3.705000 ;
-      RECT 10.930000  1.310000 11.260000 1.530000 ;
-      RECT 10.930000  1.530000 12.880000 1.700000 ;
-      RECT 10.930000  1.700000 11.260000 1.820000 ;
-      RECT 11.255000  0.365000 12.205000 0.780000 ;
-      RECT 11.965000  2.350000 12.880000 2.520000 ;
-      RECT 11.965000  2.520000 12.295000 2.770000 ;
-      RECT 12.200000  1.880000 12.530000 2.000000 ;
-      RECT 12.710000  0.515000 13.075000 0.975000 ;
-      RECT 12.710000  0.975000 12.880000 1.530000 ;
-      RECT 12.710000  1.700000 12.880000 2.350000 ;
-      RECT 13.060000  2.175000 13.950000 3.755000 ;
-      RECT 13.255000  0.365000 13.845000 1.495000 ;
-      RECT 14.665000  0.825000 15.015000 1.505000 ;
-      RECT 14.665000  1.505000 16.160000 1.835000 ;
-      RECT 14.665000  1.835000 14.995000 3.005000 ;
-      RECT 15.175000  2.175000 16.125000 3.755000 ;
-      RECT 15.195000  0.365000 16.145000 1.325000 ;
-    LAYER mcon ;
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-      RECT  0.155000  3.985000  0.325000 4.155000 ;
-      RECT  0.595000  3.505000  0.765000 3.675000 ;
-      RECT  0.635000 -0.085000  0.805000 0.085000 ;
-      RECT  0.635000  3.985000  0.805000 4.155000 ;
-      RECT  0.705000  0.395000  0.875000 0.565000 ;
-      RECT  0.955000  3.505000  1.125000 3.675000 ;
-      RECT  1.065000  0.395000  1.235000 0.565000 ;
-      RECT  1.115000 -0.085000  1.285000 0.085000 ;
-      RECT  1.115000  3.985000  1.285000 4.155000 ;
-      RECT  1.315000  3.505000  1.485000 3.675000 ;
-      RECT  1.425000  0.395000  1.595000 0.565000 ;
-      RECT  1.595000 -0.085000  1.765000 0.085000 ;
-      RECT  1.595000  3.985000  1.765000 4.155000 ;
-      RECT  2.075000 -0.085000  2.245000 0.085000 ;
-      RECT  2.075000  1.580000  2.245000 1.750000 ;
-      RECT  2.075000  3.985000  2.245000 4.155000 ;
-      RECT  2.395000  0.395000  2.565000 0.565000 ;
-      RECT  2.555000 -0.085000  2.725000 0.085000 ;
-      RECT  2.555000  3.985000  2.725000 4.155000 ;
-      RECT  2.755000  0.395000  2.925000 0.565000 ;
-      RECT  3.035000 -0.085000  3.205000 0.085000 ;
-      RECT  3.035000  3.985000  3.205000 4.155000 ;
-      RECT  3.115000  0.395000  3.285000 0.565000 ;
-      RECT  3.385000  3.505000  3.555000 3.675000 ;
-      RECT  3.515000 -0.085000  3.685000 0.085000 ;
-      RECT  3.515000  3.985000  3.685000 4.155000 ;
-      RECT  3.995000 -0.085000  4.165000 0.085000 ;
-      RECT  3.995000  3.985000  4.165000 4.155000 ;
-      RECT  4.475000 -0.085000  4.645000 0.085000 ;
-      RECT  4.475000  3.985000  4.645000 4.155000 ;
-      RECT  4.955000 -0.085000  5.125000 0.085000 ;
-      RECT  4.955000  1.580000  5.125000 1.750000 ;
-      RECT  4.955000  3.985000  5.125000 4.155000 ;
-      RECT  5.435000 -0.085000  5.605000 0.085000 ;
-      RECT  5.435000  3.985000  5.605000 4.155000 ;
-      RECT  5.770000  3.505000  5.940000 3.675000 ;
-      RECT  5.915000 -0.085000  6.085000 0.085000 ;
-      RECT  5.915000  3.985000  6.085000 4.155000 ;
-      RECT  6.130000  3.505000  6.300000 3.675000 ;
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-      RECT  6.395000  3.985000  6.565000 4.155000 ;
-      RECT  6.490000  3.505000  6.660000 3.675000 ;
-      RECT  6.875000 -0.085000  7.045000 0.085000 ;
-      RECT  6.875000  3.985000  7.045000 4.155000 ;
-      RECT  7.245000  0.395000  7.415000 0.565000 ;
-      RECT  7.355000 -0.085000  7.525000 0.085000 ;
-      RECT  7.355000  3.985000  7.525000 4.155000 ;
-      RECT  7.605000  0.395000  7.775000 0.565000 ;
-      RECT  7.835000 -0.085000  8.005000 0.085000 ;
-      RECT  7.835000  3.985000  8.005000 4.155000 ;
-      RECT  7.945000  3.505000  8.115000 3.675000 ;
-      RECT  7.965000  0.395000  8.135000 0.565000 ;
-      RECT  8.305000  3.505000  8.475000 3.675000 ;
-      RECT  8.315000 -0.085000  8.485000 0.085000 ;
-      RECT  8.315000  3.985000  8.485000 4.155000 ;
-      RECT  8.665000  3.505000  8.835000 3.675000 ;
-      RECT  8.795000 -0.085000  8.965000 0.085000 ;
-      RECT  8.795000  3.985000  8.965000 4.155000 ;
-      RECT  9.275000 -0.085000  9.445000 0.085000 ;
-      RECT  9.275000  3.985000  9.445000 4.155000 ;
-      RECT  9.755000 -0.085000  9.925000 0.085000 ;
-      RECT  9.755000  1.580000  9.925000 1.750000 ;
-      RECT  9.755000  3.985000  9.925000 4.155000 ;
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-      RECT 11.340000  3.505000 11.510000 3.675000 ;
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-      RECT 11.675000  3.985000 11.845000 4.155000 ;
-      RECT 12.005000  0.395000 12.175000 0.565000 ;
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-      RECT 12.635000 -0.085000 12.805000 0.085000 ;
-      RECT 12.635000  3.985000 12.805000 4.155000 ;
-      RECT 13.060000  3.505000 13.230000 3.675000 ;
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-      RECT 13.115000  3.985000 13.285000 4.155000 ;
-      RECT 13.285000  0.395000 13.455000 0.565000 ;
-      RECT 13.420000  3.505000 13.590000 3.675000 ;
-      RECT 13.595000 -0.085000 13.765000 0.085000 ;
-      RECT 13.595000  3.985000 13.765000 4.155000 ;
-      RECT 13.645000  0.395000 13.815000 0.565000 ;
-      RECT 13.780000  3.505000 13.950000 3.675000 ;
-      RECT 14.075000 -0.085000 14.245000 0.085000 ;
-      RECT 14.075000  3.985000 14.245000 4.155000 ;
-      RECT 14.555000 -0.085000 14.725000 0.085000 ;
-      RECT 14.555000  3.985000 14.725000 4.155000 ;
-      RECT 15.035000 -0.085000 15.205000 0.085000 ;
-      RECT 15.035000  3.985000 15.205000 4.155000 ;
-      RECT 15.205000  3.505000 15.375000 3.675000 ;
-      RECT 15.225000  0.395000 15.395000 0.565000 ;
-      RECT 15.515000 -0.085000 15.685000 0.085000 ;
-      RECT 15.515000  3.985000 15.685000 4.155000 ;
-      RECT 15.565000  3.505000 15.735000 3.675000 ;
-      RECT 15.585000  0.395000 15.755000 0.565000 ;
-      RECT 15.925000  3.505000 16.095000 3.675000 ;
-      RECT 15.945000  0.395000 16.115000 0.565000 ;
-      RECT 15.995000 -0.085000 16.165000 0.085000 ;
-      RECT 15.995000  3.985000 16.165000 4.155000 ;
-      RECT 16.475000 -0.085000 16.645000 0.085000 ;
-      RECT 16.475000  3.985000 16.645000 4.155000 ;
-    LAYER met1 ;
-      RECT 2.015000 1.550000 2.305000 1.595000 ;
-      RECT 2.015000 1.595000 9.985000 1.735000 ;
-      RECT 2.015000 1.735000 2.305000 1.780000 ;
-      RECT 4.895000 1.550000 5.185000 1.595000 ;
-      RECT 4.895000 1.735000 5.185000 1.780000 ;
-      RECT 9.695000 1.550000 9.985000 1.595000 ;
-      RECT 9.695000 1.735000 9.985000 1.780000 ;
-  END
-END sky130_fd_sc_hvl__dfrbp_1
-MACRO sky130_fd_sc_hvl__fill_1
-  CLASS CORE SPACER ;
-  FOREIGN sky130_fd_sc_hvl__fill_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  0.480000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 0.480000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER li1 ;
-        RECT 0.000000 -0.085000 0.480000 0.085000 ;
-      LAYER mcon ;
-        RECT 0.155000 -0.085000 0.325000 0.085000 ;
-    END
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 0.480000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER li1 ;
-        RECT 0.000000 3.985000 0.480000 4.155000 ;
-      LAYER mcon ;
-        RECT 0.155000 3.985000 0.325000 4.155000 ;
-    END
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 0.480000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 0.480000 3.815000 ;
-    END
-  END VPWR
-END sky130_fd_sc_hvl__fill_1
-MACRO sky130_fd_sc_hvl__fill_4
-  CLASS CORE SPACER ;
-  FOREIGN sky130_fd_sc_hvl__fill_4 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  1.920000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 1.920000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 1.920000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 1.920000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 1.920000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT 0.000000 -0.085000 1.920000 0.085000 ;
-      RECT 0.000000  3.985000 1.920000 4.155000 ;
-    LAYER mcon ;
-      RECT 0.155000 -0.085000 0.325000 0.085000 ;
-      RECT 0.155000  3.985000 0.325000 4.155000 ;
-      RECT 0.635000 -0.085000 0.805000 0.085000 ;
-      RECT 0.635000  3.985000 0.805000 4.155000 ;
-      RECT 1.115000 -0.085000 1.285000 0.085000 ;
-      RECT 1.115000  3.985000 1.285000 4.155000 ;
-      RECT 1.595000 -0.085000 1.765000 0.085000 ;
-      RECT 1.595000  3.985000 1.765000 4.155000 ;
-  END
-END sky130_fd_sc_hvl__fill_4
-MACRO sky130_fd_sc_hvl__fill_8
-  CLASS CORE SPACER ;
-  FOREIGN sky130_fd_sc_hvl__fill_8 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  3.840000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 3.840000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 3.840000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 3.840000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 3.840000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT 0.000000 -0.085000 3.840000 0.085000 ;
-      RECT 0.000000  3.985000 3.840000 4.155000 ;
-    LAYER mcon ;
-      RECT 0.155000 -0.085000 0.325000 0.085000 ;
-      RECT 0.155000  3.985000 0.325000 4.155000 ;
-      RECT 0.635000 -0.085000 0.805000 0.085000 ;
-      RECT 0.635000  3.985000 0.805000 4.155000 ;
-      RECT 1.115000 -0.085000 1.285000 0.085000 ;
-      RECT 1.115000  3.985000 1.285000 4.155000 ;
-      RECT 1.595000 -0.085000 1.765000 0.085000 ;
-      RECT 1.595000  3.985000 1.765000 4.155000 ;
-      RECT 2.075000 -0.085000 2.245000 0.085000 ;
-      RECT 2.075000  3.985000 2.245000 4.155000 ;
-      RECT 2.555000 -0.085000 2.725000 0.085000 ;
-      RECT 2.555000  3.985000 2.725000 4.155000 ;
-      RECT 3.035000 -0.085000 3.205000 0.085000 ;
-      RECT 3.035000  3.985000 3.205000 4.155000 ;
-      RECT 3.515000 -0.085000 3.685000 0.085000 ;
-      RECT 3.515000  3.985000 3.685000 4.155000 ;
-  END
-END sky130_fd_sc_hvl__fill_8
-MACRO sky130_fd_sc_hvl__fill_2
-  CLASS CORE SPACER ;
-  FOREIGN sky130_fd_sc_hvl__fill_2 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  0.960000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 0.960000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 0.960000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 0.960000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 0.960000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT 0.000000 -0.085000 0.960000 0.085000 ;
-      RECT 0.000000  3.985000 0.960000 4.155000 ;
-    LAYER mcon ;
-      RECT 0.155000 -0.085000 0.325000 0.085000 ;
-      RECT 0.155000  3.985000 0.325000 4.155000 ;
-      RECT 0.635000 -0.085000 0.805000 0.085000 ;
-      RECT 0.635000  3.985000 0.805000 4.155000 ;
-  END
-END sky130_fd_sc_hvl__fill_2
-MACRO sky130_fd_sc_hvl__schmittbuf_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__schmittbuf_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  5.280000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN A
-    ANTENNAGATEAREA  1.170000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 2.015000 1.855000 3.305000 2.150000 ;
-    END
-  END A
-  PIN X
-    ANTENNADIFFAREA  0.596250 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 4.860000 0.515000 5.195000 3.715000 ;
-    END
-  END X
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 5.280000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER li1 ;
-        RECT 0.000000 -0.085000 5.280000 0.085000 ;
-      LAYER mcon ;
-        RECT 0.155000 -0.085000 0.325000 0.085000 ;
-        RECT 0.635000 -0.085000 0.805000 0.085000 ;
-        RECT 1.115000 -0.085000 1.285000 0.085000 ;
-        RECT 1.595000 -0.085000 1.765000 0.085000 ;
-        RECT 2.075000 -0.085000 2.245000 0.085000 ;
-        RECT 2.555000 -0.085000 2.725000 0.085000 ;
-        RECT 3.035000 -0.085000 3.205000 0.085000 ;
-        RECT 3.515000 -0.085000 3.685000 0.085000 ;
-        RECT 3.995000 -0.085000 4.165000 0.085000 ;
-        RECT 4.475000 -0.085000 4.645000 0.085000 ;
-        RECT 4.955000 -0.085000 5.125000 0.085000 ;
-    END
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 5.280000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER li1 ;
-        RECT 0.000000 3.985000 5.280000 4.155000 ;
-      LAYER mcon ;
-        RECT 0.155000 3.985000 0.325000 4.155000 ;
-        RECT 0.635000 3.985000 0.805000 4.155000 ;
-        RECT 1.115000 3.985000 1.285000 4.155000 ;
-        RECT 1.595000 3.985000 1.765000 4.155000 ;
-        RECT 2.075000 3.985000 2.245000 4.155000 ;
-        RECT 2.555000 3.985000 2.725000 4.155000 ;
-        RECT 3.035000 3.985000 3.205000 4.155000 ;
-        RECT 3.515000 3.985000 3.685000 4.155000 ;
-        RECT 3.995000 3.985000 4.165000 4.155000 ;
-        RECT 4.475000 3.985000 4.645000 4.155000 ;
-        RECT 4.955000 3.985000 5.125000 4.155000 ;
-    END
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 5.280000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 5.280000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT 0.085000 1.805000 0.530000 1.975000 ;
-      RECT 0.085000 1.975000 0.255000 3.485000 ;
-      RECT 0.085000 3.485000 1.030000 3.655000 ;
-      RECT 0.280000 1.090000 0.530000 1.805000 ;
-      RECT 0.430000 2.165000 0.875000 2.335000 ;
-      RECT 0.430000 2.335000 0.680000 3.085000 ;
-      RECT 0.705000 0.570000 2.010000 0.795000 ;
-      RECT 0.705000 0.795000 0.875000 2.165000 ;
-      RECT 0.740000 3.405000 1.030000 3.485000 ;
-      RECT 0.740000 3.655000 1.030000 3.735000 ;
-      RECT 1.045000 1.655000 4.690000 1.685000 ;
-      RECT 1.045000 1.685000 1.835000 1.985000 ;
-      RECT 1.060000 0.975000 2.720000 1.145000 ;
-      RECT 1.060000 1.145000 1.390000 1.410000 ;
-      RECT 1.200000 2.295000 1.460000 3.235000 ;
-      RECT 1.200000 3.235000 2.790000 3.405000 ;
-      RECT 1.600000 1.315000 1.940000 1.505000 ;
-      RECT 1.600000 1.505000 4.210000 1.645000 ;
-      RECT 1.600000 1.645000 4.690000 1.655000 ;
-      RECT 1.655000 1.985000 1.835000 2.330000 ;
-      RECT 1.655000 2.330000 2.010000 3.065000 ;
-      RECT 2.390000 1.145000 2.720000 1.335000 ;
-      RECT 2.460000 2.320000 2.790000 3.235000 ;
-      RECT 3.120000 0.375000 4.630000 1.285000 ;
-      RECT 3.130000 3.405000 4.570000 3.735000 ;
-      RECT 3.235000 2.320000 4.570000 3.405000 ;
-      RECT 3.855000 1.685000 4.690000 2.055000 ;
-    LAYER mcon ;
-      RECT 3.210000 0.425000 3.380000 0.595000 ;
-      RECT 3.225000 3.475000 3.395000 3.645000 ;
-      RECT 3.570000 0.425000 3.740000 0.595000 ;
-      RECT 3.585000 3.475000 3.755000 3.645000 ;
-      RECT 3.945000 3.475000 4.115000 3.645000 ;
-      RECT 3.980000 0.425000 4.150000 0.595000 ;
-      RECT 4.305000 3.475000 4.475000 3.645000 ;
-      RECT 4.410000 0.425000 4.580000 0.595000 ;
-  END
-END sky130_fd_sc_hvl__schmittbuf_1
-MACRO sky130_fd_sc_hvl__sdfxtp_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__sdfxtp_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  14.88000 BY  4.070000 ;
-  SYMMETRY X Y ;
-  SITE unithv ;
-  PIN D
-    ANTENNAGATEAREA  0.420000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 0.605000 2.205000 2.755000 2.520000 ;
-    END
-  END D
-  PIN Q
-    ANTENNADIFFAREA  0.596250 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 13.660000 0.615000 14.020000 1.505000 ;
-        RECT 13.660000 2.195000 14.020000 3.735000 ;
-        RECT 13.850000 1.505000 14.755000 1.780000 ;
-        RECT 13.850000 1.780000 14.020000 2.195000 ;
-    END
-  END Q
-  PIN SCD
-    ANTENNAGATEAREA  0.420000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 3.600000 2.215000 4.195000 2.765000 ;
-    END
-  END SCD
-  PIN SCE
-    ANTENNAGATEAREA  0.840000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 0.605000 1.445000 1.795000 1.855000 ;
-        RECT 0.605000 1.855000 3.050000 2.025000 ;
-        RECT 2.720000 1.095000 3.050000 1.855000 ;
-    END
-  END SCE
-  PIN CLK
-    ANTENNAGATEAREA  0.585000 ;
-    DIRECTION INPUT ;
-    USE CLOCK ;
-    PORT
-      LAYER li1 ;
-        RECT 4.345000 1.175000 4.675000 1.685000 ;
-    END
-  END CLK
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 0.255000 14.880000 0.625000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 -0.115000 14.880000 0.115000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 14.880000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.445000 14.880000 3.815000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT  0.000000 -0.085000 14.880000 0.085000 ;
-      RECT  0.000000  3.985000 14.880000 4.155000 ;
-      RECT  0.125000  0.515000  0.455000 1.095000 ;
-      RECT  0.125000  1.095000  2.305000 1.265000 ;
-      RECT  0.125000  1.265000  0.380000 3.425000 ;
-      RECT  0.905000  0.365000  1.855000 0.915000 ;
-      RECT  0.910000  2.925000  1.860000 3.705000 ;
-      RECT  1.975000  1.265000  2.305000 1.675000 ;
-      RECT  2.395000  0.495000  2.725000 0.745000 ;
-      RECT  2.395000  0.745000  3.400000 0.915000 ;
-      RECT  2.400000  2.925000  3.400000 3.095000 ;
-      RECT  2.400000  3.095000  2.730000 3.425000 ;
-      RECT  3.230000  0.915000  3.400000 1.865000 ;
-      RECT  3.230000  1.865000  6.780000 2.035000 ;
-      RECT  3.230000  2.035000  3.400000 2.925000 ;
-      RECT  3.580000  0.365000  4.485000 0.995000 ;
-      RECT  3.635000  2.945000  4.585000 3.735000 ;
-      RECT  4.665000  0.515000  5.025000 0.975000 ;
-      RECT  4.765000  2.595000  5.605000 2.765000 ;
-      RECT  4.765000  2.765000  5.095000 3.735000 ;
-      RECT  4.855000  0.975000  5.025000 1.155000 ;
-      RECT  4.855000  1.155000  5.870000 1.325000 ;
-      RECT  5.215000  0.365000  5.805000 0.975000 ;
-      RECT  5.275000  2.215000  5.605000 2.595000 ;
-      RECT  5.315000  2.945000  5.905000 3.735000 ;
-      RECT  5.540000  1.325000  5.870000 1.685000 ;
-      RECT  5.995000  0.265000  8.210000 0.435000 ;
-      RECT  5.995000  0.435000  6.325000 0.975000 ;
-      RECT  6.095000  2.945000  6.425000 3.335000 ;
-      RECT  6.095000  3.335000  7.325000 3.505000 ;
-      RECT  6.095000  3.505000  6.425000 3.735000 ;
-      RECT  6.565000  0.615000  6.895000 0.995000 ;
-      RECT  6.565000  0.995000  6.780000 1.865000 ;
-      RECT  6.610000  2.035000  6.780000 2.695000 ;
-      RECT  6.610000  2.695000  6.975000 3.155000 ;
-      RECT  6.960000  2.225000  7.325000 2.515000 ;
-      RECT  7.075000  0.435000  7.245000 2.225000 ;
-      RECT  7.155000  2.515000  7.325000 3.335000 ;
-      RECT  7.425000  0.615000  7.755000 0.995000 ;
-      RECT  7.505000  0.995000  7.755000 1.605000 ;
-      RECT  7.505000  1.605000  9.685000 1.775000 ;
-      RECT  7.505000  1.775000  7.675000 2.675000 ;
-      RECT  7.505000  2.675000  7.755000 3.175000 ;
-      RECT  7.880000  1.955000  8.210000 2.495000 ;
-      RECT  7.935000  0.435000  8.210000 1.255000 ;
-      RECT  7.935000  1.255000 10.295000 1.425000 ;
-      RECT  8.040000  2.495000  8.210000 3.155000 ;
-      RECT  8.040000  3.155000 10.490000 3.325000 ;
-      RECT  8.620000  1.955000 10.645000 2.125000 ;
-      RECT  8.620000  2.125000  8.950000 2.555000 ;
-      RECT  8.680000  0.365000  9.630000 1.075000 ;
-      RECT  9.030000  3.505000  9.980000 3.755000 ;
-      RECT  9.810000  0.495000 10.140000 0.905000 ;
-      RECT  9.810000  0.905000 10.645000 1.075000 ;
-      RECT  9.810000  2.125000  9.980000 2.675000 ;
-      RECT  9.810000  2.675000 10.140000 2.975000 ;
-      RECT 10.045000  1.425000 10.295000 1.775000 ;
-      RECT 10.160000  2.305000 10.490000 2.495000 ;
-      RECT 10.320000  2.495000 10.490000 3.155000 ;
-      RECT 10.320000  3.325000 11.450000 3.495000 ;
-      RECT 10.475000  1.075000 10.645000 1.955000 ;
-      RECT 10.670000  2.675000 11.075000 3.145000 ;
-      RECT 10.825000  0.495000 11.800000 0.665000 ;
-      RECT 10.825000  0.665000 11.075000 2.675000 ;
-      RECT 11.255000  1.085000 11.450000 3.325000 ;
-      RECT 11.630000  0.665000 11.800000 2.345000 ;
-      RECT 11.630000  2.345000 12.930000 2.515000 ;
-      RECT 11.980000  0.365000 12.930000 1.305000 ;
-      RECT 11.980000  1.485000 13.440000 1.655000 ;
-      RECT 11.980000  1.655000 12.310000 2.155000 ;
-      RECT 11.980000  2.695000 12.930000 3.735000 ;
-      RECT 12.600000  1.845000 12.930000 2.345000 ;
-      RECT 13.110000  0.515000 13.440000 1.485000 ;
-      RECT 13.110000  1.655000 13.440000 1.685000 ;
-      RECT 13.110000  1.685000 13.670000 2.015000 ;
-      RECT 13.110000  2.015000 13.440000 3.735000 ;
-      RECT 14.200000  0.365000 14.790000 1.325000 ;
-      RECT 14.200000  2.195000 14.790000 3.735000 ;
-    LAYER mcon ;
-      RECT  0.155000 -0.085000  0.325000 0.085000 ;
-      RECT  0.155000  3.985000  0.325000 4.155000 ;
-      RECT  0.635000 -0.085000  0.805000 0.085000 ;
-      RECT  0.635000  3.985000  0.805000 4.155000 ;
-      RECT  0.935000  0.395000  1.105000 0.565000 ;
-      RECT  0.940000  3.505000  1.110000 3.675000 ;
-      RECT  1.115000 -0.085000  1.285000 0.085000 ;
-      RECT  1.115000  3.985000  1.285000 4.155000 ;
-      RECT  1.295000  0.395000  1.465000 0.565000 ;
-      RECT  1.300000  3.505000  1.470000 3.675000 ;
-      RECT  1.595000 -0.085000  1.765000 0.085000 ;
-      RECT  1.595000  3.985000  1.765000 4.155000 ;
-      RECT  1.655000  0.395000  1.825000 0.565000 ;
-      RECT  1.660000  3.505000  1.830000 3.675000 ;
-      RECT  2.075000 -0.085000  2.245000 0.085000 ;
-      RECT  2.075000  3.985000  2.245000 4.155000 ;
-      RECT  2.555000 -0.085000  2.725000 0.085000 ;
-      RECT  2.555000  3.985000  2.725000 4.155000 ;
-      RECT  3.035000 -0.085000  3.205000 0.085000 ;
-      RECT  3.035000  3.985000  3.205000 4.155000 ;
-      RECT  3.515000 -0.085000  3.685000 0.085000 ;
-      RECT  3.515000  3.985000  3.685000 4.155000 ;
-      RECT  3.590000  0.395000  3.760000 0.565000 ;
-      RECT  3.665000  3.505000  3.835000 3.675000 ;
-      RECT  3.950000  0.395000  4.120000 0.565000 ;
-      RECT  3.995000 -0.085000  4.165000 0.085000 ;
-      RECT  3.995000  3.985000  4.165000 4.155000 ;
-      RECT  4.025000  3.505000  4.195000 3.675000 ;
-      RECT  4.310000  0.395000  4.480000 0.565000 ;
-      RECT  4.385000  3.505000  4.555000 3.675000 ;
-      RECT  4.475000 -0.085000  4.645000 0.085000 ;
-      RECT  4.475000  3.985000  4.645000 4.155000 ;
-      RECT  4.955000 -0.085000  5.125000 0.085000 ;
-      RECT  4.955000  3.985000  5.125000 4.155000 ;
-      RECT  5.245000  0.395000  5.415000 0.565000 ;
-      RECT  5.345000  3.505000  5.515000 3.675000 ;
-      RECT  5.435000 -0.085000  5.605000 0.085000 ;
-      RECT  5.435000  3.985000  5.605000 4.155000 ;
-      RECT  5.605000  0.395000  5.775000 0.565000 ;
-      RECT  5.705000  3.505000  5.875000 3.675000 ;
-      RECT  5.915000 -0.085000  6.085000 0.085000 ;
-      RECT  5.915000  3.985000  6.085000 4.155000 ;
-      RECT  6.395000 -0.085000  6.565000 0.085000 ;
-      RECT  6.395000  3.985000  6.565000 4.155000 ;
-      RECT  6.875000 -0.085000  7.045000 0.085000 ;
-      RECT  6.875000  3.985000  7.045000 4.155000 ;
-      RECT  7.355000 -0.085000  7.525000 0.085000 ;
-      RECT  7.355000  3.985000  7.525000 4.155000 ;
-      RECT  7.835000 -0.085000  8.005000 0.085000 ;
-      RECT  7.835000  3.985000  8.005000 4.155000 ;
-      RECT  8.315000 -0.085000  8.485000 0.085000 ;
-      RECT  8.315000  3.985000  8.485000 4.155000 ;
-      RECT  8.710000  0.395000  8.880000 0.565000 ;
-      RECT  8.795000 -0.085000  8.965000 0.085000 ;
-      RECT  8.795000  3.985000  8.965000 4.155000 ;
-      RECT  9.060000  3.535000  9.230000 3.705000 ;
-      RECT  9.070000  0.395000  9.240000 0.565000 ;
-      RECT  9.275000 -0.085000  9.445000 0.085000 ;
-      RECT  9.275000  3.985000  9.445000 4.155000 ;
-      RECT  9.420000  3.535000  9.590000 3.705000 ;
-      RECT  9.430000  0.395000  9.600000 0.565000 ;
-      RECT  9.755000 -0.085000  9.925000 0.085000 ;
-      RECT  9.755000  3.985000  9.925000 4.155000 ;
-      RECT  9.780000  3.535000  9.950000 3.705000 ;
-      RECT 10.235000 -0.085000 10.405000 0.085000 ;
-      RECT 10.235000  3.985000 10.405000 4.155000 ;
-      RECT 10.715000 -0.085000 10.885000 0.085000 ;
-      RECT 10.715000  3.985000 10.885000 4.155000 ;
-      RECT 11.195000 -0.085000 11.365000 0.085000 ;
-      RECT 11.195000  3.985000 11.365000 4.155000 ;
-      RECT 11.675000 -0.085000 11.845000 0.085000 ;
-      RECT 11.675000  3.985000 11.845000 4.155000 ;
-      RECT 12.010000  0.395000 12.180000 0.565000 ;
-      RECT 12.010000  3.505000 12.180000 3.675000 ;
-      RECT 12.155000 -0.085000 12.325000 0.085000 ;
-      RECT 12.155000  3.985000 12.325000 4.155000 ;
-      RECT 12.370000  0.395000 12.540000 0.565000 ;
-      RECT 12.370000  3.505000 12.540000 3.675000 ;
-      RECT 12.635000 -0.085000 12.805000 0.085000 ;
-      RECT 12.635000  3.985000 12.805000 4.155000 ;
-      RECT 12.730000  0.395000 12.900000 0.565000 ;
-      RECT 12.730000  3.505000 12.900000 3.675000 ;
-      RECT 13.115000 -0.085000 13.285000 0.085000 ;
-      RECT 13.115000  3.985000 13.285000 4.155000 ;
-      RECT 13.595000 -0.085000 13.765000 0.085000 ;
-      RECT 13.595000  3.985000 13.765000 4.155000 ;
-      RECT 14.075000 -0.085000 14.245000 0.085000 ;
-      RECT 14.075000  3.985000 14.245000 4.155000 ;
-      RECT 14.230000  0.395000 14.400000 0.565000 ;
-      RECT 14.230000  3.505000 14.400000 3.675000 ;
-      RECT 14.555000 -0.085000 14.725000 0.085000 ;
-      RECT 14.555000  3.985000 14.725000 4.155000 ;
-      RECT 14.590000  0.395000 14.760000 0.565000 ;
-      RECT 14.590000  3.505000 14.760000 3.675000 ;
-  END
-END sky130_fd_sc_hvl__sdfxtp_1
-MACRO sky130_fd_sc_hvl__lsbufhv2hv_hl_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__lsbufhv2hv_hl_1 ;
-  ORIGIN  0.000000  0.000000 ;
-  SIZE  8.640000 BY  8.140000 ;
-  SYMMETRY X Y ;
-  SITE unithvdbl ;
-  PIN A
-    ANTENNAGATEAREA  0.585000 ;
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 4.355000 1.775000 4.685000 2.900000 ;
-    END
-  END A
-  PIN X
-    ANTENNADIFFAREA  0.626250 ;
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER li1 ;
-        RECT 2.995000 0.495000 3.395000 4.065000 ;
-    END
-  END X
-  PIN LOWHVPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.070000 3.020000 8.570000 3.305000 ;
-    END
-  END LOWHVPWR
-  PIN VGND
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 7.515000 8.640000 7.885000 ;
-    END
-  END VGND
-  PIN VNB
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 8.025000 8.640000 8.255000 ;
-    END
-  END VNB
-  PIN VPB
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 3.955000 8.640000 4.185000 ;
-    END
-  END VPB
-  PIN VPWR
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT
-      LAYER met1 ;
-        RECT 0.000000 4.325000 8.640000 4.695000 ;
-    END
-  END VPWR
-  OBS
-    LAYER li1 ;
-      RECT 0.000000 -0.085000 8.640000 0.085000 ;
-      RECT 0.000000  3.985000 0.800000 4.155000 ;
-      RECT 0.000000  8.055000 8.640000 8.225000 ;
-      RECT 3.130000  4.265000 5.095000 4.835000 ;
-      RECT 3.565000  0.365000 4.515000 1.265000 ;
-      RECT 3.565000  1.435000 5.115000 1.605000 ;
-      RECT 3.565000  1.605000 3.895000 2.065000 ;
-      RECT 3.565000  2.485000 4.185000 4.265000 ;
-      RECT 4.865000  0.495000 5.115000 1.435000 ;
-      RECT 4.865000  1.605000 5.115000 3.315000 ;
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-        RECT 2.445000 1.955000 2.810000 2.540000 ;
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-    PORT
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-END sky130_fd_sc_hvl__einvp_1
-MACRO sky130_fd_sc_hvl__a21oi_1
-  CLASS CORE ;
-  FOREIGN sky130_fd_sc_hvl__a21oi_1 ;
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commit	c98236505c3a83925213f6f29533def100239611	[log] [tgz]
author	Ahmed Ghazy <ax3ghazy@aucegypt.edu>	Sun Nov 29 20:10:43 2020 +0200
committer	Ahmed Ghazy <ax3ghazy@aucegypt.edu>	Sun Nov 29 20:10:43 2020 +0200
tree	697648900ade2c0f4dbad6b0ff2b6af63a3db289
parent	740defbfb78892a0a0fd50a50364f7a7bede2c10 [diff]