| |
| reading lef ... |
| |
| units: 1000 |
| #layers: 13 |
| #macros: 69 |
| #vias: 25 |
| #viarulegen: 25 |
| |
| reading def ... |
| |
| design: simple_por |
| die area: ( 0 0 ) ( 24780 45820 ) |
| trackPts: 12 |
| defvias: 4 |
| #components: 16 |
| #terminals: 5 |
| #snets: 2 |
| #nets: 5 |
| |
| reading guide ... |
| |
| #guides: 10 |
| Warning: met2 does not have viaDef align with layer direction, generating new viaDef via2_FR... |
| Warning: met4 does not have viaDef align with layer direction, generating new viaDef via4_FR... |
| done initConstraintLayerIdx |
| List of default vias: |
| Layer mcon |
| default via: L1M1_PR_MR |
| Layer via |
| default via: M1M2_PR |
| Layer via2 |
| default via: via2_FR |
| Layer via3 |
| default via: M3M4_PR_M |
| Layer via4 |
| default via: via4_FR |
| Writing reference output def... |
| |
| libcell analysis ... |
| |
| instance analysis ... |
| #unique instances = 9 |
| |
| init region query ... |
| complete FR_MASTERSLICE |
| complete FR_VIA |
| complete li1 |
| complete mcon |
| complete met1 |
| complete via |
| complete met2 |
| complete via2 |
| complete met3 |
| complete via3 |
| complete met4 |
| complete via4 |
| complete met5 |
| |
| FR_MASTERSLICE shape region query size = 0 |
| FR_VIA shape region query size = 0 |
| li1 shape region query size = 150 |
| mcon shape region query size = 260 |
| met1 shape region query size = 78 |
| via shape region query size = 40 |
| met2 shape region query size = 22 |
| via2 shape region query size = 40 |
| met3 shape region query size = 21 |
| via3 shape region query size = 40 |
| met4 shape region query size = 28 |
| via4 shape region query size = 13 |
| met5 shape region query size = 20 |
| |
| |
| start pin access |
| complete 6 pins |
| complete 7 unique inst patterns |
| complete 3 groups |
| Expt1 runtime (pin-level access point gen): 0.0124197 |
| Expt2 runtime (design-level access pattern gen): 0.00342962 |
| #scanned instances = 16 |
| #unique instances = 9 |
| #stdCellGenAp = 44 |
| #stdCellValidPlanarAp = 0 |
| #stdCellValidViaAp = 36 |
| #stdCellPinNoAp = 0 |
| #stdCellPinCnt = 5 |
| #instTermValidViaApCnt = 0 |
| #macroGenAp = 0 |
| #macroValidPlanarAp = 0 |
| #macroValidViaAp = 0 |
| #macroNoAp = 0 |
| |
| complete pin access |
| cpu time = 00:00:00, elapsed time = 00:00:00, memory = 6.60 (MB), peak = 6.93 (MB) |
| |
| post process guides ... |
| GCELLGRID X -1 DO 6 STEP 7200 ; |
| GCELLGRID Y -1 DO 3 STEP 7200 ; |
| complete FR_MASTERSLICE |
| complete FR_VIA |
| complete li1 |
| complete mcon |
| complete met1 |
| complete via |
| complete met2 |
| complete via2 |
| complete met3 |
| complete via3 |
| complete met4 |
| complete via4 |
| complete met5 |
| |
| building cmap ... |
| |
| init guide query ... |
| complete FR_MASTERSLICE (guide) |
| complete FR_VIA (guide) |
| complete li1 (guide) |
| complete mcon (guide) |
| complete met1 (guide) |
| complete via (guide) |
| complete met2 (guide) |
| complete via2 (guide) |
| complete met3 (guide) |
| complete via3 (guide) |
| complete met4 (guide) |
| complete via4 (guide) |
| complete met5 (guide) |
| |
| FR_MASTERSLICE guide region query size = 0 |
| FR_VIA guide region query size = 0 |
| li1 guide region query size = 4 |
| mcon guide region query size = 0 |
| met1 guide region query size = 3 |
| via guide region query size = 0 |
| met2 guide region query size = 2 |
| via2 guide region query size = 0 |
| met3 guide region query size = 0 |
| via3 guide region query size = 0 |
| met4 guide region query size = 0 |
| via4 guide region query size = 0 |
| met5 guide region query size = 0 |
| |
| init gr pin query ... |
| |
| |
| start track assignment |
| Done with 6 vertical wires in 1 frboxes and 3 horizontal wires in 1 frboxes. |
| Done with 1 vertical wires in 1 frboxes and 0 horizontal wires in 1 frboxes. |
| |
| complete track assignment |
| cpu time = 00:00:00, elapsed time = 00:00:00, memory = 6.93 (MB), peak = 7.11 (MB) |
| |
| post processing ... |
| |
| start routing data preparation |
| initVia2ViaMinLen_minSpc li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370) |
| initVia2ViaMinLen_minSpc met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460) |
| initVia2ViaMinLen_minSpc met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630) |
| initVia2ViaMinLen_minSpc met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680) |
| initVia2ViaMinLen_minSpc met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020) |
| initVia2ViaMinLen_minSpc met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0) |
| initVia2ViaMinLen_minimumcut li1 (d2d, d2u, u2d, u2u) = (0, 0, 0, 370) |
| initVia2ViaMinLen_minimumcut li1 zerolen (b, b, b, b) = (1, 1, 1, 1) |
| initVia2ViaMinLen_minimumcut met1 (d2d, d2u, u2d, u2u) = (430, 445, 445, 460) |
| initVia2ViaMinLen_minimumcut met1 zerolen (b, b, b, b) = (1, 1, 1, 1) |
| initVia2ViaMinLen_minimumcut met2 (d2d, d2u, u2d, u2u) = (460, 485, 485, 630) |
| initVia2ViaMinLen_minimumcut met2 zerolen (b, b, b, b) = (1, 1, 1, 1) |
| initVia2ViaMinLen_minimumcut met3 (d2d, d2u, u2d, u2u) = (630, 655, 655, 680) |
| initVia2ViaMinLen_minimumcut met3 zerolen (b, b, b, b) = (1, 1, 1, 1) |
| initVia2ViaMinLen_minimumcut met4 (d2d, d2u, u2d, u2u) = (630, 1055, 1055, 3020) |
| initVia2ViaMinLen_minimumcut met4 zerolen (b, b, b, b) = (1, 1, 1, 1) |
| initVia2ViaMinLen_minimumcut met5 (d2d, d2u, u2d, u2u) = (1480, 0, 0, 0) |
| initVia2ViaMinLen_minimumcut met5 zerolen (b, b, b, b) = (1, 1, 1, 1) |
| initVia2ViaMinLenNew_minSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370) |
| initVia2ViaMinLenNew_minSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460) |
| initVia2ViaMinLenNew_minSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630) |
| initVia2ViaMinLenNew_minSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630) |
| initVia2ViaMinLenNew_minSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020) |
| initVia2ViaMinLenNew_minSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0) |
| initVia2ViaMinLenNew_minimumcut li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370) |
| initVia2ViaMinLenNew_minimumcut met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460) |
| initVia2ViaMinLenNew_minimumcut met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630) |
| initVia2ViaMinLenNew_minimumcut met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630) |
| initVia2ViaMinLenNew_minimumcut met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020) |
| initVia2ViaMinLenNew_minimumcut met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1480, 1480, 0, 0, 0, 0, 0, 0) |
| initVia2ViaMinLenNew_cutSpc li1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (0, 0, 0, 0, 0, 0, 430, 370) |
| initVia2ViaMinLenNew_cutSpc met1 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (430, 370, 445, 385, 445, 385, 460, 460) |
| initVia2ViaMinLenNew_cutSpc met2 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (460, 460, 410, 485, 410, 485, 630, 630) |
| initVia2ViaMinLenNew_cutSpc met3 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (630, 630, 655, 625, 655, 625, 680, 630) |
| initVia2ViaMinLenNew_cutSpc met4 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (680, 630, 1055, 1055, 1055, 1055, 3020, 3020) |
| initVia2ViaMinLenNew_cutSpc met5 (d2d-x, d2d-y, d2u-x, d2u-y, u2d-x, u2d-y, u2u-x, u2u-y) = (1600, 1600, 0, 0, 0, 0, 0, 0) |
| cpu time = 00:00:00, elapsed time = 00:00:00, memory = 7.15 (MB), peak = 7.15 (MB) |
| |
| start detail routing ... |
| start 0th optimization iteration ... |
| completing 10% with 0 violations |
| elapsed time = 00:00:00, memory = 8.21 (MB) |
| number of violations = 0 |
| cpu time = 00:00:00, elapsed time = 00:00:00, memory = 8.20 (MB), peak = 371.90 (MB) |
| total wire length = 30 um |
| total wire length on LAYER li1 = 0 um |
| total wire length on LAYER met1 = 9 um |
| total wire length on LAYER met2 = 20 um |
| total wire length on LAYER met3 = 0 um |
| total wire length on LAYER met4 = 0 um |
| total wire length on LAYER met5 = 0 um |
| total number of vias = 10 |
| up-via summary (total 10): |
| |
| --------------------- |
| FR_MASTERSLICE 0 |
| li1 5 |
| met1 5 |
| met2 0 |
| met3 0 |
| met4 0 |
| --------------------- |
| 10 |
| |
| |
| start 1st optimization iteration ... |
| completing 10% with 0 violations |
| elapsed time = 00:00:00, memory = 9.75 (MB) |
| completing 20% with 0 violations |
| elapsed time = 00:00:00, memory = 9.84 (MB) |
| number of violations = 0 |
| cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.20 (MB), peak = 371.90 (MB) |
| total wire length = 30 um |
| total wire length on LAYER li1 = 0 um |
| total wire length on LAYER met1 = 9 um |
| total wire length on LAYER met2 = 20 um |
| total wire length on LAYER met3 = 0 um |
| total wire length on LAYER met4 = 0 um |
| total wire length on LAYER met5 = 0 um |
| total number of vias = 10 |
| up-via summary (total 10): |
| |
| --------------------- |
| FR_MASTERSLICE 0 |
| li1 5 |
| met1 5 |
| met2 0 |
| met3 0 |
| met4 0 |
| --------------------- |
| 10 |
| |
| |
| start 2nd optimization iteration ... |
| completing 10% with 0 violations |
| elapsed time = 00:00:00, memory = 14.20 (MB) |
| completing 20% with 0 violations |
| elapsed time = 00:00:00, memory = 14.20 (MB) |
| completing 30% with 0 violations |
| elapsed time = 00:00:00, memory = 14.20 (MB) |
| completing 40% with 0 violations |
| elapsed time = 00:00:00, memory = 14.20 (MB) |
| number of violations = 0 |
| cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.20 (MB), peak = 371.90 (MB) |
| total wire length = 30 um |
| total wire length on LAYER li1 = 0 um |
| total wire length on LAYER met1 = 9 um |
| total wire length on LAYER met2 = 20 um |
| total wire length on LAYER met3 = 0 um |
| total wire length on LAYER met4 = 0 um |
| total wire length on LAYER met5 = 0 um |
| total number of vias = 10 |
| up-via summary (total 10): |
| |
| --------------------- |
| FR_MASTERSLICE 0 |
| li1 5 |
| met1 5 |
| met2 0 |
| met3 0 |
| met4 0 |
| --------------------- |
| 10 |
| |
| |
| start 17th optimization iteration ... |
| completing 10% with 0 violations |
| elapsed time = 00:00:00, memory = 14.20 (MB) |
| completing 20% with 0 violations |
| elapsed time = 00:00:00, memory = 14.20 (MB) |
| number of violations = 0 |
| cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.20 (MB), peak = 371.90 (MB) |
| total wire length = 30 um |
| total wire length on LAYER li1 = 0 um |
| total wire length on LAYER met1 = 9 um |
| total wire length on LAYER met2 = 20 um |
| total wire length on LAYER met3 = 0 um |
| total wire length on LAYER met4 = 0 um |
| total wire length on LAYER met5 = 0 um |
| total number of vias = 10 |
| up-via summary (total 10): |
| |
| --------------------- |
| FR_MASTERSLICE 0 |
| li1 5 |
| met1 5 |
| met2 0 |
| met3 0 |
| met4 0 |
| --------------------- |
| 10 |
| |
| |
| start 25th optimization iteration ... |
| completing 10% with 0 violations |
| elapsed time = 00:00:00, memory = 14.46 (MB) |
| completing 20% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| number of violations = 0 |
| cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.70 (MB), peak = 371.90 (MB) |
| total wire length = 30 um |
| total wire length on LAYER li1 = 0 um |
| total wire length on LAYER met1 = 9 um |
| total wire length on LAYER met2 = 20 um |
| total wire length on LAYER met3 = 0 um |
| total wire length on LAYER met4 = 0 um |
| total wire length on LAYER met5 = 0 um |
| total number of vias = 10 |
| up-via summary (total 10): |
| |
| --------------------- |
| FR_MASTERSLICE 0 |
| li1 5 |
| met1 5 |
| met2 0 |
| met3 0 |
| met4 0 |
| --------------------- |
| 10 |
| |
| |
| start 33rd optimization iteration ... |
| completing 10% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 20% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 30% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 40% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 50% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 60% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| number of violations = 0 |
| cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.70 (MB), peak = 371.90 (MB) |
| total wire length = 30 um |
| total wire length on LAYER li1 = 0 um |
| total wire length on LAYER met1 = 9 um |
| total wire length on LAYER met2 = 20 um |
| total wire length on LAYER met3 = 0 um |
| total wire length on LAYER met4 = 0 um |
| total wire length on LAYER met5 = 0 um |
| total number of vias = 10 |
| up-via summary (total 10): |
| |
| --------------------- |
| FR_MASTERSLICE 0 |
| li1 5 |
| met1 5 |
| met2 0 |
| met3 0 |
| met4 0 |
| --------------------- |
| 10 |
| |
| |
| start 41st optimization iteration ... |
| completing 10% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 20% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 30% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 40% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 50% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 60% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| number of violations = 0 |
| cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.70 (MB), peak = 371.90 (MB) |
| total wire length = 30 um |
| total wire length on LAYER li1 = 0 um |
| total wire length on LAYER met1 = 9 um |
| total wire length on LAYER met2 = 20 um |
| total wire length on LAYER met3 = 0 um |
| total wire length on LAYER met4 = 0 um |
| total wire length on LAYER met5 = 0 um |
| total number of vias = 10 |
| up-via summary (total 10): |
| |
| --------------------- |
| FR_MASTERSLICE 0 |
| li1 5 |
| met1 5 |
| met2 0 |
| met3 0 |
| met4 0 |
| --------------------- |
| 10 |
| |
| |
| start 49th optimization iteration ... |
| completing 10% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 20% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| number of violations = 0 |
| cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.70 (MB), peak = 371.90 (MB) |
| total wire length = 30 um |
| total wire length on LAYER li1 = 0 um |
| total wire length on LAYER met1 = 9 um |
| total wire length on LAYER met2 = 20 um |
| total wire length on LAYER met3 = 0 um |
| total wire length on LAYER met4 = 0 um |
| total wire length on LAYER met5 = 0 um |
| total number of vias = 10 |
| up-via summary (total 10): |
| |
| --------------------- |
| FR_MASTERSLICE 0 |
| li1 5 |
| met1 5 |
| met2 0 |
| met3 0 |
| met4 0 |
| --------------------- |
| 10 |
| |
| |
| start 57th optimization iteration ... |
| completing 10% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 20% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 30% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 40% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 50% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| completing 60% with 0 violations |
| elapsed time = 00:00:00, memory = 14.70 (MB) |
| number of violations = 0 |
| cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.70 (MB), peak = 371.90 (MB) |
| total wire length = 30 um |
| total wire length on LAYER li1 = 0 um |
| total wire length on LAYER met1 = 9 um |
| total wire length on LAYER met2 = 20 um |
| total wire length on LAYER met3 = 0 um |
| total wire length on LAYER met4 = 0 um |
| total wire length on LAYER met5 = 0 um |
| total number of vias = 10 |
| up-via summary (total 10): |
| |
| --------------------- |
| FR_MASTERSLICE 0 |
| li1 5 |
| met1 5 |
| met2 0 |
| met3 0 |
| met4 0 |
| --------------------- |
| 10 |
| |
| |
| complete detail routing |
| total wire length = 30 um |
| total wire length on LAYER li1 = 0 um |
| total wire length on LAYER met1 = 9 um |
| total wire length on LAYER met2 = 20 um |
| total wire length on LAYER met3 = 0 um |
| total wire length on LAYER met4 = 0 um |
| total wire length on LAYER met5 = 0 um |
| total number of vias = 10 |
| up-via summary (total 10): |
| |
| --------------------- |
| FR_MASTERSLICE 0 |
| li1 5 |
| met1 5 |
| met2 0 |
| met3 0 |
| met4 0 |
| --------------------- |
| 10 |
| |
| cpu time = 00:00:00, elapsed time = 00:00:00, memory = 14.70 (MB), peak = 371.90 (MB) |
| |
| post processing ... |
| |
| Runtime taken (hrt): 0.95639 |
