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| /----------------------------------------------------------------------------\ |
| | | |
| | yosys -- Yosys Open SYnthesis Suite | |
| | | |
| | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> | |
| | | |
| | Permission to use, copy, modify, and/or distribute this software for any | |
| | purpose with or without fee is hereby granted, provided that the above | |
| | copyright notice and this permission notice appear in all copies. | |
| | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| | | |
| \----------------------------------------------------------------------------/ |
| |
| Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) |
| |
| [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. |
| |
| 1. Executing Verilog-2005 frontend: /project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.powered.v |
| Parsing Verilog input from `/project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.powered.v' to AST representation. |
| Generating RTLIL representation for module `\simple_por'. |
| /project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.powered.v:12: Warning: Identifier `\_0_' is implicitly declared. |
| /project/openlane/simple_por/runs/simple_por/results/lvs/simple_por.lvs.powered.v:18: Warning: Identifier `\mid' is implicitly declared. |
| Successfully finished Verilog frontend. |
| |
| 2. Executing Verilog backend. |
| Dumping module `\simple_por'. |
| |
| Warnings: 2 unique messages, 2 total |
| End of script. Logfile hash: b41ccc5405, CPU: user 0.02s system 0.00s, MEM: 7.59 MB peak |
| Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) |
| Time spent: 79% 2x write_verilog (0 sec), 20% 2x read_verilog (0 sec) |
