| OpenROAD 0.9.0 e582f2522b |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| Notice 0: Reading LEF file: /project/openlane/simple_por/runs/simple_por/tmp/merged.lef |
| Notice 0: Created 13 technology layers |
| Notice 0: Created 25 technology vias |
| Notice 0: Created 69 library cells |
| Notice 0: Finished LEF file: /project/openlane/simple_por/runs/simple_por/tmp/merged.lef |
| Notice 0: |
| Reading DEF file: /project/openlane/simple_por/runs/simple_por/tmp/floorplan/verilog2def_openroad.def |
| Notice 0: Design: simple_por |
| Notice 0: Created 3 pins. |
| Notice 0: Created 3 components and 18 component-terminals. |
| Notice 0: Created 5 nets and 5 connections. |
| Notice 0: Finished DEF file: /project/openlane/simple_por/runs/simple_por/tmp/floorplan/verilog2def_openroad.def |
| #Macro blocks found: 0 |
| Warning: using the default boundaries offset (5 microns) |
| Warning: using the default min distance between IO pins (2 tracks) |
| WARNING: force pin spread option has no effect when using random pin placement |
| > Running IO placement |
| * Num of slots 90 |
| * Num of I/O 3 |
| * Num of I/O w/sink 1 |
| * Num of I/O w/o sink 2 |
| * Slots Per Section 200 |
| * Slots Increase Factor 0.01 |
| * Usage Per Section 0.8 |
| * Usage Increase Factor 0.01 |
| * Force Pin Spread 1 |
| |
| WARNING: running random pin placement |
| RandomMode Even |
| > IO placement done. |
