openlane/simple_por/runs/simple_por/logs/synthesis/yosys.log

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Liberty frontend.
Imported 57 cell types from liberty file.

2. Executing Liberty frontend.
Imported 8 cell types from liberty file.

3. Executing Verilog-2005 frontend: /project/openlane/simple_por/../../verilog/rtl/simple_por.v
Parsing SystemVerilog input from `/project/openlane/simple_por/../../verilog/rtl/simple_por.v' to AST representation.
Generating RTLIL representation for module `\simple_por'.
Successfully finished Verilog frontend.

4. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/simple_por/runs/simple_por/tmp/synthesis/hierarchy.dot'.
Dumping module simple_por to page 1.

5. Executing HIERARCHY pass (managing design hierarchy).

5.1. Analyzing design hierarchy..
Top module:  \simple_por

5.2. Analyzing design hierarchy..
Top module:  \simple_por
Removed 0 unused modules.

6. Executing SYNTH pass.

6.1. Executing HIERARCHY pass (managing design hierarchy).

6.1.1. Analyzing design hierarchy..
Top module:  \simple_por

6.1.2. Analyzing design hierarchy..
Top module:  \simple_por
Removed 0 unused modules.

6.2. Executing PROC pass (convert processes to netlists).

6.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

6.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

6.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 3 assignments to connections.

6.2.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:0$3'.
  Set init value: \inode = 1'0

6.2.5. Executing PROC_ARST pass (detect async resets in processes).

6.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:0$3'.
Creating decoders for process `\simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:26$2'.
Creating decoders for process `\simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:23$1'.

6.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).

6.2.8. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\simple_por.\inode' using process `\simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:26$2'.
  created $dff cell `$procdff$4' with negative edge clock.
Creating register for signal `\simple_por.\inode' using process `\simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:23$1'.
  created $dff cell `$procdff$5' with positive edge clock.

6.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:0$3'.
Removing empty process `simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:26$2'.
Removing empty process `simple_por.$proc$/project/openlane/simple_por/../../verilog/rtl/simple_por.v:23$1'.
Cleaned up 0 empty switches.

6.3. Executing FLATTEN pass (flatten design).

6.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

6.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..
Removed 0 unused cells and 3 unused wires.
<suppressed ~1 debug messages>

6.6. Executing CHECK pass (checking for obvious problems).
checking module simple_por..
Warning: multiple conflicting drivers for simple_por.\inode:
    port Q[0] of cell $procdff$4 ($dff)
    port Q[0] of cell $procdff$5 ($dff)
found and reported 1 problems.

6.7. Executing OPT pass (performing simple optimizations).

6.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

6.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\simple_por'.
Removed a total of 0 cells.

6.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \simple_por..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

6.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \simple_por.
Performed a total of 0 changes.

6.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\simple_por'.
Removed a total of 0 cells.

6.7.6. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $procdff$4 ($dff) from module simple_por.

6.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..
Warning: Driver-driver conflict for \inode between cell $procdff$5.Q and constant 1'0 in simple_por: Resolved using constant.
Removed 1 unused cells and 0 unused wires.
<suppressed ~1 debug messages>

6.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

6.7.9. Rerunning OPT passes. (Maybe there is more to do..)

6.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \simple_por..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

6.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \simple_por.
Performed a total of 0 changes.

6.7.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\simple_por'.
Removed a total of 0 cells.

6.7.13. Executing OPT_DFF pass (perform DFF optimizations).

6.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..

6.7.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

6.7.16. Finished OPT passes. (There is nothing left to do.)

6.8. Executing FSM pass (extract and optimize FSM).

6.8.1. Executing FSM_DETECT pass (finding FSMs in design).

6.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).

6.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).

6.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..

6.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).

6.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

6.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

6.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

6.9. Executing OPT pass (performing simple optimizations).

6.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

6.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\simple_por'.
Removed a total of 0 cells.

6.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \simple_por..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

6.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \simple_por.
Performed a total of 0 changes.

6.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\simple_por'.
Removed a total of 0 cells.

6.9.6. Executing OPT_DFF pass (perform DFF optimizations).

6.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..

6.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

6.9.9. Finished OPT passes. (There is nothing left to do.)

6.10. Executing WREDUCE pass (reducing word size of cells).

6.11. Executing PEEPOPT pass (run peephole optimizers).

6.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..

6.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module simple_por:
  created 0 $alu and 0 $macc cells.

6.14. Executing SHARE pass (SAT-based resource sharing).

6.15. Executing OPT pass (performing simple optimizations).

6.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

6.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\simple_por'.
Removed a total of 0 cells.

6.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \simple_por..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

6.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \simple_por.
Performed a total of 0 changes.

6.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\simple_por'.
Removed a total of 0 cells.

6.15.6. Executing OPT_DFF pass (perform DFF optimizations).

6.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..

6.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

6.15.9. Finished OPT passes. (There is nothing left to do.)

6.16. Executing MEMORY pass.

6.16.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

6.16.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

6.16.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..

6.16.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

6.16.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..

6.16.6. Executing MEMORY_COLLECT pass (generating $mem cells).

6.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..

6.18. Executing OPT pass (performing simple optimizations).

6.18.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

6.18.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\simple_por'.
Removed a total of 0 cells.

6.18.3. Executing OPT_DFF pass (perform DFF optimizations).

6.18.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..

6.18.5. Finished fast OPT passes.

6.19. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

6.20. Executing OPT pass (performing simple optimizations).

6.20.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

6.20.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\simple_por'.
Removed a total of 0 cells.

6.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \simple_por..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

6.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \simple_por.
Performed a total of 0 changes.

6.20.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\simple_por'.
Removed a total of 0 cells.

6.20.6. Executing OPT_SHARE pass.

6.20.7. Executing OPT_DFF pass (perform DFF optimizations).

6.20.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..

6.20.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

6.20.10. Finished OPT passes. (There is nothing left to do.)

6.21. Executing TECHMAP pass (map to technology primitives).

6.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v
Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

6.21.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~67 debug messages>

6.22. Executing OPT pass (performing simple optimizations).

6.22.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

6.22.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\simple_por'.
Removed a total of 0 cells.

6.22.3. Executing OPT_DFF pass (perform DFF optimizations).

6.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..

6.22.5. Finished fast OPT passes.

6.23. Executing ABC pass (technology mapping using ABC).

6.23.1. Extracting gate netlist of module `\simple_por' to `<abc-temp-dir>/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

6.24. Executing OPT pass (performing simple optimizations).

6.24.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

6.24.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\simple_por'.
Removed a total of 0 cells.

6.24.3. Executing OPT_DFF pass (perform DFF optimizations).

6.24.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..

6.24.5. Finished fast OPT passes.

6.25. Executing HIERARCHY pass (managing design hierarchy).

6.25.1. Analyzing design hierarchy..
Top module:  \simple_por

6.25.2. Analyzing design hierarchy..
Top module:  \simple_por
Removed 0 unused modules.

6.26. Printing statistics.

=== simple_por ===

   Number of wires:                  5
   Number of wire bits:              5
   Number of public wires:           5
   Number of public wire bits:       5
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     sky130_fd_sc_hvl__schmittbuf_1      2

6.27. Executing CHECK pass (checking for obvious problems).
checking module simple_por..
found and reported 0 problems.

7. Executing SHARE pass (SAT-based resource sharing).

8. Executing OPT pass (performing simple optimizations).

8.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\simple_por'.
Removed a total of 0 cells.

8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \simple_por..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \simple_por.
Performed a total of 0 changes.

8.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\simple_por'.
Removed a total of 0 cells.

8.6. Executing OPT_DFF pass (perform DFF optimizations).

8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..

8.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module simple_por.

8.9. Finished OPT passes. (There is nothing left to do.)

9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

10. Printing statistics.

=== simple_por ===

   Number of wires:                  4
   Number of wire bits:              4
   Number of public wires:           4
   Number of public wire bits:       4
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     sky130_fd_sc_hvl__schmittbuf_1      2

11. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
  cell sky130_fd_sc_hvl__dfxtp_1 (noninv, pins=3, area=48.84) is a direct match for cell type $_DFF_P_.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
  cell sky130_fd_sc_hvl__dfrtp_1 (noninv, pins=4, area=62.52) is a direct match for cell type $_DFF_PN0_.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
  cell sky130_fd_sc_hvl__dfstp_1 (noninv, pins=4, area=60.56) is a direct match for cell type $_DFF_PN1_.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfstp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfxtp_1' - skipping.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hvl__dfxtp_1 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hvl__dfrtp_1 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hvl__dfstp_1 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    unmapped dff cell: $_DFFSR_NNN_
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

11.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\simple_por':

12. Printing statistics.

=== simple_por ===

   Number of wires:                  4
   Number of wire bits:              4
   Number of public wires:           4
   Number of public wire bits:       4
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     sky130_fd_sc_hvl__schmittbuf_1      2

13. Executing ABC pass (technology mapping using ABC).

13.1. Extracting gate netlist of module `\simple_por' to `/tmp/yosys-abc-hrVmdg/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

14. Executing SETUNDEF pass (replace undef values with defined constants).

15. Executing HILOMAP pass (mapping to constant drivers).

16. Executing SPLITNETS pass (splitting up multi-bit signals).

17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \simple_por..

18. Executing INSBUF pass (insert buffer cells for connected wires).

19. Executing CHECK pass (checking for obvious problems).
checking module simple_por..
found and reported 0 problems.

20. Printing statistics.

=== simple_por ===

   Number of wires:                  5
   Number of wire bits:              5
   Number of public wires:           4
   Number of public wire bits:       4
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  3
     sky130_fd_sc_hvl__conb_1        1
     sky130_fd_sc_hvl__schmittbuf_1      2

   Chip area for module '\simple_por': 52.747200

21. Executing Verilog backend.
Dumping module `\simple_por'.

Warnings: 8 unique messages, 56 total
End of script. Logfile hash: bc23914c66, CPU: user 0.44s system 0.01s, MEM: 22.57 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 28% 4x read_liberty (0 sec), 27% 1x dfflibmap (0 sec), ...