Add files via upload
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.clock_skew.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.clock_skew.rpt
new file mode 100644
index 0000000..fe2a127
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_106_/CLK ^
+ 0.78
+_108_/CLK ^
+ 0.70 -0.04 0.04
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.max.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.max.rpt
new file mode 100644
index 0000000..d3c6d56
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.max.rpt
@@ -0,0 +1,199 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.71 1.54 2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.06 net9 (net)
+ 0.71 0.03 2.34 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.72 3.06 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[16] (net)
+ 0.48 0.00 3.06 ^ io_out[16] (out)
+ 3.06 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.06 data arrival time
+-----------------------------------------------------------------------------
+ 48.69 slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.71 1.54 2.31 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.06 net5 (net)
+ 0.72 0.03 2.34 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.72 3.05 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[12] (net)
+ 0.48 0.00 3.05 ^ io_out[12] (out)
+ 3.05 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.05 data arrival time
+-----------------------------------------------------------------------------
+ 48.70 slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[3] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.83 1.51 2.28 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2 0.03 net15 (net)
+ 0.83 0.01 2.30 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.73 3.03 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[3] (net)
+ 0.48 0.00 3.03 ^ io_out[3] (out)
+ 3.03 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.03 data arrival time
+-----------------------------------------------------------------------------
+ 48.72 slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.66 1.51 2.29 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.05 net20 (net)
+ 0.66 0.02 2.31 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.71 3.02 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[8] (net)
+ 0.48 0.00 3.02 ^ io_out[8] (out)
+ 3.02 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.02 data arrival time
+-----------------------------------------------------------------------------
+ 48.73 slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.65 1.51 2.29 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.05 net2 (net)
+ 0.65 0.00 2.29 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.70 2.99 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[0] (net)
+ 0.48 0.00 2.99 ^ io_out[0] (out)
+ 2.99 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -2.99 data arrival time
+-----------------------------------------------------------------------------
+ 48.76 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.min.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.min.rpt
new file mode 100644
index 0000000..e9b8f3f
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.min.rpt
@@ -0,0 +1,244 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.70 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.40 1.14 1.84 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.05 net16 (net)
+ 0.40 0.01 1.85 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.60 0.44 2.29 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.01 _008_ (net)
+ 0.60 0.00 2.29 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.29 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.02 clock uncertainty
+ -0.07 0.95 clock reconvergence pessimism
+ 0.02 0.97 library hold time
+ 0.97 data required time
+-----------------------------------------------------------------------------
+ 0.97 data required time
+ -2.29 data arrival time
+-----------------------------------------------------------------------------
+ 1.32 slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.70 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.55 1.30 2.00 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.04 net21 (net)
+ 0.56 0.02 2.02 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.38 0.30 2.31 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _013_ (net)
+ 0.38 0.00 2.32 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.32 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.02 clock uncertainty
+ -0.07 0.95 clock reconvergence pessimism
+ 0.03 0.97 library hold time
+ 0.97 data required time
+-----------------------------------------------------------------------------
+ 0.97 data required time
+ -2.32 data arrival time
+-----------------------------------------------------------------------------
+ 1.34 slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.31 0.71 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.71 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.57 1.31 2.02 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.04 net6 (net)
+ 0.57 0.01 2.03 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.39 0.30 2.33 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _017_ (net)
+ 0.39 0.00 2.34 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.34 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.03 clock uncertainty
+ -0.07 0.96 clock reconvergence pessimism
+ 0.02 0.98 library hold time
+ 0.98 data required time
+-----------------------------------------------------------------------------
+ 0.98 data required time
+ -2.34 data arrival time
+-----------------------------------------------------------------------------
+ 1.36 slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.70 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.57 1.31 2.01 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.04 net10 (net)
+ 0.58 0.01 2.03 ^ _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.40 0.31 2.33 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _001_ (net)
+ 0.40 0.00 2.34 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.34 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.02 clock uncertainty
+ -0.07 0.95 clock reconvergence pessimism
+ 0.02 0.97 library hold time
+ 0.97 data required time
+-----------------------------------------------------------------------------
+ 0.97 data required time
+ -2.34 data arrival time
+-----------------------------------------------------------------------------
+ 1.37 slack (MET)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.70 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.63 1.35 2.05 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.05 net13 (net)
+ 0.63 0.01 2.06 ^ _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.38 0.29 2.35 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _005_ (net)
+ 0.38 0.00 2.36 v _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.36 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.02 clock uncertainty
+ -0.07 0.95 clock reconvergence pessimism
+ 0.03 0.97 library hold time
+ 0.97 data required time
+-----------------------------------------------------------------------------
+ 0.97 data required time
+ -2.36 data arrival time
+-----------------------------------------------------------------------------
+ 1.38 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.rpt
new file mode 100644
index 0000000..f5a5b4c
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.rpt
@@ -0,0 +1,48 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.71 1.54 2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.06 net9 (net)
+ 0.71 0.03 2.34 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.72 3.06 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[16] (net)
+ 0.48 0.00 3.06 ^ io_out[16] (out)
+ 3.06 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.06 data arrival time
+-----------------------------------------------------------------------------
+ 48.69 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.tns.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.wns.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/10-cts_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.area.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.area.rpt
new file mode 100644
index 0000000..9849480
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.area.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 67586 u^2 3% utilization.
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.clock_skew.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.clock_skew.rpt
new file mode 100644
index 0000000..fe2a127
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_106_/CLK ^
+ 0.78
+_108_/CLK ^
+ 0.70 -0.04 0.04
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.max.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.max.rpt
new file mode 100644
index 0000000..d3c6d56
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.max.rpt
@@ -0,0 +1,199 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.71 1.54 2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.06 net9 (net)
+ 0.71 0.03 2.34 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.72 3.06 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[16] (net)
+ 0.48 0.00 3.06 ^ io_out[16] (out)
+ 3.06 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.06 data arrival time
+-----------------------------------------------------------------------------
+ 48.69 slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.71 1.54 2.31 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.06 net5 (net)
+ 0.72 0.03 2.34 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.72 3.05 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[12] (net)
+ 0.48 0.00 3.05 ^ io_out[12] (out)
+ 3.05 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.05 data arrival time
+-----------------------------------------------------------------------------
+ 48.70 slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[3] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.83 1.51 2.28 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2 0.03 net15 (net)
+ 0.83 0.01 2.30 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.73 3.03 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[3] (net)
+ 0.48 0.00 3.03 ^ io_out[3] (out)
+ 3.03 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.03 data arrival time
+-----------------------------------------------------------------------------
+ 48.72 slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.66 1.51 2.29 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.05 net20 (net)
+ 0.66 0.02 2.31 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.71 3.02 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[8] (net)
+ 0.48 0.00 3.02 ^ io_out[8] (out)
+ 3.02 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.02 data arrival time
+-----------------------------------------------------------------------------
+ 48.73 slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.65 1.51 2.29 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.05 net2 (net)
+ 0.65 0.00 2.29 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.70 2.99 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[0] (net)
+ 0.48 0.00 2.99 ^ io_out[0] (out)
+ 2.99 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -2.99 data arrival time
+-----------------------------------------------------------------------------
+ 48.76 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.min.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.min.rpt
new file mode 100644
index 0000000..e9b8f3f
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.min.rpt
@@ -0,0 +1,244 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.70 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.40 1.14 1.84 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.05 net16 (net)
+ 0.40 0.01 1.85 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.60 0.44 2.29 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.01 _008_ (net)
+ 0.60 0.00 2.29 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.29 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.02 clock uncertainty
+ -0.07 0.95 clock reconvergence pessimism
+ 0.02 0.97 library hold time
+ 0.97 data required time
+-----------------------------------------------------------------------------
+ 0.97 data required time
+ -2.29 data arrival time
+-----------------------------------------------------------------------------
+ 1.32 slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.70 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.55 1.30 2.00 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.04 net21 (net)
+ 0.56 0.02 2.02 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.38 0.30 2.31 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _013_ (net)
+ 0.38 0.00 2.32 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.32 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.02 clock uncertainty
+ -0.07 0.95 clock reconvergence pessimism
+ 0.03 0.97 library hold time
+ 0.97 data required time
+-----------------------------------------------------------------------------
+ 0.97 data required time
+ -2.32 data arrival time
+-----------------------------------------------------------------------------
+ 1.34 slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.31 0.71 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.71 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.57 1.31 2.02 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.04 net6 (net)
+ 0.57 0.01 2.03 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.39 0.30 2.33 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _017_ (net)
+ 0.39 0.00 2.34 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.34 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.03 clock uncertainty
+ -0.07 0.96 clock reconvergence pessimism
+ 0.02 0.98 library hold time
+ 0.98 data required time
+-----------------------------------------------------------------------------
+ 0.98 data required time
+ -2.34 data arrival time
+-----------------------------------------------------------------------------
+ 1.36 slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.70 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.57 1.31 2.01 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.04 net10 (net)
+ 0.58 0.01 2.03 ^ _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.40 0.31 2.33 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _001_ (net)
+ 0.40 0.00 2.34 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.34 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.02 clock uncertainty
+ -0.07 0.95 clock reconvergence pessimism
+ 0.02 0.97 library hold time
+ 0.97 data required time
+-----------------------------------------------------------------------------
+ 0.97 data required time
+ -2.34 data arrival time
+-----------------------------------------------------------------------------
+ 1.37 slack (MET)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.70 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.63 1.35 2.05 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.05 net13 (net)
+ 0.63 0.01 2.06 ^ _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.38 0.29 2.35 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _005_ (net)
+ 0.38 0.00 2.36 v _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.36 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.02 clock uncertainty
+ -0.07 0.95 clock reconvergence pessimism
+ 0.03 0.97 library hold time
+ 0.97 data required time
+-----------------------------------------------------------------------------
+ 0.97 data required time
+ -2.36 data arrival time
+-----------------------------------------------------------------------------
+ 1.38 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.power.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.power.rpt
new file mode 100644
index 0000000..2d78dc8
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.power.rpt
@@ -0,0 +1,14 @@
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 7.07e-05 7.86e-06 1.98e-09 7.86e-05 42.6%
+Combinational 6.84e-05 3.72e-05 3.25e-07 1.06e-04 57.4%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 1.39e-04 4.50e-05 3.27e-07 1.85e-04 100.0%
+ 75.4% 24.4% 0.2%
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.rpt
new file mode 100644
index 0000000..f5a5b4c
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.rpt
@@ -0,0 +1,48 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.71 1.54 2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.06 net9 (net)
+ 0.71 0.03 2.34 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.72 3.06 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[16] (net)
+ 0.48 0.00 3.06 ^ io_out[16] (out)
+ 3.06 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.06 data arrival time
+-----------------------------------------------------------------------------
+ 48.69 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.slew.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.slew.rpt
new file mode 100644
index 0000000..ed40823
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.slew.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.tns.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.wns.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.worst_slack.rpt b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.worst_slack.rpt
new file mode 100644
index 0000000..81210e2
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.worst_slack.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 48.69
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 1.32
diff --git a/openlane/cntr_example/runs/cntr_example/reports/floorplan/3-initial_fp_core_area.rpt b/openlane/cntr_example/runs/cntr_example/reports/floorplan/3-initial_fp_core_area.rpt
new file mode 100644
index 0000000..ae9d3e8
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/floorplan/3-initial_fp_core_area.rpt
@@ -0,0 +1 @@
+6.72 15.68 1492.96 1481.76
\ No newline at end of file
diff --git a/openlane/cntr_example/runs/cntr_example/reports/floorplan/3-initial_fp_die_area.rpt b/openlane/cntr_example/runs/cntr_example/reports/floorplan/3-initial_fp_die_area.rpt
new file mode 100644
index 0000000..1a41984
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/floorplan/3-initial_fp_die_area.rpt
@@ -0,0 +1 @@
+0.0 0.0 1500.0 1500.0
\ No newline at end of file
diff --git a/openlane/cntr_example/runs/cntr_example/reports/manufacturability.rpt b/openlane/cntr_example/runs/cntr_example/reports/manufacturability.rpt
new file mode 100644
index 0000000..5bf264e
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/manufacturability.rpt
@@ -0,0 +1,16 @@
+Design Name: cntr_example
+Run Directory: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29
+----------------------------------------
+
+Magic DRC Summary:
+Source: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.rpt
+Total Magic DRC violations is 0
+----------------------------------------
+
+LVS Summary:
+Source: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/cntr_example.lvs.lef.log
+Source not found.
+----------------------------------------
+
+Antenna Summary:
+No antenna report found.
\ No newline at end of file
diff --git a/openlane/cntr_example/runs/cntr_example/reports/metrics.csv b/openlane/cntr_example/runs/cntr_example/reports/metrics.csv
new file mode 100644
index 0000000..6e9a62b
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/metrics.csv
@@ -0,0 +1,2 @@
+design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
+/home/htf6ry/gf180-demo/openlane/cntr_example,cntr_example,22_12_03_16_29,flow completed,0h4m55s0ms,0h1m40s0ms,47.22222222222222,9.0,9.444444444444445,0.1,1476.13,85,0,0,0,0,0,0,0,-1,0,-1,-1,64292,963,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,121739074.0,0.0,1.21,1.47,0.02,-1,0.91,40,362,20,152,0,0,0,50,0,0,5,0,0,10,5,20,21,20,3,748,13914,0,14662,2178946.7391999997,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,65.0,15.384615384615385,65,AREA 0,10,20,1,153.6,153.18,0.25,0.3,gf180mcu_fd_sc_mcu7t5v0,4
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.clock_skew.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.clock_skew.rpt
new file mode 100644
index 0000000..0315719
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_094_/CLK ^
+ 0.23
+_094_/CLK ^
+ 0.21 0.00 0.02
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.max.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.max.rpt
new file mode 100644
index 0000000..cf27d03
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.max.rpt
@@ -0,0 +1,174 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 13.00 13.00 ^ input external delay
+ 0.49 0.27 13.27 ^ wb_rst_i (in)
+ 2 0.02 wb_rst_i (net)
+ 0.49 0.00 13.27 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.29 1.05 14.31 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 10 0.05 _021_ (net)
+ 1.29 0.00 14.31 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.65 0.32 14.63 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _022_ (net)
+ 0.65 0.00 14.63 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.98 0.79 15.42 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _001_ (net)
+ 0.98 0.00 15.42 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 15.42 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ 64.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.44 64.31 library setup time
+ 64.31 data required time
+-----------------------------------------------------------------------------
+ 64.31 data required time
+ -15.42 data arrival time
+-----------------------------------------------------------------------------
+ 48.89 slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.93 2.77 2.77 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.10 io_out[12] (net)
+ 2.93 0.09 2.86 ^ io_out[12] (out)
+ 2.86 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -2.86 data arrival time
+-----------------------------------------------------------------------------
+ 48.89 slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.92 2.76 2.76 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.10 io_out[16] (net)
+ 2.93 0.09 2.85 ^ io_out[16] (out)
+ 2.85 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -2.85 data arrival time
+-----------------------------------------------------------------------------
+ 48.90 slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 13.00 13.00 ^ input external delay
+ 0.49 0.27 13.27 ^ wb_rst_i (in)
+ 2 0.02 wb_rst_i (net)
+ 0.49 0.00 13.27 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.29 1.05 14.31 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 10 0.05 _021_ (net)
+ 1.29 0.00 14.32 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.64 0.30 14.61 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _032_ (net)
+ 0.64 0.00 14.61 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.98 0.78 15.40 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _009_ (net)
+ 0.98 0.00 15.40 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 15.40 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ 64.75 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.44 64.31 library setup time
+ 64.31 data required time
+-----------------------------------------------------------------------------
+ 64.31 data required time
+ -15.40 data arrival time
+-----------------------------------------------------------------------------
+ 48.91 slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 13.00 13.00 ^ input external delay
+ 0.49 0.27 13.27 ^ wb_rst_i (in)
+ 2 0.02 wb_rst_i (net)
+ 0.49 0.00 13.27 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.29 1.05 14.31 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 10 0.05 _021_ (net)
+ 1.29 0.00 14.32 ^ _086_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.63 0.30 14.61 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _042_ (net)
+ 0.63 0.00 14.61 v _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.97 0.77 15.39 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _017_ (net)
+ 0.97 0.00 15.39 ^ _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 15.39 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ 64.75 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.44 64.31 library setup time
+ 64.31 data required time
+-----------------------------------------------------------------------------
+ 64.31 data required time
+ -15.39 data arrival time
+-----------------------------------------------------------------------------
+ 48.92 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.min.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.min.rpt
new file mode 100644
index 0000000..856a30f
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.min.rpt
@@ -0,0 +1,179 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.18 1.54 1.54 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.08 io_out[6] (net)
+ 1.18 0.02 1.56 v _070_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.50 0.47 2.03 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _033_ (net)
+ 0.50 0.00 2.03 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.32 0.29 2.32 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.01 _010_ (net)
+ 0.32 0.00 2.32 v _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.32 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.03 0.28 library hold time
+ 0.28 data required time
+-----------------------------------------------------------------------------
+ 0.28 data required time
+ -2.32 data arrival time
+-----------------------------------------------------------------------------
+ 2.04 slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.20 1.55 1.55 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.08 io_out[14] (net)
+ 1.20 0.02 1.57 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.51 0.49 2.06 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _043_ (net)
+ 0.51 0.00 2.06 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.32 0.28 2.34 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.01 _018_ (net)
+ 0.32 0.00 2.34 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.34 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.03 0.28 library hold time
+ 0.28 data required time
+-----------------------------------------------------------------------------
+ 0.28 data required time
+ -2.34 data arrival time
+-----------------------------------------------------------------------------
+ 2.06 slack (MET)
+
+
+Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.15 1.53 1.53 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2 0.08 io_out[15] (net)
+ 1.15 0.00 1.54 v _092_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+ 0.42 0.54 2.07 ^ _092_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+ 1 0.00 _046_ (net)
+ 0.42 0.00 2.07 ^ _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.34 0.29 2.36 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.01 _019_ (net)
+ 0.34 0.00 2.36 v _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.36 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.03 0.28 library hold time
+ 0.28 data required time
+-----------------------------------------------------------------------------
+ 0.28 data required time
+ -2.36 data arrival time
+-----------------------------------------------------------------------------
+ 2.09 slack (MET)
+
+
+Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.17 1.53 1.53 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2 0.08 io_out[7] (net)
+ 1.17 0.02 1.56 v _074_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+ 0.42 0.54 2.09 ^ _074_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+ 1 0.00 _036_ (net)
+ 0.42 0.00 2.09 ^ _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.35 0.30 2.39 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.01 _011_ (net)
+ 0.35 0.00 2.39 v _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.39 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.02 0.27 library hold time
+ 0.27 data required time
+-----------------------------------------------------------------------------
+ 0.27 data required time
+ -2.39 data arrival time
+-----------------------------------------------------------------------------
+ 2.12 slack (MET)
+
+
+Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.29 1.59 1.59 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.08 io_out[2] (net)
+ 1.30 0.03 1.62 v _061_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.52 0.49 2.11 ^ _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _028_ (net)
+ 0.52 0.00 2.11 ^ _064_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.34 0.30 2.41 v _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.01 _006_ (net)
+ 0.34 0.00 2.42 v _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.42 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.03 0.28 library hold time
+ 0.28 data required time
+-----------------------------------------------------------------------------
+ 0.28 data required time
+ -2.42 data arrival time
+-----------------------------------------------------------------------------
+ 2.14 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.rpt
new file mode 100644
index 0000000..6b67ba2
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.rpt
@@ -0,0 +1,47 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 13.00 13.00 ^ input external delay
+ 0.49 0.27 13.27 ^ wb_rst_i (in)
+ 2 0.02 wb_rst_i (net)
+ 0.49 0.00 13.27 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 1.29 1.05 14.31 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 10 0.05 _021_ (net)
+ 1.29 0.00 14.31 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.65 0.32 14.63 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _022_ (net)
+ 0.65 0.00 14.63 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.98 0.79 15.42 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _001_ (net)
+ 0.98 0.00 15.42 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 15.42 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ 64.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ -0.44 64.31 library setup time
+ 64.31 data required time
+-----------------------------------------------------------------------------
+ 64.31 data required time
+ -15.42 data arrival time
+-----------------------------------------------------------------------------
+ 48.89 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.tns.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.wns.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.area.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.area.rpt
new file mode 100644
index 0000000..e9f50e3
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.area.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 67257 u^2 3% utilization.
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.clock_skew.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.clock_skew.rpt
new file mode 100644
index 0000000..0315719
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_094_/CLK ^
+ 0.23
+_094_/CLK ^
+ 0.21 0.00 0.02
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.max.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.max.rpt
new file mode 100644
index 0000000..58c58b8
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.max.rpt
@@ -0,0 +1,209 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 13.00 13.00 ^ input external delay
+ 0.14 0.04 13.04 ^ wb_rst_i (in)
+ 1 0.00 wb_rst_i (net)
+ 0.14 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.70 0.62 13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2 0.03 net1 (net)
+ 0.70 0.01 13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 0.66 0.68 14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 10 0.05 _021_ (net)
+ 0.66 0.00 14.35 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.31 0.30 14.65 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _022_ (net)
+ 0.31 0.00 14.65 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.90 0.72 15.37 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _001_ (net)
+ 0.90 0.00 15.37 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 15.37 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ 64.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ -0.47 64.28 library setup time
+ 64.28 data required time
+-----------------------------------------------------------------------------
+ 64.28 data required time
+ -15.37 data arrival time
+-----------------------------------------------------------------------------
+ 48.91 slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 13.00 13.00 ^ input external delay
+ 0.14 0.04 13.04 ^ wb_rst_i (in)
+ 1 0.00 wb_rst_i (net)
+ 0.14 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.70 0.62 13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2 0.03 net1 (net)
+ 0.70 0.01 13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 0.66 0.68 14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 10 0.05 _021_ (net)
+ 0.66 0.00 14.35 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.30 0.28 14.63 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _032_ (net)
+ 0.30 0.00 14.63 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.89 0.71 15.34 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _009_ (net)
+ 0.89 0.00 15.35 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 15.35 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ 64.75 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ -0.47 64.28 library setup time
+ 64.28 data required time
+-----------------------------------------------------------------------------
+ 64.28 data required time
+ -15.35 data arrival time
+-----------------------------------------------------------------------------
+ 48.93 slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 13.00 13.00 ^ input external delay
+ 0.14 0.04 13.04 ^ wb_rst_i (in)
+ 1 0.00 wb_rst_i (net)
+ 0.14 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.70 0.62 13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2 0.03 net1 (net)
+ 0.70 0.01 13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 0.66 0.68 14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 10 0.05 _021_ (net)
+ 0.66 0.00 14.35 ^ _086_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.29 0.28 14.63 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _042_ (net)
+ 0.29 0.00 14.63 v _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.88 0.71 15.34 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _017_ (net)
+ 0.88 0.00 15.34 ^ _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 15.34 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ 64.75 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ -0.47 64.28 library setup time
+ 64.28 data required time
+-----------------------------------------------------------------------------
+ 64.28 data required time
+ -15.34 data arrival time
+-----------------------------------------------------------------------------
+ 48.94 slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 13.00 13.00 ^ input external delay
+ 0.14 0.04 13.04 ^ wb_rst_i (in)
+ 1 0.00 wb_rst_i (net)
+ 0.14 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.70 0.62 13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2 0.03 net1 (net)
+ 0.70 0.01 13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 0.66 0.68 14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 10 0.05 _021_ (net)
+ 0.66 0.00 14.35 ^ _077_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.28 0.28 14.63 v _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _037_ (net)
+ 0.28 0.00 14.63 v _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.87 0.70 15.33 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _013_ (net)
+ 0.87 0.00 15.33 ^ _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 15.33 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ 64.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ -0.47 64.28 library setup time
+ 64.28 data required time
+-----------------------------------------------------------------------------
+ 64.28 data required time
+ -15.33 data arrival time
+-----------------------------------------------------------------------------
+ 48.95 slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 13.00 13.00 ^ input external delay
+ 0.14 0.04 13.04 ^ wb_rst_i (in)
+ 1 0.00 wb_rst_i (net)
+ 0.14 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.70 0.62 13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2 0.03 net1 (net)
+ 0.70 0.01 13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 0.66 0.68 14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 10 0.05 _021_ (net)
+ 0.66 0.00 14.35 ^ _059_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.30 0.28 14.63 v _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.00 _027_ (net)
+ 0.30 0.00 14.63 v _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.84 0.68 15.31 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _005_ (net)
+ 0.84 0.00 15.32 ^ _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 15.32 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ 64.75 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ -0.47 64.28 library setup time
+ 64.28 data required time
+-----------------------------------------------------------------------------
+ 64.28 data required time
+ -15.32 data arrival time
+-----------------------------------------------------------------------------
+ 48.96 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.min.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.min.rpt
new file mode 100644
index 0000000..453d9d2
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.min.rpt
@@ -0,0 +1,164 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.40 1.14 1.14 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.05 net16 (net)
+ 0.40 0.01 1.15 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.60 0.44 1.59 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.01 _008_ (net)
+ 0.60 0.00 1.59 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 1.59 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.03 0.28 library hold time
+ 0.28 data required time
+-----------------------------------------------------------------------------
+ 0.28 data required time
+ -1.59 data arrival time
+-----------------------------------------------------------------------------
+ 1.32 slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.55 1.31 1.31 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.04 net21 (net)
+ 0.56 0.02 1.32 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.38 0.30 1.62 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _013_ (net)
+ 0.38 0.00 1.62 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 1.62 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.03 0.28 library hold time
+ 0.28 data required time
+-----------------------------------------------------------------------------
+ 0.28 data required time
+ -1.62 data arrival time
+-----------------------------------------------------------------------------
+ 1.34 slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.57 1.31 1.31 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.04 net6 (net)
+ 0.57 0.01 1.33 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.39 0.30 1.63 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _017_ (net)
+ 0.39 0.00 1.63 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 1.63 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.03 0.28 library hold time
+ 0.28 data required time
+-----------------------------------------------------------------------------
+ 0.28 data required time
+ -1.63 data arrival time
+-----------------------------------------------------------------------------
+ 1.36 slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.57 1.32 1.32 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.04 net10 (net)
+ 0.58 0.01 1.33 ^ _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.40 0.31 1.64 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _001_ (net)
+ 0.40 0.00 1.64 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 1.64 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.02 0.27 library hold time
+ 0.27 data required time
+-----------------------------------------------------------------------------
+ 0.27 data required time
+ -1.64 data arrival time
+-----------------------------------------------------------------------------
+ 1.37 slack (MET)
+
+
+Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.63 1.36 1.36 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.05 net13 (net)
+ 0.63 0.01 1.36 ^ _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.38 0.29 1.66 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _005_ (net)
+ 0.38 0.00 1.66 v _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 1.66 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.03 0.28 library hold time
+ 0.28 data required time
+-----------------------------------------------------------------------------
+ 0.28 data required time
+ -1.66 data arrival time
+-----------------------------------------------------------------------------
+ 1.38 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.power.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.power.rpt
new file mode 100644
index 0000000..e110b73
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.power.rpt
@@ -0,0 +1,14 @@
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 7.08e-05 7.86e-06 1.98e-09 7.86e-05 73.8%
+Combinational 9.21e-06 1.84e-05 3.24e-07 2.79e-05 26.2%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 8.00e-05 2.62e-05 3.26e-07 1.07e-04 100.0%
+ 75.1% 24.6% 0.3%
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.rpt
new file mode 100644
index 0000000..d2940b0
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.rpt
@@ -0,0 +1,50 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 13.00 13.00 ^ input external delay
+ 0.14 0.04 13.04 ^ wb_rst_i (in)
+ 1 0.00 wb_rst_i (net)
+ 0.14 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 0.70 0.62 13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2 0.03 net1 (net)
+ 0.70 0.01 13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 0.66 0.68 14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 10 0.05 _021_ (net)
+ 0.66 0.00 14.35 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.31 0.30 14.65 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _022_ (net)
+ 0.31 0.00 14.65 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.90 0.72 15.37 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _001_ (net)
+ 0.90 0.00 15.37 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 15.37 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ 64.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ -0.47 64.28 library setup time
+ 64.28 data required time
+-----------------------------------------------------------------------------
+ 64.28 data required time
+ -15.37 data arrival time
+-----------------------------------------------------------------------------
+ 48.91 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.slew.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.slew.rpt
new file mode 100644
index 0000000..ed40823
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.slew.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.tns.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.wns.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.worst_slack.rpt b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.worst_slack.rpt
new file mode 100644
index 0000000..149696c
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/placement/8-pl_rsz_sta.worst_slack.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 48.91
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 1.32
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.area.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.area.rpt
new file mode 100644
index 0000000..9849480
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.area.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 67586 u^2 3% utilization.
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.clock_skew.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.clock_skew.rpt
new file mode 100644
index 0000000..fe2a127
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_106_/CLK ^
+ 0.78
+_108_/CLK ^
+ 0.70 -0.04 0.04
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.max.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.max.rpt
new file mode 100644
index 0000000..d4d2069
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.max.rpt
@@ -0,0 +1,199 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.09 0.09 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.71 1.54 2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.06 net9 (net)
+ 0.72 0.03 2.35 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.72 3.07 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[16] (net)
+ 0.48 0.00 3.07 ^ io_out[16] (out)
+ 3.07 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.07 data arrival time
+-----------------------------------------------------------------------------
+ 48.68 slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.09 0.09 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.72 1.54 2.32 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.06 net5 (net)
+ 0.72 0.03 2.34 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.72 3.06 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[12] (net)
+ 0.48 0.00 3.06 ^ io_out[12] (out)
+ 3.06 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.06 data arrival time
+-----------------------------------------------------------------------------
+ 48.69 slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[3] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.09 0.09 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.83 1.51 2.29 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2 0.03 net15 (net)
+ 0.83 0.01 2.30 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.73 3.03 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[3] (net)
+ 0.48 0.00 3.03 ^ io_out[3] (out)
+ 3.03 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.03 data arrival time
+-----------------------------------------------------------------------------
+ 48.72 slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.09 0.09 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.66 1.51 2.29 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.05 net20 (net)
+ 0.67 0.02 2.31 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.71 3.02 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[8] (net)
+ 0.48 0.00 3.02 ^ io_out[8] (out)
+ 3.02 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.02 data arrival time
+-----------------------------------------------------------------------------
+ 48.73 slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[4] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.09 0.09 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.65 1.50 2.27 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.05 net16 (net)
+ 0.65 0.02 2.29 ^ output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.71 3.00 ^ output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[4] (net)
+ 0.48 0.00 3.00 ^ io_out[4] (out)
+ 3.00 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.00 data arrival time
+-----------------------------------------------------------------------------
+ 48.75 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.min.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.min.rpt
new file mode 100644
index 0000000..754d25b
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.min.rpt
@@ -0,0 +1,247 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.70 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.40 1.14 1.84 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.05 net16 (net)
+ 0.40 0.01 1.85 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.60 0.44 2.29 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.01 _008_ (net)
+ 0.60 0.00 2.29 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.29 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.09 0.09 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.02 clock uncertainty
+ -0.07 0.95 clock reconvergence pessimism
+ 0.02 0.97 library hold time
+ 0.97 data required time
+-----------------------------------------------------------------------------
+ 0.97 data required time
+ -2.29 data arrival time
+-----------------------------------------------------------------------------
+ 1.32 slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.70 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.55 1.30 2.00 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.04 net21 (net)
+ 0.55 0.02 2.02 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.39 0.30 2.31 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _013_ (net)
+ 0.39 0.00 2.32 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.32 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.09 0.09 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.02 clock uncertainty
+ -0.07 0.95 clock reconvergence pessimism
+ 0.02 0.97 library hold time
+ 0.97 data required time
+-----------------------------------------------------------------------------
+ 0.97 data required time
+ -2.32 data arrival time
+-----------------------------------------------------------------------------
+ 1.34 slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.31 0.71 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.71 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.57 1.31 2.02 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.04 net6 (net)
+ 0.57 0.01 2.03 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.39 0.30 2.34 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _017_ (net)
+ 0.39 0.00 2.34 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.34 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.09 0.09 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.03 clock uncertainty
+ -0.07 0.96 clock reconvergence pessimism
+ 0.02 0.98 library hold time
+ 0.98 data required time
+-----------------------------------------------------------------------------
+ 0.98 data required time
+ -2.34 data arrival time
+-----------------------------------------------------------------------------
+ 1.36 slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.70 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.58 1.31 2.01 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5 0.05 net10 (net)
+ 0.58 0.01 2.03 ^ _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.40 0.31 2.34 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.01 _001_ (net)
+ 0.40 0.00 2.34 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.34 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.09 0.09 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 9 0.03 clknet_1_1__leaf_wb_clk_i (net)
+ 0.13 0.00 0.77 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.02 clock uncertainty
+ -0.07 0.95 clock reconvergence pessimism
+ 0.02 0.97 library hold time
+ 0.97 data required time
+-----------------------------------------------------------------------------
+ 0.97 data required time
+ -2.34 data arrival time
+-----------------------------------------------------------------------------
+ 1.37 slack (MET)
+
+
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.08 0.08 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.31 0.71 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.71 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.38 1.06 1.77 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.03 net18 (net)
+ 0.38 0.01 1.77 v _070_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.37 0.33 2.10 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _033_ (net)
+ 0.37 0.00 2.10 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.31 0.26 2.37 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.01 _010_ (net)
+ 0.31 0.00 2.37 v _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.37 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.09 0.09 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 1.03 clock uncertainty
+ -0.07 0.96 clock reconvergence pessimism
+ 0.03 0.99 library hold time
+ 0.99 data required time
+-----------------------------------------------------------------------------
+ 0.99 data required time
+ -2.37 data arrival time
+-----------------------------------------------------------------------------
+ 1.38 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.power.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.power.rpt
new file mode 100644
index 0000000..398af4e
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.power.rpt
@@ -0,0 +1,14 @@
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 7.07e-05 7.81e-06 1.98e-09 7.86e-05 42.5%
+Combinational 6.84e-05 3.74e-05 3.25e-07 1.06e-04 57.5%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 1.39e-04 4.52e-05 3.27e-07 1.85e-04 100.0%
+ 75.4% 24.5% 0.2%
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.rpt
new file mode 100644
index 0000000..3e63052
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.rpt
@@ -0,0 +1,48 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.18 0.09 0.09 ^ wb_clk_i (in)
+ 1 0.02 wb_clk_i (net)
+ 0.18 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 11 0.04 clknet_1_0__leaf_wb_clk_i (net)
+ 0.14 0.00 0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.71 1.54 2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 6 0.06 net9 (net)
+ 0.72 0.03 2.35 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.72 3.07 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[16] (net)
+ 0.48 0.00 3.07 ^ io_out[16] (out)
+ 3.07 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.07 data arrival time
+-----------------------------------------------------------------------------
+ 48.68 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.slew.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.slew.rpt
new file mode 100644
index 0000000..ed40823
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.slew.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.tns.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.wns.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.worst_slack.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.worst_slack.rpt
new file mode 100644
index 0000000..0b29f0b
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/12-rt_rsz_sta.worst_slack.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 48.68
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 1.32
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.clock_skew.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.clock_skew.rpt
new file mode 100644
index 0000000..8518ccb
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_094_/CLK ^
+ 0.80
+_097_/CLK ^
+ 0.72 -0.04 0.04
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.max.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.max.rpt
new file mode 100644
index 0000000..90a07bb
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.max.rpt
@@ -0,0 +1,199 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.09 0.09 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.45 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.16 0.35 0.80 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.05 clknet_1_0__leaf_wb_clk_i (net)
+ 0.16 0.00 0.80 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.79 1.59 2.39 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 12 0.06 net9 (net)
+ 0.79 0.03 2.42 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.73 3.15 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[16] (net)
+ 0.48 0.00 3.15 ^ io_out[16] (out)
+ 3.15 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.15 data arrival time
+-----------------------------------------------------------------------------
+ 48.60 slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.09 0.09 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.34 0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.04 clknet_1_1__leaf_wb_clk_i (net)
+ 0.15 0.00 0.79 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.80 1.59 2.39 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 12 0.07 net5 (net)
+ 0.80 0.03 2.41 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.73 3.14 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[12] (net)
+ 0.48 0.00 3.14 ^ io_out[12] (out)
+ 3.14 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.14 data arrival time
+-----------------------------------------------------------------------------
+ 48.61 slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.09 0.09 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.45 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.16 0.35 0.80 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.05 clknet_1_0__leaf_wb_clk_i (net)
+ 0.16 0.00 0.80 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.74 1.56 2.36 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 12 0.06 net20 (net)
+ 0.74 0.03 2.39 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.72 3.11 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[8] (net)
+ 0.48 0.00 3.11 ^ io_out[8] (out)
+ 3.11 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.11 data arrival time
+-----------------------------------------------------------------------------
+ 48.64 slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[3] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.09 0.09 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.34 0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.04 clknet_1_1__leaf_wb_clk_i (net)
+ 0.15 0.00 0.79 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.88 1.55 2.34 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 4 0.04 net15 (net)
+ 0.88 0.01 2.35 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.74 3.09 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[3] (net)
+ 0.48 0.00 3.10 ^ io_out[3] (out)
+ 3.10 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.10 data arrival time
+-----------------------------------------------------------------------------
+ 48.65 slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[4] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.09 0.09 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.34 0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.04 clknet_1_1__leaf_wb_clk_i (net)
+ 0.15 0.00 0.79 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.73 1.55 2.34 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 12 0.06 net16 (net)
+ 0.73 0.02 2.37 ^ output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.72 3.08 ^ output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[4] (net)
+ 0.48 0.00 3.09 ^ io_out[4] (out)
+ 3.09 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.09 data arrival time
+-----------------------------------------------------------------------------
+ 48.66 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.min.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.min.rpt
new file mode 100644
index 0000000..77644d2
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.min.rpt
@@ -0,0 +1,247 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.08 0.08 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.31 0.72 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.04 clknet_1_1__leaf_wb_clk_i (net)
+ 0.15 0.00 0.72 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.43 1.17 1.89 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 12 0.06 net16 (net)
+ 0.43 0.01 1.90 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.65 0.48 2.38 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _008_ (net)
+ 0.65 0.00 2.38 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.38 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.09 0.09 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.34 0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.04 clknet_1_1__leaf_wb_clk_i (net)
+ 0.15 0.00 0.79 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.04 clock uncertainty
+ -0.08 0.97 clock reconvergence pessimism
+ 0.03 0.99 library hold time
+ 0.99 data required time
+-----------------------------------------------------------------------------
+ 0.99 data required time
+ -2.38 data arrival time
+-----------------------------------------------------------------------------
+ 1.39 slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.08 0.08 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.31 0.72 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.04 clknet_1_1__leaf_wb_clk_i (net)
+ 0.15 0.00 0.72 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.62 1.34 2.06 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 10 0.05 net21 (net)
+ 0.62 0.02 2.07 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.42 0.32 2.39 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.01 _013_ (net)
+ 0.42 0.00 2.40 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.40 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.09 0.09 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.34 0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.04 clknet_1_1__leaf_wb_clk_i (net)
+ 0.15 0.00 0.79 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.04 clock uncertainty
+ -0.08 0.97 clock reconvergence pessimism
+ 0.02 0.99 library hold time
+ 0.99 data required time
+-----------------------------------------------------------------------------
+ 0.99 data required time
+ -2.40 data arrival time
+-----------------------------------------------------------------------------
+ 1.41 slack (MET)
+
+
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.08 0.08 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.16 0.32 0.72 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.05 clknet_1_0__leaf_wb_clk_i (net)
+ 0.16 0.00 0.72 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.63 1.35 2.08 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 10 0.05 net6 (net)
+ 0.63 0.01 2.09 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.42 0.33 2.42 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 _017_ (net)
+ 0.42 0.00 2.42 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.42 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.09 0.09 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.45 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.16 0.35 0.80 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.05 clknet_1_0__leaf_wb_clk_i (net)
+ 0.16 0.00 0.80 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.05 clock uncertainty
+ -0.08 0.98 clock reconvergence pessimism
+ 0.02 0.99 library hold time
+ 0.99 data required time
+-----------------------------------------------------------------------------
+ 0.99 data required time
+ -2.42 data arrival time
+-----------------------------------------------------------------------------
+ 1.43 slack (MET)
+
+
+Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.08 0.08 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.31 0.72 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.04 clknet_1_1__leaf_wb_clk_i (net)
+ 0.15 0.00 0.72 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.64 1.35 2.07 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 10 0.05 net10 (net)
+ 0.64 0.01 2.09 ^ _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.43 0.33 2.42 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 _001_ (net)
+ 0.43 0.00 2.42 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 2.42 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.09 0.09 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.34 0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.04 clknet_1_1__leaf_wb_clk_i (net)
+ 0.15 0.00 0.79 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.04 clock uncertainty
+ -0.08 0.97 clock reconvergence pessimism
+ 0.01 0.98 library hold time
+ 0.98 data required time
+-----------------------------------------------------------------------------
+ 0.98 data required time
+ -2.42 data arrival time
+-----------------------------------------------------------------------------
+ 1.44 slack (MET)
+
+
+Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.08 0.08 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.31 0.72 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.04 clknet_1_1__leaf_wb_clk_i (net)
+ 0.15 0.00 0.72 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.39 1.07 1.79 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 4 0.03 net8 (net)
+ 0.39 0.00 1.79 v _092_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+ 0.42 0.34 2.13 ^ _092_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+ 1 0.00 _046_ (net)
+ 0.42 0.00 2.13 ^ _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.35 0.30 2.43 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.01 _019_ (net)
+ 0.35 0.00 2.43 v _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.43 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.09 0.09 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.34 0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.04 clknet_1_1__leaf_wb_clk_i (net)
+ 0.15 0.00 0.79 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 1.04 clock uncertainty
+ -0.08 0.97 clock reconvergence pessimism
+ 0.02 0.99 library hold time
+ 0.99 data required time
+-----------------------------------------------------------------------------
+ 0.99 data required time
+ -2.43 data arrival time
+-----------------------------------------------------------------------------
+ 1.44 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.rpt
new file mode 100644
index 0000000..b241e89
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.rpt
@@ -0,0 +1,48 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.19 0.09 0.09 ^ wb_clk_i (in)
+ 2 0.02 wb_clk_i (net)
+ 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.04 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.45 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.16 0.35 0.80 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.05 clknet_1_0__leaf_wb_clk_i (net)
+ 0.16 0.00 0.80 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.79 1.59 2.39 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 12 0.06 net9 (net)
+ 0.79 0.03 2.42 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 0.48 0.73 3.15 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
+ 1 0.07 io_out[16] (net)
+ 0.48 0.00 3.15 ^ io_out[16] (out)
+ 3.15 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (propagated)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -3.15 data arrival time
+-----------------------------------------------------------------------------
+ 48.60 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.tns.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.wns.rpt b/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/16-grt_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/19-wire_lengths.csv b/openlane/cntr_example/runs/cntr_example/reports/routing/19-wire_lengths.csv
new file mode 100644
index 0000000..56a75b6
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/19-wire_lengths.csv
@@ -0,0 +1,112 @@
+net,length_um
+net12,2680.31
+net5,2679.92
+net9,2649.12
+net13,2447.43
+net11,2436.85
+net17,2329.16
+net3,2240.71
+net20,2231.39
+net14,2186.55
+net2,2116.94
+net16,2100.63
+net10,1962.55
+net6,1910.84
+net15,1855.11
+net21,1749.24
+net4,1587.48
+net7,1239.3
+_015_,1173.3
+_002_,1171.06
+net18,1135.28
+_014_,1108.85
+net19,1095.46
+_001_,1085.38
+_003_,1080.34
+_009_,1066.02
+_006_,1058.74
+_017_,1050.71
+_012_,1045.3
+net8,1033.35
+_013_,1027.89
+_010_,994.1
+net1,980.1
+_005_,952.34
+_011_,946.69
+_018_,940.34
+_020_,939.48
+_000_,926.39
+_007_,924.9
+_004_,916.82
+_019_,881.54
+_016_,805.01
+_008_,672.9
+_021_,533.44
+clknet_1_0__leaf_wb_clk_i,213.77
+clknet_1_1__leaf_wb_clk_i,185.41
+_022_,106.96
+_026_,104.26
+_043_,90.72
+_025_,85.68
+_039_,85.46
+_041_,77.38
+_038_,76.26
+_029_,74.53
+wb_clk_i,71.59
+_045_,70.61
+_028_,64.4
+_023_,62.82
+_044_,62.82
+_030_,51.62
+_033_,39.25
+_036_,38.74
+_034_,36.45
+_046_,35.89
+_040_,31.92
+clknet_0_wb_clk_i,27.17
+io_out[5],25.67
+_031_,24.69
+io_out[14],24.55
+_027_,24.08
+io_out[19],23.94
+net30,23.94
+io_out[0],22.26
+net29,22.26
+io_out[17],21.75
+io_out[15],20.58
+io_out[1],20.58
+io_out[7],20.58
+net34,20.07
+net23,18.95
+io_out[10],18.39
+io_out[12],18.39
+io_out[8],18.34
+net33,17.27
+io_out[6],17.22
+io_out[3],16.66
+net37,16.15
+net24,16.1
+_035_,15.68
+io_out[2],14.42
+net36,13.3
+wb_rst_i,13.03
+_024_,11.2
+net39,11.11
+_037_,9.52
+io_out[13],9.38
+io_out[16],9.38
+io_out[4],9.38
+io_out[18],8.87
+io_out[9],8.82
+net27,8.26
+_032_,7.89
+_042_,7.89
+io_out[11],7.7
+net25,7.7
+net31,7.14
+net26,6.58
+net28,6.58
+net32,6.58
+net35,6.07
+net38,5.51
+net22,5.51
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/drt.drc b/openlane/cntr_example/runs/cntr_example/reports/routing/drt.drc
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/drt.drc
diff --git a/openlane/cntr_example/runs/cntr_example/reports/routing/drt.klayout.xml b/openlane/cntr_example/runs/cntr_example/reports/routing/drt.klayout.xml
new file mode 100644
index 0000000..37b4626
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/routing/drt.klayout.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>cntr_example</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.area.rpt b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.area.rpt
new file mode 100644
index 0000000..60077eb
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.area.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 68288 u^2 3% utilization.
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.clock_skew.rpt b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.clock_skew.rpt
new file mode 100644
index 0000000..697cb84
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_106_/CLK ^
+ 0.86
+_107_/CLK ^
+ 0.75 -0.05 0.06
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.max.rpt b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.max.rpt
new file mode 100644
index 0000000..cd9ed49
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.max.rpt
@@ -0,0 +1,240 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 13.00 13.00 ^ input external delay
+ 0.19 0.07 13.07 ^ wb_rst_i (in)
+ 2 0.00 wb_rst_i (net)
+ 0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.12 net1 (net)
+ 2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+ 1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+ 20 0.18 _020_ (net)
+ 1.63 0.02 16.44 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 18.95 11.96 28.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.43 _012_ (net)
+ 18.95 0.12 28.52 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 28.52 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock source latency
+ 0.22 0.10 65.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.08 clknet_1_0__leaf_wb_clk_i (net)
+ 0.19 0.00 65.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ -0.25 65.52 clock uncertainty
+ 0.00 65.52 clock reconvergence pessimism
+ 1.23 66.75 library setup time
+ 66.75 data required time
+-----------------------------------------------------------------------------
+ 66.75 data required time
+ -28.52 data arrival time
+-----------------------------------------------------------------------------
+ 38.23 slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 13.00 13.00 ^ input external delay
+ 0.19 0.07 13.07 ^ wb_rst_i (in)
+ 2 0.00 wb_rst_i (net)
+ 0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.12 net1 (net)
+ 2.79 0.03 15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 1.63 1.30 16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 20 0.14 _021_ (net)
+ 1.63 0.00 16.32 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1.44 0.51 16.84 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 2 0.02 _022_ (net)
+ 1.44 0.00 16.84 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 10.03 6.54 23.38 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.22 _001_ (net)
+ 10.03 0.07 23.45 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 23.45 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock source latency
+ 0.22 0.10 65.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.17 0.32 65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.06 clknet_1_1__leaf_wb_clk_i (net)
+ 0.17 0.00 65.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ -0.25 65.50 clock uncertainty
+ 0.00 65.50 clock reconvergence pessimism
+ 0.26 65.77 library setup time
+ 65.77 data required time
+-----------------------------------------------------------------------------
+ 65.77 data required time
+ -23.45 data arrival time
+-----------------------------------------------------------------------------
+ 42.32 slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 13.00 13.00 ^ input external delay
+ 0.19 0.07 13.07 ^ wb_rst_i (in)
+ 2 0.00 wb_rst_i (net)
+ 0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.12 net1 (net)
+ 2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+ 1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+ 20 0.18 _020_ (net)
+ 1.62 0.02 16.44 v _084_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 10.00 6.59 23.02 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.23 _015_ (net)
+ 10.00 0.08 23.10 ^ _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 23.10 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock source latency
+ 0.22 0.10 65.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.08 clknet_1_0__leaf_wb_clk_i (net)
+ 0.19 0.00 65.77 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ -0.25 65.52 clock uncertainty
+ 0.00 65.52 clock reconvergence pessimism
+ 0.27 65.79 library setup time
+ 65.79 data required time
+-----------------------------------------------------------------------------
+ 65.79 data required time
+ -23.10 data arrival time
+-----------------------------------------------------------------------------
+ 42.69 slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 13.00 13.00 ^ input external delay
+ 0.19 0.07 13.07 ^ wb_rst_i (in)
+ 2 0.00 wb_rst_i (net)
+ 0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.12 net1 (net)
+ 2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+ 1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+ 20 0.18 _020_ (net)
+ 1.63 0.02 16.45 v _048_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 9.99 6.50 22.95 ^ _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.23 _000_ (net)
+ 9.99 0.05 23.00 ^ _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 23.00 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock source latency
+ 0.22 0.10 65.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.08 clknet_1_0__leaf_wb_clk_i (net)
+ 0.19 0.00 65.77 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ -0.25 65.52 clock uncertainty
+ 0.00 65.52 clock reconvergence pessimism
+ 0.27 65.79 library setup time
+ 65.79 data required time
+-----------------------------------------------------------------------------
+ 65.79 data required time
+ -23.00 data arrival time
+-----------------------------------------------------------------------------
+ 42.79 slack (MET)
+
+
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 13.00 13.00 ^ input external delay
+ 0.19 0.07 13.07 ^ wb_rst_i (in)
+ 2 0.00 wb_rst_i (net)
+ 0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.12 net1 (net)
+ 2.79 0.03 15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 1.63 1.30 16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
+ 20 0.14 _021_ (net)
+ 1.63 0.01 16.33 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1.03 0.36 16.69 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _032_ (net)
+ 1.03 0.00 16.69 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 9.40 6.08 22.77 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.21 _009_ (net)
+ 9.40 0.06 22.83 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 22.83 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock source latency
+ 0.22 0.10 65.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.08 clknet_1_0__leaf_wb_clk_i (net)
+ 0.19 0.00 65.77 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ -0.25 65.52 clock uncertainty
+ 0.00 65.52 clock reconvergence pessimism
+ 0.20 65.73 library setup time
+ 65.73 data required time
+-----------------------------------------------------------------------------
+ 65.73 data required time
+ -22.83 data arrival time
+-----------------------------------------------------------------------------
+ 42.90 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.min.rpt b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.min.rpt
new file mode 100644
index 0000000..cd37947
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.min.rpt
@@ -0,0 +1,256 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.22 0.10 0.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.08 clknet_1_0__leaf_wb_clk_i (net)
+ 0.19 0.00 0.77 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 1.35 1.72 2.49 v _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 10 0.22 net6 (net)
+ 1.36 0.06 2.55 v _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.47 0.58 3.13 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _042_ (net)
+ 0.47 0.00 3.13 ^ _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1.55 1.04 4.17 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.08 _017_ (net)
+ 1.55 0.01 4.19 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 4.19 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.22 0.11 0.11 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.08 clknet_1_0__leaf_wb_clk_i (net)
+ 0.19 0.00 0.85 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.10 clock uncertainty
+ -0.08 1.02 clock reconvergence pessimism
+ -0.29 0.73 library hold time
+ 0.73 data required time
+-----------------------------------------------------------------------------
+ 0.73 data required time
+ -4.19 data arrival time
+-----------------------------------------------------------------------------
+ 3.46 slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.22 0.10 0.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.08 clknet_1_0__leaf_wb_clk_i (net)
+ 0.19 0.00 0.77 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.36 1.66 2.43 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.11 net7 (net)
+ 1.36 0.03 2.46 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.81 0.74 3.19 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.02 _043_ (net)
+ 0.81 0.00 3.19 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1.70 1.19 4.38 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.10 _018_ (net)
+ 1.70 0.02 4.40 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 4.40 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.22 0.11 0.11 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.08 clknet_1_0__leaf_wb_clk_i (net)
+ 0.19 0.00 0.85 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 1.10 clock uncertainty
+ -0.08 1.02 clock reconvergence pessimism
+ -0.35 0.67 library hold time
+ 0.67 data required time
+-----------------------------------------------------------------------------
+ 0.67 data required time
+ -4.40 data arrival time
+-----------------------------------------------------------------------------
+ 3.73 slack (MET)
+
+
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.22 0.10 0.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.08 clknet_1_0__leaf_wb_clk_i (net)
+ 0.19 0.00 0.77 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 1.44 1.79 2.56 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 12 0.23 net2 (net)
+ 1.44 0.04 2.60 v _058_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 4.10 2.67 5.27 ^ _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.09 _004_ (net)
+ 4.10 0.02 5.29 ^ _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 5.29 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.22 0.11 0.11 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.08 clknet_1_0__leaf_wb_clk_i (net)
+ 0.19 0.00 0.85 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.10 clock uncertainty
+ -0.08 1.02 clock reconvergence pessimism
+ 0.30 1.32 library hold time
+ 1.32 data required time
+-----------------------------------------------------------------------------
+ 1.32 data required time
+ -5.29 data arrival time
+-----------------------------------------------------------------------------
+ 3.97 slack (MET)
+
+
+Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.22 0.10 0.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.06 clknet_1_1__leaf_wb_clk_i (net)
+ 0.17 0.00 0.75 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.08 2.05 2.81 v _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 4 0.17 net15 (net)
+ 2.08 0.04 2.84 v _065_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+ 0.47 0.78 3.63 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
+ 1 0.01 _031_ (net)
+ 0.47 0.00 3.63 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1.57 1.05 4.68 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.09 _007_ (net)
+ 1.57 0.02 4.70 v _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 4.70 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.22 0.11 0.11 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.06 clknet_1_1__leaf_wb_clk_i (net)
+ 0.17 0.00 0.83 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.25 1.08 clock uncertainty
+ -0.08 1.00 clock reconvergence pessimism
+ -0.33 0.68 library hold time
+ 0.68 data required time
+-----------------------------------------------------------------------------
+ 0.68 data required time
+ -4.70 data arrival time
+-----------------------------------------------------------------------------
+ 4.02 slack (MET)
+
+
+Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.22 0.10 0.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.06 clknet_1_1__leaf_wb_clk_i (net)
+ 0.17 0.00 0.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 1.24 1.65 2.41 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 10 0.20 net21 (net)
+ 1.25 0.07 2.47 v _077_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 0.44 0.51 2.98 ^ _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
+ 1 0.01 _037_ (net)
+ 0.44 0.00 2.98 ^ _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2.61 1.64 4.63 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 2 0.13 _013_ (net)
+ 2.61 0.04 4.66 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 4.66 data arrival time
+
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock source latency
+ 0.22 0.11 0.11 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 18 0.06 clknet_1_1__leaf_wb_clk_i (net)
+ 0.17 0.00 0.83 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 0.25 1.08 clock uncertainty
+ -0.08 1.00 clock reconvergence pessimism
+ -0.56 0.44 library hold time
+ 0.44 data required time
+-----------------------------------------------------------------------------
+ 0.44 data required time
+ -4.66 data arrival time
+-----------------------------------------------------------------------------
+ 4.22 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.power.rpt b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.power.rpt
new file mode 100644
index 0000000..e615028
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.power.rpt
@@ -0,0 +1,14 @@
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 7.17e-05 5.86e-05 1.98e-09 1.30e-04 44.9%
+Combinational 7.29e-05 8.57e-05 1.28e-06 1.60e-04 55.1%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 1.45e-04 1.44e-04 1.28e-06 2.90e-04 100.0%
+ 49.8% 49.7% 0.4%
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.rpt b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.rpt
new file mode 100644
index 0000000..eb51bd7
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.rpt
@@ -0,0 +1,55 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: wb_rst_i (input port clocked by wb_clk_i)
+Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (propagated)
+ 13.00 13.00 ^ input external delay
+ 0.19 0.07 13.07 ^ wb_rst_i (in)
+ 2 0.00 wb_rst_i (net)
+ 0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
+ 4 0.12 net1 (net)
+ 2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+ 1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
+ 20 0.18 _020_ (net)
+ 1.63 0.02 16.44 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 18.95 11.96 28.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 2 0.43 _012_ (net)
+ 18.95 0.12 28.52 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ 28.52 data arrival time
+
+ 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock source latency
+ 0.22 0.10 65.10 ^ wb_clk_i (in)
+ 2 0.03 wb_clk_i (net)
+ 0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 2 0.05 clknet_0_wb_clk_i (net)
+ 0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
+ 22 0.08 clknet_1_0__leaf_wb_clk_i (net)
+ 0.19 0.00 65.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
+ -0.25 65.52 clock uncertainty
+ 0.00 65.52 clock reconvergence pessimism
+ 1.23 66.75 library setup time
+ 66.75 data required time
+-----------------------------------------------------------------------------
+ 66.75 data required time
+ -28.52 data arrival time
+-----------------------------------------------------------------------------
+ 38.23 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.slew.rpt b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.slew.rpt
new file mode 100644
index 0000000..897bb5f
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.slew.rpt
@@ -0,0 +1,44 @@
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+max slew
+
+Pin Limit Slew Slack
+------------------------------------------------------------
+ANTENNA__106__D/I 8.60 18.95 -10.35 (VIOLATED)
+_106_/D 8.60 18.95 -10.35 (VIOLATED)
+_076_/ZN 8.60 18.95 -10.35 (VIOLATED)
+_095_/D 8.60 10.03 -1.43 (VIOLATED)
+ANTENNA__095__D/I 8.60 10.03 -1.43 (VIOLATED)
+_051_/ZN 8.60 10.03 -1.43 (VIOLATED)
+_109_/D 8.60 10.00 -1.40 (VIOLATED)
+ANTENNA__109__D/I 8.60 10.00 -1.40 (VIOLATED)
+_084_/ZN 8.60 10.00 -1.40 (VIOLATED)
+_094_/D 8.60 9.99 -1.39 (VIOLATED)
+ANTENNA__094__D/I 8.60 9.99 -1.39 (VIOLATED)
+_048_/ZN 8.60 9.99 -1.39 (VIOLATED)
+_103_/D 8.60 9.40 -0.80 (VIOLATED)
+ANTENNA__103__D/I 8.60 9.40 -0.80 (VIOLATED)
+_069_/ZN 8.60 9.40 -0.80 (VIOLATED)
+
+max capacitance
+
+Pin Limit Cap Slack
+------------------------------------------------------------
+_076_/ZN 0.18 0.43 -0.25 (VIOLATED)
+_084_/ZN 0.18 0.23 -0.04 (VIOLATED)
+_048_/ZN 0.18 0.23 -0.04 (VIOLATED)
+_051_/ZN 0.18 0.22 -0.04 (VIOLATED)
+_069_/ZN 0.18 0.21 -0.03 (VIOLATED)
+_082_/ZN 0.18 0.19 -0.01 (VIOLATED)
+_060_/ZN 0.18 0.19 -0.01 (VIOLATED)
+_064_/ZN 0.18 0.19 -0.01 (VIOLATED)
+_075_/ZN 0.18 0.19 -0.00 (VIOLATED)
+
+
+===========================================================================
+max slew violation count 15
+max fanout violation count 0
+max cap violation count 9
+============================================================================
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.tns.rpt b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.wns.rpt b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.worst_slack.rpt b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.worst_slack.rpt
new file mode 100644
index 0000000..c212719
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/22-rcx_sta.worst_slack.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 38.23
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 3.46
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/27-cntr_example.lvs.rpt b/openlane/cntr_example/runs/cntr_example/reports/signoff/27-cntr_example.lvs.rpt
new file mode 100644
index 0000000..0a843e5
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/27-cntr_example.lvs.rpt
@@ -0,0 +1,3 @@
+LVS reports no net, device, pin, or property mismatches.
+
+Total errors = 0
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/29-antenna_violators.rpt b/openlane/cntr_example/runs/cntr_example/reports/signoff/29-antenna_violators.rpt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/29-antenna_violators.rpt
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.klayout.xml b/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.klayout.xml
new file mode 100644
index 0000000..37b4626
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.klayout.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" ?>
+<report-database>
+ <categories/>
+ <cells>
+ <cell>
+ <name>cntr_example</name>
+ </cell>
+ </cells>
+ <items/>
+</report-database>
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.rdb b/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.rdb
new file mode 100644
index 0000000..a939f10
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.rdb
@@ -0,0 +1 @@
+$cntr_example 100
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.rpt b/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.rpt
new file mode 100644
index 0000000..bb4263b
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.rpt
@@ -0,0 +1,5 @@
+cntr_example
+----------------------------------------
+[INFO]: COUNT: 0
+[INFO]: Should be divided by 3 or 4
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.tcl b/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.tcl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.tcl
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.tr b/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.tr
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/drc.tr
diff --git a/openlane/cntr_example/runs/cntr_example/reports/signoff/spice.feedback.txt b/openlane/cntr_example/runs/cntr_example/reports/signoff/spice.feedback.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/signoff/spice.feedback.txt
diff --git a/openlane/cntr_example/runs/cntr_example/reports/synthesis/1-synthesis.AREA_0.chk.rpt b/openlane/cntr_example/runs/cntr_example/reports/synthesis/1-synthesis.AREA_0.chk.rpt
new file mode 100644
index 0000000..a030c33
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/synthesis/1-synthesis.AREA_0.chk.rpt
@@ -0,0 +1,42 @@
+
+18. Executing CHECK pass (checking for obvious problems).
+Checking module cntr_example...
+Warning: Wire cntr_example.\io_out [37] is used but has no driver.
+Warning: Wire cntr_example.\io_out [36] is used but has no driver.
+Warning: Wire cntr_example.\io_out [35] is used but has no driver.
+Warning: Wire cntr_example.\io_out [34] is used but has no driver.
+Warning: Wire cntr_example.\io_out [33] is used but has no driver.
+Warning: Wire cntr_example.\io_out [32] is used but has no driver.
+Warning: Wire cntr_example.\io_out [31] is used but has no driver.
+Warning: Wire cntr_example.\io_out [30] is used but has no driver.
+Warning: Wire cntr_example.\io_out [29] is used but has no driver.
+Warning: Wire cntr_example.\io_out [28] is used but has no driver.
+Warning: Wire cntr_example.\io_out [27] is used but has no driver.
+Warning: Wire cntr_example.\io_out [26] is used but has no driver.
+Warning: Wire cntr_example.\io_out [25] is used but has no driver.
+Warning: Wire cntr_example.\io_out [24] is used but has no driver.
+Warning: Wire cntr_example.\io_out [23] is used but has no driver.
+Warning: Wire cntr_example.\io_out [22] is used but has no driver.
+Warning: Wire cntr_example.\io_out [21] is used but has no driver.
+Warning: Wire cntr_example.\io_out [20] is used but has no driver.
+Warning: Wire cntr_example.\io_out [19] is used but has no driver.
+Warning: Wire cntr_example.\io_out [18] is used but has no driver.
+Warning: Wire cntr_example.\io_out [17] is used but has no driver.
+Warning: Wire cntr_example.\io_out [16] is used but has no driver.
+Warning: Wire cntr_example.\io_out [15] is used but has no driver.
+Warning: Wire cntr_example.\io_out [14] is used but has no driver.
+Warning: Wire cntr_example.\io_out [13] is used but has no driver.
+Warning: Wire cntr_example.\io_out [12] is used but has no driver.
+Warning: Wire cntr_example.\io_out [11] is used but has no driver.
+Warning: Wire cntr_example.\io_out [10] is used but has no driver.
+Warning: Wire cntr_example.\io_out [9] is used but has no driver.
+Warning: Wire cntr_example.\io_out [8] is used but has no driver.
+Warning: Wire cntr_example.\io_out [7] is used but has no driver.
+Warning: Wire cntr_example.\io_out [6] is used but has no driver.
+Warning: Wire cntr_example.\io_out [5] is used but has no driver.
+Warning: Wire cntr_example.\io_out [4] is used but has no driver.
+Warning: Wire cntr_example.\io_out [3] is used but has no driver.
+Warning: Wire cntr_example.\io_out [2] is used but has no driver.
+Warning: Wire cntr_example.\io_out [1] is used but has no driver.
+Warning: Wire cntr_example.\io_out [0] is used but has no driver.
+Found and reported 38 problems.
diff --git a/openlane/cntr_example/runs/cntr_example/reports/synthesis/1-synthesis.AREA_0.stat.rpt b/openlane/cntr_example/runs/cntr_example/reports/synthesis/1-synthesis.AREA_0.stat.rpt
new file mode 100644
index 0000000..9aa474f
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/synthesis/1-synthesis.AREA_0.stat.rpt
@@ -0,0 +1,26 @@
+
+19. Printing statistics.
+
+=== cntr_example ===
+
+ Number of wires: 50
+ Number of wire bits: 87
+ Number of public wires: 3
+ Number of public wire bits: 40
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 85
+ gf180mcu_fd_sc_mcu7t5v0__aoi21_1 10
+ gf180mcu_fd_sc_mcu7t5v0__buf_1 1
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 20
+ gf180mcu_fd_sc_mcu7t5v0__inv_1 1
+ gf180mcu_fd_sc_mcu7t5v0__nand2_1 5
+ gf180mcu_fd_sc_mcu7t5v0__nand3_1 5
+ gf180mcu_fd_sc_mcu7t5v0__nor2_1 15
+ gf180mcu_fd_sc_mcu7t5v0__oai21_1 5
+ gf180mcu_fd_sc_mcu7t5v0__tiel 18
+ gf180mcu_fd_sc_mcu7t5v0__xor2_1 5
+
+ Chip area for module '\cntr_example': 2177.638400
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/synthesis/1-synthesis_dff.stat b/openlane/cntr_example/runs/cntr_example/reports/synthesis/1-synthesis_dff.stat
new file mode 100644
index 0000000..dba64ae
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/synthesis/1-synthesis_dff.stat
@@ -0,0 +1,21 @@
+
+11. Printing statistics.
+
+=== cntr_example ===
+
+ Number of wires: 43
+ Number of wire bits: 270
+ Number of public wires: 3
+ Number of public wire bits: 40
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 70
+ $_ANDNOT_ 5
+ $_MUX_ 20
+ $_NAND_ 5
+ $_NOT_ 5
+ $_XNOR_ 5
+ $_XOR_ 10
+ gf180mcu_fd_sc_mcu7t5v0__dffq_1 20
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/synthesis/1-synthesis_pre.stat b/openlane/cntr_example/runs/cntr_example/reports/synthesis/1-synthesis_pre.stat
new file mode 100644
index 0000000..33a74d3
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/synthesis/1-synthesis_pre.stat
@@ -0,0 +1,20 @@
+
+9. Printing statistics.
+
+=== cntr_example ===
+
+ Number of wires: 23
+ Number of wire bits: 250
+ Number of public wires: 3
+ Number of public wire bits: 40
+ Number of memories: 0
+ Number of memory bits: 0
+ Number of processes: 0
+ Number of cells: 50
+ $_ANDNOT_ 5
+ $_NAND_ 5
+ $_NOT_ 5
+ $_SDFF_PN0_ 20
+ $_XNOR_ 5
+ $_XOR_ 10
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.area.rpt b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.area.rpt
new file mode 100644
index 0000000..d116ebc
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.area.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_design_area
+============================================================================
+Design area 2178 u^2 100% utilization.
diff --git a/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.clock_skew.rpt b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.clock_skew.rpt
new file mode 100644
index 0000000..0315719
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.clock_skew.rpt
@@ -0,0 +1,11 @@
+
+===========================================================================
+ report_clock_skew
+============================================================================
+Clock wb_clk_i
+Latency CRPR Skew
+_094_/CLK ^
+ 0.23
+_094_/CLK ^
+ 0.21 0.00 0.02
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.max.rpt b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.max.rpt
new file mode 100644
index 0000000..989383f
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.max.rpt
@@ -0,0 +1,144 @@
+
+===========================================================================
+report_checks -path_delay max (Setup)
+============================================================================
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.35 2.41 2.41 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.10 io_out[0] (net)
+ 2.35 0.00 2.41 ^ io_out[0] (out)
+ 2.41 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -2.41 data arrival time
+-----------------------------------------------------------------------------
+ 49.34 slack (MET)
+
+
+Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[12] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.35 2.41 2.41 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.10 io_out[12] (net)
+ 2.35 0.00 2.41 ^ io_out[12] (out)
+ 2.41 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -2.41 data arrival time
+-----------------------------------------------------------------------------
+ 49.34 slack (MET)
+
+
+Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[16] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.35 2.41 2.41 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.10 io_out[16] (net)
+ 2.35 0.00 2.41 ^ io_out[16] (out)
+ 2.41 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -2.41 data arrival time
+-----------------------------------------------------------------------------
+ 49.34 slack (MET)
+
+
+Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[4] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.35 2.41 2.41 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.10 io_out[4] (net)
+ 2.35 0.00 2.41 ^ io_out[4] (out)
+ 2.41 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -2.41 data arrival time
+-----------------------------------------------------------------------------
+ 49.34 slack (MET)
+
+
+Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[8] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.35 2.41 2.41 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.10 io_out[8] (net)
+ 2.35 0.00 2.41 ^ io_out[8] (out)
+ 2.41 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -2.41 data arrival time
+-----------------------------------------------------------------------------
+ 49.34 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.min.rpt b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.min.rpt
new file mode 100644
index 0000000..22d27b6
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.min.rpt
@@ -0,0 +1,179 @@
+
+===========================================================================
+report_checks -path_delay min (Hold)
+============================================================================
+Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.05 1.46 1.46 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.08 io_out[18] (net)
+ 1.05 0.00 1.46 v _052_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.47 0.44 1.90 ^ _052_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _023_ (net)
+ 0.47 0.00 1.90 ^ _055_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.17 0.14 2.03 v _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 _002_ (net)
+ 0.17 0.00 2.03 v _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.03 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.07 0.32 library hold time
+ 0.32 data required time
+-----------------------------------------------------------------------------
+ 0.32 data required time
+ -2.03 data arrival time
+-----------------------------------------------------------------------------
+ 1.72 slack (MET)
+
+
+Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.05 1.46 1.46 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.08 io_out[2] (net)
+ 1.05 0.00 1.46 v _061_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.47 0.44 1.90 ^ _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _028_ (net)
+ 0.47 0.00 1.90 ^ _064_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.17 0.14 2.03 v _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 _006_ (net)
+ 0.17 0.00 2.03 v _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.03 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.07 0.32 library hold time
+ 0.32 data required time
+-----------------------------------------------------------------------------
+ 0.32 data required time
+ -2.03 data arrival time
+-----------------------------------------------------------------------------
+ 1.72 slack (MET)
+
+
+Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.05 1.46 1.46 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.08 io_out[6] (net)
+ 1.05 0.00 1.46 v _070_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.47 0.44 1.90 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _033_ (net)
+ 0.47 0.00 1.90 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.17 0.14 2.03 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 _010_ (net)
+ 0.17 0.00 2.03 v _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.03 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.07 0.32 library hold time
+ 0.32 data required time
+-----------------------------------------------------------------------------
+ 0.32 data required time
+ -2.03 data arrival time
+-----------------------------------------------------------------------------
+ 1.72 slack (MET)
+
+
+Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.05 1.46 1.46 v _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.08 io_out[10] (net)
+ 1.05 0.00 1.46 v _079_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.47 0.44 1.90 ^ _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _038_ (net)
+ 0.47 0.00 1.90 ^ _082_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.17 0.14 2.03 v _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 _014_ (net)
+ 0.17 0.00 2.03 v _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.03 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.07 0.32 library hold time
+ 0.32 data required time
+-----------------------------------------------------------------------------
+ 0.32 data required time
+ -2.03 data arrival time
+-----------------------------------------------------------------------------
+ 1.72 slack (MET)
+
+
+Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: min
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 1.05 1.46 1.46 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 3 0.08 io_out[14] (net)
+ 1.05 0.00 1.46 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 0.47 0.44 1.90 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
+ 1 0.00 _043_ (net)
+ 0.47 0.00 1.90 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 0.17 0.14 2.03 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
+ 1 0.00 _018_ (net)
+ 0.17 0.00 2.03 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.03 data arrival time
+
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.25 0.25 clock uncertainty
+ 0.00 0.25 clock reconvergence pessimism
+ 0.25 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 0.07 0.32 library hold time
+ 0.32 data required time
+-----------------------------------------------------------------------------
+ 0.32 data required time
+ -2.03 data arrival time
+-----------------------------------------------------------------------------
+ 1.72 slack (MET)
+
+
diff --git a/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.power.rpt b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.power.rpt
new file mode 100644
index 0000000..c1237ac
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.power.rpt
@@ -0,0 +1,14 @@
+
+===========================================================================
+ report_power
+============================================================================
+Group Internal Switching Leakage Total
+ Power Power Power Power (Watts)
+----------------------------------------------------------------
+Sequential 6.99e-05 1.61e-05 1.89e-09 8.60e-05 92.8%
+Combinational 4.47e-06 2.19e-06 2.66e-09 6.66e-06 7.2%
+Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
+----------------------------------------------------------------
+Total 7.43e-05 1.83e-05 4.55e-09 9.26e-05 100.0%
+ 80.2% 19.8% 0.0%
diff --git a/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.rpt b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.rpt
new file mode 100644
index 0000000..90f66fd
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.rpt
@@ -0,0 +1,37 @@
+
+===========================================================================
+report_checks -unconstrained
+============================================================================
+Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
+Endpoint: io_out[0] (output port clocked by wb_clk_i)
+Path Group: wb_clk_i
+Path Type: max
+
+Fanout Cap Slew Delay Time Description
+-----------------------------------------------------------------------------
+ 0.15 0.00 0.00 clock wb_clk_i (rise edge)
+ 0.00 0.00 clock network delay (ideal)
+ 0.15 0.00 0.00 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 2.35 2.41 2.41 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
+ 6 0.10 io_out[0] (net)
+ 2.35 0.00 2.41 ^ io_out[0] (out)
+ 2.41 data arrival time
+
+ 0.15 65.00 65.00 clock wb_clk_i (rise edge)
+ 0.00 65.00 clock network delay (ideal)
+ -0.25 64.75 clock uncertainty
+ 0.00 64.75 clock reconvergence pessimism
+ -13.00 51.75 output external delay
+ 51.75 data required time
+-----------------------------------------------------------------------------
+ 51.75 data required time
+ -2.41 data arrival time
+-----------------------------------------------------------------------------
+ 49.34 slack (MET)
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+No paths found.
diff --git a/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.slew.rpt b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.slew.rpt
new file mode 100644
index 0000000..ed40823
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.slew.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 0
+max cap violation count 0
+============================================================================
diff --git a/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.tns.rpt b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.tns.rpt
new file mode 100644
index 0000000..d3d84b6
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.tns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_tns
+============================================================================
+tns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.wns.rpt b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.wns.rpt
new file mode 100644
index 0000000..3b7f864
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.wns.rpt
@@ -0,0 +1,5 @@
+
+===========================================================================
+ report_wns
+============================================================================
+wns 0.00
diff --git a/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.worst_slack.rpt b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.worst_slack.rpt
new file mode 100644
index 0000000..6ab52db
--- /dev/null
+++ b/openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.worst_slack.rpt
@@ -0,0 +1,10 @@
+
+===========================================================================
+ report_worst_slack -max (Setup)
+============================================================================
+worst slack 49.34
+
+===========================================================================
+ report_worst_slack -min (Hold)
+============================================================================
+worst slack 1.72
