| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.18 1.54 1.54 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.08 io_out[6] (net) |
| 1.18 0.02 1.56 v _070_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.50 0.47 2.03 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _033_ (net) |
| 0.50 0.00 2.03 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.32 0.29 2.32 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.01 _010_ (net) |
| 0.32 0.00 2.32 v _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.32 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.03 0.28 library hold time |
| 0.28 data required time |
| ----------------------------------------------------------------------------- |
| 0.28 data required time |
| -2.32 data arrival time |
| ----------------------------------------------------------------------------- |
| 2.04 slack (MET) |
| |
| |
| Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.20 1.55 1.55 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.08 io_out[14] (net) |
| 1.20 0.02 1.57 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.51 0.49 2.06 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _043_ (net) |
| 0.51 0.00 2.06 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.32 0.28 2.34 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.01 _018_ (net) |
| 0.32 0.00 2.34 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.34 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.03 0.28 library hold time |
| 0.28 data required time |
| ----------------------------------------------------------------------------- |
| 0.28 data required time |
| -2.34 data arrival time |
| ----------------------------------------------------------------------------- |
| 2.06 slack (MET) |
| |
| |
| Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.15 1.53 1.53 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2 0.08 io_out[15] (net) |
| 1.15 0.00 1.54 v _092_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 0.42 0.54 2.07 ^ _092_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 1 0.00 _046_ (net) |
| 0.42 0.00 2.07 ^ _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.34 0.29 2.36 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.01 _019_ (net) |
| 0.34 0.00 2.36 v _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.36 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.03 0.28 library hold time |
| 0.28 data required time |
| ----------------------------------------------------------------------------- |
| 0.28 data required time |
| -2.36 data arrival time |
| ----------------------------------------------------------------------------- |
| 2.09 slack (MET) |
| |
| |
| Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.17 1.53 1.53 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2 0.08 io_out[7] (net) |
| 1.17 0.02 1.56 v _074_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 0.42 0.54 2.09 ^ _074_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 1 0.00 _036_ (net) |
| 0.42 0.00 2.09 ^ _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.35 0.30 2.39 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.01 _011_ (net) |
| 0.35 0.00 2.39 v _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.39 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.02 0.27 library hold time |
| 0.27 data required time |
| ----------------------------------------------------------------------------- |
| 0.27 data required time |
| -2.39 data arrival time |
| ----------------------------------------------------------------------------- |
| 2.12 slack (MET) |
| |
| |
| Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.29 1.59 1.59 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.08 io_out[2] (net) |
| 1.30 0.03 1.62 v _061_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.52 0.49 2.11 ^ _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _028_ (net) |
| 0.52 0.00 2.11 ^ _064_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.34 0.30 2.41 v _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.01 _006_ (net) |
| 0.34 0.00 2.42 v _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.42 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.03 0.28 library hold time |
| 0.28 data required time |
| ----------------------------------------------------------------------------- |
| 0.28 data required time |
| -2.42 data arrival time |
| ----------------------------------------------------------------------------- |
| 2.14 slack (MET) |
| |
| |