openlane/cntr_example/runs/cntr_example/reports/cts/11-cts_rsz_sta.max.rpt

===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[16] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.18    0.08    0.08 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.04                           clknet_0_wb_clk_i (net)
                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.14    0.00    0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
                  0.71    1.54    2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
     6    0.06                           net9 (net)
                  0.71    0.03    2.34 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
                  0.48    0.72    3.06 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
     1    0.07                           io_out[16] (net)
                  0.48    0.00    3.06 ^ io_out[16] (out)
                                  3.06   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -3.06   data arrival time
-----------------------------------------------------------------------------
                                 48.69   slack (MET)


Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[12] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.18    0.08    0.08 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.04                           clknet_0_wb_clk_i (net)
                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.13    0.00    0.77 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
                  0.71    1.54    2.31 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
     6    0.06                           net5 (net)
                  0.72    0.03    2.34 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
                  0.48    0.72    3.05 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
     1    0.07                           io_out[12] (net)
                  0.48    0.00    3.05 ^ io_out[12] (out)
                                  3.05   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -3.05   data arrival time
-----------------------------------------------------------------------------
                                 48.70   slack (MET)


Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[3] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.18    0.08    0.08 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.04                           clknet_0_wb_clk_i (net)
                  0.15    0.00    0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.13    0.33    0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     9    0.03                           clknet_1_1__leaf_wb_clk_i (net)
                  0.13    0.00    0.77 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  0.83    1.51    2.28 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     2    0.03                           net15 (net)
                  0.83    0.01    2.30 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
                  0.48    0.73    3.03 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
     1    0.07                           io_out[3] (net)
                  0.48    0.00    3.03 ^ io_out[3] (out)
                                  3.03   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -3.03   data arrival time
-----------------------------------------------------------------------------
                                 48.72   slack (MET)


Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[8] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.18    0.08    0.08 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.04                           clknet_0_wb_clk_i (net)
                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.14    0.00    0.78 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
                  0.66    1.51    2.29 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
     6    0.05                           net20 (net)
                  0.66    0.02    2.31 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
                  0.48    0.71    3.02 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
     1    0.07                           io_out[8] (net)
                  0.48    0.00    3.02 ^ io_out[8] (out)
                                  3.02   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -3.02   data arrival time
-----------------------------------------------------------------------------
                                 48.73   slack (MET)


Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.18    0.08    0.08 ^ wb_clk_i (in)
     1    0.02                           wb_clk_i (net)
                  0.18    0.00    0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.15    0.36    0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
     2    0.04                           clknet_0_wb_clk_i (net)
                  0.15    0.00    0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
                  0.14    0.34    0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
    11    0.04                           clknet_1_0__leaf_wb_clk_i (net)
                  0.14    0.00    0.78 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
                  0.65    1.51    2.29 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
     6    0.05                           net2 (net)
                  0.65    0.00    2.29 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
                  0.48    0.70    2.99 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
     1    0.07                           io_out[0] (net)
                  0.48    0.00    2.99 ^ io_out[0] (out)
                                  2.99   data arrival time

                         65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (propagated)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.99   data arrival time
-----------------------------------------------------------------------------
                                 48.76   slack (MET)