openlane/cntr_example/runs/cntr_example/reports/placement/7-gpl_sta.max.rpt

===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                         13.00   13.00 ^ input external delay
                  0.49    0.27   13.27 ^ wb_rst_i (in)
     2    0.02                           wb_rst_i (net)
                  0.49    0.00   13.27 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
                  1.29    1.05   14.31 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
    10    0.05                           _021_ (net)
                  1.29    0.00   14.31 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
                  0.65    0.32   14.63 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
     1    0.01                           _022_ (net)
                  0.65    0.00   14.63 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
                  0.98    0.79   15.42 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
     1    0.01                           _001_ (net)
                  0.98    0.00   15.42 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                 15.42   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                                 64.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                         -0.44   64.31   library setup time
                                 64.31   data required time
-----------------------------------------------------------------------------
                                 64.31   data required time
                                -15.42   data arrival time
-----------------------------------------------------------------------------
                                 48.89   slack (MET)


Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[12] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                  0.15    0.00    0.00 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  2.93    2.77    2.77 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     6    0.10                           io_out[12] (net)
                  2.93    0.09    2.86 ^ io_out[12] (out)
                                  2.86   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.86   data arrival time
-----------------------------------------------------------------------------
                                 48.89   slack (MET)


Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[16] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                  0.15    0.00    0.00 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  2.92    2.76    2.76 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     6    0.10                           io_out[16] (net)
                  2.93    0.09    2.85 ^ io_out[16] (out)
                                  2.85   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.85   data arrival time
-----------------------------------------------------------------------------
                                 48.90   slack (MET)


Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                         13.00   13.00 ^ input external delay
                  0.49    0.27   13.27 ^ wb_rst_i (in)
     2    0.02                           wb_rst_i (net)
                  0.49    0.00   13.27 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
                  1.29    1.05   14.31 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
    10    0.05                           _021_ (net)
                  1.29    0.00   14.32 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
                  0.64    0.30   14.61 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
     1    0.00                           _032_ (net)
                  0.64    0.00   14.61 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
                  0.98    0.78   15.40 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
     1    0.01                           _009_ (net)
                  0.98    0.00   15.40 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                 15.40   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                                 64.75 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                         -0.44   64.31   library setup time
                                 64.31   data required time
-----------------------------------------------------------------------------
                                 64.31   data required time
                                -15.40   data arrival time
-----------------------------------------------------------------------------
                                 48.91   slack (MET)


Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                         13.00   13.00 ^ input external delay
                  0.49    0.27   13.27 ^ wb_rst_i (in)
     2    0.02                           wb_rst_i (net)
                  0.49    0.00   13.27 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
                  1.29    1.05   14.31 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
    10    0.05                           _021_ (net)
                  1.29    0.00   14.32 ^ _086_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
                  0.63    0.30   14.61 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
     1    0.00                           _042_ (net)
                  0.63    0.00   14.61 v _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
                  0.97    0.77   15.39 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
     1    0.01                           _017_ (net)
                  0.97    0.00   15.39 ^ _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                                 15.39   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                                 64.75 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                         -0.44   64.31   library setup time
                                 64.31   data required time
-----------------------------------------------------------------------------
                                 64.31   data required time
                                -15.39   data arrival time
-----------------------------------------------------------------------------
                                 48.92   slack (MET)