openlane/cntr_example/runs/cntr_example/reports/synthesis/2-syn_sta.rpt

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report_checks -unconstrained
============================================================================
Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                  0.15    0.00    0.00   clock wb_clk_i (rise edge)
                          0.00    0.00   clock network delay (ideal)
                  0.15    0.00    0.00 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
                  2.35    2.41    2.41 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
     6    0.10                           io_out[0] (net)
                  2.35    0.00    2.41 ^ io_out[0] (out)
                                  2.41   data arrival time

                  0.15   65.00   65.00   clock wb_clk_i (rise edge)
                          0.00   65.00   clock network delay (ideal)
                         -0.25   64.75   clock uncertainty
                          0.00   64.75   clock reconvergence pessimism
                        -13.00   51.75   output external delay
                                 51.75   data required time
-----------------------------------------------------------------------------
                                 51.75   data required time
                                 -2.41   data arrival time
-----------------------------------------------------------------------------
                                 49.34   slack (MET)



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report_checks --slack_max -0.01
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No paths found.