| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.40 1.14 1.14 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 6 0.05 net16 (net) |
| 0.40 0.01 1.15 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.60 0.44 1.59 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.01 _008_ (net) |
| 0.60 0.00 1.59 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 1.59 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.03 0.28 library hold time |
| 0.28 data required time |
| ----------------------------------------------------------------------------- |
| 0.28 data required time |
| -1.59 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.32 slack (MET) |
| |
| |
| Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.55 1.31 1.31 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 5 0.04 net21 (net) |
| 0.56 0.02 1.32 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.38 0.30 1.62 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _013_ (net) |
| 0.38 0.00 1.62 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 1.62 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.03 0.28 library hold time |
| 0.28 data required time |
| ----------------------------------------------------------------------------- |
| 0.28 data required time |
| -1.62 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.34 slack (MET) |
| |
| |
| Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.57 1.31 1.31 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 5 0.04 net6 (net) |
| 0.57 0.01 1.33 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.39 0.30 1.63 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _017_ (net) |
| 0.39 0.00 1.63 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 1.63 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.03 0.28 library hold time |
| 0.28 data required time |
| ----------------------------------------------------------------------------- |
| 0.28 data required time |
| -1.63 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.36 slack (MET) |
| |
| |
| Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.57 1.32 1.32 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 5 0.04 net10 (net) |
| 0.58 0.01 1.33 ^ _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.40 0.31 1.64 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _001_ (net) |
| 0.40 0.00 1.64 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 1.64 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.02 0.27 library hold time |
| 0.27 data required time |
| ----------------------------------------------------------------------------- |
| 0.27 data required time |
| -1.64 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.37 slack (MET) |
| |
| |
| Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.63 1.36 1.36 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 5 0.05 net13 (net) |
| 0.63 0.01 1.36 ^ _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.38 0.29 1.66 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _005_ (net) |
| 0.38 0.00 1.66 v _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 1.66 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.03 0.28 library hold time |
| 0.28 data required time |
| ----------------------------------------------------------------------------- |
| 0.28 data required time |
| -1.66 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.38 slack (MET) |
| |
| |