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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-020 / 6cae81d7b7d1ee2875dee53f68163cb5765585ca / . / openlane / cntr_example / runs / cntr_example / reports / signoff / 22-rcx_sta.min.rpt
blob: cd37947132df22c3428b6e9050c87c7cac046359 [file] [log] [blame]
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.35 1.72 2.49 v _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.22 net6 (net)
1.36 0.06 2.55 v _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.47 0.58 3.13 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _042_ (net)
0.47 0.00 3.13 ^ _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1.55 1.04 4.17 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.08 _017_ (net)
1.55 0.01 4.19 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4.19 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.10 clock uncertainty
-0.08 1.02 clock reconvergence pessimism
-0.29 0.73 library hold time
0.73 data required time
-----------------------------------------------------------------------------
0.73 data required time
-4.19 data arrival time
-----------------------------------------------------------------------------
3.46 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.36 1.66 2.43 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.11 net7 (net)
1.36 0.03 2.46 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.81 0.74 3.19 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.02 _043_ (net)
0.81 0.00 3.19 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.70 1.19 4.38 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.10 _018_ (net)
1.70 0.02 4.40 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.40 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.10 clock uncertainty
-0.08 1.02 clock reconvergence pessimism
-0.35 0.67 library hold time
0.67 data required time
-----------------------------------------------------------------------------
0.67 data required time
-4.40 data arrival time
-----------------------------------------------------------------------------
3.73 slack (MET)
Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.44 1.79 2.56 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.23 net2 (net)
1.44 0.04 2.60 v _058_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.10 2.67 5.27 ^ _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.09 _004_ (net)
4.10 0.02 5.29 ^ _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.29 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.10 clock uncertainty
-0.08 1.02 clock reconvergence pessimism
0.30 1.32 library hold time
1.32 data required time
-----------------------------------------------------------------------------
1.32 data required time
-5.29 data arrival time
-----------------------------------------------------------------------------
3.97 slack (MET)
Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.08 2.05 2.81 v _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.17 net15 (net)
2.08 0.04 2.84 v _065_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.47 0.78 3.63 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _031_ (net)
0.47 0.00 3.63 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.57 1.05 4.68 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.09 _007_ (net)
1.57 0.02 4.70 v _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.70 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.08 clock uncertainty
-0.08 1.00 clock reconvergence pessimism
-0.33 0.68 library hold time
0.68 data required time
-----------------------------------------------------------------------------
0.68 data required time
-4.70 data arrival time
-----------------------------------------------------------------------------
4.02 slack (MET)
Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.24 1.65 2.41 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.20 net21 (net)
1.25 0.07 2.47 v _077_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.44 0.51 2.98 ^ _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _037_ (net)
0.44 0.00 2.98 ^ _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2.61 1.64 4.63 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.13 _013_ (net)
2.61 0.04 4.66 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4.66 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.08 clock uncertainty
-0.08 1.00 clock reconvergence pessimism
-0.56 0.44 library hold time
0.44 data required time
-----------------------------------------------------------------------------
0.44 data required time
-4.66 data arrival time
-----------------------------------------------------------------------------
4.22 slack (MET)