Add files via upload
diff --git a/openlane/cntr_example/runs/cntr_example/cmds.log b/openlane/cntr_example/runs/cntr_example/cmds.log
index 4d1ac2f..fc141bc 100644
--- a/openlane/cntr_example/runs/cntr_example/cmds.log
+++ b/openlane/cntr_example/runs/cntr_example/cmds.log
@@ -1,122 +1,122 @@
-Sat Dec 03 21:29:36 UTC 2022 - Executing "/openlane/scripts/mergeLef.py -o /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef -i /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef |& tee /dev/null"
+Sun Dec 04 02:36:22 UTC 2022 - Executing "/openlane/scripts/mergeLef.py -o /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef -i /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef |& tee /dev/null"
-Sat Dec 03 21:29:36 UTC 2022 - Executing "python3 /openlane/scripts/mergeLib.py --output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/merged.lib --name gf180mcuC_merged /home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib"
+Sun Dec 04 02:36:22 UTC 2022 - Executing "python3 /openlane/scripts/mergeLib.py --output /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/merged.lib --name gf180mcuC_merged /home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib"
-Sat Dec 03 21:29:36 UTC 2022 - Executing "python3 /openlane/scripts/libtrim.py --cell-file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/trimmed.lib.exclude.list --output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/trimmed.lib /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/merged.lib"
+Sun Dec 04 02:36:23 UTC 2022 - Executing "python3 /openlane/scripts/libtrim.py --cell-file /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/trimmed.lib.exclude.list --output /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/trimmed.lib /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/merged.lib"
-Sat Dec 03 21:29:37 UTC 2022 - Executing "python3 /openlane/scripts/libtrim.py --cell-file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/cts.lib.exclude.list --output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/cts.lib /home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib"
+Sun Dec 04 02:36:23 UTC 2022 - Executing "python3 /openlane/scripts/libtrim.py --cell-file /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/cts.lib.exclude.list --output /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/cts.lib /home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib"
-Sat Dec 03 21:29:37 UTC 2022 - Executing "python3 /openlane/scripts/new_tracks.py -i /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info -o /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/config.tracks"
+Sun Dec 04 02:36:24 UTC 2022 - Executing "python3 /openlane/scripts/new_tracks.py -i /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info -o /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/config.tracks"
-Sat Dec 03 21:29:37 UTC 2022 - Executing "echo {OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988} > /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/OPENLANE_VERSION"
+Sun Dec 04 02:36:24 UTC 2022 - Executing "echo {OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988} > /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/OPENLANE_VERSION"
-Sat Dec 03 21:29:38 UTC 2022 - Executing "sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1 direction : "inout";/g} /home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib > /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/1-gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.no_pg.lib"
+Sun Dec 04 02:36:24 UTC 2022 - Executing "sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1 direction : "inout";/g} /home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib > /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/1-gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.no_pg.lib"
-Sat Dec 03 21:29:38 UTC 2022 - Executing "sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1 direction : "inout";/g} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/trimmed.lib > /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/1-trimmed.no_pg.lib"
+Sun Dec 04 02:36:24 UTC 2022 - Executing "sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1 direction : "inout";/g} /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/trimmed.lib > /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/1-trimmed.no_pg.lib"
-Sat Dec 03 21:29:38 UTC 2022 - Executing "yosys -c /openlane/scripts/yosys/synth.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/synthesis/1-synthesis.log"
+Sun Dec 04 02:36:25 UTC 2022 - Executing "yosys -c /openlane/scripts/yosys/synth.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/synthesis/1-synthesis.log"
-Sat Dec 03 21:29:40 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/results\/synthesis\/cntr_example.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+Sun Dec 04 02:36:26 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo-fiveguys\/openlane\/cntr_example\/runs\/22_12_03_21_36\/results\/synthesis\/cntr_example.v/} /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/config.tcl"
-Sat Dec 03 21:29:40 UTC 2022 - Executing "sed -i /defparam/d /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/synthesis/cntr_example.v"
+Sun Dec 04 02:36:26 UTC 2022 - Executing "sed -i /defparam/d /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/synthesis/cntr_example.v"
-Sat Dec 03 21:29:40 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/synthesis/2-sta.log"
+Sun Dec 04 02:36:26 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/synthesis/2-sta.log"
-Sat Dec 03 21:29:41 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/floorplan.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/3-initial_fp.log"
+Sun Dec 04 02:36:28 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/floorplan.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/floorplan/3-initial_fp.log"
-Sat Dec 03 21:29:42 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/floorplan.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/3-initial_fp.log"
+Sun Dec 04 02:36:28 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/floorplan.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/floorplan/3-initial_fp.log"
-Sat Dec 03 21:29:42 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/defutil.py extract_core_dims --output-data /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/dimensions.txt --input-lef /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan/3-initial_fp.def"
+Sun Dec 04 02:36:29 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/defutil.py extract_core_dims --output-data /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/dimensions.txt --input-lef /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/floorplan/3-initial_fp.def"
-Sat Dec 03 21:29:43 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/ioplacer.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/4-io.log"
+Sun Dec 04 02:36:30 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/ioplacer.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/floorplan/4-io.log"
-Sat Dec 03 21:29:43 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/tapcell.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/5-tap.log"
+Sun Dec 04 02:36:30 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/tapcell.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/floorplan/5-tap.log"
-Sat Dec 03 21:29:44 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/pdn.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/6-pdn.log"
+Sun Dec 04 02:36:31 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/pdn.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/floorplan/6-pdn.log"
-Sat Dec 03 21:29:46 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/gpl.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement/7-global.log"
+Sun Dec 04 02:36:34 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/gpl.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/placement/7-global.log"
-Sat Dec 03 21:30:02 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/resizer.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement/8-resizer.log"
+Sun Dec 04 02:36:51 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/resizer.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/placement/8-resizer.log"
-Sat Dec 03 21:30:03 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/tmp\/placement\/8-resizer.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+Sun Dec 04 02:36:52 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo-fiveguys\/openlane\/cntr_example\/runs\/22_12_03_21_36\/tmp\/placement\/8-resizer.nl.v/} /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/config.tcl"
-Sat Dec 03 21:30:03 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/dpl.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement/9-detailed.log"
+Sun Dec 04 02:36:52 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/dpl.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/placement/9-detailed.log"
-Sat Dec 03 21:30:04 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/results\/placement\/cntr_example.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+Sun Dec 04 02:36:53 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo-fiveguys\/openlane\/cntr_example\/runs\/22_12_03_21_36\/results\/placement\/cntr_example.nl.v/} /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/config.tcl"
-Sat Dec 03 21:30:04 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/cts.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/cts/10-cts.log"
+Sun Dec 04 02:36:54 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/cts.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/cts/10-cts.log"
-Sat Dec 03 21:30:35 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/resizer_timing.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/cts/11-resizer.log"
+Sun Dec 04 02:37:27 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/resizer_timing.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/cts/11-resizer.log"
-Sat Dec 03 21:30:36 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/tmp\/cts\/11-cntr_example.resized.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+Sun Dec 04 02:37:28 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo-fiveguys\/openlane\/cntr_example\/runs\/22_12_03_21_36\/tmp\/cts\/11-cntr_example.resized.nl.v/} /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/config.tcl"
-Sat Dec 03 21:30:36 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/resizer_routing_timing.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/12-resizer.log"
+Sun Dec 04 02:37:28 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/resizer_routing_timing.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/12-resizer.log"
-Sat Dec 03 21:30:38 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/tmp\/12-cntr_example.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+Sun Dec 04 02:37:29 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo-fiveguys\/openlane\/cntr_example\/runs\/22_12_03_21_36\/tmp\/12-cntr_example.nl.v/} /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/config.tcl"
-Sat Dec 03 21:30:38 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/diodes.py place --diode-cell gf180mcu_fd_sc_mcu7t5v0__antenna --diode-pin I --fake-diode-cell gf180mcu_fd_sc_mcu7t5v0__antenna --input-lef /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef --output-def /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/13-diodes.def --output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/13-diodes.odb /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.odb |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/13-diodes.log"
+Sun Dec 04 02:37:30 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/diodes.py place --diode-cell gf180mcu_fd_sc_mcu7t5v0__antenna --diode-pin I --fake-diode-cell gf180mcu_fd_sc_mcu7t5v0__antenna --input-lef /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef --output-def /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/13-diodes.def --output /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/13-diodes.odb /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/12-cntr_example.odb |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/13-diodes.log"
-Sat Dec 03 21:30:38 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/dpl.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/14-diode_legalization.log"
+Sun Dec 04 02:37:30 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/dpl.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/14-diode_legalization.log"
-Sat Dec 03 21:30:39 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/tmp\/routing\/diodes.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+Sun Dec 04 02:37:31 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo-fiveguys\/openlane\/cntr_example\/runs\/22_12_03_21_36\/tmp\/routing\/diodes.nl.v/} /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/config.tcl"
-Sat Dec 03 21:30:39 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/fill.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/15-fill.log"
+Sun Dec 04 02:37:31 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/fill.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/15-fill.log"
-Sat Dec 03 21:30:41 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/tmp\/routing\/15-fill.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+Sun Dec 04 02:37:33 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo-fiveguys\/openlane\/cntr_example\/runs\/22_12_03_21_36\/tmp\/routing\/15-fill.nl.v/} /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/config.tcl"
-Sat Dec 03 21:30:41 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/groute.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/16-global.log"
+Sun Dec 04 02:37:33 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/groute.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/16-global.log"
-Sat Dec 03 21:30:43 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/write_views.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/16-global_write_netlist.log"
+Sun Dec 04 02:37:35 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/write_views.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/16-global_write_netlist.log"
-Sat Dec 03 21:30:44 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/tmp\/routing\/global.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+Sun Dec 04 02:37:36 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo-fiveguys\/openlane\/cntr_example\/runs\/22_12_03_21_36\/tmp\/routing\/global.nl.v/} /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/config.tcl"
-Sat Dec 03 21:30:44 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/droute.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/18-detailed.log"
+Sun Dec 04 02:37:36 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/droute.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/18-detailed.log"
-Sat Dec 03 21:31:15 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/results\/routing\/cntr_example.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+Sun Dec 04 02:38:16 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo-fiveguys\/openlane\/cntr_example\/runs\/22_12_03_21_36\/results\/routing\/cntr_example.nl.v/} /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/config.tcl"
-Sat Dec 03 21:31:15 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py tr to_klayout -o /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/routing/drt.klayout.xml --design-name cntr_example /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/routing/drt.drc"
+Sun Dec 04 02:38:16 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py tr to_klayout -o /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/routing/drt.klayout.xml --design-name cntr_example /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/routing/drt.drc"
-Sat Dec 03 21:31:15 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/wire_lengths.py --report-out /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/routing/19-wire_lengths.csv --input-lef /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef --output-def /dev/null --output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.odb /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.odb |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/19-wire_lengths.log"
+Sun Dec 04 02:38:16 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/wire_lengths.py --report-out /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/routing/19-wire_lengths.csv --input-lef /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef --output-def /dev/null --output /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.odb /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.odb |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/19-wire_lengths.log"
-Sat Dec 03 21:31:16 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/rcx.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/20-parasitics_extraction.nom.log"
+Sun Dec 04 02:38:17 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/rcx.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/20-parasitics_extraction.nom.log"
-Sat Dec 03 21:31:18 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta_multi_corner.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/21-rcx_mcsta.nom.log"
+Sun Dec 04 02:38:18 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta_multi_corner.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/21-rcx_mcsta.nom.log"
-Sat Dec 03 21:31:21 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/22-rcx_sta.log"
+Sun Dec 04 02:38:22 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/sta.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/22-rcx_sta.log"
-Sat Dec 03 21:31:22 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/def/mag_gds.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/23-gdsii.log"
+Sun Dec 04 02:38:23 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/def/mag_gds.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/23-gdsii.log"
-Sat Dec 03 21:31:23 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/gds/mag_with_pointers.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/23-gds_ptrs.log"
+Sun Dec 04 02:38:25 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/gds/mag_with_pointers.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/23-gds_ptrs.log"
-Sat Dec 03 21:31:26 UTC 2022 - Executing "sed -i -n {/^<< properties >>/,/^<< end >>/p} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/gds_ptrs.mag"
+Sun Dec 04 02:38:27 UTC 2022 - Executing "sed -i -n {/^<< properties >>/,/^<< end >>/p} /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff/gds_ptrs.mag"
-Sat Dec 03 21:31:26 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/mag/lef.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/23-lef.log"
+Sun Dec 04 02:38:27 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/mag/lef.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/23-lef.log"
-Sat Dec 03 21:31:30 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/lef/maglef.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/23-maglef.log"
+Sun Dec 04 02:38:32 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/lef/maglef.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/23-maglef.log"
-Sat Dec 03 21:31:31 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/extract_spice.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/24-spice.log"
+Sun Dec 04 02:38:33 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/extract_spice.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/24-spice.log"
-Sat Dec 03 21:31:46 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/power_utils.py write_powered_def --output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.p.def --input-lef /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef --power-port vdd --ground-port vss --powered-netlist {} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/25-write_powered_def.log"
+Sun Dec 04 02:38:49 UTC 2022 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/power_utils.py write_powered_def --output /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff/24-cntr_example.p.def --input-lef /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef --power-port vdd --ground-port vss --powered-netlist {} /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.def |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/25-write_powered_def.log"
-Sat Dec 03 21:31:47 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/write_views.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/25-write_powered_verilog.log"
+Sun Dec 04 02:38:50 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/write_views.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/25-write_powered_verilog.log"
-Sat Dec 03 21:31:49 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo\/openlane\/cntr_example\/runs\/22_12_03_16_29\/tmp\/signoff\/24-cntr_example.nl.v/} /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl"
+Sun Dec 04 02:38:51 UTC 2022 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/htf6ry\/gf180-demo-fiveguys\/openlane\/cntr_example\/runs\/22_12_03_21_36\/tmp\/signoff\/24-cntr_example.nl.v/} /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/config.tcl"
-Sat Dec 03 21:31:49 UTC 2022 - Executing "netgen -batch source /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/27-setup_file.lef.lvs |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/27-lvs.lef.log"
+Sun Dec 04 02:38:51 UTC 2022 - Executing "netgen -batch source /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff/27-setup_file.lef.lvs |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/27-lvs.lef.log"
-Sat Dec 03 21:31:50 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/drc.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/28-drc.log"
+Sun Dec 04 02:38:53 UTC 2022 - Executing "magic -noconsole -dnull -rcfile /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/magic/gf180mcuC.magicrc < /openlane/scripts/magic/drc.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/28-drc.log"
-Sat Dec 03 21:34:30 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_tcl -o /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.tcl /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.rpt"
+Sun Dec 04 02:41:40 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_tcl -o /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/drc.tcl /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/drc.rpt"
-Sat Dec 03 21:34:30 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_tr -o /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.tr /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.rpt"
+Sun Dec 04 02:41:40 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_tr -o /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/drc.tr /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/drc.rpt"
-Sat Dec 03 21:34:30 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py tr to_klayout -o /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.klayout.xml --design-name cntr_example /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.tr"
+Sun Dec 04 02:41:40 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py tr to_klayout -o /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/drc.klayout.xml --design-name cntr_example /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/drc.tr"
-Sat Dec 03 21:34:30 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_rdb -o /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.rdb /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.rpt"
+Sun Dec 04 02:41:40 UTC 2022 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_rdb -o /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/drc.rdb /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/drc.rpt"
-Sat Dec 03 21:34:30 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/antenna_check.tcl |& tee /dev/null /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/29-antenna.log"
+Sun Dec 04 02:41:40 UTC 2022 - Executing "openroad -exit /openlane/scripts/openroad/antenna_check.tcl |& tee /dev/null /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/29-antenna.log"
-Sat Dec 03 21:34:31 UTC 2022 - Executing "python3 /openlane/scripts/extract_antenna_violators.py --output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/29-antenna_violators.rpt /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/29-antenna.log"
+Sun Dec 04 02:41:41 UTC 2022 - Executing "python3 /openlane/scripts/extract_antenna_violators.py --output /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/29-antenna_violators.rpt /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/29-antenna.log"
-Sat Dec 03 21:34:31 UTC 2022 - Executing "python3 /openlane/scripts/generate_reports.py -d /home/htf6ry/gf180-demo/openlane/cntr_example --design_name cntr_example --tag 22_12_03_16_29 --output_file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/metrics.csv --man_report /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/manufacturability.rpt --run_path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29"
+Sun Dec 04 02:41:42 UTC 2022 - Executing "python3 /openlane/scripts/generate_reports.py -d /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example --design_name cntr_example --tag 22_12_03_21_36 --output_file /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/metrics.csv --man_report /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/manufacturability.rpt --run_path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36"
diff --git a/openlane/cntr_example/runs/cntr_example/config.tcl b/openlane/cntr_example/runs/cntr_example/config.tcl
index d9d5f76..16926c3 100644
--- a/openlane/cntr_example/runs/cntr_example/config.tcl
+++ b/openlane/cntr_example/runs/cntr_example/config.tcl
@@ -28,7 +28,7 @@
set ::env(DECAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__fillcap_*}
set ::env(DEFAULT_MAX_TRAN) {3}
set ::env(DEF_UNITS_PER_MICRON) {2000}
-set ::env(DESIGN_CONFIG) {/home/htf6ry/gf180-demo/openlane/cntr_example/config.tcl}
+set ::env(DESIGN_CONFIG) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/config.tcl}
set ::env(DESIGN_IS_CORE) {0}
set ::env(DESIGN_NAME) {cntr_example}
set ::env(DETAILED_ROUTER) {tritonroute}
@@ -98,7 +98,7 @@
set ::env(FULL_ADDER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/fa_map.v}
set ::env(GDS_FILES) {/home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/gds/gf180mcu_fd_sc_mcu7t5v0.gds}
set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
-set ::env(GLB_CFG_FILE) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl}
+set ::env(GLB_CFG_FILE) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/config.tcl}
set ::env(GLB_OPTIMIZE_MIRRORING) {1}
set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
@@ -138,7 +138,7 @@
set ::env(LIB_SLOWEST) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ss_125C_1v62.lib}
set ::env(LIB_SYNTH) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib}
set ::env(LIB_TYPICAL) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib}
-set ::env(LOGS_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs}
+set ::env(LOGS_DIR) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs}
set ::env(LVS_CONNECT_BY_LABEL) {0}
set ::env(LVS_INSERT_POWER_PINS) {1}
set ::env(MACRO_BLOCKAGES_LAYER) {Metal1 Metal2 Metal3 Metal4 Metal5}
@@ -213,8 +213,8 @@
set ::env(RCX_RULES) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom.magic}
set ::env(RCX_RULES_MAX) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.max.magic}
set ::env(RCX_RULES_MIN) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.min.magic}
-set ::env(REPORTS_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports}
-set ::env(RESULTS_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results}
+set ::env(REPORTS_DIR) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports}
+set ::env(RESULTS_DIR) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results}
set ::env(RIGHT_MARGIN_MULT) {12}
set ::env(RIPPLE_CARRY_ADDER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/rca_map.v}
set ::env(ROUTING_CORES) {2}
@@ -223,7 +223,7 @@
set ::env(RT_MAX_LAYER) {Metal4}
set ::env(RT_MIN_LAYER) {Metal2}
set ::env(RUN_CVC) {1}
-set ::env(RUN_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29}
+set ::env(RUN_DIR) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36}
set ::env(RUN_DRT) {1}
set ::env(RUN_FILL_INSERTION) {1}
set ::env(RUN_IRDROP_REPORT) {0}
@@ -234,11 +234,11 @@
set ::env(RUN_MAGIC) {1}
set ::env(RUN_MAGIC_DRC) {1}
set ::env(RUN_SPEF_EXTRACTION) {1}
-set ::env(RUN_TAG) {22_12_03_16_29}
+set ::env(RUN_TAG) {22_12_03_21_36}
set ::env(RUN_TAP_DECAP_INSERTION) {1}
set ::env(SCLPATH) {/home/htf6ry/GF180PDK//gf180mcuC/gf180mcu_fd_sc_mcu7t5v0}
set ::env(SPEF_EXTRACTOR) {openrcx}
-set ::env(START_TIME) {2022.12.03_21.29.36}
+set ::env(START_TIME) {2022.12.04_02.36.22}
set ::env(STA_REPORT_POWER) {1}
set ::env(STA_WRITE_LIB) {1}
set ::env(STD_CELL_GROUND_PINS) {VSS}
@@ -275,7 +275,7 @@
set ::env(TAKE_LAYOUT_SCROT) {0}
set ::env(TECH_LEF) {/home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/techlef/gf180mcu_fd_sc_mcu7t5v0.tlef}
set ::env(TERMINAL_OUTPUT) {/dev/null}
-set ::env(TMP_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp}
+set ::env(TMP_DIR) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp}
set ::env(TOP_MARGIN_MULT) {4}
set ::env(TRACKS_INFO_FILE) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info}
set ::env(TRISTATE_BUFFER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tribuff_map.v}
@@ -283,51 +283,51 @@
set ::env(USE_GPIO_PADS) {0}
set ::env(VDD_NETS) {vdd}
set ::env(VDD_PIN) {VDD}
-set ::env(VERILOG_FILES) {/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v}
+set ::env(VERILOG_FILES) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v}
set ::env(WIRE_RC_LAYER) {Metal2}
set ::env(YOSYS_REWRITE_VERILOG) {0}
-set ::env(cts_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/cts}
-set ::env(cts_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/cts}
-set ::env(cts_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts}
-set ::env(cts_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts}
-set ::env(eco_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/eco}
-set ::env(eco_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/eco}
-set ::env(eco_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/eco}
-set ::env(eco_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/eco}
-set ::env(floorplan_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan}
-set ::env(floorplan_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/floorplan}
-set ::env(floorplan_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/floorplan}
-set ::env(floorplan_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan}
-set ::env(placement_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement}
-set ::env(placement_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/placement}
-set ::env(placement_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/placement}
-set ::env(placement_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement}
-set ::env(routing_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing}
-set ::env(routing_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/routing}
-set ::env(routing_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing}
-set ::env(routing_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing}
-set ::env(signoff_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff}
-set ::env(signoff_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff}
-set ::env(signoff_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff}
-set ::env(signoff_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff}
-set ::env(synthesis_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/synthesis}
-set ::env(synthesis_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/synthesis}
-set ::env(synthesis_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/synthesis}
-set ::env(synthesis_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis}
+set ::env(cts_logs) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/cts}
+set ::env(cts_reports) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/cts}
+set ::env(cts_results) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/cts}
+set ::env(cts_tmpfiles) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts}
+set ::env(eco_logs) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/eco}
+set ::env(eco_reports) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/eco}
+set ::env(eco_results) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/eco}
+set ::env(eco_tmpfiles) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/eco}
+set ::env(floorplan_logs) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/floorplan}
+set ::env(floorplan_reports) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/floorplan}
+set ::env(floorplan_results) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/floorplan}
+set ::env(floorplan_tmpfiles) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/floorplan}
+set ::env(placement_logs) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/placement}
+set ::env(placement_reports) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/placement}
+set ::env(placement_results) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/placement}
+set ::env(placement_tmpfiles) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement}
+set ::env(routing_logs) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing}
+set ::env(routing_reports) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/routing}
+set ::env(routing_results) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing}
+set ::env(routing_tmpfiles) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing}
+set ::env(signoff_logs) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff}
+set ::env(signoff_reports) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff}
+set ::env(signoff_results) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff}
+set ::env(signoff_tmpfiles) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff}
+set ::env(synthesis_logs) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/synthesis}
+set ::env(synthesis_reports) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/synthesis}
+set ::env(synthesis_results) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/synthesis}
+set ::env(synthesis_tmpfiles) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis}
set ::env(SYNTH_MAX_TRAN) {3}
set ::env(CURRENT_INDEX) 29
-set ::env(CURRENT_DEF) /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def
-set ::env(CURRENT_GUIDE) /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.guide
-set ::env(CURRENT_NETLIST) /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.nl.v
+set ::env(CURRENT_DEF) /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.def
+set ::env(CURRENT_GUIDE) /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/16-global.guide
+set ::env(CURRENT_NETLIST) /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff/24-cntr_example.nl.v
set ::env(CURRENT_POWERED_NETLIST) {0}
-set ::env(CURRENT_ODB) /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.odb
+set ::env(CURRENT_ODB) /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.odb
set ::env(PDK_ROOT) {/home/htf6ry/GF180PDK/}
-set ::env(ANTENNA_CHECK_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.p.def}
-set ::env(ANTENNA_VIOLATOR_LIST) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/29-antenna_violators.rpt}
+set ::env(ANTENNA_CHECK_CURRENT_DEF) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff/24-cntr_example.p.def}
+set ::env(ANTENNA_VIOLATOR_LIST) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/29-antenna_violators.rpt}
set ::env(BASE_SDC_FILE) {/openlane/scripts/base.sdc}
set ::env(BASIC_PREP_COMPLETE) {1}
set ::env(BOTTOM_MARGIN_MULT) {4}
-set ::env(CARAVEL_ROOT) {/home/htf6ry/gf180-demo/caravel}
+set ::env(CARAVEL_ROOT) {/home/htf6ry/gf180-demo-fiveguys/caravel}
set ::env(CARRY_SELECT_ADDER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/csa_map.v}
set ::env(CELLS_LEF) {/home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/lef/gf180mcu_fd_sc_mcu7t5v0.lef}
set ::env(CELL_PAD_EXCLUDE) {gf180mcu_fd_sc_mcu7t5v0__filltie_* gf180mcu_fd_sc_mcu7t5v0__filldecap_* gf180mcu_fd_sc_mcu7t5v0__fill_* gf180mcu_fd_sc_mcu7t5v0__endcap_*}
@@ -345,7 +345,7 @@
set ::env(CORE_WIDTH) {1486.24}
set ::env(CTS_CLK_BUFFER_LIST) {gf180mcu_fd_sc_mcu7t5v0__clkbuf_2 gf180mcu_fd_sc_mcu7t5v0__clkbuf_4 gf180mcu_fd_sc_mcu7t5v0__clkbuf_8}
set ::env(CTS_CLK_MAX_WIRE_LENGTH) {0}
-set ::env(CTS_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/placement/cntr_example.def}
+set ::env(CTS_CURRENT_DEF) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/placement/cntr_example.def}
set ::env(CTS_DISABLE_POST_PROCESSING) {0}
set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
set ::env(CTS_MAX_CAP) {0.5}
@@ -355,37 +355,37 @@
set ::env(CTS_SINK_CLUSTERING_SIZE) {25}
set ::env(CTS_TARGET_SKEW) {200}
set ::env(CTS_TOLERANCE) {100}
-set ::env(CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.p.def}
-set ::env(CURRENT_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing}
-set ::env(CURRENT_GDS) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.gds}
-set ::env(CURRENT_GUIDE) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.guide}
+set ::env(CURRENT_DEF) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff/24-cntr_example.p.def}
+set ::env(CURRENT_DIR) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing}
+set ::env(CURRENT_GDS) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/cntr_example.gds}
+set ::env(CURRENT_GUIDE) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/16-global.guide}
set ::env(CURRENT_INDEX) {29}
-set ::env(CURRENT_LIB) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.lib}
-set ::env(CURRENT_NETLIST) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.nl.v}
-set ::env(CURRENT_ODB) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.odb}
-set ::env(CURRENT_POWERED_NETLIST) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.pnl.v}
-set ::env(CURRENT_SDC) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.sdc}
-set ::env(CURRENT_SDF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.sdf}
-set ::env(CURRENT_SPEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.spef}
+set ::env(CURRENT_LIB) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.lib}
+set ::env(CURRENT_NETLIST) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff/24-cntr_example.nl.v}
+set ::env(CURRENT_ODB) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.odb}
+set ::env(CURRENT_POWERED_NETLIST) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff/24-cntr_example.pnl.v}
+set ::env(CURRENT_SDC) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/12-cntr_example.sdc}
+set ::env(CURRENT_SDF) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.sdf}
+set ::env(CURRENT_SPEF) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.spef}
set ::env(CURRENT_STEP) {}
set ::env(DATA_WIRE_RC_LAYER) {Metal2}
set ::env(DECAP_CELL) {gf180mcu_fd_sc_mcu7t5v0__fillcap_*}
set ::env(DEFAULT_MAX_TRAN) {3}
set ::env(DEF_UNITS_PER_MICRON) {2000}
-set ::env(DESIGN_CONFIG) {/home/htf6ry/gf180-demo/openlane/cntr_example/config.tcl}
-set ::env(DESIGN_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example}
+set ::env(DESIGN_CONFIG) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/config.tcl}
+set ::env(DESIGN_DIR) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example}
set ::env(DESIGN_IS_CORE) {0}
set ::env(DESIGN_NAME) {cntr_example}
set ::env(DETAILED_ROUTER) {tritonroute}
set ::env(DIE_AREA) {0.0 0.0 1500.0 1500.0}
set ::env(DIODE_CELL) {gf180mcu_fd_sc_mcu7t5v0__antenna}
set ::env(DIODE_CELL_PIN) {I}
-set ::env(DIODE_INSERTION_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def}
+set ::env(DIODE_INSERTION_CURRENT_DEF) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.def}
set ::env(DIODE_INSERTION_STRATEGY) {4}
set ::env(DIODE_PADDING) {2}
set ::env(DONT_USE_CELLS) {gf180mcu_fd_sc_mcu7t5v0__mux2_1 gf180mcu_fd_sc_mcu7t5v0__oai33_2 }
set ::env(DPL_CELL_PADDING) {2}
-set ::env(DRC_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.p.def}
+set ::env(DRC_CURRENT_DEF) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff/24-cntr_example.p.def}
set ::env(DRC_EXCLUDE_CELL_LIST) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/drc_exclude.cells}
set ::env(DRT_MIN_LAYER) {Metal1}
@@ -394,7 +394,7 @@
set ::env(ECO_FINISH) {0}
set ::env(ECO_ITER) {0}
set ::env(ECO_SKIP_PIN) {1}
-set ::env(EXT_NETLIST) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.spice}
+set ::env(EXT_NETLIST) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/cntr_example.spice}
set ::env(FILL_CELL) {gf180mcu_fd_sc_mcu7t5v0__fill_*}
set ::env(FP_ASPECT_RATIO) {1}
set ::env(FP_CORE_UTIL) {20}
@@ -447,7 +447,7 @@
set ::env(FULL_ADDER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/fa_map.v}
set ::env(GDS_FILES) {/home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/gds/gf180mcu_fd_sc_mcu7t5v0.gds}
set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
-set ::env(GLB_CFG_FILE) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/config.tcl}
+set ::env(GLB_CFG_FILE) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/config.tcl}
set ::env(GLB_OPTIMIZE_MIRRORING) {1}
set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
@@ -476,7 +476,7 @@
set ::env(GRT_MAX_DIODE_INS_ITERS) {1}
set ::env(GRT_OVERFLOW_ITERS) {50}
set ::env(HOME) {/}
-set ::env(HOSTNAME) {8af15976aba8}
+set ::env(HOSTNAME) {b3b1df10ba60}
set ::env(IO_PCT) {0.2}
set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/klayout/gf180mcuC_mr.drc}
@@ -485,24 +485,24 @@
set ::env(KLAYOUT_XOR_GDS) {1}
set ::env(KLAYOUT_XOR_XML) {1}
set ::env(LANG) {en_US.UTF-8}
-set ::env(LAST_TIMING_REPORT_TAG) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/22-rcx_sta}
+set ::env(LAST_TIMING_REPORT_TAG) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/22-rcx_sta}
set ::env(LC_ALL) {en_US.UTF-8}
set ::env(LC_CTYPE) {en_US.UTF-8}
set ::env(LD_LIBRARY_PATH) {/build//lib:/build//lib/Linux-x86_64:}
set ::env(LEC_ENABLE) {0}
set ::env(LEFT_MARGIN_MULT) {12}
-set ::env(LIB_CTS) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/cts.lib}
+set ::env(LIB_CTS) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/cts.lib}
set ::env(LIB_FASTEST) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ff_n40C_5v50.lib}
set ::env(LIB_SLOWEST) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__ss_125C_1v62.lib}
-set ::env(LIB_SYNTH) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/trimmed.lib}
+set ::env(LIB_SYNTH) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/trimmed.lib}
set ::env(LIB_SYNTH_COMPLETE) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib}
-set ::env(LIB_SYNTH_COMPLETE_NO_PG) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/1-gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.no_pg.lib}
-set ::env(LIB_SYNTH_MERGED) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/merged.lib}
-set ::env(LIB_SYNTH_NO_PG) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/1-trimmed.no_pg.lib}
+set ::env(LIB_SYNTH_COMPLETE_NO_PG) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/1-gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.no_pg.lib}
+set ::env(LIB_SYNTH_MERGED) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/merged.lib}
+set ::env(LIB_SYNTH_NO_PG) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/1-trimmed.no_pg.lib}
set ::env(LIB_TYPICAL) {/home/htf6ry/GF180PDK//gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib}
-set ::env(LOGS_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs}
+set ::env(LOGS_DIR) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs}
set ::env(LVS_CONNECT_BY_LABEL) {0}
-set ::env(LVS_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def}
+set ::env(LVS_CURRENT_DEF) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.def}
set ::env(LVS_INSERT_POWER_PINS) {1}
set ::env(MACRO_BLOCKAGES_LAYER) {Metal1 Metal2 Metal3 Metal4 Metal5}
set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
@@ -511,7 +511,7 @@
set ::env(MAGIC_DISABLE_HIER_GDS) {1}
set ::env(MAGIC_DRC_USE_GDS) {1}
set ::env(MAGIC_EXT_USE_GDS) {0}
-set ::env(MAGIC_GDS) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.magic.gds}
+set ::env(MAGIC_GDS) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/cntr_example.magic.gds}
set ::env(MAGIC_GENERATE_GDS) {1}
set ::env(MAGIC_GENERATE_LEF) {1}
set ::env(MAGIC_GENERATE_MAGLEF) {1}
@@ -524,27 +524,27 @@
set ::env(MAGTYPE) {maglef}
set ::env(MANPATH) {/build//share/man:}
set ::env(MAX_METAL_LAYER) {5}
-set ::env(MCW_ROOT) {/home/htf6ry/gf180-demo/mgmt_core_wrapper}
-set ::env(MC_SDF_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/sdf}
-set ::env(MC_SPEF_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/spef}
-set ::env(MERGED_LEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef}
+set ::env(MCW_ROOT) {/home/htf6ry/gf180-demo-fiveguys/mgmt_core_wrapper}
+set ::env(MC_SDF_DIR) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/sdf}
+set ::env(MC_SPEF_DIR) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/spef}
+set ::env(MERGED_LEF) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef}
set ::env(METAL_LAYER_NAMES) {Metal1 Metal2 Metal3 Metal4 Metal5}
set ::env(MISMATCHES_OK) {1}
set ::env(NETGEN_SETUP_FILE) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl}
set ::env(NO_SYNTH_CELL_LIST) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/no_synth.cells}
set ::env(OPENLANE_ROOT) {/openlane}
-set ::env(OPENLANE_RUN_TAG) {22_12_03_16_29}
+set ::env(OPENLANE_RUN_TAG) {22_12_03_21_36}
set ::env(OPENLANE_VERBOSE) {0}
set ::env(OPENLANE_VERSION) {cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988}
set ::env(OPENROAD) {/build/}
set ::env(OPENROAD_BIN) {openroad}
-set ::env(PARSITICS_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def}
+set ::env(PARSITICS_CURRENT_DEF) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.def}
set ::env(PATH) {/openlane:/openlane/scripts:/build//bin:/build//bin/Linux-x86_64:/build//pdn/scripts:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin}
set ::env(PDK) {gf180mcuC}
set ::env(PDKPATH) {/home/htf6ry/GF180PDK//gf180mcuC}
set ::env(PDK_ROOT) {/home/htf6ry/GF180PDK/}
set ::env(PDN_CFG) {/openlane/scripts/openroad/common/pdn_cfg.tcl}
-set ::env(PLACEMENT_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan/6-pdn.def}
+set ::env(PLACEMENT_CURRENT_DEF) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/floorplan/6-pdn.def}
set ::env(PLACE_SITE) {GF018hv5v_mcu_sc7}
set ::env(PLACE_SITE_HEIGHT) {3.92}
set ::env(PLACE_SITE_WIDTH) {0.56}
@@ -598,20 +598,20 @@
set ::env(RCX_RULES) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom.magic}
set ::env(RCX_RULES_MAX) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.max.magic}
set ::env(RCX_RULES_MIN) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.min.magic}
-set ::env(RCX_SDC_FILE) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.sdc}
-set ::env(REPORTS_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports}
-set ::env(RESULTS_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results}
+set ::env(RCX_SDC_FILE) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/12-cntr_example.sdc}
+set ::env(REPORTS_DIR) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports}
+set ::env(RESULTS_DIR) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results}
set ::env(RIGHT_MARGIN_MULT) {12}
set ::env(RIPPLE_CARRY_ADDER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/rca_map.v}
set ::env(ROUTING_CORES) {2}
-set ::env(ROUTING_CURRENT_DEF) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.def}
+set ::env(ROUTING_CURRENT_DEF) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.def}
set ::env(RSZ_DONT_TOUCH_RX) {\$^}
-set ::env(RSZ_LIB) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/resizer_gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib}
+set ::env(RSZ_LIB) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/resizer_gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib}
set ::env(RSZ_USE_OLD_REMOVER) {0}
set ::env(RT_MAX_LAYER) {Metal4}
set ::env(RT_MIN_LAYER) {Metal2}
set ::env(RUN_CVC) {1}
-set ::env(RUN_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29}
+set ::env(RUN_DIR) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36}
set ::env(RUN_DRT) {1}
set ::env(RUN_FILL_INSERTION) {1}
set ::env(RUN_IRDROP_REPORT) {0}
@@ -623,13 +623,13 @@
set ::env(RUN_MAGIC_DRC) {1}
set ::env(RUN_SPEF_EXTRACTION) {1}
set ::env(RUN_STANDALONE) {1}
-set ::env(RUN_TAG) {22_12_03_16_29}
+set ::env(RUN_TAG) {22_12_03_21_36}
set ::env(RUN_TAP_DECAP_INSERTION) {1}
set ::env(SCLPATH) {/home/htf6ry/GF180PDK//gf180mcuC/gf180mcu_fd_sc_mcu7t5v0}
set ::env(SCRIPTS_DIR) {/openlane/scripts}
set ::env(SHLVL) {1}
set ::env(SPEF_EXTRACTOR) {openrcx}
-set ::env(START_TIME) {2022.12.03_21.29.36}
+set ::env(START_TIME) {2022.12.04_02.36.22}
set ::env(STA_PRE_CTS) {0}
set ::env(STA_REPORT_POWER) {1}
set ::env(STA_WRITE_LIB) {1}
@@ -671,10 +671,10 @@
set ::env(TECH_METAL_LAYERS) {Metal1 Metal2 Metal3 Metal4 Metal5}
set ::env(TERM) {xterm}
set ::env(TERMINAL_OUTPUT) {/dev/null}
-set ::env(TMP_DIR) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp}
+set ::env(TMP_DIR) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp}
set ::env(TOP_MARGIN_MULT) {4}
set ::env(TRACKS_INFO_FILE) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tracks.info}
-set ::env(TRACKS_INFO_FILE_PROCESSED) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/config.tracks}
+set ::env(TRACKS_INFO_FILE_PROCESSED) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/config.tracks}
set ::env(TRISTATE_BUFFER_MAP) {/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/gf180mcu_fd_sc_mcu7t5v0/tribuff_map.v}
set ::env(USE_ARC_ANTENNA_CHECK) {1}
set ::env(USE_GPIO_PADS) {0}
@@ -682,41 +682,41 @@
set ::env(VDD_NET) {vdd}
set ::env(VDD_NETS) {vdd}
set ::env(VDD_PIN) {vdd}
-set ::env(VERILOG_FILES) {/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v}
+set ::env(VERILOG_FILES) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v}
set ::env(WIRE_RC_LAYER) {Metal2}
set ::env(YOSYS_REWRITE_VERILOG) {0}
set ::env(_) {/openlane/flow.tcl}
-set ::env(cts_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/cts}
-set ::env(cts_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/cts}
-set ::env(cts_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts}
-set ::env(cts_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts}
-set ::env(drc_prefix) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc}
-set ::env(eco_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/eco}
-set ::env(eco_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/eco}
-set ::env(eco_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/eco}
-set ::env(eco_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/eco}
-set ::env(floorplan_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan}
-set ::env(floorplan_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/floorplan}
-set ::env(floorplan_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/floorplan}
-set ::env(floorplan_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan}
-set ::env(fp_report_prefix) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/floorplan/3-initial_fp}
-set ::env(placement_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement}
-set ::env(placement_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/placement}
-set ::env(placement_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/placement}
-set ::env(placement_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement}
-set ::env(routing_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing}
-set ::env(routing_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/routing}
-set ::env(routing_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing}
-set ::env(routing_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing}
-set ::env(signoff_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff}
-set ::env(signoff_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff}
-set ::env(signoff_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff}
-set ::env(signoff_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff}
-set ::env(synth_report_prefix) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/synthesis/1-synthesis}
-set ::env(synthesis_logs) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/synthesis}
-set ::env(synthesis_reports) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/synthesis}
-set ::env(synthesis_results) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/synthesis}
-set ::env(synthesis_tmpfiles) {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis}
-set ::env(timer_end) {1670103271}
-set ::env(timer_routed) {1670103076}
-set ::env(timer_start) {1670102976}
+set ::env(cts_logs) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/cts}
+set ::env(cts_reports) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/cts}
+set ::env(cts_results) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/cts}
+set ::env(cts_tmpfiles) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts}
+set ::env(drc_prefix) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/drc}
+set ::env(eco_logs) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/eco}
+set ::env(eco_reports) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/eco}
+set ::env(eco_results) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/eco}
+set ::env(eco_tmpfiles) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/eco}
+set ::env(floorplan_logs) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/floorplan}
+set ::env(floorplan_reports) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/floorplan}
+set ::env(floorplan_results) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/floorplan}
+set ::env(floorplan_tmpfiles) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/floorplan}
+set ::env(fp_report_prefix) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/floorplan/3-initial_fp}
+set ::env(placement_logs) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/placement}
+set ::env(placement_reports) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/placement}
+set ::env(placement_results) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/placement}
+set ::env(placement_tmpfiles) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement}
+set ::env(routing_logs) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing}
+set ::env(routing_reports) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/routing}
+set ::env(routing_results) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing}
+set ::env(routing_tmpfiles) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing}
+set ::env(signoff_logs) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff}
+set ::env(signoff_reports) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff}
+set ::env(signoff_results) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff}
+set ::env(signoff_tmpfiles) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff}
+set ::env(synth_report_prefix) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/synthesis/1-synthesis}
+set ::env(synthesis_logs) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/synthesis}
+set ::env(synthesis_reports) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/synthesis}
+set ::env(synthesis_results) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/synthesis}
+set ::env(synthesis_tmpfiles) {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis}
+set ::env(timer_end) {1670121701}
+set ::env(timer_routed) {1670121497}
+set ::env(timer_start) {1670121382}
diff --git a/openlane/cntr_example/runs/cntr_example/config_in.tcl b/openlane/cntr_example/runs/cntr_example/config_in.tcl
index 7a88c06..624b731 100644
--- a/openlane/cntr_example/runs/cntr_example/config_in.tcl
+++ b/openlane/cntr_example/runs/cntr_example/config_in.tcl
@@ -13,11 +13,13 @@
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/../../verilog/rtl/cntr_example.v]
# set absolute size of the die to 300 x 300 um
-#set ::env(DIE_AREA) "0 0 900 900" for two 4-bit counter
+#for two 4-bit counter
+#set ::env(DIE_AREA) "0 0 400 400"
set ::env(DIE_AREA) "0 0 1500 1500"
set ::env(FP_SIZING) absolute
-#set ::env(FP_CORE_UTIL) 40 for two 4-bit counter
+#for two 4-bit counter
+#set ::env(FP_CORE_UTIL) 40
set ::env(FP_CORE_UTIL) 20
set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
@@ -27,7 +29,8 @@
# clock period is ns
# need 40MHz for VGA out = 25ns
# copied from VGA example
-#set ::env(CLOCK_PERIOD) "35" for two 4-bit counter
+# for two 4-bit counter
+#set ::env(CLOCK_PERIOD) "30"
set ::env(CLOCK_PERIOD) "65"
set ::env(CLOCK_PORT) "wb_clk_i"
#set ::env(CLOCK_PORT) "clk"
diff --git a/openlane/cntr_example/runs/cntr_example/logs/cts/10-cts.log b/openlane/cntr_example/runs/cntr_example/logs/cts/10-cts.log
index e0ce5cd..7dc09f3 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/cts/10-cts.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/cts/10-cts.log
@@ -56,9 +56,9 @@
[INFO]: Repairing long wires on clock nets...
[INFO RSZ-0058] Using max wire length 22815um.
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.odb...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.def...
-Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.sdc...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/cts/cntr_example.odb...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/cts/cntr_example.def...
+Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/cts/cntr_example.sdc...
[INFO]: Legalizing...
Placement Analysis
---------------------------------
@@ -74,9 +74,9 @@
[INFO DPL-0022] HPWL after 60457.6 u
[INFO DPL-0023] HPWL delta -0.2 %
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.odb...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.def...
-Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.sdc...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/cts/cntr_example.odb...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/cts/cntr_example.def...
+Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/cts/cntr_example.sdc...
cts_report
[INFO CTS-0003] Total number of Clock Roots: 1.
[INFO CTS-0004] Total number of Buffers Inserted: 3.
@@ -655,6 +655,6 @@
Design area 67586 u^2 3% utilization.
area_report_end
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.odb...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.def...
-Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/cts/cntr_example.sdc...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/cts/cntr_example.odb...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/cts/cntr_example.def...
+Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/cts/cntr_example.sdc...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/cts/11-resizer.log b/openlane/cntr_example/runs/cntr_example/logs/cts/11-resizer.log
index 6f4a3a8..4e92434 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/cts/11-resizer.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/cts/11-resizer.log
@@ -17,11 +17,11 @@
[INFO DPL-0022] HPWL after 60457.6 u
[INFO DPL-0023] HPWL delta -0.2 %
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.odb...
-Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.nl.v...
-Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.pnl.v...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.def...
-Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.sdc...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.odb...
+Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.def...
+Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.sdc...
min_report
===========================================================================
@@ -594,8 +594,8 @@
Design area 67586 u^2 3% utilization.
area_report_end
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.odb...
-Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.nl.v...
-Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.pnl.v...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.def...
-Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/cts/11-cntr_example.resized.sdc...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.odb...
+Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.def...
+Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.sdc...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/floorplan/3-initial_fp.log b/openlane/cntr_example/runs/cntr_example/logs/floorplan/3-initial_fp.log
index c8ec028..6a52f0f 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/floorplan/3-initial_fp.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/floorplan/3-initial_fp.log
@@ -1,16 +1,16 @@
OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
-[INFO ODB-0222] Reading LEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
+[INFO ODB-0222] Reading LEF file: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 60 technology vias
[INFO ODB-0225] Created 229 library cells
-[INFO ODB-0226] Finished LEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
+[INFO ODB-0226] Finished LEF file: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef
Reading netlist...
[INFO IFP-0001] Added 374 rows of 2654 sites.
[INFO IFP-0030] Inserted 0 tiecells using gf180mcu_fd_sc_mcu7t5v0__tiel/ZN.
[INFO IFP-0030] Inserted 0 tiecells using gf180mcu_fd_sc_mcu7t5v0__tieh/Z.
[INFO] Extracting DIE_AREA and CORE_AREA from the floorplan
-[INFO] Floorplanned on a die area of 0.0 0.0 1500.0 1500.0 (microns). Saving to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/floorplan/3-initial_fp_die_area.rpt.
-[INFO] Floorplanned on a core area of 6.72 15.68 1492.96 1481.76 (microns). Saving to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/floorplan/3-initial_fp_core_area.rpt.
+[INFO] Floorplanned on a die area of 0.0 0.0 1500.0 1500.0 (microns). Saving to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/floorplan/3-initial_fp_die_area.rpt.
+[INFO] Floorplanned on a core area of 6.72 15.68 1492.96 1481.76 (microns). Saving to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/floorplan/3-initial_fp_core_area.rpt.
[WARNING] Did not save OpenROAD database!
diff --git a/openlane/cntr_example/runs/cntr_example/logs/floorplan/4-io.log b/openlane/cntr_example/runs/cntr_example/logs/floorplan/4-io.log
index 718922b..a8dc43d 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/floorplan/4-io.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/floorplan/4-io.log
@@ -4,5 +4,5 @@
Found 0 macro blocks.
Using 1u default distance from corners.
[INFO PPL-0007] Random pin placement.
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan/4-io.odb...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan/4-io.def...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/floorplan/4-io.odb...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/floorplan/4-io.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/floorplan/5-tap.log b/openlane/cntr_example/runs/cntr_example/logs/floorplan/5-tap.log
index 722ea74..0d06355 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/floorplan/5-tap.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/floorplan/5-tap.log
@@ -3,5 +3,5 @@
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO TAP-0004] Inserted 748 endcaps.
[INFO TAP-0005] Inserted 13914 tapcells.
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/floorplan/cntr_example.odb...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/floorplan/cntr_example.def...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/floorplan/cntr_example.odb...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/floorplan/cntr_example.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/floorplan/6-pdn.log b/openlane/cntr_example/runs/cntr_example/logs/floorplan/6-pdn.log
index 87eec12..f1ad69b 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/floorplan/6-pdn.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/floorplan/6-pdn.log
@@ -57,5 +57,5 @@
[INFO PSM-0064] Number of voltage sources = 17.
[INFO PSM-0040] All PDN stripes on net vss are connected.
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan/6-pdn.odb...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/floorplan/6-pdn.def...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/floorplan/6-pdn.odb...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/floorplan/6-pdn.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/placement/7-global.log b/openlane/cntr_example/runs/cntr_example/logs/placement/7-global.log
index da8647a..58dc863 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/placement/7-global.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/placement/7-global.log
@@ -324,8 +324,8 @@
[INFO GPL-0103] Weighted 25 nets.
[NesterovSolve] Finished with Overflow: 0.088836
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/7-global.odb...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/7-global.def...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/7-global.odb...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/7-global.def...
[INFO]: Setting RC values...
min_report
@@ -808,5 +808,5 @@
Design area 66550 u^2 3% utilization.
area_report_end
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/7-global.odb...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/7-global.def...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/7-global.odb...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/7-global.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/placement/8-resizer.log b/openlane/cntr_example/runs/cntr_example/logs/placement/8-resizer.log
index 0558bcb..e1cb3ab 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/placement/8-resizer.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/placement/8-resizer.log
@@ -21,11 +21,11 @@
[INFO DPL-0022] HPWL after 60307.8 u
[INFO DPL-0023] HPWL delta -0.2 %
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.odb...
-Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.nl.v...
-Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.pnl.v...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.def...
-Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.sdc...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.odb...
+Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.def...
+Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.sdc...
min_report
===========================================================================
@@ -530,8 +530,8 @@
Design area 67257 u^2 3% utilization.
area_report_end
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.odb...
-Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.nl.v...
-Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.pnl.v...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.def...
-Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/placement/8-resizer.sdc...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.odb...
+Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.def...
+Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.sdc...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/placement/9-detailed.log b/openlane/cntr_example/runs/cntr_example/logs/placement/9-detailed.log
index b5fd200..5073e63 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/placement/9-detailed.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/placement/9-detailed.log
@@ -15,7 +15,7 @@
[INFO DPL-0022] HPWL after 60307.8 u
[INFO DPL-0023] HPWL delta -0.2 %
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/placement/cntr_example.odb...
-Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/placement/cntr_example.nl.v...
-Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/placement/cntr_example.pnl.v...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/placement/cntr_example.def...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/placement/cntr_example.odb...
+Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/placement/cntr_example.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/placement/cntr_example.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/placement/cntr_example.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/routing/12-resizer.log b/openlane/cntr_example/runs/cntr_example/logs/routing/12-resizer.log
index c1c3f7c..ba9db47 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/routing/12-resizer.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/routing/12-resizer.log
@@ -65,11 +65,11 @@
[INFO DPL-0022] HPWL after 60457.6 u
[INFO DPL-0023] HPWL delta -0.2 %
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.odb...
-Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.nl.v...
-Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.pnl.v...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.def...
-Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.sdc...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/12-cntr_example.odb...
+Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/12-cntr_example.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/12-cntr_example.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/12-cntr_example.def...
+Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/12-cntr_example.sdc...
min_report
===========================================================================
@@ -645,8 +645,8 @@
Design area 67586 u^2 3% utilization.
area_report_end
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.odb...
-Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.nl.v...
-Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.pnl.v...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.def...
-Writing timing constraints to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/12-cntr_example.sdc...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/12-cntr_example.odb...
+Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/12-cntr_example.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/12-cntr_example.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/12-cntr_example.def...
+Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/12-cntr_example.sdc...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/routing/14-diode_legalization.log b/openlane/cntr_example/runs/cntr_example/logs/routing/14-diode_legalization.log
index 4b0b796..b78bcd6 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/routing/14-diode_legalization.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/routing/14-diode_legalization.log
@@ -15,7 +15,7 @@
[INFO DPL-0022] HPWL after 60491.0 u
[INFO DPL-0023] HPWL delta -0.2 %
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/diodes.odb...
-Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/diodes.nl.v...
-Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/diodes.pnl.v...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/diodes.def...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/diodes.odb...
+Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/diodes.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/diodes.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/diodes.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/routing/15-fill.log b/openlane/cntr_example/runs/cntr_example/logs/routing/15-fill.log
index f6254b2..9160206 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/routing/15-fill.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/routing/15-fill.log
@@ -3,7 +3,7 @@
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO DPL-0001] Placed 43438 filler instances.
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/15-fill.odb...
-Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/15-fill.nl.v...
-Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/15-fill.pnl.v...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/15-fill.def...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/15-fill.odb...
+Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/15-fill.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/15-fill.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/15-fill.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/routing/16-global.log b/openlane/cntr_example/runs/cntr_example/logs/routing/16-global.log
index 6db2e65..d62d139 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/routing/16-global.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/routing/16-global.log
@@ -50,9 +50,9 @@
[INFO GRT-0018] Total wirelength: 69106 um
[INFO GRT-0014] Routed nets: 111
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.odb...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.def...
-Writing routing guides to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.guide...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/16-global.odb...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/16-global.def...
+Writing routing guides to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/16-global.guide...
[INFO]: Setting RC values...
min_report
@@ -629,6 +629,6 @@
Design area 68288 u^2 3% utilization.
area_report_end
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.odb...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.def...
-Writing routing guides to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/16-global.guide...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/16-global.odb...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/16-global.def...
+Writing routing guides to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/16-global.guide...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/routing/16-global_write_netlist.log b/openlane/cntr_example/runs/cntr_example/logs/routing/16-global_write_netlist.log
index 534b935..2004d16 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/routing/16-global_write_netlist.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/routing/16-global_write_netlist.log
@@ -3,5 +3,5 @@
Components of this program may be licensed under more restrictive licenses which must be honored.
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
-Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/global.nl.v...
-Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/routing/global.pnl.v...
+Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/global.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/global.pnl.v...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/routing/18-detailed.log b/openlane/cntr_example/runs/cntr_example/logs/routing/18-detailed.log
index c992ea8..2ab3363 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/routing/18-detailed.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/routing/18-detailed.log
@@ -89,7 +89,7 @@
#macroValidViaAp = 0
#macroNoAp = 0
[INFO DRT-0166] Complete pin access.
-[INFO DRT-0267] cpu time = 00:00:02, elapsed time = 00:00:01, memory = 326.21 (MB), peak = 360.11 (MB)
+[INFO DRT-0267] cpu time = 00:00:02, elapsed time = 00:00:01, memory = 325.39 (MB), peak = 359.21 (MB)
Number of guides: 1196
@@ -137,36 +137,36 @@
[INFO DRT-0184] Done with 402 vertical wires in 4 frboxes and 647 horizontal wires in 4 frboxes.
[INFO DRT-0186] Done with 36 vertical wires in 4 frboxes and 59 horizontal wires in 4 frboxes.
[INFO DRT-0182] Complete track assignment.
-[INFO DRT-0267] cpu time = 00:00:04, elapsed time = 00:00:02, memory = 415.68 (MB), peak = 632.34 (MB)
+[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:04, memory = 456.02 (MB), peak = 630.75 (MB)
[INFO DRT-0187] Start routing data preparation.
-[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 415.68 (MB), peak = 632.34 (MB)
+[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 456.02 (MB), peak = 630.75 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
Completing 10% with 0 violations.
- elapsed time = 00:00:01, memory = 769.63 (MB).
+ elapsed time = 00:00:01, memory = 774.91 (MB).
Completing 20% with 0 violations.
- elapsed time = 00:00:02, memory = 1252.08 (MB).
+ elapsed time = 00:00:02, memory = 1248.09 (MB).
Completing 30% with 0 violations.
- elapsed time = 00:00:03, memory = 1007.61 (MB).
+ elapsed time = 00:00:04, memory = 1052.14 (MB).
Completing 40% with 0 violations.
- elapsed time = 00:00:04, memory = 1230.75 (MB).
+ elapsed time = 00:00:06, memory = 1255.17 (MB).
Completing 50% with 0 violations.
- elapsed time = 00:00:06, memory = 1436.59 (MB).
+ elapsed time = 00:00:07, memory = 1467.45 (MB).
Completing 60% with 0 violations.
- elapsed time = 00:00:07, memory = 1437.64 (MB).
+ elapsed time = 00:00:09, memory = 1153.80 (MB).
Completing 70% with 0 violations.
- elapsed time = 00:00:08, memory = 1438.79 (MB).
+ elapsed time = 00:00:10, memory = 1374.27 (MB).
Completing 80% with 0 violations.
- elapsed time = 00:00:09, memory = 1458.67 (MB).
+ elapsed time = 00:00:12, memory = 1055.23 (MB).
Completing 90% with 0 violations.
- elapsed time = 00:00:10, memory = 1458.69 (MB).
+ elapsed time = 00:00:13, memory = 1275.92 (MB).
Completing 100% with 1 violations.
- elapsed time = 00:00:12, memory = 1412.00 (MB).
+ elapsed time = 00:00:15, memory = 1437.05 (MB).
[INFO DRT-0199] Number of violations = 35.
Viol/Layer Metal2 Metal3
Metal Spacing 1 0
Recheck 27 7
-[INFO DRT-0267] cpu time = 00:00:23, elapsed time = 00:00:12, memory = 1348.21 (MB), peak = 1476.13 (MB)
+[INFO DRT-0267] cpu time = 00:00:28, elapsed time = 00:00:15, memory = 1437.05 (MB), peak = 1475.48 (MB)
Total wire length = 64342 um.
Total wire length on LAYER Metal1 = 9 um.
Total wire length on LAYER Metal2 = 28450 um.
@@ -188,27 +188,27 @@
[INFO DRT-0195] Start 1st optimization iteration.
Completing 10% with 35 violations.
- elapsed time = 00:00:00, memory = 1348.21 (MB).
+ elapsed time = 00:00:01, memory = 1438.08 (MB).
Completing 20% with 35 violations.
- elapsed time = 00:00:02, memory = 1358.78 (MB).
+ elapsed time = 00:00:02, memory = 1439.04 (MB).
Completing 30% with 19 violations.
- elapsed time = 00:00:03, memory = 1000.30 (MB).
+ elapsed time = 00:00:04, memory = 1453.16 (MB).
Completing 40% with 19 violations.
- elapsed time = 00:00:04, memory = 1226.32 (MB).
+ elapsed time = 00:00:05, memory = 1453.31 (MB).
Completing 50% with 19 violations.
- elapsed time = 00:00:05, memory = 1441.34 (MB).
+ elapsed time = 00:00:07, memory = 1544.83 (MB).
Completing 60% with 6 violations.
- elapsed time = 00:00:07, memory = 1442.63 (MB).
+ elapsed time = 00:00:09, memory = 1545.09 (MB).
Completing 70% with 6 violations.
- elapsed time = 00:00:08, memory = 1443.66 (MB).
+ elapsed time = 00:00:10, memory = 1545.17 (MB).
Completing 80% with 2 violations.
- elapsed time = 00:00:09, memory = 1011.70 (MB).
+ elapsed time = 00:00:12, memory = 1058.07 (MB).
Completing 90% with 2 violations.
- elapsed time = 00:00:10, memory = 1240.90 (MB).
+ elapsed time = 00:00:14, memory = 1314.85 (MB).
Completing 100% with 0 violations.
- elapsed time = 00:00:12, memory = 1441.73 (MB).
+ elapsed time = 00:00:15, memory = 1520.32 (MB).
[INFO DRT-0199] Number of violations = 0.
-[INFO DRT-0267] cpu time = 00:00:23, elapsed time = 00:00:12, memory = 902.64 (MB), peak = 1476.13 (MB)
+[INFO DRT-0267] cpu time = 00:00:30, elapsed time = 00:00:16, memory = 1520.32 (MB), peak = 1545.43 (MB)
Total wire length = 64292 um.
Total wire length on LAYER Metal1 = 7 um.
Total wire length on LAYER Metal2 = 28409 um.
@@ -248,11 +248,11 @@
963
-[INFO DRT-0267] cpu time = 00:00:46, elapsed time = 00:00:24, memory = 902.64 (MB), peak = 1476.13 (MB)
+[INFO DRT-0267] cpu time = 00:00:58, elapsed time = 00:00:31, memory = 1520.32 (MB), peak = 1545.43 (MB)
[INFO DRT-0180] Post processing.
Setting global connections for newly added cells...
-Writing OpenROAD database to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.odb...
-Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.nl.v...
-Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.pnl.v...
-Writing layout to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def...
+Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.odb...
+Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.pnl.v...
+Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.def...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/20-parasitics_extraction.nom.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/20-parasitics_extraction.nom.log
index 941f3fc..e4a1611 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/signoff/20-parasitics_extraction.nom.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/20-parasitics_extraction.nom.log
@@ -1,18 +1,18 @@
OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
-[INFO ODB-0222] Reading LEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
+[INFO ODB-0222] Reading LEF file: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 60 technology vias
[INFO ODB-0225] Created 229 library cells
-[INFO ODB-0226] Finished LEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
-[INFO ODB-0127] Reading DEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def
+[INFO ODB-0226] Finished LEF file: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef
+[INFO ODB-0127] Reading DEF file: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.def
[INFO ODB-0128] Design: cntr_example
[INFO ODB-0130] Created 42 pins.
[INFO ODB-0131] Created 58369 components and 117183 component-terminals.
[INFO ODB-0132] Created 2 special nets and 116738 connections.
[INFO ODB-0133] Created 111 nets and 445 connections.
-[INFO ODB-0134] Finished DEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def
+[INFO ODB-0134] Finished DEF file: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.def
Using RCX ruleset '/home/htf6ry/GF180PDK//gf180mcuC/libs.tech/openlane/rules.openrcx.gf180mcuC.nom.magic'...
[INFO RCX-0431] Defined process_corner X with ext_model_index 0
[INFO RCX-0029] Defined extraction corner X
@@ -29,10 +29,10 @@
[INFO RCX-0442] 100% completion -- 1249 wires have been extracted
[INFO RCX-0045] Extract 111 nets, 919 rsegs, 919 caps, 708 ccs
[INFO RCX-0015] Finished extracting cntr_example.
-Writing result to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.spef...
+Writing result to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.spef...
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
-Writing extracted parasitics to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.spef...
+Writing extracted parasitics to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.spef...
[INFO RCX-0016] Writing SPEF ...
[INFO RCX-0443] 111 nets finished
[INFO RCX-0017] Finished writing SPEF ...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/21-rcx_mcsta.nom.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/21-rcx_mcsta.nom.log
index 71dc7b9..c6332b1 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/signoff/21-rcx_mcsta.nom.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/21-rcx_mcsta.nom.log
@@ -11494,10 +11494,10 @@
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing SDF files for all corners...
-Writing SDF for the ff corner to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.ff.sdf...
-Writing SDF for the ss corner to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.ss.sdf...
-Writing SDF for the tt corner to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.tt.sdf...
+Writing SDF for the ff corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.ff.sdf...
+Writing SDF for the ss corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.ss.sdf...
+Writing SDF for the tt corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.tt.sdf...
Writing timing models for all corners...
-Writing timing models for the ff corner to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.ff.lib...
-Writing timing models for the ss corner to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.ss.lib...
-Writing timing models for the tt corner to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.tt.lib...
+Writing timing models for the ff corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.ff.lib...
+Writing timing models for the ss corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.ss.lib...
+Writing timing models for the tt corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.tt.lib...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/22-rcx_sta.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/22-rcx_sta.log
index a52a107..af93436 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/signoff/22-rcx_sta.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/22-rcx_sta.log
@@ -668,5 +668,5 @@
area_report_end
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
-Writing SDF to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.sdf...
-Writing timing model to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/mca/process_corner_nom/cntr_example.lib...
+Writing SDF to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.sdf...
+Writing timing model to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.lib...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/23-gds_ptrs.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-gds_ptrs.log
index 026aa90..cd4400b 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/signoff/23-gds_ptrs.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-gds_ptrs.log
@@ -147,4 +147,4 @@
45000 uses
50000 uses
55000 uses
-[INFO]: Wrote /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/gds_ptrs.mag including GDS pointers.
+[INFO]: Wrote /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff/gds_ptrs.mag including GDS pointers.
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/23-gdsii.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-gdsii.log
index e0c066d..c442a21 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/signoff/23-gdsii.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-gdsii.log
@@ -51,7 +51,7 @@
LEF read, Line 301 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 302 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read: Processed 1366 lines.
-Reading DEF data from file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def.
+Reading DEF data from file /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.def.
This action cannot be undone.
Processed 3 vias total.
Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_1 geometry by factor of 2
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/23-lef.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-lef.log
index 90f5135..a0e2fdd 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/signoff/23-lef.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-lef.log
@@ -66,82 +66,82 @@
cntr_example: 130000 rects
cntr_example: 140000 rects
[INFO]: Writing abstract LEF
-Generating LEF output /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.lef for cell cntr_example:
+Generating LEF output /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/cntr_example.lef for cell cntr_example:
Diagnostic: Write LEF header for cell cntr_example
Diagnostic: Writing LEF output for cell cntr_example
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_4" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_4" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__clkbuf_4.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__buf_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__buf_1.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__buf_1" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__buf_1.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__buf_1.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__tiel" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__tiel.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__tiel" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__tiel.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__tiel.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__clkbuf_16.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffq_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__dffq_1.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffq_1" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__dffq_1.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__dffq_1.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffq_2" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__dffq_2.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__dffq_2" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__dffq_2.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__dffq_2.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nor2_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nor2_1.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nor2_1" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nor2_1.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nor2_1.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__xor2_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__xor2_1.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__xor2_1" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__xor2_1.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__xor2_1.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nand2_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nand2_1.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nand2_1" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nand2_1.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nand2_1.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nand3_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nand3_1.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__nand3_1" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__nand3_1.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__nand3_1.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi21_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__aoi21_1" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__aoi21_1.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai21_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__oai21_1.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__oai21_1" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__oai21_1.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__oai21_1.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__buf_2" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__buf_2.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__buf_2" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__buf_2.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__buf_2.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkinv_3" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__clkinv_3" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__clkinv_3.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__filltie" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__filltie.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__filltie" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__filltie.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__filltie.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__endcap" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__endcap.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__endcap" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__endcap.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__endcap.mag.
The discovered version will be used.
Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__endcap geometry by factor of 2
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fill_1" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fill_1.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fill_1" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fill_1.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fill_1.mag.
The discovered version will be used.
Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_1 geometry by factor of 2
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fill_2" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fill_2.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fill_2" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fill_2.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fill_2.mag.
The discovered version will be used.
Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_2 geometry by factor of 2
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_4" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_4" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_4.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_32" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_32" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_32.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_8" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_8" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_8.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_16" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_16" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_16.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_64" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__fillcap_64" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__fillcap_64.mag.
The discovered version will be used.
-Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__antenna" at bad file path /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/gf180mcu_fd_sc_mcu7t5v0__antenna.mag.
+Warning: Parent cell lists instance of "gf180mcu_fd_sc_mcu7t5v0__antenna" at bad file path /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/gf180mcu_fd_sc_mcu7t5v0__antenna.mag.
The cell exists in the search paths at /home/htf6ry/GF180PDK/gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/maglef/gf180mcu_fd_sc_mcu7t5v0__antenna.mag.
The discovered version will be used.
Diagnostic: Scale value is 0.005000
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/23-maglef.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-maglef.log
index 5ac081d..0b9a635 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/signoff/23-maglef.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/23-maglef.log
@@ -12,7 +12,7 @@
Scaled tech values by 10 / 1 to match internal grid scaling
Loading gf180mcuC Device Generator Menu ...
Using technology "gf180mcuC", version 1.0.349-0-g0059588
-Reading LEF data from file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.lef.
+Reading LEF data from file /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/cntr_example.lef.
This action cannot be undone.
LEF read: Processed 470 lines.
[INFO]: DONE GENERATING MAGLEF VIEW
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/24-spice.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/24-spice.log
index 9301061..24e281a 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/signoff/24-spice.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/24-spice.log
@@ -51,7 +51,7 @@
LEF read, Line 301 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 302 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read: Processed 1366 lines.
-Reading DEF data from file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def.
+Reading DEF data from file /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.def.
This action cannot be undone.
Processed 3 vias total.
Scaled magic input cell gf180mcu_fd_sc_mcu7t5v0__fill_1 geometry by factor of 2
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/25-write_powered_def.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/25-write_powered_def.log
index 62b684f..e707db1 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/signoff/25-write_powered_def.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/25-write_powered_def.log
@@ -1,18 +1,18 @@
OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
-[INFO ODB-0222] Reading LEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
+[INFO ODB-0222] Reading LEF file: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 60 technology vias
[INFO ODB-0225] Created 229 library cells
-[INFO ODB-0226] Finished LEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
-[INFO ODB-0127] Reading DEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def
+[INFO ODB-0226] Finished LEF file: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef
+[INFO ODB-0127] Reading DEF file: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.def
[INFO ODB-0128] Design: cntr_example
[INFO ODB-0130] Created 42 pins.
[INFO ODB-0131] Created 58369 components and 117183 component-terminals.
[INFO ODB-0132] Created 2 special nets and 116738 connections.
[INFO ODB-0133] Created 111 nets and 445 connections.
-[INFO ODB-0134] Finished DEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/routing/cntr_example.def
+[INFO ODB-0134] Finished DEF file: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/cntr_example.def
Top-level design name: cntr_example
Found default power net 'vdd'
Found default ground net 'vss'
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/25-write_powered_verilog.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/25-write_powered_verilog.log
index ad665d3..e2b2ddb 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/signoff/25-write_powered_verilog.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/25-write_powered_verilog.log
@@ -3,5 +3,5 @@
Components of this program may be licensed under more restrictive licenses which must be honored.
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
-Writing netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.nl.v...
-Writing powered netlist to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.pnl.v...
+Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff/24-cntr_example.nl.v...
+Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff/24-cntr_example.pnl.v...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/27-lvs.lef.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/27-lvs.lef.log
index ebac821..75b0482 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/signoff/27-lvs.lef.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/27-lvs.lef.log
@@ -2,8 +2,8 @@
Warning: netgen command 'format' use fully-qualified name '::netgen::format'
Warning: netgen command 'global' use fully-qualified name '::netgen::global'
Generating JSON file result
-Reading netlist file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.spice
-Reading netlist file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.pnl.v
+Reading netlist file /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/cntr_example.spice
+Reading netlist file /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff/24-cntr_example.pnl.v
Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match.
Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__clkinv_3.
Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__nor2_1.
@@ -30,8 +30,8 @@
Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fill_2.
Creating placeholder cell definition for module gf180mcu_fd_sc_mcu7t5v0__fillcap_64.
Reading setup file /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl
-Comparison output logged to file /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/27-cntr_example.lef.lvs.log
-Logging to file "/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/27-cntr_example.lef.lvs.log" enabled
+Comparison output logged to file /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/27-cntr_example.lef.lvs.log
+Logging to file "/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/27-cntr_example.lef.lvs.log" enabled
Contents of circuit 1: Circuit: 'gf180mcu_fd_sc_mcu7t5v0__fillcap_4'
Circuit gf180mcu_fd_sc_mcu7t5v0__fillcap_4 contains 0 device instances.
@@ -317,5 +317,5 @@
Final result:
Circuits match uniquely.
.
-Logging to file "/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/27-cntr_example.lef.lvs.log" disabled
+Logging to file "/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/27-cntr_example.lef.lvs.log" disabled
LVS Done.
diff --git a/openlane/cntr_example/runs/cntr_example/logs/signoff/28-drc.log b/openlane/cntr_example/runs/cntr_example/logs/signoff/28-drc.log
index ff74d83..2fe4d92 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/signoff/28-drc.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/signoff/28-drc.log
@@ -154,6 +154,6 @@
No errors found.
[INFO]: COUNT: 0
[INFO]: Should be divided by 3 or 4
-[INFO]: DRC Checking DONE (/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/drc.rpt)
-[INFO]: Saving mag view with DRC errors (/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.drc.mag)
+[INFO]: DRC Checking DONE (/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/drc.rpt)
+[INFO]: Saving mag view with DRC errors (/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/cntr_example.drc.mag)
[INFO]: Saved
diff --git a/openlane/cntr_example/runs/cntr_example/logs/synthesis/1-synthesis.log b/openlane/cntr_example/runs/cntr_example/logs/synthesis/1-synthesis.log
index 517c198..a7b7cab 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/synthesis/1-synthesis.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/synthesis/1-synthesis.log
@@ -28,8 +28,8 @@
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
Defining MPRJ_IO_PADS=38
-1. Executing Verilog-2005 frontend: /home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v
-Parsing SystemVerilog input from `/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v' to AST representation.
+1. Executing Verilog-2005 frontend: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v
+Parsing SystemVerilog input from `/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v' to AST representation.
Generating RTLIL representation for module `\cntr_example'.
Generating RTLIL representation for module `\cntr_1'.
Generating RTLIL representation for module `\cntr_2'.
@@ -39,7 +39,7 @@
Successfully finished Verilog frontend.
2. Generating Graphviz representation of design.
-Writing dot description to `/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/hierarchy.dot'.
+Writing dot description to `/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/hierarchy.dot'.
Dumping module cntr_example to page 1.
Warning: WIDTHLABEL \io_out [19:16] 4
Warning: WIDTHLABEL \io_out [15:12] 4
@@ -137,11 +137,11 @@
Cleaned up 0 empty switches.
4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
-Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28 in module $paramod\cntr_1\BITS=s32'00000000000000000000000000010100.
-Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25 in module $paramod\cntr_2\BITS=s32'00000000000000000000000000010100.
-Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22 in module $paramod\cntr_3\BITS=s32'00000000000000000000000000010100.
-Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19 in module $paramod\cntr_4\BITS=s32'00000000000000000000000000010100.
-Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16 in module $paramod\cntr_5\BITS=s32'00000000000000000000000000010100.
+Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28 in module $paramod\cntr_1\BITS=s32'00000000000000000000000000010100.
+Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25 in module $paramod\cntr_2\BITS=s32'00000000000000000000000000010100.
+Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22 in module $paramod\cntr_3\BITS=s32'00000000000000000000000000010100.
+Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19 in module $paramod\cntr_4\BITS=s32'00000000000000000000000000010100.
+Marked 1 switch rules as full_case in process $proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16 in module $paramod\cntr_5\BITS=s32'00000000000000000000000000010100.
Removed a total of 0 dead cases.
4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
@@ -157,44 +157,44 @@
<suppressed ~5 debug messages>
4.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
-Creating decoders for process `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
+Creating decoders for process `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
1/1: $0\out1[19:0]
-Creating decoders for process `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
+Creating decoders for process `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
1/1: $0\out2[19:0]
-Creating decoders for process `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
+Creating decoders for process `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
1/1: $0\out3[19:0]
-Creating decoders for process `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
+Creating decoders for process `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
1/1: $0\out4[19:0]
-Creating decoders for process `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
+Creating decoders for process `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
1/1: $0\out5[19:0]
4.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
4.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
-Creating register for signal `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.\out1' using process `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
+Creating register for signal `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.\out1' using process `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
created $dff cell `$procdff$51' with positive edge clock.
-Creating register for signal `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.\out2' using process `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
+Creating register for signal `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.\out2' using process `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
created $dff cell `$procdff$52' with positive edge clock.
-Creating register for signal `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.\out3' using process `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
+Creating register for signal `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.\out3' using process `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
created $dff cell `$procdff$53' with positive edge clock.
-Creating register for signal `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.\out4' using process `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
+Creating register for signal `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.\out4' using process `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
created $dff cell `$procdff$54' with positive edge clock.
-Creating register for signal `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.\out5' using process `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
+Creating register for signal `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.\out5' using process `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
created $dff cell `$procdff$55' with positive edge clock.
4.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
4.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
-Found and cleaned up 1 empty switch in `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
-Removing empty process `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
-Found and cleaned up 1 empty switch in `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
-Removing empty process `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
-Found and cleaned up 1 empty switch in `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
-Removing empty process `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
-Found and cleaned up 1 empty switch in `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
-Removing empty process `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
-Found and cleaned up 1 empty switch in `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
-Removing empty process `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
+Found and cleaned up 1 empty switch in `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
+Removing empty process `$paramod\cntr_1\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:186$28'.
+Found and cleaned up 1 empty switch in `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
+Removing empty process `$paramod\cntr_2\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:206$25'.
+Found and cleaned up 1 empty switch in `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
+Removing empty process `$paramod\cntr_3\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:226$22'.
+Found and cleaned up 1 empty switch in `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
+Removing empty process `$paramod\cntr_4\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:246$19'.
+Found and cleaned up 1 empty switch in `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
+Removing empty process `$paramod\cntr_5\BITS=s32'00000000000000000000000000010100.$proc$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:266$16'.
Cleaned up 5 empty switches.
4.2.12. Executing OPT_EXPR pass (perform const folding).
@@ -328,11 +328,11 @@
Removed a total of 0 cells.
4.9.6. Executing OPT_DFF pass (perform DFF optimizations).
-Adding SRST signal on $flatten\cntr_5.$procdff$55 ($dff) from module cntr_example (D = $flatten\cntr_5.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18_Y [19:0], Q = \cntr_5.out5, rval = 20'00000000000000000000).
-Adding SRST signal on $flatten\cntr_4.$procdff$54 ($dff) from module cntr_example (D = $flatten\cntr_4.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21_Y [19:0], Q = \cntr_4.out4, rval = 20'00000000000000000000).
-Adding SRST signal on $flatten\cntr_3.$procdff$53 ($dff) from module cntr_example (D = $flatten\cntr_3.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24_Y [19:0], Q = \cntr_3.out3, rval = 20'00000000000000000000).
-Adding SRST signal on $flatten\cntr_2.$procdff$52 ($dff) from module cntr_example (D = $flatten\cntr_2.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27_Y [19:0], Q = \cntr_2.out2, rval = 20'00000000000000000000).
-Adding SRST signal on $flatten\cntr_1.$procdff$51 ($dff) from module cntr_example (D = $flatten\cntr_1.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30_Y [19:0], Q = \cntr_1.out1, rval = 20'00000000000000000000).
+Adding SRST signal on $flatten\cntr_5.$procdff$55 ($dff) from module cntr_example (D = $flatten\cntr_5.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18_Y [19:0], Q = \cntr_5.out5, rval = 20'00000000000000000000).
+Adding SRST signal on $flatten\cntr_4.$procdff$54 ($dff) from module cntr_example (D = $flatten\cntr_4.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21_Y [19:0], Q = \cntr_4.out4, rval = 20'00000000000000000000).
+Adding SRST signal on $flatten\cntr_3.$procdff$53 ($dff) from module cntr_example (D = $flatten\cntr_3.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24_Y [19:0], Q = \cntr_3.out3, rval = 20'00000000000000000000).
+Adding SRST signal on $flatten\cntr_2.$procdff$52 ($dff) from module cntr_example (D = $flatten\cntr_2.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27_Y [19:0], Q = \cntr_2.out2, rval = 20'00000000000000000000).
+Adding SRST signal on $flatten\cntr_1.$procdff$51 ($dff) from module cntr_example (D = $flatten\cntr_1.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30_Y [19:0], Q = \cntr_1.out1, rval = 20'00000000000000000000).
4.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cntr_example..
@@ -369,21 +369,21 @@
4.9.16. Finished OPT passes. (There is nothing left to do.)
4.10. Executing WREDUCE pass (reducing word size of cells).
-Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_1.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30 ($add).
-Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_1.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30 ($add).
-Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_2.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27 ($add).
-Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_2.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27 ($add).
-Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_3.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24 ($add).
-Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_3.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24 ($add).
-Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_4.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21 ($add).
-Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_4.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21 ($add).
-Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_5.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18 ($add).
-Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_5.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18 ($add).
-Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_1.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30_Y.
-Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_2.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27_Y.
-Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_3.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24_Y.
-Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_4.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21_Y.
-Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_5.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18_Y.
+Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_1.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30 ($add).
+Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_1.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30 ($add).
+Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_2.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27 ($add).
+Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_2.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27 ($add).
+Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_3.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24 ($add).
+Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_3.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24 ($add).
+Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_4.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21 ($add).
+Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_4.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21 ($add).
+Removed top 31 bits (of 32) from port B of cell cntr_example.$flatten\cntr_5.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18 ($add).
+Removed top 12 bits (of 32) from port Y of cell cntr_example.$flatten\cntr_5.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18 ($add).
+Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_1.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30_Y.
+Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_2.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27_Y.
+Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_3.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24_Y.
+Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_4.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21_Y.
+Removed top 12 bits (of 32) from wire cntr_example.$flatten\cntr_5.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18_Y.
4.11. Executing PEEPOPT pass (run peephole optimizers).
@@ -394,21 +394,21 @@
4.13. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module cntr_example:
- creating $macc model for $flatten\cntr_1.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30 ($add).
- creating $macc model for $flatten\cntr_2.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27 ($add).
- creating $macc model for $flatten\cntr_3.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24 ($add).
- creating $macc model for $flatten\cntr_4.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21 ($add).
- creating $macc model for $flatten\cntr_5.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18 ($add).
- creating $alu model for $macc $flatten\cntr_5.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18.
- creating $alu model for $macc $flatten\cntr_4.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21.
- creating $alu model for $macc $flatten\cntr_3.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24.
- creating $alu model for $macc $flatten\cntr_2.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27.
- creating $alu model for $macc $flatten\cntr_1.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30.
- creating $alu cell for $flatten\cntr_1.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30: $auto$alumacc.cc:485:replace_alu$66
- creating $alu cell for $flatten\cntr_2.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27: $auto$alumacc.cc:485:replace_alu$69
- creating $alu cell for $flatten\cntr_3.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24: $auto$alumacc.cc:485:replace_alu$72
- creating $alu cell for $flatten\cntr_4.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21: $auto$alumacc.cc:485:replace_alu$75
- creating $alu cell for $flatten\cntr_5.$add$/home/htf6ry/gf180-demo/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18: $auto$alumacc.cc:485:replace_alu$78
+ creating $macc model for $flatten\cntr_1.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30 ($add).
+ creating $macc model for $flatten\cntr_2.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27 ($add).
+ creating $macc model for $flatten\cntr_3.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24 ($add).
+ creating $macc model for $flatten\cntr_4.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21 ($add).
+ creating $macc model for $flatten\cntr_5.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18 ($add).
+ creating $alu model for $macc $flatten\cntr_5.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18.
+ creating $alu model for $macc $flatten\cntr_4.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21.
+ creating $alu model for $macc $flatten\cntr_3.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24.
+ creating $alu model for $macc $flatten\cntr_2.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27.
+ creating $alu model for $macc $flatten\cntr_1.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30.
+ creating $alu cell for $flatten\cntr_1.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:190$30: $auto$alumacc.cc:485:replace_alu$66
+ creating $alu cell for $flatten\cntr_2.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:210$27: $auto$alumacc.cc:485:replace_alu$69
+ creating $alu cell for $flatten\cntr_3.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:230$24: $auto$alumacc.cc:485:replace_alu$72
+ creating $alu cell for $flatten\cntr_4.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:250$21: $auto$alumacc.cc:485:replace_alu$75
+ creating $alu cell for $flatten\cntr_5.$add$/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/../../verilog/rtl/cntr_example.v:270$18: $auto$alumacc.cc:485:replace_alu$78
created 5 $alu and 0 $macc cells.
4.14. Executing SHARE pass (SAT-based resource sharing).
@@ -672,7 +672,7 @@
Found and reported 0 problems.
5. Generating Graphviz representation of design.
-Writing dot description to `/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/post_techmap.dot'.
+Writing dot description to `/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/post_techmap.dot'.
Dumping module cntr_example to page 1.
Warning: WIDTHLABEL \cntr_3.out3 [0] 1
Warning: WIDTHLABEL $auto$alumacc.cc:485:replace_alu$72.X [0] 1
@@ -891,16 +891,16 @@
12. Executing ABC pass (technology mapping using ABC).
-12.1. Extracting gate netlist of module `\cntr_example' to `/tmp/yosys-abc-V62u8j/input.blif'..
+12.1. Extracting gate netlist of module `\cntr_example' to `/tmp/yosys-abc-1aa5wH/input.blif'..
Extracted 50 gates and 72 wires to a netlist network with 21 inputs and 20 outputs.
12.1.1. Executing ABC.
-Running ABC command: "/build/bin/yosys-abc" -s -f /tmp/yosys-abc-V62u8j/abc.script 2>&1
-ABC: ABC command line: "source /tmp/yosys-abc-V62u8j/abc.script".
+Running ABC command: "/build/bin/yosys-abc" -s -f /tmp/yosys-abc-1aa5wH/abc.script 2>&1
+ABC: ABC command line: "source /tmp/yosys-abc-1aa5wH/abc.script".
ABC:
-ABC: + read_blif /tmp/yosys-abc-V62u8j/input.blif
-ABC: + read_lib -w /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/trimmed.lib
-ABC: Parsing finished successfully. Parsing time = 0.10 sec
+ABC: + read_blif /tmp/yosys-abc-1aa5wH/input.blif
+ABC: + read_lib -w /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/trimmed.lib
+ABC: Parsing finished successfully. Parsing time = 0.11 sec
ABC: Scl_LibertyReadGenlib() skipped cell "gf180mcu_fd_sc_mcu7t5v0__antenna" without logic function.
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "gf180mcu_fd_sc_mcu7t5v0__bufz_2".
@@ -973,13 +973,13 @@
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latsnq_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latsnq_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "gf180mcu_fd_sc_mcu7t5v0__latsnq_4".
-ABC: Library "gf180mcuC_merged" from "/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/trimmed.lib" has 143 cells (72 skipped: 36 seq; 15 tri-state; 21 no func; 0 dont_use). Time = 0.21 sec
-ABC: Memory = 23.58 MB. Time = 0.21 sec
+ABC: Library "gf180mcuC_merged" from "/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/trimmed.lib" has 143 cells (72 skipped: 36 seq; 15 tri-state; 21 no func; 0 dont_use). Time = 0.22 sec
+ABC: Memory = 23.58 MB. Time = 0.22 sec
ABC: Warning: Detected 6 multi-output gates (for example, "gf180mcu_fd_sc_mcu7t5v0__addf_1").
-ABC: + read_constr -v /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/synthesis.sdc
+ABC: + read_constr -v /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/synthesis.sdc
ABC: Setting driving cell to be "gf180mcu_fd_sc_mcu7t5v0__inv_1".
ABC: Setting output load to be 72.910004.
-ABC: + read_constr /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/synthesis/synthesis.sdc
+ABC: + read_constr /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/synthesis/synthesis.sdc
ABC: + fx
ABC: + mfs
ABC: + strash
@@ -1054,7 +1054,7 @@
ABC: Start-point = pi20 (\wb_rst_i). End-point = po1 ($auto$rtlil.cc:2560:MuxGate$1324).
ABC: + print_stats -m
ABC: netlist : i/o = 21/ 20 lat = 0 nd = 47 edge = 112 area =746.35 delay = 3.00 lev = 3
-ABC: + write_blif /tmp/yosys-abc-V62u8j/output.blif
+ABC: + write_blif /tmp/yosys-abc-1aa5wH/output.blif
12.1.2. Re-integrating ABC results.
ABC RESULTS: gf180mcu_fd_sc_mcu7t5v0__inv_1 cells: 1
@@ -1158,6 +1158,6 @@
Dumping module `\cntr_example'.
Warnings: 88 unique messages, 166 total
-End of script. Logfile hash: 383cbbea59, CPU: user 1.22s system 0.04s, MEM: 58.29 MB peak
+End of script. Logfile hash: b06cb83cf0, CPU: user 1.31s system 0.02s, MEM: 58.17 MB peak
Yosys 0.22 (git sha1 f109fa3d4c5, gcc 8.3.1 -fPIC -Os)
-Time spent: 30% 1x dfflibmap (0 sec), 30% 4x stat (0 sec), ...
+Time spent: 31% 1x dfflibmap (0 sec), 28% 4x stat (0 sec), ...
diff --git a/openlane/cntr_example/runs/cntr_example/logs/synthesis/2-sta.log b/openlane/cntr_example/runs/cntr_example/logs/synthesis/2-sta.log
index bc96fa2..547eaae 100644
--- a/openlane/cntr_example/runs/cntr_example/logs/synthesis/2-sta.log
+++ b/openlane/cntr_example/runs/cntr_example/logs/synthesis/2-sta.log
@@ -1,11 +1,11 @@
OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
-[INFO ODB-0222] Reading LEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
+[INFO ODB-0222] Reading LEF file: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 60 technology vias
[INFO ODB-0225] Created 229 library cells
-[INFO ODB-0226] Finished LEF file: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/merged.nom.lef
+[INFO ODB-0226] Finished LEF file: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef
Reading netlist...
[INFO]: Setting output delay to: 13.0
[INFO]: Setting input delay to: 13.0
@@ -454,4 +454,4 @@
Design area 2178 u^2 100% utilization.
area_report_end
[WARNING] Did not save OpenROAD database!
-Writing SDF to /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/synthesis/cntr_example.sdf...
+Writing SDF to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/synthesis/cntr_example.sdf...
diff --git a/openlane/cntr_example/runs/cntr_example/openlane.log b/openlane/cntr_example/runs/cntr_example/openlane.log
index c935a06..b516604 100644
--- a/openlane/cntr_example/runs/cntr_example/openlane.log
+++ b/openlane/cntr_example/runs/cntr_example/openlane.log
@@ -1,50 +1,50 @@
-[INFO]: Run Directory: /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29
+[INFO]: Run Directory: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36
[INFO]: Preparing LEF files for the nom corner...
-[INFO]: Running Synthesis (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/synthesis/1-synthesis.log)...
-[INFO]: Running Single-Corner Static Timing Analysis (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/synthesis/2-sta.log)...
-[INFO]: Running Initial Floorplanning (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/3-initial_fp.log)...
+[INFO]: Running Synthesis (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/synthesis/1-synthesis.log)...
+[INFO]: Running Single-Corner Static Timing Analysis (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/synthesis/2-sta.log)...
+[INFO]: Running Initial Floorplanning (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/floorplan/3-initial_fp.log)...
[INFO]: Floorplanned with width 1486.24 and height 1466.08.
[INFO]: Running IO Placement...
-[INFO]: Running Tap/Decap Insertion (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/5-tap.log)...
+[INFO]: Running Tap/Decap Insertion (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/floorplan/5-tap.log)...
[INFO]: Power planning with power {vdd} and ground {vss}...
-[INFO]: Generating PDN (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/floorplan/6-pdn.log)...
-[INFO]: Running Global Placement (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement/7-global.log)...
-[INFO]: Running Placement Resizer Design Optimizations (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement/8-resizer.log)...
-[INFO]: Running Detailed Placement (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/placement/9-detailed.log)...
-[INFO]: Running Clock Tree Synthesis (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/cts/10-cts.log)...
-[INFO]: Running Placement Resizer Timing Optimizations (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/cts/11-resizer.log)...
-[INFO]: Running Global Routing Resizer Timing Optimizations (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/12-resizer.log)...
-[INFO]: Running Diode Insertion (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/13-diodes.log)...
-[INFO]: Running Detailed Placement (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/14-diode_legalization.log)...
-[INFO]: Running Fill Insertion (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/15-fill.log)...
-[INFO]: Running Global Routing (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/16-global.log)...
-[INFO]: Writing Verilog (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/16-global_write_netlist.log)...
-[INFO]: Running Detailed Routing (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/18-detailed.log)...
+[INFO]: Generating PDN (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/floorplan/6-pdn.log)...
+[INFO]: Running Global Placement (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/placement/7-global.log)...
+[INFO]: Running Placement Resizer Design Optimizations (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/placement/8-resizer.log)...
+[INFO]: Running Detailed Placement (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/placement/9-detailed.log)...
+[INFO]: Running Clock Tree Synthesis (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/cts/10-cts.log)...
+[INFO]: Running Placement Resizer Timing Optimizations (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/cts/11-resizer.log)...
+[INFO]: Running Global Routing Resizer Timing Optimizations (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/12-resizer.log)...
+[INFO]: Running Diode Insertion (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/13-diodes.log)...
+[INFO]: Running Detailed Placement (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/14-diode_legalization.log)...
+[INFO]: Running Fill Insertion (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/15-fill.log)...
+[INFO]: Running Global Routing (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/16-global.log)...
+[INFO]: Writing Verilog (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/16-global_write_netlist.log)...
+[INFO]: Running Detailed Routing (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/18-detailed.log)...
[INFO]: No DRC violations after detailed routing.
-[INFO]: Checking Wire Lengths (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/routing/19-wire_lengths.log)...
-[INFO]: Running SPEF Extraction at the nom process corner (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/20-parasitics_extraction.nom.log)...
-[INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/21-rcx_mcsta.nom.log)...
-[INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/22-rcx_sta.log)...
+[INFO]: Checking Wire Lengths (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/routing/19-wire_lengths.log)...
+[INFO]: Running SPEF Extraction at the nom process corner (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/20-parasitics_extraction.nom.log)...
+[INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/21-rcx_mcsta.nom.log)...
+[INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/22-rcx_sta.log)...
[INFO]: Running Magic to generate various views...
-[INFO]: Streaming out GDSII with Magic (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/23-gdsii.log)...
+[INFO]: Streaming out GDSII with Magic (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/23-gdsii.log)...
[INFO]: Generating MAGLEF views...
-[INFO]: Running Magic Spice Export from LEF (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/24-spice.log)...
-[INFO]: Writing Powered Verilog (logs: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/25-write_powered_def.log, ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/25-write_powered_verilog.log)...
-[INFO]: Writing Verilog (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/25-write_powered_verilog.log)...
-[INFO]: Running LVS (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/27-lvs.lef.log)...
-[INFO]: Running Magic DRC (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/28-drc.log)...
+[INFO]: Running Magic Spice Export from LEF (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/24-spice.log)...
+[INFO]: Writing Powered Verilog (logs: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/25-write_powered_def.log, ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/25-write_powered_verilog.log)...
+[INFO]: Writing Verilog (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/25-write_powered_verilog.log)...
+[INFO]: Running LVS (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/27-lvs.lef.log)...
+[INFO]: Running Magic DRC (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/28-drc.log)...
[INFO]: Converting Magic DRC database to various tool-readable formats...
[INFO]: No DRC violations after GDS streaming out.
-[INFO]: Running OpenROAD Antenna Rule Checker (log: ../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/29-antenna.log)...
+[INFO]: Running OpenROAD Antenna Rule Checker (log: ../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/29-antenna.log)...
[WARNING]: This PDK does not support the Circuit Validity Checker, skipping...
-[INFO]: Saving current set of views in '../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/final'...
-[INFO]: Saving current set of views in '../home/htf6ry/gf180-demo'...
+[INFO]: Saving current set of views in '../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/final'...
+[INFO]: Saving current set of views in '../home/htf6ry/gf180-demo-fiveguys'...
[INFO]: Saving runtime environment...
[INFO]: Generating final set of reports...
-[INFO]: Created manufacturability report at '../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/manufacturability.rpt'.
-[INFO]: Created metrics report at '../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/metrics.csv'.
-[WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/22-rcx_sta.slew.rpt'.
-[WARNING]: There are max capacitance violations in the design at the typical corner. Please refer to '../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/22-rcx_sta.slew.rpt'.
+[INFO]: Created manufacturability report at '../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/manufacturability.rpt'.
+[INFO]: Created metrics report at '../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/metrics.csv'.
+[WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/22-rcx_sta.slew.rpt'.
+[WARNING]: There are max capacitance violations in the design at the typical corner. Please refer to '../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/22-rcx_sta.slew.rpt'.
[INFO]: There are no hold violations in the design at the typical corner.
[INFO]: There are no setup violations in the design at the typical corner.
[SUCCESS]: Flow complete.
diff --git a/openlane/cntr_example/runs/cntr_example/runtime.yaml b/openlane/cntr_example/runs/cntr_example/runtime.yaml
index c7ea24c..363730f 100644
--- a/openlane/cntr_example/runs/cntr_example/runtime.yaml
+++ b/openlane/cntr_example/runs/cntr_example/runtime.yaml
@@ -1,97 +1,97 @@
- status: 0 - openlane design prep
- runtime_s: 1.83
- runtime_ts: 0h0m1s830ms
+ runtime_s: 2.3
+ runtime_ts: 0h0m2s302ms
- status: 1 - synthesis - yosys
- runtime_s: 2.21
- runtime_ts: 0h0m2s209ms
+ runtime_s: 2.43
+ runtime_ts: 0h0m2s431ms
- status: 2 - sta - openroad
- runtime_s: 0.81
- runtime_ts: 0h0m0s807ms
+ runtime_s: 0.95
+ runtime_ts: 0h0m0s953ms
- status: 3 - floorplan initialization - openroad
- runtime_s: 1.47
- runtime_ts: 0h0m1s468ms
+ runtime_s: 1.66
+ runtime_ts: 0h0m1s656ms
- status: 4 - ioplace - openroad
- runtime_s: 0.71
- runtime_ts: 0h0m0s714ms
+ runtime_s: 0.77
+ runtime_ts: 0h0m0s768ms
- status: 5 - tap/decap insertion - openroad
- runtime_s: 0.81
- runtime_ts: 0h0m0s806ms
+ runtime_s: 0.86
+ runtime_ts: 0h0m0s863ms
- status: 6 - pdn generation - openroad
- runtime_s: 1.91
- runtime_ts: 0h0m1s907ms
+ runtime_s: 2.0
+ runtime_ts: 0h0m2s1ms
- status: 7 - global placement - openroad
- runtime_s: 15.42
- runtime_ts: 0h0m15s419ms
+ runtime_s: 17.13
+ runtime_ts: 0h0m17s129ms
- status: 8 - resizer design optimizations - openroad
- runtime_s: 1.34
- runtime_ts: 0h0m1s345ms
+ runtime_s: 1.44
+ runtime_ts: 0h0m1s437ms
- status: 9 - detailed placement - openroad
- runtime_s: 0.98
- runtime_ts: 0h0m0s977ms
+ runtime_s: 1.14
+ runtime_ts: 0h0m1s137ms
- status: 10 - cts - openroad
- runtime_s: 30.52
- runtime_ts: 0h0m30s522ms
+ runtime_s: 33.01
+ runtime_ts: 0h0m33s14ms
- status: 11 - resizer timing optimizations - openroad
- runtime_s: 1.27
- runtime_ts: 0h0m1s274ms
+ runtime_s: 1.39
+ runtime_ts: 0h0m1s387ms
- status: 12 - resizer timing optimizations - openroad
runtime_s: 1.43
- runtime_ts: 0h0m1s427ms
+ runtime_ts: 0h0m1s433ms
- status: 14 - detailed placement - openroad
- runtime_s: 1.0
- runtime_ts: 0h0m0s998ms
-- status: 14 - diode insertion - openlane
- runtime_s: 1.09
- runtime_ts: 0h0m1s90ms
-- status: 15 - fill insertion - openroad
- runtime_s: 1.45
- runtime_ts: 0h0m1s453ms
-- status: 17 - write verilog - openroad
- runtime_s: 0.99
- runtime_ts: 0h0m0s993ms
-- status: 17 - global routing - openroad
- runtime_s: 1.08
- runtime_ts: 0h0m1s84ms
-- status: 18 - detailed_routing - openroad
- runtime_s: 31.16
- runtime_ts: 0h0m31s158ms
-- status: 19 - wire lengths - openlane
- runtime_s: 0.72
- runtime_ts: 0h0m0s720ms
-- status: 20 - parasitics extraction - openroad
- runtime_s: 1.15
- runtime_ts: 0h0m1s145ms
-- status: 21 - sta - openroad
- runtime_s: 2.87
- runtime_ts: 0h0m2s865ms
-- status: 22 - sta - openroad
- runtime_s: 1.27
- runtime_ts: 0h0m1s270ms
-- status: 23 - gdsii - magic
- runtime_s: 8.63
- runtime_ts: 0h0m8s634ms
-- status: 24 - spice extraction - magic
- runtime_s: 15.51
- runtime_ts: 0h0m15s506ms
-- status: 26 - write verilog - openroad
- runtime_s: 1.04
- runtime_ts: 0h0m1s42ms
-- status: 26 - write powered verilog - openlane
- runtime_s: 1.14
- runtime_ts: 0h0m1s141ms
-- status: 27 - lvs - netgen
runtime_s: 1.01
runtime_ts: 0h0m1s12ms
+- status: 14 - diode insertion - openlane
+ runtime_s: 1.1
+ runtime_ts: 0h0m1s102ms
+- status: 15 - fill insertion - openroad
+ runtime_s: 1.5
+ runtime_ts: 0h0m1s496ms
+- status: 17 - write verilog - openroad
+ runtime_s: 1.1
+ runtime_ts: 0h0m1s102ms
+- status: 17 - global routing - openroad
+ runtime_s: 1.21
+ runtime_ts: 0h0m1s205ms
+- status: 18 - detailed_routing - openroad
+ runtime_s: 39.6
+ runtime_ts: 0h0m39s595ms
+- status: 19 - wire lengths - openlane
+ runtime_s: 0.77
+ runtime_ts: 0h0m0s767ms
+- status: 20 - parasitics extraction - openroad
+ runtime_s: 1.31
+ runtime_ts: 0h0m1s312ms
+- status: 21 - sta - openroad
+ runtime_s: 3.05
+ runtime_ts: 0h0m3s48ms
+- status: 22 - sta - openroad
+ runtime_s: 1.29
+ runtime_ts: 0h0m1s294ms
+- status: 23 - gdsii - magic
+ runtime_s: 9.45
+ runtime_ts: 0h0m9s451ms
+- status: 24 - spice extraction - magic
+ runtime_s: 15.95
+ runtime_ts: 0h0m15s948ms
+- status: 26 - write verilog - openroad
+ runtime_s: 1.04
+ runtime_ts: 0h0m1s44ms
+- status: 26 - write powered verilog - openlane
+ runtime_s: 1.19
+ runtime_ts: 0h0m1s185ms
+- status: 27 - lvs - netgen
+ runtime_s: 1.14
+ runtime_ts: 0h0m1s140ms
- status: 28 - drc - magic
- runtime_s: 160.14
- runtime_ts: 0h2m40s137ms
+ runtime_s: 167.5
+ runtime_ts: 0h2m47s497ms
- status: 29 - antenna check - openroad
- runtime_s: 0.99
- runtime_ts: 0h0m0s991ms
+ runtime_s: 1.0
+ runtime_ts: 0h0m1s0ms
---
- status: routed
- runtime_s: 100.0
- runtime_ts: 0h1m40s0ms
+ runtime_s: 115.0
+ runtime_ts: 0h1m55s0ms
- status: flow completed
- runtime_s: 295.0
- runtime_ts: 0h4m55s0ms
+ runtime_s: 319.0
+ runtime_ts: 0h5m19s0ms
diff --git a/openlane/cntr_example/runs/cntr_example/tmp/12-cntr_example.sdc b/openlane/cntr_example/runs/cntr_example/tmp/12-cntr_example.sdc
index 557bdf5..e5794db 100644
--- a/openlane/cntr_example/runs/cntr_example/tmp/12-cntr_example.sdc
+++ b/openlane/cntr_example/runs/cntr_example/tmp/12-cntr_example.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Sat Dec 3 21:30:38 2022
+# Sun Dec 4 02:37:29 2022
###############################################################################
current_design cntr_example
###############################################################################
diff --git a/openlane/cntr_example/runs/cntr_example/tmp/cts/11-cntr_example.resized.sdc b/openlane/cntr_example/runs/cntr_example/tmp/cts/11-cntr_example.resized.sdc
index 59936a2..6494068 100644
--- a/openlane/cntr_example/runs/cntr_example/tmp/cts/11-cntr_example.resized.sdc
+++ b/openlane/cntr_example/runs/cntr_example/tmp/cts/11-cntr_example.resized.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Sat Dec 3 21:30:36 2022
+# Sun Dec 4 02:37:28 2022
###############################################################################
current_design cntr_example
###############################################################################
diff --git a/openlane/cntr_example/runs/cntr_example/tmp/floorplan/3-initial_fp.sdc b/openlane/cntr_example/runs/cntr_example/tmp/floorplan/3-initial_fp.sdc
index ad39987..24edbb7 100644
--- a/openlane/cntr_example/runs/cntr_example/tmp/floorplan/3-initial_fp.sdc
+++ b/openlane/cntr_example/runs/cntr_example/tmp/floorplan/3-initial_fp.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Sat Dec 3 21:29:42 2022
+# Sun Dec 4 02:36:28 2022
###############################################################################
current_design cntr_example
###############################################################################
diff --git a/openlane/cntr_example/runs/cntr_example/tmp/placement/8-resizer.sdc b/openlane/cntr_example/runs/cntr_example/tmp/placement/8-resizer.sdc
index 8ecf0e0..0590185 100644
--- a/openlane/cntr_example/runs/cntr_example/tmp/placement/8-resizer.sdc
+++ b/openlane/cntr_example/runs/cntr_example/tmp/placement/8-resizer.sdc
@@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
-# Sat Dec 3 21:30:03 2022
+# Sun Dec 4 02:36:52 2022
###############################################################################
current_design cntr_example
###############################################################################
diff --git a/openlane/cntr_example/runs/cntr_example/tmp/signoff/27-setup_file.lef.lvs b/openlane/cntr_example/runs/cntr_example/tmp/signoff/27-setup_file.lef.lvs
index 4fb8f45..8105d29 100644
--- a/openlane/cntr_example/runs/cntr_example/tmp/signoff/27-setup_file.lef.lvs
+++ b/openlane/cntr_example/runs/cntr_example/tmp/signoff/27-setup_file.lef.lvs
@@ -1 +1 @@
-lvs {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.spice cntr_example} {/home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/tmp/signoff/24-cntr_example.pnl.v cntr_example} /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/logs/signoff/27-cntr_example.lef.lvs.log -json
+lvs {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/cntr_example.spice cntr_example} {/home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/signoff/24-cntr_example.pnl.v cntr_example} /home/htf6ry/GF180PDK//gf180mcuC/libs.tech/netgen/gf180mcuC_setup.tcl /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/logs/signoff/27-cntr_example.lef.lvs.log -json
diff --git a/openlane/cntr_example/runs/cntr_example/tmp/signoff/gds_ptrs.mag b/openlane/cntr_example/runs/cntr_example/tmp/signoff/gds_ptrs.mag
index 915505a..b3ffae8 100644
--- a/openlane/cntr_example/runs/cntr_example/tmp/signoff/gds_ptrs.mag
+++ b/openlane/cntr_example/runs/cntr_example/tmp/signoff/gds_ptrs.mag
@@ -1,6 +1,6 @@
<< properties >>
string FIXED_BBOX 0 0 300000 300000
string GDS_END 8011482
-string GDS_FILE /home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/results/signoff/cntr_example.magic.gds
+string GDS_FILE /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/signoff/cntr_example.magic.gds
string GDS_START 105720
<< end >>
diff --git a/openlane/cntr_example/runs/cntr_example/warnings.log b/openlane/cntr_example/runs/cntr_example/warnings.log
index 6eebec7..e19fe47 100644
--- a/openlane/cntr_example/runs/cntr_example/warnings.log
+++ b/openlane/cntr_example/runs/cntr_example/warnings.log
@@ -1,3 +1,3 @@
[WARNING]: This PDK does not support the Circuit Validity Checker, skipping...
-[WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/22-rcx_sta.slew.rpt'.
-[WARNING]: There are max capacitance violations in the design at the typical corner. Please refer to '../home/htf6ry/gf180-demo/openlane/cntr_example/runs/22_12_03_16_29/reports/signoff/22-rcx_sta.slew.rpt'.
+[WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/22-rcx_sta.slew.rpt'.
+[WARNING]: There are max capacitance violations in the design at the typical corner. Please refer to '../home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/reports/signoff/22-rcx_sta.slew.rpt'.
