| OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO]: Setting RC values... |
| [INFO RSZ-0027] Inserted 1 input buffers. |
| [INFO RSZ-0028] Inserted 20 output buffers. |
| [INFO RSZ-0058] Using max wire length 22815um. |
| [INFO RSZ-0039] Resized 37 instances. |
| [INFO RSZ-0042] Inserted 18 tie gf180mcu_fd_sc_mcu7t5v0__tiel instances. |
| Placement Analysis |
| --------------------------------- |
| total displacement 241.6 u |
| average displacement 0.0 u |
| max displacement 9.5 u |
| original HPWL 60426.6 u |
| legalized HPWL 60417.9 u |
| delta HPWL 0 % |
| |
| [INFO DPL-0020] Mirrored 62 instances |
| [INFO DPL-0021] HPWL before 60417.9 u |
| [INFO DPL-0022] HPWL after 60307.8 u |
| [INFO DPL-0023] HPWL delta -0.2 % |
| Setting global connections for newly added cells... |
| Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.odb... |
| Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.nl.v... |
| Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.pnl.v... |
| Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.def... |
| Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.sdc... |
| min_report |
| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.40 1.14 1.14 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 6 0.05 net16 (net) |
| 0.40 0.01 1.15 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.60 0.44 1.59 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.01 _008_ (net) |
| 0.60 0.00 1.59 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 1.59 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.03 0.28 library hold time |
| 0.28 data required time |
| ----------------------------------------------------------------------------- |
| 0.28 data required time |
| -1.59 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.32 slack (MET) |
| |
| |
| Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.55 1.31 1.31 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 5 0.04 net21 (net) |
| 0.56 0.02 1.32 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.38 0.30 1.62 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _013_ (net) |
| 0.38 0.00 1.62 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 1.62 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.03 0.28 library hold time |
| 0.28 data required time |
| ----------------------------------------------------------------------------- |
| 0.28 data required time |
| -1.62 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.34 slack (MET) |
| |
| |
| Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.57 1.31 1.31 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 5 0.04 net6 (net) |
| 0.57 0.01 1.33 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.39 0.30 1.63 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _017_ (net) |
| 0.39 0.00 1.63 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 1.63 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.03 0.28 library hold time |
| 0.28 data required time |
| ----------------------------------------------------------------------------- |
| 0.28 data required time |
| -1.63 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.36 slack (MET) |
| |
| |
| Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.57 1.32 1.32 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 5 0.04 net10 (net) |
| 0.58 0.01 1.33 ^ _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.40 0.31 1.64 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _001_ (net) |
| 0.40 0.00 1.64 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 1.64 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.02 0.27 library hold time |
| 0.27 data required time |
| ----------------------------------------------------------------------------- |
| 0.27 data required time |
| -1.64 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.37 slack (MET) |
| |
| |
| Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.63 1.36 1.36 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 5 0.05 net13 (net) |
| 0.63 0.01 1.36 ^ _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.38 0.29 1.66 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _005_ (net) |
| 0.38 0.00 1.66 v _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 1.66 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.03 0.28 library hold time |
| 0.28 data required time |
| ----------------------------------------------------------------------------- |
| 0.28 data required time |
| -1.66 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.38 slack (MET) |
| |
| |
| min_report_end |
| max_report |
| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.14 0.04 13.04 ^ wb_rst_i (in) |
| 1 0.00 wb_rst_i (net) |
| 0.14 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.70 0.62 13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2 0.03 net1 (net) |
| 0.70 0.01 13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 0.66 0.68 14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 10 0.05 _021_ (net) |
| 0.66 0.00 14.35 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.31 0.30 14.65 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.01 _022_ (net) |
| 0.31 0.00 14.65 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.90 0.72 15.37 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _001_ (net) |
| 0.90 0.00 15.37 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 15.37 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| -0.47 64.28 library setup time |
| 64.28 data required time |
| ----------------------------------------------------------------------------- |
| 64.28 data required time |
| -15.37 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.91 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.14 0.04 13.04 ^ wb_rst_i (in) |
| 1 0.00 wb_rst_i (net) |
| 0.14 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.70 0.62 13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2 0.03 net1 (net) |
| 0.70 0.01 13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 0.66 0.68 14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 10 0.05 _021_ (net) |
| 0.66 0.00 14.35 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.30 0.28 14.63 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.00 _032_ (net) |
| 0.30 0.00 14.63 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.89 0.71 15.34 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _009_ (net) |
| 0.89 0.00 15.35 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 15.35 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| -0.47 64.28 library setup time |
| 64.28 data required time |
| ----------------------------------------------------------------------------- |
| 64.28 data required time |
| -15.35 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.93 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.14 0.04 13.04 ^ wb_rst_i (in) |
| 1 0.00 wb_rst_i (net) |
| 0.14 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.70 0.62 13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2 0.03 net1 (net) |
| 0.70 0.01 13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 0.66 0.68 14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 10 0.05 _021_ (net) |
| 0.66 0.00 14.35 ^ _086_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.29 0.28 14.63 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.00 _042_ (net) |
| 0.29 0.00 14.63 v _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.88 0.71 15.34 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _017_ (net) |
| 0.88 0.00 15.34 ^ _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 15.34 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| -0.47 64.28 library setup time |
| 64.28 data required time |
| ----------------------------------------------------------------------------- |
| 64.28 data required time |
| -15.34 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.94 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.14 0.04 13.04 ^ wb_rst_i (in) |
| 1 0.00 wb_rst_i (net) |
| 0.14 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.70 0.62 13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2 0.03 net1 (net) |
| 0.70 0.01 13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 0.66 0.68 14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 10 0.05 _021_ (net) |
| 0.66 0.00 14.35 ^ _077_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.28 0.28 14.63 v _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.00 _037_ (net) |
| 0.28 0.00 14.63 v _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.87 0.70 15.33 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _013_ (net) |
| 0.87 0.00 15.33 ^ _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 15.33 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| -0.47 64.28 library setup time |
| 64.28 data required time |
| ----------------------------------------------------------------------------- |
| 64.28 data required time |
| -15.33 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.95 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.14 0.04 13.04 ^ wb_rst_i (in) |
| 1 0.00 wb_rst_i (net) |
| 0.14 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.70 0.62 13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2 0.03 net1 (net) |
| 0.70 0.01 13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 0.66 0.68 14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 10 0.05 _021_ (net) |
| 0.66 0.00 14.35 ^ _059_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.30 0.28 14.63 v _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.00 _027_ (net) |
| 0.30 0.00 14.63 v _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.84 0.68 15.31 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _005_ (net) |
| 0.84 0.00 15.32 ^ _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 15.32 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| -0.47 64.28 library setup time |
| 64.28 data required time |
| ----------------------------------------------------------------------------- |
| 64.28 data required time |
| -15.32 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.96 slack (MET) |
| |
| |
| max_report_end |
| check_report |
| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 13.00 13.00 ^ input external delay |
| 0.14 0.04 13.04 ^ wb_rst_i (in) |
| 1 0.00 wb_rst_i (net) |
| 0.14 0.00 13.04 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 0.70 0.62 13.67 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2 0.03 net1 (net) |
| 0.70 0.01 13.67 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 0.66 0.68 14.35 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 10 0.05 _021_ (net) |
| 0.66 0.00 14.35 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.31 0.30 14.65 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.01 _022_ (net) |
| 0.31 0.00 14.65 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.90 0.72 15.37 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _001_ (net) |
| 0.90 0.00 15.37 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 15.37 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| 64.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| -0.47 64.28 library setup time |
| 64.28 data required time |
| ----------------------------------------------------------------------------- |
| 64.28 data required time |
| -15.37 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.91 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
| check_report_end |
| check_slew |
| |
| =========================================================================== |
| report_check_types -max_slew -max_cap -max_fanout -violators |
| ============================================================================ |
| |
| =========================================================================== |
| max slew violation count 0 |
| max fanout violation count 0 |
| max cap violation count 0 |
| ============================================================================ |
| check_slew_end |
| tns_report |
| |
| =========================================================================== |
| report_tns |
| ============================================================================ |
| tns 0.00 |
| tns_report_end |
| wns_report |
| |
| =========================================================================== |
| report_wns |
| ============================================================================ |
| wns 0.00 |
| wns_report_end |
| worst_slack |
| |
| =========================================================================== |
| report_worst_slack -max (Setup) |
| ============================================================================ |
| worst slack 48.91 |
| |
| =========================================================================== |
| report_worst_slack -min (Hold) |
| ============================================================================ |
| worst slack 1.32 |
| worst_slack_end |
| clock_skew |
| |
| =========================================================================== |
| report_clock_skew |
| ============================================================================ |
| Clock wb_clk_i |
| Latency CRPR Skew |
| _094_/CLK ^ |
| 0.23 |
| _094_/CLK ^ |
| 0.21 0.00 0.02 |
| |
| clock_skew_end |
| power_report |
| |
| =========================================================================== |
| report_power |
| ============================================================================ |
| Group Internal Switching Leakage Total |
| Power Power Power Power (Watts) |
| ---------------------------------------------------------------- |
| Sequential 7.08e-05 7.86e-06 1.98e-09 7.86e-05 73.8% |
| Combinational 9.21e-06 1.84e-05 3.24e-07 2.79e-05 26.2% |
| Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| ---------------------------------------------------------------- |
| Total 8.00e-05 2.62e-05 3.26e-07 1.07e-04 100.0% |
| 75.1% 24.6% 0.3% |
| power_report_end |
| area_report |
| |
| =========================================================================== |
| report_design_area |
| ============================================================================ |
| Design area 67257 u^2 3% utilization. |
| area_report_end |
| Setting global connections for newly added cells... |
| Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.odb... |
| Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.nl.v... |
| Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.pnl.v... |
| Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.def... |
| Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/placement/8-resizer.sdc... |
