| OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO]: Setting signal min routing layer to: Metal2 and clock min routing layer to Metal2. |
| [INFO]: Setting signal max routing layer to: Metal4 and clock max routing layer to Metal4. |
| -congestion_iterations 50 -verbose |
| [INFO GRT-0020] Min routing layer: Metal2 |
| [INFO GRT-0021] Max routing layer: Metal4 |
| [INFO GRT-0022] Global adjustment: 30% |
| [INFO GRT-0023] Grid origin: (0, 0) |
| [INFO GRT-0043] No OR_DEFAULT vias defined. |
| [INFO GRT-0088] Layer Metal1 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5450 |
| [INFO GRT-0088] Layer Metal2 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5800 |
| [INFO GRT-0088] Layer Metal3 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5800 |
| [INFO GRT-0088] Layer Metal4 Track-Pitch = 0.5600 line-2-Via Pitch: 0.5800 |
| [INFO GRT-0019] Found 4 clock nets. |
| [WARNING GRT-0036] Pin io_out[19] is outside die area. |
| [WARNING GRT-0036] Pin io_out[27] is outside die area. |
| [INFO GRT-0001] Minimum degree: 2 |
| [INFO GRT-0002] Maximum degree: 23 |
| [INFO GRT-0003] Macros: 0 |
| [INFO GRT-0004] Blockages: 0 |
| |
| [INFO GRT-0053] Routing resources analysis: |
| Routing Original Derated Resource |
| Layer Direction Resources Resources Reduction (%) |
| --------------------------------------------------------------- |
| Metal1 Horizontal 0 0 0.00% |
| Metal2 Vertical 443576 286032 35.52% |
| Metal3 Horizontal 443576 286032 35.52% |
| Metal4 Vertical 443576 283057 36.19% |
| --------------------------------------------------------------- |
| |
| [INFO GRT-0197] Via related to pin nodes: 697 |
| [INFO GRT-0198] Via related Steiner nodes: 25 |
| [INFO GRT-0199] Via filling finished. |
| [INFO GRT-0111] Final number of vias: 849 |
| [INFO GRT-0112] Final usage 3D: 10288 |
| |
| [INFO GRT-0096] Final congestion report: |
| Layer Resource Demand Usage (%) Max H / Max V / Total Overflow |
| --------------------------------------------------------------------------------------- |
| Metal1 0 0 0.00% 0 / 0 / 0 |
| Metal2 286032 3461 1.21% 0 / 0 / 0 |
| Metal3 286032 4213 1.47% 0 / 0 / 0 |
| Metal4 283057 67 0.02% 0 / 0 / 0 |
| --------------------------------------------------------------------------------------- |
| Total 855121 7741 0.91% 0 / 0 / 0 |
| |
| [INFO GRT-0018] Total wirelength: 69106 um |
| [INFO GRT-0014] Routed nets: 111 |
| Setting global connections for newly added cells... |
| Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/16-global.odb... |
| Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/16-global.def... |
| Writing routing guides to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/16-global.guide... |
| [INFO]: Setting RC values... |
| min_report |
| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.08 0.08 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.31 0.72 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.15 0.00 0.72 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.43 1.17 1.89 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 12 0.06 net16 (net) |
| 0.43 0.01 1.90 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.65 0.48 2.38 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.01 _008_ (net) |
| 0.65 0.00 2.38 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 2.38 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.09 0.09 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.34 0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.15 0.00 0.79 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.25 1.04 clock uncertainty |
| -0.08 0.97 clock reconvergence pessimism |
| 0.03 0.99 library hold time |
| 0.99 data required time |
| ----------------------------------------------------------------------------- |
| 0.99 data required time |
| -2.38 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.39 slack (MET) |
| |
| |
| Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.08 0.08 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.31 0.72 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.15 0.00 0.72 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.62 1.34 2.06 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 10 0.05 net21 (net) |
| 0.62 0.02 2.07 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.42 0.32 2.39 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 2 0.01 _013_ (net) |
| 0.42 0.00 2.40 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 2.40 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.09 0.09 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.34 0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.15 0.00 0.79 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.25 1.04 clock uncertainty |
| -0.08 0.97 clock reconvergence pessimism |
| 0.02 0.99 library hold time |
| 0.99 data required time |
| ----------------------------------------------------------------------------- |
| 0.99 data required time |
| -2.40 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.41 slack (MET) |
| |
| |
| Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.08 0.08 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.40 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.16 0.32 0.72 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.05 clknet_1_0__leaf_wb_clk_i (net) |
| 0.16 0.00 0.72 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.63 1.35 2.08 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 10 0.05 net6 (net) |
| 0.63 0.01 2.09 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.42 0.33 2.42 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 2 0.02 _017_ (net) |
| 0.42 0.00 2.42 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 2.42 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.09 0.09 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.45 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.16 0.35 0.80 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.05 clknet_1_0__leaf_wb_clk_i (net) |
| 0.16 0.00 0.80 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.25 1.05 clock uncertainty |
| -0.08 0.98 clock reconvergence pessimism |
| 0.02 0.99 library hold time |
| 0.99 data required time |
| ----------------------------------------------------------------------------- |
| 0.99 data required time |
| -2.42 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.43 slack (MET) |
| |
| |
| Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.08 0.08 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.31 0.72 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.15 0.00 0.72 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.64 1.35 2.07 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 10 0.05 net10 (net) |
| 0.64 0.01 2.09 ^ _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.43 0.33 2.42 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 2 0.02 _001_ (net) |
| 0.43 0.00 2.42 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 2.42 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.09 0.09 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.34 0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.15 0.00 0.79 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.25 1.04 clock uncertainty |
| -0.08 0.97 clock reconvergence pessimism |
| 0.01 0.98 library hold time |
| 0.98 data required time |
| ----------------------------------------------------------------------------- |
| 0.98 data required time |
| -2.42 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.44 slack (MET) |
| |
| |
| Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.08 0.08 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.31 0.72 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.15 0.00 0.72 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.39 1.07 1.79 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4 0.03 net8 (net) |
| 0.39 0.00 1.79 v _092_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 0.42 0.34 2.13 ^ _092_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 1 0.00 _046_ (net) |
| 0.42 0.00 2.13 ^ _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.35 0.30 2.43 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.01 _019_ (net) |
| 0.35 0.00 2.43 v _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.43 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.09 0.09 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.34 0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.15 0.00 0.79 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 1.04 clock uncertainty |
| -0.08 0.97 clock reconvergence pessimism |
| 0.02 0.99 library hold time |
| 0.99 data required time |
| ----------------------------------------------------------------------------- |
| 0.99 data required time |
| -2.43 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.44 slack (MET) |
| |
| |
| min_report_end |
| max_report |
| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[16] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.09 0.09 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.45 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.16 0.35 0.80 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.05 clknet_1_0__leaf_wb_clk_i (net) |
| 0.16 0.00 0.80 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.79 1.59 2.39 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 12 0.06 net9 (net) |
| 0.79 0.03 2.42 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 0.48 0.73 3.15 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 1 0.07 io_out[16] (net) |
| 0.48 0.00 3.15 ^ io_out[16] (out) |
| 3.15 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -3.15 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.60 slack (MET) |
| |
| |
| Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[12] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.09 0.09 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.34 0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.15 0.00 0.79 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.80 1.59 2.39 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 12 0.07 net5 (net) |
| 0.80 0.03 2.41 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 0.48 0.73 3.14 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 1 0.07 io_out[12] (net) |
| 0.48 0.00 3.14 ^ io_out[12] (out) |
| 3.14 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -3.14 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.61 slack (MET) |
| |
| |
| Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[8] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.09 0.09 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.45 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.16 0.35 0.80 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.05 clknet_1_0__leaf_wb_clk_i (net) |
| 0.16 0.00 0.80 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.74 1.56 2.36 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 12 0.06 net20 (net) |
| 0.74 0.03 2.39 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 0.48 0.72 3.11 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 1 0.07 io_out[8] (net) |
| 0.48 0.00 3.11 ^ io_out[8] (out) |
| 3.11 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -3.11 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.64 slack (MET) |
| |
| |
| Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[3] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.09 0.09 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.34 0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.15 0.00 0.79 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.88 1.55 2.34 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4 0.04 net15 (net) |
| 0.88 0.01 2.35 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 0.48 0.74 3.09 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 1 0.07 io_out[3] (net) |
| 0.48 0.00 3.10 ^ io_out[3] (out) |
| 3.10 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -3.10 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.65 slack (MET) |
| |
| |
| Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[4] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.09 0.09 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.45 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.34 0.79 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.04 clknet_1_1__leaf_wb_clk_i (net) |
| 0.15 0.00 0.79 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.73 1.55 2.34 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 12 0.06 net16 (net) |
| 0.73 0.02 2.37 ^ output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 0.48 0.72 3.08 ^ output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 1 0.07 io_out[4] (net) |
| 0.48 0.00 3.09 ^ io_out[4] (out) |
| 3.09 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -3.09 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.66 slack (MET) |
| |
| |
| max_report_end |
| check_report |
| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[16] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.19 0.09 0.09 ^ wb_clk_i (in) |
| 2 0.02 wb_clk_i (net) |
| 0.19 0.00 0.09 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.45 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.45 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.16 0.35 0.80 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.05 clknet_1_0__leaf_wb_clk_i (net) |
| 0.16 0.00 0.80 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.79 1.59 2.39 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 12 0.06 net9 (net) |
| 0.79 0.03 2.42 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 0.48 0.73 3.15 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 1 0.07 io_out[16] (net) |
| 0.48 0.00 3.15 ^ io_out[16] (out) |
| 3.15 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -3.15 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.60 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
| check_report_end |
| check_slew |
| |
| =========================================================================== |
| report_check_types -max_slew -max_cap -max_fanout -violators |
| ============================================================================ |
| |
| =========================================================================== |
| max slew violation count 0 |
| max fanout violation count 0 |
| max cap violation count 0 |
| ============================================================================ |
| check_slew_end |
| tns_report |
| |
| =========================================================================== |
| report_tns |
| ============================================================================ |
| tns 0.00 |
| tns_report_end |
| wns_report |
| |
| =========================================================================== |
| report_wns |
| ============================================================================ |
| wns 0.00 |
| wns_report_end |
| worst_slack |
| |
| =========================================================================== |
| report_worst_slack -max (Setup) |
| ============================================================================ |
| worst slack 48.60 |
| |
| =========================================================================== |
| report_worst_slack -min (Hold) |
| ============================================================================ |
| worst slack 1.39 |
| worst_slack_end |
| clock_skew |
| |
| =========================================================================== |
| report_clock_skew |
| ============================================================================ |
| Clock wb_clk_i |
| Latency CRPR Skew |
| _094_/CLK ^ |
| 0.80 |
| _097_/CLK ^ |
| 0.72 -0.04 0.04 |
| |
| clock_skew_end |
| power_report |
| |
| =========================================================================== |
| report_power |
| ============================================================================ |
| Group Internal Switching Leakage Total |
| Power Power Power Power (Watts) |
| ---------------------------------------------------------------- |
| Sequential 7.08e-05 8.74e-06 1.98e-09 7.95e-05 41.6% |
| Combinational 6.84e-05 4.20e-05 1.28e-06 1.12e-04 58.4% |
| Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| ---------------------------------------------------------------- |
| Total 1.39e-04 5.07e-05 1.28e-06 1.91e-04 100.0% |
| 72.8% 26.5% 0.7% |
| power_report_end |
| area_report |
| |
| =========================================================================== |
| report_design_area |
| ============================================================================ |
| Design area 68288 u^2 3% utilization. |
| area_report_end |
| Setting global connections for newly added cells... |
| Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/16-global.odb... |
| Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/16-global.def... |
| Writing routing guides to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/routing/16-global.guide... |
