Google Git
Sign in
foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-020 / 51b79e39caef2eb24780a74a0232c46e5411a1a3 / . / openlane / cntr_example / runs / cntr_example / logs / signoff / 21-rcx_mcsta.nom.log
blob: c6332b1b50079d009cb0b1ea6ab20f5ea1feef71 [file] [log] [blame]
OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
min_report
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
======================= Slowest Corner ===================================
Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.44 8.89 12.91 v _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.22 net6 (net)
5.45 0.06 12.97 v _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1.91 4.04 17.01 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _042_ (net)
1.91 0.00 17.01 ^ _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
6.07 4.35 21.37 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.08 _017_ (net)
6.07 0.01 21.38 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
21.38 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.69 clock uncertainty
-0.42 4.27 clock reconvergence pessimism
-1.19 3.07 library hold time
3.07 data required time
-----------------------------------------------------------------------------
3.07 data required time
-21.38 data arrival time
-----------------------------------------------------------------------------
18.30 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.45 8.33 12.34 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.11 net7 (net)
5.45 0.02 12.37 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
4.11 5.02 17.39 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.01 _043_ (net)
4.11 0.00 17.39 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
6.85 5.56 22.95 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.10 _018_ (net)
6.85 0.02 22.97 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
22.97 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 4.69 clock uncertainty
-0.42 4.27 clock reconvergence pessimism
-1.57 2.69 library hold time
2.69 data required time
-----------------------------------------------------------------------------
2.69 data required time
-22.97 data arrival time
-----------------------------------------------------------------------------
20.27 slack (MET)
Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 3.90 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.31 9.89 13.79 v _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.17 net15 (net)
8.31 0.04 13.83 v _065_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2.79 4.83 18.67 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _031_ (net)
2.79 0.00 18.67 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
6.27 4.77 23.44 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.09 _007_ (net)
6.27 0.02 23.46 v _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
23.46 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 4.56 clock uncertainty
-0.41 4.15 clock reconvergence pessimism
-1.47 2.69 library hold time
2.69 data required time
-----------------------------------------------------------------------------
2.69 data required time
-23.46 data arrival time
-----------------------------------------------------------------------------
20.77 slack (MET)
Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 3.90 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.03 8.59 12.50 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.20 net21 (net)
5.03 0.07 12.56 v _077_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1.69 3.60 16.16 ^ _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.00 _037_ (net)
1.69 0.00 16.16 ^ _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
10.35 6.71 22.87 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.13 _013_ (net)
10.35 0.04 22.91 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
22.91 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.56 clock uncertainty
-0.41 4.15 clock reconvergence pessimism
-2.35 1.80 library hold time
1.80 data required time
-----------------------------------------------------------------------------
1.80 data required time
-22.91 data arrival time
-----------------------------------------------------------------------------
21.11 slack (MET)
Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.52 10.07 14.09 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.17 net18 (net)
8.52 0.04 14.13 v _070_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
3.55 5.50 19.63 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _033_ (net)
3.55 0.00 19.63 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
9.40 6.79 26.42 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.13 _010_ (net)
9.40 0.03 26.45 v _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
26.45 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 4.69 clock uncertainty
-0.42 4.27 clock reconvergence pessimism
-2.27 2.00 library hold time
2.00 data required time
-----------------------------------------------------------------------------
2.00 data required time
-26.45 data arrival time
-----------------------------------------------------------------------------
24.45 slack (MET)
Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
7.92 10.30 14.32 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.32 net11 (net)
7.93 0.10 14.41 v _052_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
4.62 6.13 20.54 ^ _052_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.02 _023_ (net)
4.62 0.00 20.54 ^ _055_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
8.06 6.47 27.01 v _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.12 _002_ (net)
8.06 0.03 27.04 v _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
27.04 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.69 clock uncertainty
-0.42 4.27 clock reconvergence pessimism
-1.73 2.54 library hold time
2.54 data required time
-----------------------------------------------------------------------------
2.54 data required time
-27.04 data arrival time
-----------------------------------------------------------------------------
24.50 slack (MET)
Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.77 9.08 13.10 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.23 net2 (net)
5.77 0.04 13.14 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1.94 4.21 17.35 ^ _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _027_ (net)
1.94 0.00 17.35 ^ _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
14.19 9.01 26.36 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.19 _005_ (net)
14.19 0.04 26.40 v _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
26.40 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.57 clock uncertainty
-0.24 4.33 clock reconvergence pessimism
-3.24 1.09 library hold time
1.09 data required time
-----------------------------------------------------------------------------
1.09 data required time
-26.40 data arrival time
-----------------------------------------------------------------------------
25.31 slack (MET)
Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
14.64 14.99 19.01 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.23 net2 (net)
14.64 0.04 19.05 ^ _058_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
6.62 9.20 28.25 v _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.09 _004_ (net)
6.62 0.02 28.27 v _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
28.27 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.69 clock uncertainty
-0.42 4.27 clock reconvergence pessimism
-1.35 2.92 library hold time
2.92 data required time
-----------------------------------------------------------------------------
2.92 data required time
-28.27 data arrival time
-----------------------------------------------------------------------------
25.35 slack (MET)
Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 3.90 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.03 8.59 12.50 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.20 net21 (net)
5.03 0.06 12.56 v _079_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
4.01 4.81 17.37 ^ _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.01 _038_ (net)
4.01 0.00 17.37 ^ _082_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
13.20 9.16 26.54 v _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _014_ (net)
13.20 0.06 26.59 v _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
26.59 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.56 clock uncertainty
-0.41 4.15 clock reconvergence pessimism
-3.02 1.14 library hold time
1.14 data required time
-----------------------------------------------------------------------------
1.14 data required time
-26.59 data arrival time
-----------------------------------------------------------------------------
25.46 slack (MET)
Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4.94 8.60 12.62 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.20 net14 (net)
4.94 0.05 12.67 v _061_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
4.66 5.16 17.82 ^ _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.02 _028_ (net)
4.66 0.00 17.82 ^ _064_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
12.85 9.28 27.11 v _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _006_ (net)
12.85 0.04 27.15 v _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
27.15 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.69 clock uncertainty
-0.42 4.27 clock reconvergence pessimism
-2.89 1.38 library hold time
1.38 data required time
-----------------------------------------------------------------------------
1.38 data required time
-27.15 data arrival time
-----------------------------------------------------------------------------
25.77 slack (MET)
Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4.39 8.28 12.30 v _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.17 net4 (net)
4.39 0.05 12.35 v _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
4.21 4.29 16.63 ^ _083_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2 0.01 _041_ (net)
4.21 0.00 16.63 ^ _084_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
14.71 10.69 27.32 v _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.23 _015_ (net)
14.71 0.07 27.39 v _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
27.39 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.69 clock uncertainty
-0.42 4.27 clock reconvergence pessimism
-3.30 0.96 library hold time
0.96 data required time
-----------------------------------------------------------------------------
0.96 data required time
-27.39 data arrival time
-----------------------------------------------------------------------------
26.43 slack (MET)
Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 3.90 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
11.47 11.70 15.61 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net8 (net)
11.47 0.04 15.64 v _092_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
4.49 7.14 22.78 ^ _092_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _046_ (net)
4.49 0.00 22.78 ^ _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
9.32 7.33 30.11 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _019_ (net)
9.32 0.03 30.14 v _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
30.14 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 4.57 clock uncertainty
-0.41 4.15 clock reconvergence pessimism
-2.30 1.86 library hold time
1.86 data required time
-----------------------------------------------------------------------------
1.86 data required time
-30.14 data arrival time
-----------------------------------------------------------------------------
28.28 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 v input external delay
0.41 0.14 13.14 v wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.41 0.00 13.14 v input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
5.89 5.27 18.41 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
5.89 0.02 18.43 v _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
7.49 7.06 25.49 ^ _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.17 _020_ (net)
7.49 0.03 25.52 ^ _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
6.15 6.41 31.93 v _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.08 _016_ (net)
6.15 0.01 31.94 v _110_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
31.94 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.57 clock uncertainty
0.00 4.57 clock reconvergence pessimism
-1.27 3.30 library hold time
3.30 data required time
-----------------------------------------------------------------------------
3.30 data required time
-31.94 data arrival time
-----------------------------------------------------------------------------
28.64 slack (MET)
Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 3.90 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
7.80 10.12 14.03 v _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.32 net12 (net)
7.80 0.11 14.13 v _056_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
6.66 7.08 21.21 ^ _056_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2 0.02 _026_ (net)
6.66 0.00 21.21 ^ _057_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
10.90 9.21 30.42 v _057_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.16 _003_ (net)
10.90 0.05 30.47 v _097_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
30.47 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.56 clock uncertainty
-0.41 4.15 clock reconvergence pessimism
-2.48 1.67 library hold time
1.67 data required time
-----------------------------------------------------------------------------
1.67 data required time
-30.47 data arrival time
-----------------------------------------------------------------------------
28.79 slack (MET)
Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[11] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4.39 8.28 12.30 v _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.17 net4 (net)
4.39 0.03 12.33 v output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.80 4.37 16.71 v output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[11] (net)
1.80 0.00 16.71 v io_out[11] (out)
16.71 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-16.71 data arrival time
-----------------------------------------------------------------------------
29.46 slack (MET)
Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
9.63 10.70 14.72 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net19 (net)
9.63 0.04 14.76 v _074_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
4.72 6.66 21.42 ^ _074_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _036_ (net)
4.72 0.00 21.42 ^ _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
12.33 9.37 30.79 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _011_ (net)
12.33 0.05 30.84 v _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
30.84 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 4.69 clock uncertainty
-0.42 4.27 clock reconvergence pessimism
-2.99 1.28 library hold time
1.28 data required time
-----------------------------------------------------------------------------
1.28 data required time
-30.84 data arrival time
-----------------------------------------------------------------------------
29.56 slack (MET)
Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[9] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 3.90 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.03 8.59 12.50 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.20 net21 (net)
5.03 0.04 12.54 v output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.81 4.63 17.17 v output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[9] (net)
1.81 0.00 17.17 v io_out[9] (out)
17.17 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-17.17 data arrival time
-----------------------------------------------------------------------------
29.92 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[14] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.45 8.33 12.34 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.11 net7 (net)
5.45 0.02 12.37 v output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.83 4.82 17.18 v output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[14] (net)
1.83 0.00 17.19 v io_out[14] (out)
17.19 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-17.19 data arrival time
-----------------------------------------------------------------------------
29.94 slack (MET)
Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[2] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4.94 8.60 12.62 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.20 net14 (net)
4.94 0.07 12.69 v output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.81 4.60 17.29 v output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[2] (net)
1.81 0.00 17.29 v io_out[2] (out)
17.29 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-17.29 data arrival time
-----------------------------------------------------------------------------
30.04 slack (MET)
Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
9.92 11.40 15.42 v _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.41 net17 (net)
9.92 0.13 15.55 v _068_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1.95 5.43 20.97 ^ _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _032_ (net)
1.95 0.00 20.97 ^ _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
15.90 9.98 30.95 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.21 _009_ (net)
15.90 0.05 31.01 v _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
31.01 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.69 clock uncertainty
-0.42 4.27 clock reconvergence pessimism
-3.56 0.71 library hold time
0.71 data required time
-----------------------------------------------------------------------------
0.71 data required time
-31.01 data arrival time
-----------------------------------------------------------------------------
30.30 slack (MET)
Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[13] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.44 8.89 12.91 v _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.22 net6 (net)
5.45 0.07 12.98 v output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.81 4.81 17.79 v output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[13] (net)
1.81 0.00 17.79 v io_out[13] (out)
17.79 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-17.79 data arrival time
-----------------------------------------------------------------------------
30.54 slack (MET)
Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.77 9.08 13.10 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.23 net2 (net)
5.77 0.02 13.12 v output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.83 4.94 18.06 v output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[0] (net)
1.83 0.00 18.06 v io_out[0] (out)
18.06 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-18.06 data arrival time
-----------------------------------------------------------------------------
30.81 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 v input external delay
0.41 0.14 13.14 v wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.41 0.00 13.14 v input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
5.89 5.27 18.41 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
5.89 0.02 18.43 v _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
7.49 7.06 25.49 ^ _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.17 _020_ (net)
7.49 0.03 25.52 ^ _067_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
9.43 8.58 34.10 v _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _008_ (net)
9.43 0.02 34.12 v _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
34.12 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.57 clock uncertainty
0.00 4.57 clock reconvergence pessimism
-2.13 2.43 library hold time
2.43 data required time
-----------------------------------------------------------------------------
2.43 data required time
-34.12 data arrival time
-----------------------------------------------------------------------------
31.69 slack (MET)
Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
8.84 10.81 14.83 v _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.36 net9 (net)
8.84 0.12 14.95 v _050_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
3.13 6.89 21.83 ^ _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
2 0.02 _022_ (net)
3.13 0.00 21.84 ^ _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
16.97 11.05 32.88 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.22 _001_ (net)
16.97 0.06 32.94 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
32.94 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.56 clock uncertainty
-0.24 4.33 clock reconvergence pessimism
-3.83 0.50 library hold time
0.50 data required time
-----------------------------------------------------------------------------
0.50 data required time
-32.94 data arrival time
-----------------------------------------------------------------------------
32.44 slack (MET)
Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[3] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 3.90 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.31 9.89 13.79 v _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.17 net15 (net)
8.31 0.05 13.85 v output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.87 5.85 19.70 v output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[3] (net)
1.87 0.00 19.70 v io_out[3] (out)
19.70 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-19.70 data arrival time
-----------------------------------------------------------------------------
32.45 slack (MET)
Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[19] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 3.90 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
7.80 10.12 14.03 v _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.32 net12 (net)
7.81 0.17 14.19 v output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.87 5.68 19.88 v output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[19] (net)
1.87 0.00 19.88 v io_out[19] (out)
19.88 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-19.88 data arrival time
-----------------------------------------------------------------------------
32.63 slack (MET)
Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[6] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
8.52 10.07 14.09 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.17 net18 (net)
8.52 0.02 14.11 v output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.87 5.92 20.03 v output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[6] (net)
1.87 0.00 20.03 v io_out[6] (out)
20.03 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-20.03 data arrival time
-----------------------------------------------------------------------------
32.78 slack (MET)
Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[18] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
7.92 10.30 14.32 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.32 net11 (net)
7.93 0.13 14.44 v output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.85 5.71 20.16 v output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[18] (net)
1.85 0.00 20.16 v io_out[18] (out)
20.16 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-20.16 data arrival time
-----------------------------------------------------------------------------
32.91 slack (MET)
Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[16] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
8.84 10.81 14.83 v _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.36 net9 (net)
8.84 0.14 14.97 v output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.87 6.03 21.00 v output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[16] (net)
1.87 0.00 21.00 v io_out[16] (out)
21.00 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-21.00 data arrival time
-----------------------------------------------------------------------------
33.75 slack (MET)
Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[7] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
9.63 10.70 14.72 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net19 (net)
9.63 0.03 14.75 v output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.89 6.31 21.06 v output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[7] (net)
1.89 0.00 21.07 v io_out[7] (out)
21.07 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-21.07 data arrival time
-----------------------------------------------------------------------------
33.82 slack (MET)
Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[8] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
9.12 10.97 14.99 v _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.37 net20 (net)
9.13 0.15 15.14 v output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.88 6.14 21.28 v output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[8] (net)
1.88 0.00 21.28 v io_out[8] (out)
21.28 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-21.28 data arrival time
-----------------------------------------------------------------------------
34.03 slack (MET)
Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 4.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.02 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
9.92 11.40 15.42 v _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.41 net17 (net)
9.93 0.18 15.61 v output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.91 6.40 22.01 v output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[5] (net)
1.91 0.00 22.01 v io_out[5] (out)
22.01 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-22.01 data arrival time
-----------------------------------------------------------------------------
34.76 slack (MET)
Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[15] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 3.90 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
11.47 11.70 15.61 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net8 (net)
11.47 0.00 15.61 v output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.93 6.86 22.47 v output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[15] (net)
1.93 0.00 22.47 v io_out[15] (out)
22.47 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-22.47 data arrival time
-----------------------------------------------------------------------------
35.22 slack (MET)
Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[10] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 3.90 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10.91 11.93 15.83 v _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.45 net3 (net)
10.91 0.17 16.00 v output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.94 6.71 22.71 v output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[10] (net)
1.94 0.00 22.71 v io_out[10] (out)
22.71 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-22.71 data arrival time
-----------------------------------------------------------------------------
35.46 slack (MET)
Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[12] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 3.90 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
11.32 12.15 16.06 v _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.46 net5 (net)
11.33 0.21 16.26 v output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.93 6.82 23.08 v output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[12] (net)
1.93 0.00 23.08 v io_out[12] (out)
23.08 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-23.08 data arrival time
-----------------------------------------------------------------------------
35.83 slack (MET)
Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[4] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 3.90 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
11.51 12.26 16.16 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net16 (net)
11.52 0.20 16.36 v output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.92 6.87 23.23 v output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[4] (net)
1.92 0.00 23.23 v io_out[4] (out)
23.23 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-23.23 data arrival time
-----------------------------------------------------------------------------
35.98 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 v input external delay
0.41 0.14 13.14 v wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.41 0.00 13.14 v input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
5.89 5.27 18.41 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
5.89 0.02 18.43 v _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
7.49 7.06 25.49 ^ _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.17 _020_ (net)
7.49 0.02 25.52 ^ _048_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
14.79 12.08 37.60 v _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.23 _000_ (net)
14.79 0.05 37.65 v _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
37.65 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.69 clock uncertainty
0.00 4.69 clock reconvergence pessimism
-3.32 1.37 library hold time
1.37 data required time
-----------------------------------------------------------------------------
1.37 data required time
-37.65 data arrival time
-----------------------------------------------------------------------------
36.27 slack (MET)
Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 3.90 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12.75 12.99 16.90 v _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.52 net13 (net)
12.75 0.06 16.96 v output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.96 7.24 24.20 v output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[1] (net)
1.96 0.00 24.20 v io_out[1] (out)
24.20 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-24.20 data arrival time
-----------------------------------------------------------------------------
36.95 slack (MET)
Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[17] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.49 0.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 2.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 3.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 3.90 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12.80 13.00 16.90 v _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.53 net10 (net)
12.81 0.19 17.09 v output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1.99 7.28 24.38 v output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[17] (net)
1.99 0.00 24.38 v io_out[17] (out)
24.38 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-24.38 data arrival time
-----------------------------------------------------------------------------
37.13 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 v input external delay
0.41 0.14 13.14 v wb_rst_i (in)
2 0.01 wb_rst_i (net)
0.41 0.00 13.14 v input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
5.89 5.27 18.41 v input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
5.89 0.02 18.43 v _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
7.49 7.06 25.49 ^ _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.17 _020_ (net)
7.49 0.02 25.51 ^ _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
27.34 20.23 45.74 v _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.43 _012_ (net)
27.34 0.10 45.85 v _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
45.85 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 4.69 clock uncertainty
0.00 4.69 clock reconvergence pessimism
-5.89 -1.20 library hold time
-1.20 data required time
-----------------------------------------------------------------------------
-1.20 data required time
-45.85 data arrival time
-----------------------------------------------------------------------------
47.05 slack (MET)
======================= Typical Corner ===================================
Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.35 1.72 2.49 v _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.22 net6 (net)
1.36 0.06 2.55 v _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.47 0.58 3.13 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _042_ (net)
0.47 0.00 3.13 ^ _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1.55 1.04 4.17 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.08 _017_ (net)
1.55 0.01 4.19 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4.19 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.10 clock uncertainty
-0.08 1.02 clock reconvergence pessimism
-0.29 0.73 library hold time
0.73 data required time
-----------------------------------------------------------------------------
0.73 data required time
-4.19 data arrival time
-----------------------------------------------------------------------------
3.46 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.36 1.66 2.43 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.11 net7 (net)
1.36 0.03 2.46 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.81 0.74 3.19 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.02 _043_ (net)
0.81 0.00 3.19 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.70 1.19 4.38 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.10 _018_ (net)
1.70 0.02 4.40 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.40 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.10 clock uncertainty
-0.08 1.02 clock reconvergence pessimism
-0.35 0.67 library hold time
0.67 data required time
-----------------------------------------------------------------------------
0.67 data required time
-4.40 data arrival time
-----------------------------------------------------------------------------
3.73 slack (MET)
Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.44 1.79 2.56 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.23 net2 (net)
1.44 0.04 2.60 v _058_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.10 2.67 5.27 ^ _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.09 _004_ (net)
4.10 0.02 5.29 ^ _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.29 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.10 clock uncertainty
-0.08 1.02 clock reconvergence pessimism
0.30 1.32 library hold time
1.32 data required time
-----------------------------------------------------------------------------
1.32 data required time
-5.29 data arrival time
-----------------------------------------------------------------------------
3.97 slack (MET)
Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.08 2.05 2.81 v _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.17 net15 (net)
2.08 0.04 2.84 v _065_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.47 0.78 3.63 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _031_ (net)
0.47 0.00 3.63 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.57 1.05 4.68 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.09 _007_ (net)
1.57 0.02 4.70 v _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.70 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.08 clock uncertainty
-0.08 1.00 clock reconvergence pessimism
-0.33 0.68 library hold time
0.68 data required time
-----------------------------------------------------------------------------
0.68 data required time
-4.70 data arrival time
-----------------------------------------------------------------------------
4.02 slack (MET)
Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.24 1.65 2.41 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.20 net21 (net)
1.25 0.07 2.47 v _077_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.44 0.51 2.98 ^ _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _037_ (net)
0.44 0.00 2.98 ^ _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2.61 1.64 4.63 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.13 _013_ (net)
2.61 0.04 4.66 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4.66 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.08 clock uncertainty
-0.08 1.00 clock reconvergence pessimism
-0.56 0.44 library hold time
0.44 data required time
-----------------------------------------------------------------------------
0.44 data required time
-4.66 data arrival time
-----------------------------------------------------------------------------
4.22 slack (MET)
Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.97 2.05 2.83 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.32 net11 (net)
1.99 0.10 2.92 v _052_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.95 0.88 3.81 ^ _052_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.02 _023_ (net)
0.95 0.00 3.81 ^ _055_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.01 1.40 5.21 v _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.12 _002_ (net)
2.01 0.03 5.24 v _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.24 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.10 clock uncertainty
-0.08 1.02 clock reconvergence pessimism
-0.41 0.62 library hold time
0.62 data required time
-----------------------------------------------------------------------------
0.62 data required time
-5.24 data arrival time
-----------------------------------------------------------------------------
4.62 slack (MET)
Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.13 2.09 2.87 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.17 net18 (net)
2.13 0.04 2.91 v _070_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.80 0.76 3.67 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _033_ (net)
0.80 0.00 3.67 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.33 1.55 5.22 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.13 _010_ (net)
2.34 0.03 5.25 v _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.25 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.86 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.11 clock uncertainty
-0.08 1.02 clock reconvergence pessimism
-0.52 0.51 library hold time
0.51 data required time
-----------------------------------------------------------------------------
0.51 data required time
-5.25 data arrival time
-----------------------------------------------------------------------------
4.75 slack (MET)
Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.83 2.50 3.25 v _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net5 (net)
2.84 0.10 3.36 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.75 2.90 6.25 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.08 _016_ (net)
3.75 0.01 6.27 ^ _110_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6.27 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.08 clock uncertainty
-0.08 1.00 clock reconvergence pessimism
0.25 1.26 library hold time
1.26 data required time
-----------------------------------------------------------------------------
1.26 data required time
-6.27 data arrival time
-----------------------------------------------------------------------------
5.01 slack (MET)
Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.22 1.65 2.42 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.20 net14 (net)
1.22 0.05 2.47 v _061_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.86 0.76 3.23 ^ _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.02 _028_ (net)
0.86 0.00 3.23 ^ _064_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.24 2.09 5.32 v _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _006_ (net)
3.24 0.04 5.36 v _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.36 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.10 clock uncertainty
-0.08 1.02 clock reconvergence pessimism
-0.70 0.32 library hold time
0.32 data required time
-----------------------------------------------------------------------------
0.32 data required time
-5.36 data arrival time
-----------------------------------------------------------------------------
5.04 slack (MET)
Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.24 1.65 2.41 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.20 net21 (net)
1.25 0.06 2.47 v _079_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.84 0.79 3.26 ^ _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.01 _038_ (net)
0.84 0.00 3.26 ^ _082_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.29 2.10 5.36 v _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _014_ (net)
3.30 0.06 5.42 v _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.42 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.08 clock uncertainty
-0.08 1.00 clock reconvergence pessimism
-0.72 0.28 library hold time
0.28 data required time
-----------------------------------------------------------------------------
0.28 data required time
-5.42 data arrival time
-----------------------------------------------------------------------------
5.14 slack (MET)
Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.44 1.79 2.56 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.23 net2 (net)
1.44 0.04 2.60 v _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.48 0.68 3.28 ^ _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _027_ (net)
0.48 0.00 3.28 ^ _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
3.58 2.22 5.50 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.19 _005_ (net)
3.59 0.04 5.54 v _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.54 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.08 clock uncertainty
-0.05 1.04 clock reconvergence pessimism
-0.78 0.25 library hold time
0.25 data required time
-----------------------------------------------------------------------------
0.25 data required time
-5.54 data arrival time
-----------------------------------------------------------------------------
5.28 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.36 1.66 2.43 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.11 net7 (net)
1.36 0.03 2.46 v _089_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
1.06 1.02 3.47 ^ _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
4 0.03 _044_ (net)
1.06 0.00 3.47 ^ _092_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.74 0.72 4.19 ^ _092_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _046_ (net)
0.74 0.00 4.19 ^ _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.38 1.59 5.78 v _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _019_ (net)
2.38 0.03 5.81 v _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.81 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.08 clock uncertainty
-0.05 1.04 clock reconvergence pessimism
-0.53 0.51 library hold time
0.51 data required time
-----------------------------------------------------------------------------
0.51 data required time
-5.81 data arrival time
-----------------------------------------------------------------------------
5.30 slack (MET)
Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.08 1.58 2.35 v _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.17 net4 (net)
1.09 0.05 2.39 v _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.69 0.69 3.09 ^ _083_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2 0.01 _041_ (net)
0.69 0.00 3.09 ^ _084_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.88 2.43 5.51 v _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.23 _015_ (net)
3.89 0.07 5.59 v _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.59 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.10 clock uncertainty
-0.08 1.02 clock reconvergence pessimism
-0.85 0.18 library hold time
0.18 data required time
-----------------------------------------------------------------------------
0.18 data required time
-5.59 data arrival time
-----------------------------------------------------------------------------
5.41 slack (MET)
Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.93 1.99 2.74 v _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.32 net12 (net)
1.95 0.11 2.85 v _056_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1.08 1.15 4.00 ^ _056_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2 0.02 _026_ (net)
1.08 0.00 4.00 ^ _057_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.82 1.92 5.92 v _057_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.16 _003_ (net)
2.82 0.05 5.96 v _097_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.96 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.08 clock uncertainty
-0.08 1.00 clock reconvergence pessimism
-0.61 0.39 library hold time
0.39 data required time
-----------------------------------------------------------------------------
0.39 data required time
-5.96 data arrival time
-----------------------------------------------------------------------------
5.57 slack (MET)
Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.40 2.25 3.03 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net19 (net)
2.41 0.04 3.07 v _074_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.78 1.08 4.14 ^ _074_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _036_ (net)
0.78 0.00 4.14 ^ _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.23 2.08 6.22 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _011_ (net)
3.23 0.05 6.27 v _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6.27 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 1.10 clock uncertainty
-0.08 1.02 clock reconvergence pessimism
-0.73 0.29 library hold time
0.29 data required time
-----------------------------------------------------------------------------
0.29 data required time
-6.27 data arrival time
-----------------------------------------------------------------------------
5.98 slack (MET)
Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.88 2.52 3.27 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net16 (net)
2.89 0.10 3.37 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
6.14 4.21 7.58 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _008_ (net)
6.14 0.02 7.60 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
7.60 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.08 clock uncertainty
-0.08 1.00 clock reconvergence pessimism
0.54 1.54 library hold time
1.54 data required time
-----------------------------------------------------------------------------
1.54 data required time
-7.60 data arrival time
-----------------------------------------------------------------------------
6.06 slack (MET)
Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.47 2.30 3.07 v _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.41 net17 (net)
2.50 0.13 3.20 v _068_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.48 0.78 3.98 ^ _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _032_ (net)
0.48 0.00 3.98 ^ _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
4.01 2.45 6.43 v _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.21 _009_ (net)
4.01 0.05 6.48 v _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6.48 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.86 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.11 clock uncertainty
-0.08 1.02 clock reconvergence pessimism
-0.87 0.15 library hold time
0.15 data required time
-----------------------------------------------------------------------------
0.15 data required time
-6.48 data arrival time
-----------------------------------------------------------------------------
6.33 slack (MET)
Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.21 2.17 2.95 v _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.36 net9 (net)
2.23 0.12 3.06 v _050_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.66 1.12 4.19 ^ _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
2 0.02 _022_ (net)
0.66 0.00 4.19 ^ _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
4.27 2.65 6.84 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.22 _001_ (net)
4.28 0.06 6.90 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6.90 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.08 clock uncertainty
-0.05 1.04 clock reconvergence pessimism
-0.94 0.10 library hold time
0.10 data required time
-----------------------------------------------------------------------------
0.10 data required time
-6.90 data arrival time
-----------------------------------------------------------------------------
6.80 slack (MET)
Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.21 2.17 2.95 v _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.36 net9 (net)
2.22 0.10 3.04 v _048_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
9.99 6.13 9.18 ^ _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.23 _000_ (net)
9.99 0.05 9.22 ^ _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
9.22 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.10 clock uncertainty
-0.08 1.02 clock reconvergence pessimism
1.05 2.07 library hold time
2.07 data required time
-----------------------------------------------------------------------------
2.07 data required time
-9.22 data arrival time
-----------------------------------------------------------------------------
7.15 slack (MET)
Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4.32 3.34 4.12 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.37 net20 (net)
4.33 0.11 4.23 ^ _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.15 5.58 9.81 v _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.43 _012_ (net)
7.15 0.10 9.91 v _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
9.91 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.86 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 1.11 clock uncertainty
-0.08 1.02 clock reconvergence pessimism
-1.55 -0.53 library hold time
-0.53 data required time
-----------------------------------------------------------------------------
-0.53 data required time
-9.91 data arrival time
-----------------------------------------------------------------------------
10.44 slack (MET)
Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[11] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.08 1.58 2.35 v _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.17 net4 (net)
1.09 0.03 2.38 v output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.45 0.77 3.15 v output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[11] (net)
0.45 0.00 3.15 v io_out[11] (out)
3.15 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.15 data arrival time
-----------------------------------------------------------------------------
15.90 slack (MET)
Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[9] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.24 1.65 2.41 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.20 net21 (net)
1.25 0.04 2.45 v output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.45 0.81 3.25 v output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[9] (net)
0.45 0.00 3.26 v io_out[9] (out)
3.26 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.26 data arrival time
-----------------------------------------------------------------------------
16.01 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[14] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.36 1.66 2.43 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.11 net7 (net)
1.36 0.02 2.45 v output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.46 0.83 3.28 v output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[14] (net)
0.46 0.00 3.28 v io_out[14] (out)
3.28 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.28 data arrival time
-----------------------------------------------------------------------------
16.03 slack (MET)
Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[2] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.22 1.65 2.42 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.20 net14 (net)
1.23 0.07 2.49 v output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.45 0.80 3.29 v output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[2] (net)
0.45 0.00 3.29 v io_out[2] (out)
3.29 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.29 data arrival time
-----------------------------------------------------------------------------
16.04 slack (MET)
Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[13] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.35 1.72 2.49 v _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.22 net6 (net)
1.36 0.07 2.56 v output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.46 0.83 3.39 v output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[13] (net)
0.46 0.00 3.39 v io_out[13] (out)
3.39 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.39 data arrival time
-----------------------------------------------------------------------------
16.14 slack (MET)
Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.44 1.79 2.56 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.23 net2 (net)
1.44 0.02 2.58 v output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.46 0.84 3.42 v output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[0] (net)
0.46 0.00 3.42 v io_out[0] (out)
3.42 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.42 data arrival time
-----------------------------------------------------------------------------
16.17 slack (MET)
Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[3] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.08 2.05 2.81 v _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.17 net15 (net)
2.09 0.05 2.86 v output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.47 0.95 3.81 v output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[3] (net)
0.47 0.00 3.81 v io_out[3] (out)
3.81 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.81 data arrival time
-----------------------------------------------------------------------------
16.56 slack (MET)
Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[19] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.93 1.99 2.74 v _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.32 net12 (net)
1.98 0.16 2.90 v output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.47 0.93 3.84 v output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[19] (net)
0.47 0.00 3.84 v io_out[19] (out)
3.84 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.84 data arrival time
-----------------------------------------------------------------------------
16.59 slack (MET)
Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[6] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.13 2.09 2.87 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.17 net18 (net)
2.13 0.02 2.89 v output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.47 0.96 3.85 v output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[6] (net)
0.47 0.00 3.85 v io_out[6] (out)
3.85 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.85 data arrival time
-----------------------------------------------------------------------------
16.60 slack (MET)
Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[18] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.97 2.05 2.83 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.32 net11 (net)
2.00 0.13 2.95 v output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.47 0.94 3.89 v output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[18] (net)
0.47 0.00 3.89 v io_out[18] (out)
3.89 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-3.89 data arrival time
-----------------------------------------------------------------------------
16.64 slack (MET)
Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[16] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.21 2.17 2.95 v _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.36 net9 (net)
2.24 0.14 3.09 v output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.47 0.97 4.06 v output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[16] (net)
0.47 0.00 4.06 v io_out[16] (out)
4.06 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-4.06 data arrival time
-----------------------------------------------------------------------------
16.81 slack (MET)
Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[7] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.40 2.25 3.03 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net19 (net)
2.41 0.03 3.06 v output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.48 1.00 4.06 v output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[7] (net)
0.48 0.00 4.06 v io_out[7] (out)
4.06 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-4.06 data arrival time
-----------------------------------------------------------------------------
16.81 slack (MET)
Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[8] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.28 2.21 2.98 v _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.37 net20 (net)
2.31 0.15 3.13 v output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.48 0.99 4.12 v output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[8] (net)
0.48 0.00 4.12 v io_out[8] (out)
4.12 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-4.12 data arrival time
-----------------------------------------------------------------------------
16.87 slack (MET)
Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.77 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.47 2.30 3.07 v _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.41 net17 (net)
2.52 0.18 3.25 v output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.48 1.02 4.27 v output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[5] (net)
0.48 0.00 4.27 v io_out[5] (out)
4.27 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-4.27 data arrival time
-----------------------------------------------------------------------------
17.02 slack (MET)
Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[15] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.88 2.52 3.27 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net8 (net)
2.88 0.00 3.28 v output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.49 1.07 4.34 v output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[15] (net)
0.49 0.00 4.34 v io_out[15] (out)
4.34 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-4.34 data arrival time
-----------------------------------------------------------------------------
17.09 slack (MET)
Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[10] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.72 2.46 3.21 v _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.45 net3 (net)
2.76 0.17 3.38 v output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.49 1.05 4.43 v output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[10] (net)
0.49 0.00 4.43 v io_out[10] (out)
4.43 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-4.43 data arrival time
-----------------------------------------------------------------------------
17.18 slack (MET)
Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[12] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.83 2.50 3.25 v _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net5 (net)
2.88 0.21 3.46 v output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.49 1.07 4.53 v output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[12] (net)
0.49 0.00 4.53 v io_out[12] (out)
4.53 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-4.53 data arrival time
-----------------------------------------------------------------------------
17.28 slack (MET)
Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[4] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.88 2.52 3.27 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net16 (net)
2.92 0.20 3.47 v output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.49 1.07 4.54 v output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[4] (net)
0.49 0.00 4.54 v io_out[4] (out)
4.54 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-4.54 data arrival time
-----------------------------------------------------------------------------
17.29 slack (MET)
Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
3.19 2.78 3.53 v _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.52 net13 (net)
3.19 0.06 3.59 v output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.50 1.11 4.70 v output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[1] (net)
0.50 0.00 4.70 v io_out[1] (out)
4.70 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-4.70 data arrival time
-----------------------------------------------------------------------------
17.45 slack (MET)
Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[17] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.10 0.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
3.20 2.72 3.47 v _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.53 net10 (net)
3.24 0.19 3.66 v output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.50 1.12 4.79 v output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[17] (net)
0.50 0.00 4.79 v io_out[17] (out)
4.79 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-4.79 data arrival time
-----------------------------------------------------------------------------
17.54 slack (MET)
======================= Fastest Corner ===================================
Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.17 1.04 1.40 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.22 net6 (net)
1.18 0.06 1.46 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.80 0.52 1.98 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.08 _017_ (net)
0.80 0.01 2.00 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.00 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.65 clock uncertainty
-0.04 0.62 clock reconvergence pessimism
-0.12 0.50 library hold time
0.50 data required time
-----------------------------------------------------------------------------
0.50 data required time
-2.00 data arrival time
-----------------------------------------------------------------------------
1.50 slack (MET)
Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.75 0.83 1.20 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.23 net2 (net)
0.76 0.04 1.24 v _058_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.71 1.11 2.35 ^ _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.09 _004_ (net)
1.71 0.02 2.37 ^ _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.37 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.65 clock uncertainty
-0.04 0.62 clock reconvergence pessimism
0.17 0.78 library hold time
0.78 data required time
-----------------------------------------------------------------------------
0.78 data required time
-2.37 data arrival time
-----------------------------------------------------------------------------
1.58 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.36 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.72 0.78 1.15 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.11 net7 (net)
0.73 0.02 1.17 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.39 0.32 1.49 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.02 _043_ (net)
0.39 0.00 1.49 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
0.89 0.59 2.08 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.10 _018_ (net)
0.89 0.02 2.10 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.10 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.65 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
-0.16 0.46 library hold time
0.46 data required time
-----------------------------------------------------------------------------
0.46 data required time
-2.10 data arrival time
-----------------------------------------------------------------------------
1.64 slack (MET)
Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.36 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.64 0.75 1.11 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.20 net14 (net)
0.66 0.05 1.16 v _062_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
0.43 0.40 1.57 ^ _062_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
4 0.02 _029_ (net)
0.43 0.00 1.57 ^ _065_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.15 0.08 1.65 v _065_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _031_ (net)
0.15 0.00 1.65 v _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.65 0.94 2.59 ^ _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.09 _007_ (net)
1.65 0.02 2.61 ^ _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.61 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.02 0.62 clock reconvergence pessimism
0.16 0.78 library hold time
0.78 data required time
-----------------------------------------------------------------------------
0.78 data required time
-2.61 data arrival time
-----------------------------------------------------------------------------
1.83 slack (MET)
Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.08 0.99 1.34 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.20 net21 (net)
1.09 0.07 1.41 ^ _077_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.22 0.11 1.52 v _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _037_ (net)
0.22 0.00 1.52 v _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1.91 1.09 2.61 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.13 _013_ (net)
1.91 0.04 2.65 ^ _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.65 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.64 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
0.19 0.80 library hold time
0.80 data required time
-----------------------------------------------------------------------------
0.80 data required time
-2.65 data arrival time
-----------------------------------------------------------------------------
1.85 slack (MET)
Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.36 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.04 0.95 1.31 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.32 net11 (net)
1.07 0.10 1.41 v _052_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.48 0.39 1.80 ^ _052_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.02 _023_ (net)
0.48 0.00 1.80 ^ _055_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.05 0.69 2.50 v _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.12 _002_ (net)
1.05 0.03 2.53 v _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.53 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.65 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
-0.18 0.43 library hold time
0.43 data required time
-----------------------------------------------------------------------------
0.43 data required time
-2.53 data arrival time
-----------------------------------------------------------------------------
2.09 slack (MET)
Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.49 1.17 1.52 v _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net5 (net)
1.51 0.10 1.63 v _085_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.56 1.26 2.89 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.08 _016_ (net)
1.56 0.01 2.90 ^ _110_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.90 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.64 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
0.15 0.75 library hold time
0.75 data required time
-----------------------------------------------------------------------------
0.75 data required time
-2.90 data arrival time
-----------------------------------------------------------------------------
2.15 slack (MET)
Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.24 1.10 1.46 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.23 net2 (net)
1.25 0.04 1.50 ^ _059_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.24 0.08 1.58 v _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _027_ (net)
0.24 0.00 1.58 v _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2.62 1.48 3.06 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.19 _005_ (net)
2.62 0.04 3.10 ^ _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
3.10 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.64 clock uncertainty
-0.02 0.62 clock reconvergence pessimism
0.29 0.91 library hold time
0.91 data required time
-----------------------------------------------------------------------------
0.91 data required time
-3.10 data arrival time
-----------------------------------------------------------------------------
2.19 slack (MET)
Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.14 1.01 1.38 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.17 net18 (net)
1.14 0.04 1.42 v _070_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.43 0.34 1.76 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _033_ (net)
0.43 0.00 1.76 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.22 0.78 2.54 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.13 _010_ (net)
1.22 0.03 2.58 v _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.58 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.65 clock uncertainty
-0.04 0.62 clock reconvergence pessimism
-0.24 0.38 library hold time
0.38 data required time
-----------------------------------------------------------------------------
0.38 data required time
-2.58 data arrival time
-----------------------------------------------------------------------------
2.20 slack (MET)
Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.36 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.64 0.75 1.11 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.20 net14 (net)
0.66 0.05 1.16 v _061_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.40 0.33 1.49 ^ _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.02 _028_ (net)
0.40 0.00 1.50 ^ _064_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.69 1.05 2.54 v _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _006_ (net)
1.69 0.04 2.58 v _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.58 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.65 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
-0.32 0.29 library hold time
0.29 data required time
-----------------------------------------------------------------------------
0.29 data required time
-2.58 data arrival time
-----------------------------------------------------------------------------
2.29 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.36 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.72 0.78 1.15 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.11 net7 (net)
0.73 0.02 1.17 v _089_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
0.50 0.47 1.64 ^ _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
4 0.03 _044_ (net)
0.50 0.00 1.64 ^ _092_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.19 0.12 1.77 v _092_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _046_ (net)
0.19 0.00 1.77 v _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.53 1.42 3.19 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _019_ (net)
2.53 0.03 3.22 ^ _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.22 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.64 clock uncertainty
-0.02 0.62 clock reconvergence pessimism
0.28 0.90 library hold time
0.90 data required time
-----------------------------------------------------------------------------
0.90 data required time
-3.22 data arrival time
-----------------------------------------------------------------------------
2.32 slack (MET)
Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.66 0.75 1.11 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.20 net21 (net)
0.68 0.06 1.17 v _079_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
0.38 0.37 1.54 ^ _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.01 _038_ (net)
0.38 0.00 1.54 ^ _082_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.72 1.05 2.59 v _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _014_ (net)
1.72 0.06 2.65 v _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.65 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.64 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
-0.33 0.27 library hold time
0.27 data required time
-----------------------------------------------------------------------------
0.27 data required time
-2.65 data arrival time
-----------------------------------------------------------------------------
2.38 slack (MET)
Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.36 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.57 0.72 1.08 v _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.17 net4 (net)
0.58 0.04 1.13 v _083_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.29 0.32 1.45 ^ _083_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2 0.01 _041_ (net)
0.29 0.00 1.45 ^ _084_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.01 1.22 2.66 v _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.23 _015_ (net)
2.01 0.07 2.74 v _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.74 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.65 clock uncertainty
-0.04 0.62 clock reconvergence pessimism
-0.40 0.22 library hold time
0.22 data required time
-----------------------------------------------------------------------------
0.22 data required time
-2.74 data arrival time
-----------------------------------------------------------------------------
2.52 slack (MET)
Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.51 1.17 1.53 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net16 (net)
1.53 0.10 1.62 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.55 1.78 3.40 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _008_ (net)
2.56 0.02 3.42 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
3.42 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.64 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
0.28 0.89 library hold time
0.89 data required time
-----------------------------------------------------------------------------
0.89 data required time
-3.42 data arrival time
-----------------------------------------------------------------------------
2.53 slack (MET)
Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.01 0.89 1.25 v _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.32 net12 (net)
1.05 0.10 1.35 v _056_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.45 0.54 1.89 ^ _056_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2 0.02 _026_ (net)
0.45 0.00 1.89 ^ _057_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.46 0.94 2.83 v _057_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.16 _003_ (net)
1.47 0.05 2.88 v _097_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.88 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.64 clock uncertainty
-0.04 0.61 clock reconvergence pessimism
-0.27 0.33 library hold time
0.33 data required time
-----------------------------------------------------------------------------
0.33 data required time
-2.88 data arrival time
-----------------------------------------------------------------------------
2.54 slack (MET)
Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.28 1.10 1.46 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net19 (net)
1.29 0.04 1.50 v _074_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
0.33 0.52 2.03 ^ _074_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _036_ (net)
0.33 0.00 2.03 ^ _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.67 1.04 3.06 v _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _011_ (net)
1.68 0.05 3.11 v _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.11 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.25 0.65 clock uncertainty
-0.04 0.62 clock reconvergence pessimism
-0.34 0.27 library hold time
0.27 data required time
-----------------------------------------------------------------------------
0.27 data required time
-3.11 data arrival time
-----------------------------------------------------------------------------
2.84 slack (MET)
Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.15 1.52 1.89 ^ _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.41 net17 (net)
2.17 0.13 2.02 ^ _068_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.24 0.11 2.12 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _032_ (net)
0.24 0.00 2.12 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2.93 1.64 3.77 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.21 _009_ (net)
2.94 0.05 3.82 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
3.82 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.65 clock uncertainty
-0.04 0.62 clock reconvergence pessimism
0.34 0.95 library hold time
0.95 data required time
-----------------------------------------------------------------------------
0.95 data required time
-3.82 data arrival time
-----------------------------------------------------------------------------
2.87 slack (MET)
Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.91 1.42 1.79 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.36 net9 (net)
1.94 0.12 1.90 ^ _050_/A1 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.30 0.15 2.05 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
2 0.02 _022_ (net)
0.30 0.00 2.05 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
3.13 1.76 3.81 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.22 _001_ (net)
3.14 0.06 3.87 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
3.87 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.64 clock uncertainty
-0.02 0.62 clock reconvergence pessimism
0.36 0.98 library hold time
0.98 data required time
-----------------------------------------------------------------------------
0.98 data required time
-3.87 data arrival time
-----------------------------------------------------------------------------
2.88 slack (MET)
Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.16 1.01 1.37 v _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.36 net9 (net)
1.19 0.09 1.47 v _048_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.15 2.51 3.98 ^ _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.23 _000_ (net)
4.15 0.05 4.03 ^ _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4.03 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.65 clock uncertainty
-0.04 0.62 clock reconvergence pessimism
0.50 1.12 library hold time
1.12 data required time
-----------------------------------------------------------------------------
1.12 data required time
-4.03 data arrival time
-----------------------------------------------------------------------------
2.91 slack (MET)
Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.20 1.02 1.38 v _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.37 net20 (net)
1.23 0.11 1.49 v _076_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.84 4.46 5.95 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.43 _012_ (net)
7.84 0.10 6.05 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6.05 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.25 0.65 clock uncertainty
-0.04 0.62 clock reconvergence pessimism
1.01 1.63 library hold time
1.63 data required time
-----------------------------------------------------------------------------
1.63 data required time
-6.05 data arrival time
-----------------------------------------------------------------------------
4.43 slack (MET)
Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[11] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.36 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.57 0.72 1.08 v _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.17 net4 (net)
0.57 0.03 1.11 v output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.23 0.35 1.47 v output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[11] (net)
0.23 0.00 1.47 v io_out[11] (out)
1.47 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.47 data arrival time
-----------------------------------------------------------------------------
14.22 slack (MET)
Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[9] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.66 0.75 1.11 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.20 net21 (net)
0.66 0.04 1.15 v output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.23 0.37 1.52 v output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[9] (net)
0.23 0.00 1.52 v io_out[9] (out)
1.52 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.52 data arrival time
-----------------------------------------------------------------------------
14.27 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[14] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.36 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
0.72 0.78 1.15 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.11 net7 (net)
0.72 0.02 1.17 v output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.23 0.38 1.55 v output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[14] (net)
0.23 0.00 1.55 v io_out[14] (out)
1.55 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.55 data arrival time
-----------------------------------------------------------------------------
14.30 slack (MET)
Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[2] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.36 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.64 0.75 1.11 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.20 net14 (net)
0.67 0.07 1.18 v output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.23 0.37 1.55 v output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[2] (net)
0.23 0.00 1.55 v io_out[2] (out)
1.55 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.55 data arrival time
-----------------------------------------------------------------------------
14.30 slack (MET)
Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[13] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.71 0.78 1.15 v _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.22 net6 (net)
0.73 0.07 1.22 v output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.23 0.38 1.60 v output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[13] (net)
0.23 0.00 1.60 v io_out[13] (out)
1.60 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.60 data arrival time
-----------------------------------------------------------------------------
14.35 slack (MET)
Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.75 0.83 1.20 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.23 net2 (net)
0.76 0.02 1.22 v output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.23 0.38 1.60 v output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[0] (net)
0.23 0.00 1.60 v io_out[0] (out)
1.60 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.60 data arrival time
-----------------------------------------------------------------------------
14.35 slack (MET)
Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[3] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.11 0.99 1.34 v _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.17 net15 (net)
1.11 0.05 1.40 v output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.24 0.43 1.83 v output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[3] (net)
0.24 0.00 1.83 v io_out[3] (out)
1.83 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.83 data arrival time
-----------------------------------------------------------------------------
14.58 slack (MET)
Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[6] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.14 1.01 1.38 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.17 net18 (net)
1.14 0.02 1.40 v output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.24 0.43 1.83 v output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[6] (net)
0.24 0.00 1.83 v io_out[6] (out)
1.83 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.83 data arrival time
-----------------------------------------------------------------------------
14.58 slack (MET)
Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[19] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.01 0.89 1.25 v _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.32 net12 (net)
1.10 0.16 1.41 v output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.24 0.43 1.83 v output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[19] (net)
0.24 0.00 1.84 v io_out[19] (out)
1.84 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.84 data arrival time
-----------------------------------------------------------------------------
14.59 slack (MET)
Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[18] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.36 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.04 0.95 1.31 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.32 net11 (net)
1.09 0.12 1.44 v output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.24 0.43 1.86 v output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[18] (net)
0.24 0.00 1.87 v io_out[18] (out)
1.87 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.87 data arrival time
-----------------------------------------------------------------------------
14.62 slack (MET)
Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[7] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.28 1.10 1.46 v _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net19 (net)
1.29 0.03 1.50 v output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.25 0.45 1.95 v output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[7] (net)
0.25 0.00 1.95 v io_out[7] (out)
1.95 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.95 data arrival time
-----------------------------------------------------------------------------
14.70 slack (MET)
Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[16] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.16 1.01 1.37 v _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.36 net9 (net)
1.22 0.14 1.51 v output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.24 0.44 1.95 v output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[16] (net)
0.24 0.00 1.95 v io_out[16] (out)
1.95 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.95 data arrival time
-----------------------------------------------------------------------------
14.70 slack (MET)
Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[8] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.20 1.02 1.38 v _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.37 net20 (net)
1.26 0.15 1.53 v output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.25 0.45 1.98 v output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[8] (net)
0.25 0.00 1.98 v io_out[8] (out)
1.98 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-1.98 data arrival time
-----------------------------------------------------------------------------
14.73 slack (MET)
Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 0.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.37 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.30 1.05 1.42 v _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.41 net17 (net)
1.38 0.18 1.60 v output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.25 0.46 2.06 v output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[5] (net)
0.25 0.00 2.06 v io_out[5] (out)
2.06 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.06 data arrival time
-----------------------------------------------------------------------------
14.81 slack (MET)
Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[15] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.53 1.25 1.60 v _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net8 (net)
1.53 0.00 1.60 v output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.25 0.48 2.08 v output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[15] (net)
0.25 0.00 2.08 v io_out[15] (out)
2.08 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.08 data arrival time
-----------------------------------------------------------------------------
14.83 slack (MET)
Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[10] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.44 1.16 1.51 v _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.45 net3 (net)
1.50 0.17 1.68 v output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.25 0.47 2.15 v output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[10] (net)
0.25 0.00 2.16 v io_out[10] (out)
2.16 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.16 data arrival time
-----------------------------------------------------------------------------
14.91 slack (MET)
Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[4] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.51 1.17 1.53 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net16 (net)
1.60 0.19 1.72 v output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.25 0.48 2.20 v output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[4] (net)
0.25 0.00 2.20 v io_out[4] (out)
2.20 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.20 data arrival time
-----------------------------------------------------------------------------
14.95 slack (MET)
Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[12] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.49 1.17 1.52 v _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net5 (net)
1.58 0.20 1.73 v output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.25 0.48 2.21 v output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[12] (net)
0.25 0.00 2.21 v io_out[12] (out)
2.21 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.21 data arrival time
-----------------------------------------------------------------------------
14.96 slack (MET)
Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.69 1.36 1.71 v _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.52 net13 (net)
1.70 0.06 1.77 v output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.26 0.49 2.27 v output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[1] (net)
0.26 0.00 2.27 v io_out[1] (out)
2.27 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.27 data arrival time
-----------------------------------------------------------------------------
15.02 slack (MET)
Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[17] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: min
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 0.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 0.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.36 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.69 1.29 1.64 v _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.53 net10 (net)
1.76 0.19 1.83 v output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.26 0.50 2.33 v output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[17] (net)
0.26 0.00 2.33 v io_out[17] (out)
2.33 data arrival time
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-13.00 -12.75 output external delay
-12.75 data required time
-----------------------------------------------------------------------------
-12.75 data required time
-2.33 data arrival time
-----------------------------------------------------------------------------
15.08 slack (MET)
min_report_end
max_report
===========================================================================
report_checks -path_delay max (Setup)
============================================================================
======================= Slowest Corner ===================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
1.05 0.40 13.40 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
1.05 0.00 13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
15.05 10.77 24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
15.05 0.03 24.20 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
7.05 8.58 32.77 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.17 _020_ (net)
7.05 0.02 32.79 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
115.68 78.45 111.25 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.43 _012_ (net)
115.68 0.12 111.36 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
111.36 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 69.02 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.77 clock uncertainty
0.00 68.77 clock reconvergence pessimism
-5.79 62.98 library setup time
62.98 data required time
-----------------------------------------------------------------------------
62.98 data required time
-111.36 data arrival time
-----------------------------------------------------------------------------
-48.38 slack (VIOLATED)
Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
28.12 25.04 29.35 ^ _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.45 net3 (net)
28.12 0.13 29.48 ^ _080_/A3 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
8.98 9.01 38.49 v _080_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
4 0.03 _039_ (net)
8.98 0.00 38.49 v _083_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
3.35 8.55 47.04 v _083_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2 0.01 _041_ (net)
3.35 0.00 47.04 v _084_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
60.94 41.50 88.53 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.23 _015_ (net)
60.94 0.08 88.61 ^ _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
88.61 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 69.02 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.77 clock uncertainty
0.24 69.00 clock reconvergence pessimism
-5.13 63.87 library setup time
63.87 data required time
-----------------------------------------------------------------------------
63.87 data required time
-88.61 data arrival time
-----------------------------------------------------------------------------
-24.75 slack (VIOLATED)
Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
29.73 26.04 30.35 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net16 (net)
29.73 0.14 30.49 ^ _071_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
9.32 9.68 40.17 v _071_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
2 0.03 _034_ (net)
9.32 0.00 40.17 v _074_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
5.61 8.80 48.97 v _074_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _036_ (net)
5.61 0.00 48.97 v _075_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
50.53 35.59 84.55 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _011_ (net)
50.53 0.05 84.61 ^ _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
84.61 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 69.02 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 68.77 clock uncertainty
0.24 69.00 clock reconvergence pessimism
-4.87 64.13 library setup time
64.13 data required time
-----------------------------------------------------------------------------
64.13 data required time
-84.61 data arrival time
-----------------------------------------------------------------------------
-20.47 slack (VIOLATED)
Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
33.05 28.16 32.48 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.53 net10 (net)
33.05 0.17 32.65 ^ _050_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
7.05 7.55 40.20 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
2 0.02 _022_ (net)
7.05 0.00 40.20 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
60.98 43.38 83.58 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.22 _001_ (net)
60.98 0.07 83.65 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
83.65 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 68.90 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.65 clock uncertainty
0.41 69.06 clock reconvergence pessimism
-5.18 63.88 library setup time
63.88 data required time
-----------------------------------------------------------------------------
63.88 data required time
-83.65 data arrival time
-----------------------------------------------------------------------------
-19.76 slack (VIOLATED)
Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
33.05 28.16 32.48 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.53 net10 (net)
33.05 0.17 32.65 ^ _053_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
6.70 7.54 40.19 v _053_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
2 0.01 _024_ (net)
6.70 0.00 40.19 v _056_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
5.75 7.97 48.15 v _056_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
2 0.02 _026_ (net)
5.75 0.00 48.15 v _057_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
44.17 31.50 79.65 ^ _057_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.16 _003_ (net)
44.17 0.05 79.71 ^ _097_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
79.71 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 68.90 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.65 clock uncertainty
0.41 69.06 clock reconvergence pessimism
-4.98 64.08 library setup time
64.08 data required time
-----------------------------------------------------------------------------
64.08 data required time
-79.71 data arrival time
-----------------------------------------------------------------------------
-15.63 slack (VIOLATED)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
1.05 0.40 13.40 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
1.05 0.00 13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
15.05 10.77 24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
15.05 0.03 24.20 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
8.71 9.44 33.63 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
8.71 0.01 33.64 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
5.32 3.36 37.00 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _032_ (net)
5.32 0.00 37.00 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
57.10 40.20 77.20 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.21 _009_ (net)
57.10 0.06 77.26 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
77.26 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 69.02 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.77 clock uncertainty
0.00 68.77 clock reconvergence pessimism
-5.09 63.68 library setup time
63.68 data required time
-----------------------------------------------------------------------------
63.68 data required time
-77.26 data arrival time
-----------------------------------------------------------------------------
-13.58 slack (VIOLATED)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
1.05 0.40 13.40 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
1.05 0.00 13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
15.05 10.77 24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
15.05 0.03 24.20 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
7.05 8.58 32.77 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.17 _020_ (net)
7.05 0.02 32.79 v _048_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
60.93 42.88 75.68 ^ _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.23 _000_ (net)
60.93 0.05 75.73 ^ _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
75.73 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 69.02 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.77 clock uncertainty
0.00 68.77 clock reconvergence pessimism
-5.13 63.63 library setup time
63.63 data required time
-----------------------------------------------------------------------------
63.63 data required time
-75.73 data arrival time
-----------------------------------------------------------------------------
-12.10 slack (VIOLATED)
Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
29.21 25.72 30.03 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.46 net5 (net)
29.21 0.14 30.17 ^ _089_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
9.48 9.92 40.10 v _089_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
4 0.03 _044_ (net)
9.48 0.00 40.10 v _092_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
6.14 8.82 48.92 v _092_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _046_ (net)
6.14 0.00 48.92 v _093_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
37.15 27.08 76.00 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _019_ (net)
37.15 0.04 76.04 ^ _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
76.04 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 68.90 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 68.65 clock uncertainty
0.41 69.07 clock reconvergence pessimism
-4.76 64.30 library setup time
64.30 data required time
-----------------------------------------------------------------------------
64.30 data required time
-76.04 data arrival time
-----------------------------------------------------------------------------
-11.73 slack (VIOLATED)
Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
32.73 28.04 32.35 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.52 net13 (net)
32.73 0.08 32.43 ^ _061_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
6.02 7.06 39.49 v _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.02 _028_ (net)
6.02 0.00 39.49 v _064_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
50.62 35.83 75.33 ^ _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _006_ (net)
50.62 0.04 75.37 ^ _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
75.37 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 69.02 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.77 clock uncertainty
0.24 69.00 clock reconvergence pessimism
-5.01 63.99 library setup time
63.99 data required time
-----------------------------------------------------------------------------
63.99 data required time
-75.37 data arrival time
-----------------------------------------------------------------------------
-11.38 slack (VIOLATED)
Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
32.73 28.04 32.35 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.52 net13 (net)
32.73 0.08 32.43 ^ _059_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
5.40 5.49 37.92 v _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _027_ (net)
5.40 0.00 37.92 v _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
50.93 36.24 74.16 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.19 _005_ (net)
50.93 0.04 74.20 ^ _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
74.20 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 68.90 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.65 clock uncertainty
0.41 69.06 clock reconvergence pessimism
-5.06 64.00 library setup time
64.00 data required time
-----------------------------------------------------------------------------
64.00 data required time
-74.20 data arrival time
-----------------------------------------------------------------------------
-10.20 slack (VIOLATED)
Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
28.12 25.04 29.35 ^ _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.45 net3 (net)
28.12 0.14 29.49 ^ _079_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
5.77 6.39 35.88 v _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.01 _038_ (net)
5.77 0.00 35.88 v _082_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
51.57 36.33 72.20 ^ _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _014_ (net)
51.57 0.06 72.27 ^ _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
72.27 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 68.90 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.65 clock uncertainty
0.41 69.06 clock reconvergence pessimism
-5.07 63.99 library setup time
63.99 data required time
-----------------------------------------------------------------------------
63.99 data required time
-72.27 data arrival time
-----------------------------------------------------------------------------
-8.27 slack (VIOLATED)
Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
32.73 28.04 32.35 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.52 net13 (net)
32.73 0.08 32.43 ^ _062_/A2 (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
7.78 9.04 41.48 v _062_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand3_1)
4 0.02 _029_ (net)
7.78 0.00 41.48 v _065_/A2 (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
4.11 7.73 49.21 v _065_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1)
1 0.01 _031_ (net)
4.11 0.00 49.21 v _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
24.15 17.86 67.07 ^ _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.09 _007_ (net)
24.15 0.02 67.09 ^ _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
67.09 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 68.90 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 68.65 clock uncertainty
0.41 69.06 clock reconvergence pessimism
-4.62 64.45 library setup time
64.45 data required time
-----------------------------------------------------------------------------
64.45 data required time
-67.09 data arrival time
-----------------------------------------------------------------------------
-2.64 slack (VIOLATED)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
1.05 0.40 13.40 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
1.05 0.00 13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
15.05 10.77 24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
15.05 0.03 24.20 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
8.71 9.44 33.63 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
8.71 0.01 33.64 ^ _077_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
4.19 3.14 36.78 v _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.00 _037_ (net)
4.19 0.00 36.78 v _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
37.02 26.77 63.54 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.13 _013_ (net)
37.02 0.04 63.58 ^ _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
63.58 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 68.90 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.65 clock uncertainty
0.00 68.65 clock reconvergence pessimism
-4.90 63.75 library setup time
63.75 data required time
-----------------------------------------------------------------------------
63.75 data required time
-63.58 data arrival time
-----------------------------------------------------------------------------
0.17 slack (MET)
Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
33.05 28.16 32.48 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.53 net10 (net)
33.05 0.16 32.64 ^ _052_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
5.92 6.89 39.53 v _052_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.02 _023_ (net)
5.92 0.00 39.53 v _055_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
31.46 23.31 62.85 ^ _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.12 _002_ (net)
31.46 0.03 62.88 ^ _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
62.88 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 69.02 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.77 clock uncertainty
0.24 69.00 clock reconvergence pessimism
-4.78 64.22 library setup time
64.22 data required time
-----------------------------------------------------------------------------
64.22 data required time
-62.88 data arrival time
-----------------------------------------------------------------------------
1.34 slack (MET)
Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
29.73 26.04 30.35 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net16 (net)
29.73 0.14 30.49 ^ _070_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
5.82 5.37 35.87 v _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1 0.01 _033_ (net)
5.82 0.00 35.87 v _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
36.53 26.57 62.44 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.13 _010_ (net)
36.53 0.04 62.48 ^ _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
62.48 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 69.02 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 68.77 clock uncertainty
0.24 69.00 clock reconvergence pessimism
-4.71 64.29 library setup time
64.29 data required time
-----------------------------------------------------------------------------
64.29 data required time
-62.48 data arrival time
-----------------------------------------------------------------------------
1.82 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
1.05 0.40 13.40 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
1.05 0.00 13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
15.05 10.77 24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
15.05 0.03 24.20 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
7.05 8.58 32.77 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.17 _020_ (net)
7.05 0.03 32.80 v _067_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
37.40 27.60 60.40 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _008_ (net)
37.40 0.02 60.42 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
60.42 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 68.90 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.65 clock uncertainty
0.00 68.65 clock reconvergence pessimism
-4.90 63.75 library setup time
63.75 data required time
-----------------------------------------------------------------------------
63.75 data required time
-60.42 data arrival time
-----------------------------------------------------------------------------
3.33 slack (MET)
Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
29.21 25.72 30.03 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.46 net5 (net)
29.21 0.15 30.18 ^ _088_/A1 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
6.51 6.41 36.59 v _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.01 _043_ (net)
6.51 0.00 36.59 v _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
26.61 20.41 57.00 ^ _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.10 _018_ (net)
26.61 0.02 57.02 ^ _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
57.02 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 69.02 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 68.77 clock uncertainty
0.24 69.00 clock reconvergence pessimism
-4.60 64.41 library setup time
64.41 data required time
-----------------------------------------------------------------------------
64.41 data required time
-57.02 data arrival time
-----------------------------------------------------------------------------
7.39 slack (MET)
Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[17] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
33.05 28.16 32.48 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.53 net10 (net)
33.05 0.21 32.69 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.90 9.24 41.93 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[17] (net)
2.90 0.00 41.93 ^ io_out[17] (out)
41.93 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-41.93 data arrival time
-----------------------------------------------------------------------------
9.82 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
1.05 0.40 13.40 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
1.05 0.00 13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
15.05 10.77 24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
15.05 0.03 24.20 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
8.71 9.44 33.63 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
8.71 0.01 33.64 ^ _086_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
5.19 3.32 36.96 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _042_ (net)
5.19 0.00 36.96 v _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
21.59 17.15 54.11 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.08 _017_ (net)
21.59 0.02 54.13 ^ _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
54.13 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 69.02 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.77 clock uncertainty
0.00 68.77 clock reconvergence pessimism
-4.66 64.10 library setup time
64.10 data required time
-----------------------------------------------------------------------------
64.10 data required time
-54.13 data arrival time
-----------------------------------------------------------------------------
9.97 slack (MET)
Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
32.73 28.04 32.35 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.52 net13 (net)
32.73 0.07 32.42 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.86 9.16 41.58 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[1] (net)
2.86 0.00 41.58 ^ io_out[1] (out)
41.58 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-41.58 data arrival time
-----------------------------------------------------------------------------
10.17 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
1.05 0.40 13.40 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
1.05 0.00 13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
15.05 10.77 24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
15.05 0.03 24.20 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
7.05 8.58 32.77 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.17 _020_ (net)
7.05 0.03 32.80 v _058_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
24.96 19.50 52.30 ^ _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.09 _004_ (net)
24.96 0.02 52.32 ^ _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
52.32 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 69.02 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.77 clock uncertainty
0.00 68.77 clock reconvergence pessimism
-4.70 64.06 library setup time
64.06 data required time
-----------------------------------------------------------------------------
64.06 data required time
-52.32 data arrival time
-----------------------------------------------------------------------------
11.74 slack (MET)
Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[4] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
29.73 26.04 30.35 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net16 (net)
29.73 0.22 30.57 ^ output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.90 8.77 39.34 ^ output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[4] (net)
2.90 0.00 39.34 ^ io_out[4] (out)
39.34 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-39.34 data arrival time
-----------------------------------------------------------------------------
12.41 slack (MET)
Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[12] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
29.21 25.72 30.03 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.46 net5 (net)
29.22 0.23 30.26 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.82 8.72 38.98 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[12] (net)
2.82 0.00 38.99 ^ io_out[12] (out)
38.99 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-38.99 data arrival time
-----------------------------------------------------------------------------
12.76 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
1.05 0.40 13.40 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
1.05 0.00 13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
15.05 10.77 24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
15.05 0.03 24.20 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
7.05 8.58 32.77 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.17 _020_ (net)
7.05 0.03 32.80 v _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
22.83 18.12 50.92 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.08 _016_ (net)
22.83 0.01 50.94 ^ _110_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
50.94 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.67 68.90 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 68.90 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.65 clock uncertainty
0.00 68.65 clock reconvergence pessimism
-4.73 63.92 library setup time
63.92 data required time
-----------------------------------------------------------------------------
63.92 data required time
-50.94 data arrival time
-----------------------------------------------------------------------------
12.99 slack (MET)
Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[15] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.32 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
29.50 25.54 29.85 ^ _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net8 (net)
29.50 0.00 29.86 ^ output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.91 8.76 38.61 ^ output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[15] (net)
2.91 0.00 38.61 ^ io_out[15] (out)
38.61 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-38.61 data arrival time
-----------------------------------------------------------------------------
13.14 slack (MET)
Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[10] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
28.12 25.04 29.35 ^ _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.45 net3 (net)
28.12 0.19 29.54 ^ output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.84 8.60 38.15 ^ output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[10] (net)
2.84 0.00 38.15 ^ io_out[10] (out)
38.15 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-38.15 data arrival time
-----------------------------------------------------------------------------
13.60 slack (MET)
Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
25.58 23.46 27.90 ^ _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.41 net17 (net)
25.59 0.20 28.11 ^ output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.79 8.27 36.38 ^ output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[5] (net)
2.79 0.00 36.38 ^ io_out[5] (out)
36.38 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-36.38 data arrival time
-----------------------------------------------------------------------------
15.37 slack (MET)
Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[7] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
24.78 22.56 27.00 ^ _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net19 (net)
24.78 0.04 27.04 ^ output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.87 8.16 35.20 ^ output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[7] (net)
2.87 0.00 35.20 ^ io_out[7] (out)
35.20 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-35.20 data arrival time
-----------------------------------------------------------------------------
16.55 slack (MET)
Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[8] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
23.49 22.15 26.60 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.37 net20 (net)
23.50 0.17 26.76 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.86 8.00 34.77 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[8] (net)
2.86 0.00 34.77 ^ io_out[8] (out)
34.77 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-34.77 data arrival time
-----------------------------------------------------------------------------
16.98 slack (MET)
Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[16] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
22.74 21.68 26.12 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.36 net9 (net)
22.74 0.15 26.28 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.83 7.90 34.18 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[16] (net)
2.83 0.00 34.18 ^ io_out[16] (out)
34.18 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-34.18 data arrival time
-----------------------------------------------------------------------------
17.57 slack (MET)
Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[6] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.90 20.72 25.16 ^ _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.17 net18 (net)
21.90 0.03 25.19 ^ output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.84 7.80 32.99 ^ output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[6] (net)
2.84 0.00 32.99 ^ io_out[6] (out)
32.99 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-32.99 data arrival time
-----------------------------------------------------------------------------
18.76 slack (MET)
Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[3] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
21.37 20.31 24.63 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.17 net15 (net)
21.37 0.06 24.69 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.83 7.74 32.42 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[3] (net)
2.83 0.00 32.42 ^ io_out[3] (out)
32.42 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-32.42 data arrival time
-----------------------------------------------------------------------------
19.33 slack (MET)
Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[18] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
20.37 20.18 24.62 ^ _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.32 net11 (net)
20.37 0.14 24.76 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.81 7.60 32.36 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[18] (net)
2.81 0.00 32.36 ^ io_out[18] (out)
32.36 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-32.36 data arrival time
-----------------------------------------------------------------------------
19.39 slack (MET)
Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[19] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
19.98 19.84 24.16 ^ _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.32 net12 (net)
19.99 0.18 24.34 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.74 7.57 31.91 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[19] (net)
2.74 0.00 31.91 ^ io_out[19] (out)
31.91 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-31.91 data arrival time
-----------------------------------------------------------------------------
19.84 slack (MET)
Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
14.64 16.57 21.01 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.23 net2 (net)
14.64 0.02 21.03 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.78 6.79 27.82 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[0] (net)
2.78 0.00 27.82 ^ io_out[0] (out)
27.82 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-27.82 data arrival time
-----------------------------------------------------------------------------
23.93 slack (MET)
Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[13] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
13.88 16.06 20.50 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.22 net6 (net)
13.88 0.08 20.57 ^ output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.75 6.66 27.23 ^ output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[13] (net)
2.75 0.00 27.24 ^ io_out[13] (out)
27.24 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-27.24 data arrival time
-----------------------------------------------------------------------------
24.51 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[14] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
13.98 15.67 20.11 ^ _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.11 net7 (net)
13.98 0.02 20.13 ^ output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.70 6.70 26.83 ^ output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[14] (net)
2.70 0.00 26.83 ^ io_out[14] (out)
26.83 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-26.83 data arrival time
-----------------------------------------------------------------------------
24.92 slack (MET)
Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[2] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12.52 15.20 19.64 ^ _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.20 net14 (net)
12.53 0.08 19.72 ^ output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.75 6.42 26.14 ^ output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[2] (net)
2.75 0.00 26.14 ^ io_out[2] (out)
26.14 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-26.14 data arrival time
-----------------------------------------------------------------------------
25.61 slack (MET)
Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[9] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.83 1.84 4.31 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.83 0.00 4.31 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12.76 15.29 19.60 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.20 net21 (net)
12.76 0.05 19.65 ^ output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.74 6.45 26.10 ^ output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[9] (net)
2.74 0.00 26.10 ^ io_out[9] (out)
26.10 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-26.10 data arrival time
-----------------------------------------------------------------------------
25.65 slack (MET)
Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[11] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
1.13 0.55 0.55 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 0.55 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.92 2.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 2.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.97 4.44 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 4.44 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
11.06 14.27 18.71 ^ _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.17 net4 (net)
11.06 0.03 18.75 ^ output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
2.73 6.14 24.89 ^ output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[11] (net)
2.73 0.00 24.89 ^ io_out[11] (out)
24.89 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-24.89 data arrival time
-----------------------------------------------------------------------------
26.86 slack (MET)
======================= Typical Corner ===================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
1.63 0.02 16.44 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
18.95 11.96 28.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.43 _012_ (net)
18.95 0.12 28.52 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
28.52 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.52 clock uncertainty
0.00 65.52 clock reconvergence pessimism
1.23 66.75 library setup time
66.75 data required time
-----------------------------------------------------------------------------
66.75 data required time
-28.52 data arrival time
-----------------------------------------------------------------------------
38.23 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
1.63 1.30 16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
1.63 0.00 16.32 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1.44 0.51 16.84 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
2 0.02 _022_ (net)
1.44 0.00 16.84 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
10.03 6.54 23.38 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.22 _001_ (net)
10.03 0.07 23.45 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
23.45 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 65.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.50 clock uncertainty
0.00 65.50 clock reconvergence pessimism
0.26 65.77 library setup time
65.77 data required time
-----------------------------------------------------------------------------
65.77 data required time
-23.45 data arrival time
-----------------------------------------------------------------------------
42.32 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
1.62 0.02 16.44 v _084_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
10.00 6.59 23.02 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.23 _015_ (net)
10.00 0.08 23.10 ^ _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
23.10 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.77 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.52 clock uncertainty
0.00 65.52 clock reconvergence pessimism
0.27 65.79 library setup time
65.79 data required time
-----------------------------------------------------------------------------
65.79 data required time
-23.10 data arrival time
-----------------------------------------------------------------------------
42.69 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
1.63 0.02 16.45 v _048_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
9.99 6.50 22.95 ^ _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.23 _000_ (net)
9.99 0.05 23.00 ^ _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
23.00 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.77 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.52 clock uncertainty
0.00 65.52 clock reconvergence pessimism
0.27 65.79 library setup time
65.79 data required time
-----------------------------------------------------------------------------
65.79 data required time
-23.00 data arrival time
-----------------------------------------------------------------------------
42.79 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
1.63 1.30 16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
1.63 0.01 16.33 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1.03 0.36 16.69 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _032_ (net)
1.03 0.00 16.69 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
9.40 6.08 22.77 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.21 _009_ (net)
9.40 0.06 22.83 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
22.83 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.77 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.52 clock uncertainty
0.00 65.52 clock reconvergence pessimism
0.20 65.73 library setup time
65.73 data required time
-----------------------------------------------------------------------------
65.73 data required time
-22.83 data arrival time
-----------------------------------------------------------------------------
42.90 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
1.63 1.30 16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
1.63 0.01 16.33 ^ _059_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1.17 0.36 16.69 v _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _027_ (net)
1.17 0.00 16.69 v _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
8.39 5.50 22.18 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.19 _005_ (net)
8.39 0.04 22.22 ^ _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
22.22 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 65.75 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.50 clock uncertainty
0.00 65.50 clock reconvergence pessimism
0.09 65.59 library setup time
65.59 data required time
-----------------------------------------------------------------------------
65.59 data required time
-22.22 data arrival time
-----------------------------------------------------------------------------
43.37 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
1.63 1.30 16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
1.63 0.01 16.33 ^ _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.67 0.50 16.82 v _063_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
2 0.02 _030_ (net)
0.67 0.00 16.82 v _064_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
8.31 5.29 22.12 ^ _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _006_ (net)
8.31 0.04 22.16 ^ _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
22.16 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.77 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.52 clock uncertainty
0.00 65.52 clock reconvergence pessimism
0.09 65.61 library setup time
65.61 data required time
-----------------------------------------------------------------------------
65.61 data required time
-22.16 data arrival time
-----------------------------------------------------------------------------
43.45 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
1.63 1.30 16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
1.63 0.00 16.32 ^ _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.48 0.29 16.61 v _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _040_ (net)
0.48 0.00 16.62 v _082_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
8.46 5.34 21.95 ^ _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _014_ (net)
8.47 0.06 22.02 ^ _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
22.02 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 65.75 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.50 clock uncertainty
0.00 65.50 clock reconvergence pessimism
0.10 65.60 library setup time
65.60 data required time
-----------------------------------------------------------------------------
65.60 data required time
-22.02 data arrival time
-----------------------------------------------------------------------------
43.58 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
1.63 0.03 16.45 v _075_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
8.29 5.56 22.00 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _011_ (net)
8.29 0.05 22.06 ^ _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
22.06 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.77 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.52 clock uncertainty
0.00 65.52 clock reconvergence pessimism
0.12 65.64 library setup time
65.64 data required time
-----------------------------------------------------------------------------
65.64 data required time
-22.06 data arrival time
-----------------------------------------------------------------------------
43.58 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
1.62 0.02 16.44 v _057_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.25 4.92 21.36 ^ _057_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.16 _003_ (net)
7.25 0.05 21.41 ^ _097_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
21.41 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 65.75 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.50 clock uncertainty
0.00 65.50 clock reconvergence pessimism
-0.03 65.47 library setup time
65.47 data required time
-----------------------------------------------------------------------------
65.47 data required time
-21.41 data arrival time
-----------------------------------------------------------------------------
44.06 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
1.63 1.30 16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
1.63 0.01 16.33 ^ _077_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.82 0.31 16.64 v _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _037_ (net)
0.82 0.00 16.64 v _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
6.11 4.03 20.67 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.13 _013_ (net)
6.11 0.04 20.71 ^ _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
20.71 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 65.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.50 clock uncertainty
0.00 65.50 clock reconvergence pessimism
-0.15 65.35 library setup time
65.35 data required time
-----------------------------------------------------------------------------
65.35 data required time
-20.71 data arrival time
-----------------------------------------------------------------------------
44.64 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
1.63 0.03 16.45 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
6.10 4.22 20.67 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _019_ (net)
6.10 0.04 20.71 ^ _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
20.71 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 65.75 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.50 clock uncertainty
0.00 65.50 clock reconvergence pessimism
-0.12 65.38 library setup time
65.38 data required time
-----------------------------------------------------------------------------
65.38 data required time
-20.71 data arrival time
-----------------------------------------------------------------------------
44.68 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
1.63 0.03 16.45 v _067_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
6.14 4.15 20.60 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _008_ (net)
6.14 0.02 20.63 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
20.63 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 65.75 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.50 clock uncertainty
0.00 65.50 clock reconvergence pessimism
-0.15 65.36 library setup time
65.36 data required time
-----------------------------------------------------------------------------
65.36 data required time
-20.63 data arrival time
-----------------------------------------------------------------------------
44.73 slack (MET)
Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[17] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6.07 4.75 5.58 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.53 net10 (net)
6.09 0.21 5.79 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.58 1.09 6.88 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[17] (net)
0.58 0.00 6.88 ^ io_out[17] (out)
6.88 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-6.88 data arrival time
-----------------------------------------------------------------------------
44.87 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
1.63 1.30 16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
1.63 0.01 16.33 ^ _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.46 0.26 16.59 v _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _035_ (net)
0.46 0.00 16.59 v _073_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
6.00 3.84 20.43 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.13 _010_ (net)
6.00 0.04 20.46 ^ _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
20.46 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.77 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.52 clock uncertainty
0.00 65.52 clock reconvergence pessimism
-0.12 65.40 library setup time
65.40 data required time
-----------------------------------------------------------------------------
65.40 data required time
-20.46 data arrival time
-----------------------------------------------------------------------------
44.94 slack (MET)
Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6.02 4.79 5.62 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.52 net13 (net)
6.02 0.07 5.69 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.57 1.08 6.77 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[1] (net)
0.57 0.00 6.77 ^ io_out[1] (out)
6.77 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-6.77 data arrival time
-----------------------------------------------------------------------------
44.98 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
1.63 1.30 16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
1.63 0.00 16.32 ^ _054_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.62 0.44 16.77 v _054_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
2 0.01 _025_ (net)
0.62 0.00 16.77 v _055_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
5.17 3.36 20.12 ^ _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.12 _002_ (net)
5.17 0.03 20.16 ^ _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
20.16 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.77 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.52 clock uncertainty
0.00 65.52 clock reconvergence pessimism
-0.23 65.29 library setup time
65.29 data required time
-----------------------------------------------------------------------------
65.29 data required time
-20.16 data arrival time
-----------------------------------------------------------------------------
45.13 slack (MET)
Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[4] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.45 4.36 5.19 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net16 (net)
5.48 0.22 5.41 ^ output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.56 1.06 6.47 ^ output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[4] (net)
0.56 0.00 6.47 ^ io_out[4] (out)
6.47 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-6.47 data arrival time
-----------------------------------------------------------------------------
45.28 slack (MET)
Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[12] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.36 4.31 5.14 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net5 (net)
5.39 0.23 5.37 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.56 1.06 6.43 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[12] (net)
0.56 0.00 6.43 ^ io_out[12] (out)
6.43 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-6.43 data arrival time
-----------------------------------------------------------------------------
45.32 slack (MET)
Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[10] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
5.16 4.20 5.03 ^ _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.45 net3 (net)
5.18 0.19 5.23 ^ output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.56 1.05 6.28 ^ output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[10] (net)
0.56 0.00 6.28 ^ io_out[10] (out)
6.28 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-6.28 data arrival time
-----------------------------------------------------------------------------
45.47 slack (MET)
Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[15] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
5.46 4.35 5.18 ^ _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net8 (net)
5.46 0.00 5.18 ^ output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.56 1.06 6.24 ^ output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[15] (net)
0.56 0.00 6.24 ^ io_out[15] (out)
6.24 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-6.24 data arrival time
-----------------------------------------------------------------------------
45.51 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
1.63 1.30 16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
1.63 0.01 16.33 ^ _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.56 0.38 16.71 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
2 0.01 _045_ (net)
0.56 0.00 16.71 v _091_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.37 2.86 19.57 ^ _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.10 _018_ (net)
4.37 0.02 19.59 ^ _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
19.59 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.77 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.52 clock uncertainty
0.00 65.52 clock reconvergence pessimism
-0.27 65.25 library setup time
65.25 data required time
-----------------------------------------------------------------------------
65.25 data required time
-19.59 data arrival time
-----------------------------------------------------------------------------
45.66 slack (MET)
Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.86 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4.69 3.90 4.76 ^ _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.41 net17 (net)
4.72 0.20 4.96 ^ output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.55 1.04 6.00 ^ output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[5] (net)
0.55 0.00 6.00 ^ io_out[5] (out)
6.00 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-6.00 data arrival time
-----------------------------------------------------------------------------
45.75 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
1.63 0.02 16.44 v _066_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.97 2.93 19.38 ^ _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.09 _007_ (net)
3.97 0.02 19.40 ^ _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
19.40 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 65.75 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.50 clock uncertainty
0.00 65.50 clock reconvergence pessimism
-0.31 65.19 library setup time
65.19 data required time
-----------------------------------------------------------------------------
65.19 data required time
-19.40 data arrival time
-----------------------------------------------------------------------------
45.79 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
1.63 0.03 16.45 v _058_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.10 2.91 19.35 ^ _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.09 _004_ (net)
4.10 0.02 19.37 ^ _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
19.37 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.77 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.52 clock uncertainty
0.00 65.52 clock reconvergence pessimism
-0.32 65.20 library setup time
65.20 data required time
-----------------------------------------------------------------------------
65.20 data required time
-19.37 data arrival time
-----------------------------------------------------------------------------
45.83 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
1.63 1.30 16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
1.63 0.01 16.33 ^ _086_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1.01 0.35 16.68 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _042_ (net)
1.01 0.00 16.68 v _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
3.59 2.52 19.20 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.08 _017_ (net)
3.59 0.02 19.22 ^ _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
19.22 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.77 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.52 clock uncertainty
0.00 65.52 clock reconvergence pessimism
-0.36 65.16 library setup time
65.16 data required time
-----------------------------------------------------------------------------
65.16 data required time
-19.22 data arrival time
-----------------------------------------------------------------------------
45.94 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
1.63 0.03 16.45 v _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.78 2.70 19.15 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.08 _016_ (net)
3.78 0.01 19.16 ^ _110_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
19.16 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.32 65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 65.75 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.50 clock uncertainty
0.00 65.50 clock reconvergence pessimism
-0.36 65.15 library setup time
65.15 data required time
-----------------------------------------------------------------------------
65.15 data required time
-19.16 data arrival time
-----------------------------------------------------------------------------
45.98 slack (MET)
Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[7] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.57 3.82 4.67 ^ _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net19 (net)
4.57 0.04 4.71 ^ output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.55 1.03 5.73 ^ output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[7] (net)
0.55 0.00 5.74 ^ io_out[7] (out)
5.74 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-5.74 data arrival time
-----------------------------------------------------------------------------
46.01 slack (MET)
Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[8] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.86 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4.32 3.69 4.55 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.37 net20 (net)
4.33 0.17 4.72 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.54 1.02 5.73 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[8] (net)
0.54 0.00 5.73 ^ io_out[8] (out)
5.73 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-5.73 data arrival time
-----------------------------------------------------------------------------
46.02 slack (MET)
Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[16] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4.18 3.62 4.47 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.36 net9 (net)
4.20 0.15 4.63 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.54 1.01 5.63 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[16] (net)
0.54 0.00 5.63 ^ io_out[16] (out)
5.63 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-5.63 data arrival time
-----------------------------------------------------------------------------
46.12 slack (MET)
Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[6] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.86 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4.04 3.49 4.35 ^ _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.17 net18 (net)
4.04 0.03 4.37 ^ output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.54 1.00 5.37 ^ output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[6] (net)
0.54 0.00 5.37 ^ io_out[6] (out)
5.37 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-5.37 data arrival time
-----------------------------------------------------------------------------
46.38 slack (MET)
Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[18] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
3.74 3.36 4.21 ^ _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.32 net11 (net)
3.75 0.14 4.35 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.53 0.99 5.34 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[18] (net)
0.53 0.00 5.34 ^ io_out[18] (out)
5.34 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-5.34 data arrival time
-----------------------------------------------------------------------------
46.41 slack (MET)
Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[3] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
3.95 3.42 4.25 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.17 net15 (net)
3.95 0.06 4.31 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.54 1.00 5.31 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[3] (net)
0.54 0.00 5.31 ^ io_out[3] (out)
5.31 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-5.31 data arrival time
-----------------------------------------------------------------------------
46.44 slack (MET)
Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[19] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
3.65 3.27 4.10 ^ _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.32 net12 (net)
3.68 0.18 4.28 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.53 0.99 5.27 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[19] (net)
0.53 0.00 5.27 ^ io_out[19] (out)
5.27 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-5.27 data arrival time
-----------------------------------------------------------------------------
46.48 slack (MET)
Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.71 2.77 3.62 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.23 net2 (net)
2.71 0.02 3.64 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.52 0.93 4.57 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[0] (net)
0.52 0.00 4.57 ^ io_out[0] (out)
4.57 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.57 data arrival time
-----------------------------------------------------------------------------
47.18 slack (MET)
Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[13] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.55 2.66 3.51 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.22 net6 (net)
2.56 0.08 3.59 ^ output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.51 0.91 4.50 ^ output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[13] (net)
0.51 0.00 4.50 ^ io_out[13] (out)
4.50 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.50 data arrival time
-----------------------------------------------------------------------------
47.25 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[14] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.59 2.60 3.46 ^ _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.11 net7 (net)
2.59 0.02 3.48 ^ output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.52 0.92 4.40 ^ output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[14] (net)
0.52 0.00 4.40 ^ io_out[14] (out)
4.40 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.40 data arrival time
-----------------------------------------------------------------------------
47.35 slack (MET)
Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[2] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.30 2.51 3.36 ^ _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.20 net14 (net)
2.31 0.08 3.44 ^ output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.51 0.90 4.34 ^ output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[2] (net)
0.51 0.00 4.34 ^ io_out[2] (out)
4.34 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.34 data arrival time
-----------------------------------------------------------------------------
47.41 slack (MET)
Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[9] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.17 0.00 0.83 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.35 2.53 3.36 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.20 net21 (net)
2.35 0.05 3.41 ^ output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.51 0.90 4.31 ^ output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[9] (net)
0.51 0.00 4.31 ^ io_out[9] (out)
4.31 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.31 data arrival time
-----------------------------------------------------------------------------
47.44 slack (MET)
Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[11] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.22 0.11 0.11 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 0.85 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.03 2.35 3.21 ^ _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.17 net4 (net)
2.04 0.03 3.24 ^ output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.50 0.87 4.11 ^ output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[11] (net)
0.50 0.00 4.11 ^ io_out[11] (out)
4.11 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-4.11 data arrival time
-----------------------------------------------------------------------------
47.64 slack (MET)
======================= Fastest Corner ===================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
0.79 0.66 14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
0.79 0.02 14.62 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.86 4.79 19.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.43 _012_ (net)
7.87 0.12 19.53 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
19.53 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 65.37 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.12 clock uncertainty
0.00 65.12 clock reconvergence pessimism
0.62 65.73 library setup time
65.73 data required time
-----------------------------------------------------------------------------
65.73 data required time
-19.53 data arrival time
-----------------------------------------------------------------------------
46.20 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
0.75 0.58 14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
0.75 0.00 14.53 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.83 0.21 14.75 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
2 0.02 _022_ (net)
0.83 0.00 14.75 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
4.18 2.63 17.38 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.22 _001_ (net)
4.18 0.07 17.45 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
17.45 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.20 65.31 library setup time
65.31 data required time
-----------------------------------------------------------------------------
65.31 data required time
-17.45 data arrival time
-----------------------------------------------------------------------------
47.86 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
0.79 0.66 14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
0.79 0.02 14.62 v _084_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.16 2.66 17.27 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.23 _015_ (net)
4.17 0.08 17.35 ^ _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
17.35 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 65.36 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.21 65.32 library setup time
65.32 data required time
-----------------------------------------------------------------------------
65.32 data required time
-17.35 data arrival time
-----------------------------------------------------------------------------
47.97 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
0.79 0.66 14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
0.79 0.02 14.63 v _048_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
4.15 2.61 17.24 ^ _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.23 _000_ (net)
4.15 0.05 17.29 ^ _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
17.29 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 65.37 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.12 clock uncertainty
0.00 65.12 clock reconvergence pessimism
0.20 65.32 library setup time
65.32 data required time
-----------------------------------------------------------------------------
65.32 data required time
-17.29 data arrival time
-----------------------------------------------------------------------------
48.03 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
0.75 0.58 14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
0.75 0.01 14.54 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.59 0.14 14.68 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _032_ (net)
0.59 0.00 14.68 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
3.92 2.45 17.13 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.21 _009_ (net)
3.92 0.06 17.19 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
17.19 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 65.37 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.12 clock uncertainty
0.00 65.12 clock reconvergence pessimism
0.18 65.29 library setup time
65.29 data required time
-----------------------------------------------------------------------------
65.29 data required time
-17.19 data arrival time
-----------------------------------------------------------------------------
48.10 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
0.75 0.58 14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
0.75 0.01 14.54 ^ _059_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.70 0.14 14.68 v _059_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _027_ (net)
0.70 0.00 14.68 v _060_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
3.50 2.23 16.91 ^ _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.19 _005_ (net)
3.50 0.04 16.95 ^ _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
16.95 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.13 65.23 library setup time
65.23 data required time
-----------------------------------------------------------------------------
65.23 data required time
-16.95 data arrival time
-----------------------------------------------------------------------------
48.28 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
0.75 0.58 14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
0.75 0.01 14.53 ^ _063_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.33 0.22 14.76 v _063_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
2 0.02 _030_ (net)
0.33 0.00 14.76 v _064_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.46 2.14 16.90 ^ _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _006_ (net)
3.46 0.04 16.94 ^ _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
16.94 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 65.36 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.13 65.24 library setup time
65.24 data required time
-----------------------------------------------------------------------------
65.24 data required time
-16.94 data arrival time
-----------------------------------------------------------------------------
48.30 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
0.79 0.66 14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
0.79 0.03 14.63 v _075_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.45 2.25 16.88 ^ _075_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _011_ (net)
3.45 0.05 16.93 ^ _105_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
16.93 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 65.37 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.12 clock uncertainty
0.00 65.12 clock reconvergence pessimism
0.15 65.26 library setup time
65.26 data required time
-----------------------------------------------------------------------------
65.26 data required time
-16.93 data arrival time
-----------------------------------------------------------------------------
48.33 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
0.75 0.58 14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
0.75 0.00 14.53 ^ _081_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.24 0.13 14.66 v _081_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _040_ (net)
0.24 0.00 14.66 v _082_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.52 2.16 16.82 ^ _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.19 _014_ (net)
3.53 0.06 16.88 ^ _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
16.88 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.13 65.24 library setup time
65.24 data required time
-----------------------------------------------------------------------------
65.24 data required time
-16.88 data arrival time
-----------------------------------------------------------------------------
48.35 slack (MET)
Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[17] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.79 2.08 2.48 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.53 net10 (net)
2.83 0.21 2.69 ^ output10/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.28 0.58 3.27 ^ output10/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[17] (net)
0.28 0.00 3.27 ^ io_out[17] (out)
3.27 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.27 data arrival time
-----------------------------------------------------------------------------
48.48 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
0.79 0.66 14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
0.79 0.02 14.62 v _057_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
3.02 2.00 16.62 ^ _057_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.16 _003_ (net)
3.02 0.05 16.67 ^ _097_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
16.67 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.07 65.18 library setup time
65.18 data required time
-----------------------------------------------------------------------------
65.18 data required time
-16.67 data arrival time
-----------------------------------------------------------------------------
48.51 slack (MET)
Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[1] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.78 2.15 2.54 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.52 net13 (net)
2.79 0.07 2.61 ^ output13/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.27 0.58 3.19 ^ output13/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[1] (net)
0.27 0.00 3.19 ^ io_out[1] (out)
3.19 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.19 data arrival time
-----------------------------------------------------------------------------
48.56 slack (MET)
Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[4] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.50 1.89 2.29 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net16 (net)
2.55 0.22 2.50 ^ output16/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.26 0.56 3.06 ^ output16/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[4] (net)
0.26 0.00 3.06 ^ io_out[4] (out)
3.06 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.06 data arrival time
-----------------------------------------------------------------------------
48.69 slack (MET)
Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[12] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.45 1.88 2.27 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.47 net5 (net)
2.51 0.23 2.50 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.27 0.56 3.06 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[12] (net)
0.27 0.00 3.06 ^ io_out[12] (out)
3.06 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-3.06 data arrival time
-----------------------------------------------------------------------------
48.69 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
0.79 0.66 14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
0.79 0.03 14.63 v _093_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.54 1.72 16.35 ^ _093_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _019_ (net)
2.54 0.04 16.38 ^ _113_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
16.38 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.03 65.14 library setup time
65.14 data required time
-----------------------------------------------------------------------------
65.14 data required time
-16.38 data arrival time
-----------------------------------------------------------------------------
48.76 slack (MET)
Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[10] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.37 1.84 2.23 ^ _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.45 net3 (net)
2.41 0.19 2.42 ^ output3/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.26 0.55 2.97 ^ output3/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[10] (net)
0.26 0.00 2.98 ^ io_out[10] (out)
2.98 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.98 data arrival time
-----------------------------------------------------------------------------
48.77 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
0.79 0.66 14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
0.79 0.03 14.63 v _067_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.56 1.68 16.31 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.14 _008_ (net)
2.56 0.02 16.33 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
16.33 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.02 65.13 library setup time
65.13 data required time
-----------------------------------------------------------------------------
65.13 data required time
-16.33 data arrival time
-----------------------------------------------------------------------------
48.80 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
0.75 0.58 14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
0.75 0.01 14.53 ^ _077_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.43 0.13 14.66 v _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _037_ (net)
0.43 0.00 14.66 v _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2.55 1.62 16.28 ^ _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.13 _013_ (net)
2.55 0.04 16.32 ^ _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
16.32 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
0.02 65.13 library setup time
65.13 data required time
-----------------------------------------------------------------------------
65.13 data required time
-16.32 data arrival time
-----------------------------------------------------------------------------
48.81 slack (MET)
Startpoint: _113_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[15] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _113_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.51 1.97 2.36 ^ _113_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.23 net8 (net)
2.51 0.00 2.36 ^ output8/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.26 0.56 2.92 ^ output8/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[15] (net)
0.26 0.00 2.92 ^ io_out[15] (out)
2.92 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.92 data arrival time
-----------------------------------------------------------------------------
48.83 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
0.75 0.58 14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
0.75 0.01 14.54 ^ _072_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.22 0.11 14.65 v _072_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
1 0.01 _035_ (net)
0.22 0.00 14.65 v _073_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.50 1.55 16.20 ^ _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.13 _010_ (net)
2.50 0.04 16.24 ^ _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
16.24 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 65.37 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.12 clock uncertainty
0.00 65.12 clock reconvergence pessimism
0.03 65.15 library setup time
65.15 data required time
-----------------------------------------------------------------------------
65.15 data required time
-16.24 data arrival time
-----------------------------------------------------------------------------
48.91 slack (MET)
Startpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[5] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
2.15 1.68 2.09 ^ _103_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.41 net17 (net)
2.20 0.20 2.29 ^ output17/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.26 0.54 2.83 ^ output17/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[5] (net)
0.26 0.00 2.83 ^ io_out[5] (out)
2.83 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.83 data arrival time
-----------------------------------------------------------------------------
48.92 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
0.75 0.58 14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
0.75 0.00 14.53 ^ _054_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.30 0.19 14.73 v _054_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
2 0.01 _025_ (net)
0.30 0.00 14.73 v _055_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2.15 1.35 16.08 ^ _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.12 _002_ (net)
2.15 0.03 16.11 ^ _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
16.11 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 65.36 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
-0.02 65.10 library setup time
65.10 data required time
-----------------------------------------------------------------------------
65.10 data required time
-16.11 data arrival time
-----------------------------------------------------------------------------
48.98 slack (MET)
Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[8] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.98 1.60 2.01 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.37 net20 (net)
2.01 0.17 2.17 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.25 0.52 2.70 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[8] (net)
0.25 0.00 2.70 ^ io_out[8] (out)
2.70 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.70 data arrival time
-----------------------------------------------------------------------------
49.05 slack (MET)
Startpoint: _105_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[7] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _105_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
2.11 1.71 2.11 ^ _105_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.20 net19 (net)
2.12 0.04 2.15 ^ output19/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.26 0.53 2.68 ^ output19/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[7] (net)
0.26 0.00 2.68 ^ io_out[7] (out)
2.68 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.68 data arrival time
-----------------------------------------------------------------------------
49.07 slack (MET)
Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[16] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.91 1.57 1.98 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.36 net9 (net)
1.95 0.15 2.13 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.25 0.52 2.65 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[16] (net)
0.25 0.00 2.65 ^ io_out[16] (out)
2.65 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.65 data arrival time
-----------------------------------------------------------------------------
49.10 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
0.79 0.66 14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
0.79 0.02 14.62 v _066_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.65 1.21 15.83 ^ _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.09 _007_ (net)
1.65 0.02 15.85 ^ _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
15.85 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
-0.07 65.04 library setup time
65.04 data required time
-----------------------------------------------------------------------------
65.04 data required time
-15.85 data arrival time
-----------------------------------------------------------------------------
49.19 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
0.75 0.58 14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
0.75 0.01 14.54 ^ _090_/A1 (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
0.27 0.16 14.70 v _090_/ZN (gf180mcu_fd_sc_mcu7t5v0__nand2_1)
2 0.01 _045_ (net)
0.27 0.00 14.70 v _091_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.82 1.16 15.86 ^ _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.10 _018_ (net)
1.82 0.02 15.88 ^ _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
15.88 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 65.36 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
-0.05 65.07 library setup time
65.07 data required time
-----------------------------------------------------------------------------
65.07 data required time
-15.88 data arrival time
-----------------------------------------------------------------------------
49.19 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
0.79 0.66 14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
0.79 0.03 14.63 v _058_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.71 1.18 15.80 ^ _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.09 _004_ (net)
1.71 0.02 15.82 ^ _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
15.82 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 65.37 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.12 clock uncertainty
0.00 65.12 clock reconvergence pessimism
-0.07 65.05 library setup time
65.05 data required time
-----------------------------------------------------------------------------
65.05 data required time
-15.82 data arrival time
-----------------------------------------------------------------------------
49.22 slack (MET)
Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[18] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.72 1.46 1.86 ^ _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.32 net11 (net)
1.75 0.14 2.00 ^ output11/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.25 0.50 2.50 ^ output11/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[18] (net)
0.25 0.00 2.50 ^ io_out[18] (out)
2.50 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.50 data arrival time
-----------------------------------------------------------------------------
49.25 slack (MET)
Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[6] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.87 1.55 1.96 ^ _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.17 net18 (net)
1.87 0.03 1.98 ^ output18/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.25 0.51 2.50 ^ output18/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[6] (net)
0.25 0.00 2.50 ^ io_out[6] (out)
2.50 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.50 data arrival time
-----------------------------------------------------------------------------
49.25 slack (MET)
Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[3] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.82 1.52 1.91 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
4 0.17 net15 (net)
1.83 0.06 1.97 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.25 0.51 2.48 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[3] (net)
0.25 0.00 2.48 ^ io_out[3] (out)
2.48 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.48 data arrival time
-----------------------------------------------------------------------------
49.27 slack (MET)
Startpoint: _097_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[19] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _097_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.66 1.39 1.79 ^ _097_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.32 net12 (net)
1.72 0.18 1.97 ^ output12/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.25 0.50 2.47 ^ output12/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[19] (net)
0.25 0.00 2.47 ^ io_out[19] (out)
2.47 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.47 data arrival time
-----------------------------------------------------------------------------
49.28 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
0.79 0.66 14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
0.79 0.03 14.63 v _085_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
1.60 1.09 15.72 ^ _085_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.08 _016_ (net)
1.60 0.01 15.74 ^ _110_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
15.74 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.15 65.35 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 65.36 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
-0.08 65.02 library setup time
65.02 data required time
-----------------------------------------------------------------------------
65.02 data required time
-15.74 data arrival time
-----------------------------------------------------------------------------
49.29 slack (MET)
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.95 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2)
0.75 0.58 14.53 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2)
20 0.14 _021_ (net)
0.75 0.01 14.54 ^ _086_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
0.53 0.14 14.68 v _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1)
1 0.01 _042_ (net)
0.53 0.00 14.68 v _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
1.51 1.02 15.70 ^ _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1)
2 0.08 _017_ (net)
1.51 0.02 15.71 ^ _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
15.71 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 65.36 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.11 clock uncertainty
0.00 65.11 clock reconvergence pessimism
-0.09 65.03 library setup time
65.03 data required time
-----------------------------------------------------------------------------
65.03 data required time
-15.71 data arrival time
-----------------------------------------------------------------------------
49.31 slack (MET)
Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[0] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.24 1.21 1.62 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
12 0.23 net2 (net)
1.25 0.02 1.64 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.24 0.46 2.09 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[0] (net)
0.24 0.00 2.10 ^ io_out[0] (out)
2.10 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.10 data arrival time
-----------------------------------------------------------------------------
49.65 slack (MET)
Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[13] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.17 1.15 1.55 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.22 net6 (net)
1.18 0.08 1.63 ^ output6/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.24 0.45 2.08 ^ output6/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[13] (net)
0.24 0.00 2.08 ^ io_out[13] (out)
2.08 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.08 data arrival time
-----------------------------------------------------------------------------
49.67 slack (MET)
Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[14] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
1.19 1.14 1.55 ^ _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1)
6 0.11 net7 (net)
1.19 0.02 1.57 ^ output7/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.24 0.45 2.02 ^ output7/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[14] (net)
0.24 0.00 2.02 ^ io_out[14] (out)
2.02 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.02 data arrival time
-----------------------------------------------------------------------------
49.73 slack (MET)
Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[2] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.05 1.08 1.48 ^ _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
6 0.20 net14 (net)
1.07 0.08 1.56 ^ output14/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.23 0.44 2.00 ^ output14/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[2] (net)
0.23 0.00 2.00 ^ io_out[2] (out)
2.00 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-2.00 data arrival time
-----------------------------------------------------------------------------
49.75 slack (MET)
Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[9] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.08 0.17 0.39 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
18 0.06 clknet_1_1__leaf_wb_clk_i (net)
0.08 0.00 0.39 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
1.08 1.09 1.48 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
10 0.20 net21 (net)
1.08 0.05 1.53 ^ output21/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.23 0.44 1.97 ^ output21/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[9] (net)
0.23 0.00 1.97 ^ io_out[9] (out)
1.97 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-1.97 data arrival time
-----------------------------------------------------------------------------
49.78 slack (MET)
Startpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Endpoint: io_out[11] (output port clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock source latency
0.10 0.05 0.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 0.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.17 0.22 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 0.22 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.18 0.40 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 0.40 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
0.93 1.02 1.42 ^ _109_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
4 0.17 net4 (net)
0.94 0.03 1.45 ^ output4/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
0.23 0.42 1.88 ^ output4/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4)
1 0.07 io_out[11] (net)
0.23 0.00 1.88 ^ io_out[11] (out)
1.88 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock network delay (propagated)
-0.25 64.75 clock uncertainty
0.00 64.75 clock reconvergence pessimism
-13.00 51.75 output external delay
51.75 data required time
-----------------------------------------------------------------------------
51.75 data required time
-1.88 data arrival time
-----------------------------------------------------------------------------
49.87 slack (MET)
max_report_end
check_report
===========================================================================
report_checks -unconstrained
============================================================================
======================= Slowest Corner ===================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
1.05 0.40 13.40 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
1.05 0.00 13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
15.05 10.77 24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
15.05 0.03 24.20 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
7.05 8.58 32.77 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.17 _020_ (net)
7.05 0.02 32.79 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
115.68 78.45 111.25 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.43 _012_ (net)
115.68 0.12 111.36 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
111.36 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 69.02 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.77 clock uncertainty
0.00 68.77 clock reconvergence pessimism
-5.79 62.98 library setup time
62.98 data required time
-----------------------------------------------------------------------------
62.98 data required time
-111.36 data arrival time
-----------------------------------------------------------------------------
-48.38 slack (VIOLATED)
======================= Typical Corner ===================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: tt
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.19 0.07 13.07 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
1.63 0.02 16.44 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
18.95 11.96 28.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.43 _012_ (net)
18.95 0.12 28.52 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
28.52 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.22 0.10 65.10 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.19 0.00 65.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.52 clock uncertainty
0.00 65.52 clock reconvergence pessimism
1.23 66.75 library setup time
66.75 data required time
-----------------------------------------------------------------------------
66.75 data required time
-28.52 data arrival time
-----------------------------------------------------------------------------
38.23 slack (MET)
======================= Fastest Corner ===================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ff
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
0.08 0.03 13.03 ^ wb_rst_i (in)
2 0.00 wb_rst_i (net)
0.08 0.00 13.03 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
1.29 0.88 13.92 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
1.29 0.03 13.94 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
0.79 0.66 14.60 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.18 _020_ (net)
0.79 0.02 14.62 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
7.86 4.79 19.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.43 _012_ (net)
7.87 0.12 19.53 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
19.53 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
0.10 0.05 65.05 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
0.10 0.00 65.05 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.07 0.15 65.20 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.05 clknet_0_wb_clk_i (net)
0.07 0.00 65.20 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.09 0.16 65.36 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.09 0.00 65.37 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 65.12 clock uncertainty
0.00 65.12 clock reconvergence pessimism
0.62 65.73 library setup time
65.73 data required time
-----------------------------------------------------------------------------
65.73 data required time
-19.53 data arrival time
-----------------------------------------------------------------------------
46.20 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= Slowest Corner ===================================
Startpoint: wb_rst_i (input port clocked by wb_clk_i)
Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i)
Path Group: wb_clk_i
Path Type: max
Corner: ss
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock wb_clk_i (rise edge)
0.00 0.00 clock network delay (propagated)
13.00 13.00 ^ input external delay
1.05 0.40 13.40 ^ wb_rst_i (in)
2 0.01 wb_rst_i (net)
1.05 0.00 13.40 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1)
15.05 10.77 24.17 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1)
4 0.12 net1 (net)
15.05 0.03 24.20 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
7.05 8.58 32.77 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3)
20 0.17 _020_ (net)
7.05 0.02 32.79 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
115.68 78.45 111.25 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1)
2 0.43 _012_ (net)
115.68 0.12 111.36 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
111.36 data arrival time
65.00 65.00 clock wb_clk_i (rise edge)
0.00 65.00 clock source latency
1.13 0.49 65.49 ^ wb_clk_i (in)
2 0.03 wb_clk_i (net)
1.13 0.00 65.49 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.74 1.74 67.23 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
2 0.04 clknet_0_wb_clk_i (net)
0.74 0.00 67.23 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
0.98 1.78 69.02 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16)
22 0.08 clknet_1_0__leaf_wb_clk_i (net)
0.98 0.00 69.02 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2)
-0.25 68.77 clock uncertainty
0.00 68.77 clock reconvergence pessimism
-5.79 62.98 library setup time
62.98 data required time
-----------------------------------------------------------------------------
62.98 data required time
-111.36 data arrival time
-----------------------------------------------------------------------------
-48.38 slack (VIOLATED)
======================= Typical Corner ===================================
No paths found.
======================= Fastest Corner ===================================
No paths found.
check_report_end
check_slew
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= Slowest Corner ===================================
max slew
Pin Limit Slew Slack
------------------------------------------------------------
ANTENNA__106__D/I 25.00 115.68 -90.68 (VIOLATED)
_076_/ZN 25.00 115.68 -90.68 (VIOLATED)
_106_/D 25.00 115.68 -90.68 (VIOLATED)
ANTENNA__095__D/I 25.00 60.98 -35.98 (VIOLATED)
_095_/D 25.00 60.98 -35.98 (VIOLATED)
_051_/ZN 25.00 60.98 -35.98 (VIOLATED)
ANTENNA__109__D/I 25.00 60.94 -35.94 (VIOLATED)
_109_/D 25.00 60.94 -35.94 (VIOLATED)
_084_/ZN 25.00 60.94 -35.94 (VIOLATED)
ANTENNA__094__D/I 25.00 60.93 -35.93 (VIOLATED)
_048_/ZN 25.00 60.93 -35.93 (VIOLATED)
_094_/D 25.00 60.93 -35.93 (VIOLATED)
ANTENNA__103__D/I 25.00 57.10 -32.10 (VIOLATED)
_103_/D 25.00 57.10 -32.10 (VIOLATED)
_069_/ZN 25.00 57.10 -32.10 (VIOLATED)
ANTENNA__108__D/I 25.00 51.57 -26.57 (VIOLATED)
_108_/D 25.00 51.57 -26.57 (VIOLATED)
_082_/ZN 25.00 51.57 -26.57 (VIOLATED)
ANTENNA__099__D/I 25.00 50.93 -25.93 (VIOLATED)
_060_/ZN 25.00 50.93 -25.93 (VIOLATED)
_099_/D 25.00 50.93 -25.93 (VIOLATED)
ANTENNA__100__D/I 25.00 50.62 -25.62 (VIOLATED)
_064_/ZN 25.00 50.62 -25.62 (VIOLATED)
_100_/D 25.00 50.62 -25.62 (VIOLATED)
ANTENNA__105__D/I 25.00 50.53 -25.53 (VIOLATED)
_105_/D 25.00 50.53 -25.53 (VIOLATED)
_075_/ZN 25.00 50.53 -25.53 (VIOLATED)
ANTENNA__097__D/I 25.00 44.17 -19.17 (VIOLATED)
_097_/D 25.00 44.17 -19.17 (VIOLATED)
_057_/ZN 25.00 44.17 -19.17 (VIOLATED)
ANTENNA__102__D/I 25.00 37.40 -12.40 (VIOLATED)
_067_/ZN 25.00 37.40 -12.40 (VIOLATED)
_102_/D 25.00 37.40 -12.40 (VIOLATED)
ANTENNA__113__D/I 25.00 37.15 -12.15 (VIOLATED)
_093_/ZN 25.00 37.15 -12.15 (VIOLATED)
_113_/D 25.00 37.15 -12.15 (VIOLATED)
ANTENNA__107__D/I 25.00 37.02 -12.02 (VIOLATED)
_107_/D 25.00 37.02 -12.02 (VIOLATED)
_078_/ZN 25.00 37.02 -12.02 (VIOLATED)
ANTENNA__104__D/I 25.00 36.53 -11.53 (VIOLATED)
_073_/ZN 25.00 36.53 -11.53 (VIOLATED)
_104_/D 25.00 36.53 -11.53 (VIOLATED)
ANTENNA_output10_I/I 25.00 33.05 -8.05 (VIOLATED)
output10/I 25.00 33.05 -8.05 (VIOLATED)
_053_/A2 25.00 33.05 -8.05 (VIOLATED)
_050_/A2 25.00 33.05 -8.05 (VIOLATED)
ANTENNA__053__A2/I 25.00 33.05 -8.05 (VIOLATED)
ANTENNA__050__A2/I 25.00 33.05 -8.05 (VIOLATED)
_052_/A2 25.00 33.05 -8.05 (VIOLATED)
ANTENNA__052__A2/I 25.00 33.05 -8.05 (VIOLATED)
_051_/A2 25.00 33.05 -8.05 (VIOLATED)
ANTENNA__051__A2/I 25.00 33.05 -8.05 (VIOLATED)
_095_/Q 25.00 33.05 -8.05 (VIOLATED)
ANTENNA__061__A2/I 25.00 32.73 -7.73 (VIOLATED)
ANTENNA__062__A2/I 25.00 32.73 -7.73 (VIOLATED)
_061_/A2 25.00 32.73 -7.73 (VIOLATED)
_062_/A2 25.00 32.73 -7.73 (VIOLATED)
ANTENNA__059__A2/I 25.00 32.73 -7.73 (VIOLATED)
_059_/A2 25.00 32.73 -7.73 (VIOLATED)
ANTENNA__060__A2/I 25.00 32.73 -7.73 (VIOLATED)
_060_/A2 25.00 32.73 -7.73 (VIOLATED)
ANTENNA_output13_I/I 25.00 32.73 -7.73 (VIOLATED)
output13/I 25.00 32.73 -7.73 (VIOLATED)
_099_/Q 25.00 32.73 -7.73 (VIOLATED)
ANTENNA__096__D/I 25.00 31.46 -6.46 (VIOLATED)
_096_/D 25.00 31.46 -6.46 (VIOLATED)
_055_/ZN 25.00 31.46 -6.46 (VIOLATED)
ANTENNA_output16_I/I 25.00 29.73 -4.73 (VIOLATED)
output16/I 25.00 29.73 -4.73 (VIOLATED)
_069_/A1 25.00 29.73 -4.73 (VIOLATED)
ANTENNA__069__A1/I 25.00 29.73 -4.73 (VIOLATED)
_068_/A1 25.00 29.73 -4.73 (VIOLATED)
ANTENNA__068__A1/I 25.00 29.73 -4.73 (VIOLATED)
ANTENNA__070__A1/I 25.00 29.73 -4.73 (VIOLATED)
_070_/A1 25.00 29.73 -4.73 (VIOLATED)
_071_/A1 25.00 29.73 -4.73 (VIOLATED)
ANTENNA__071__A1/I 25.00 29.73 -4.73 (VIOLATED)
_067_/A1 25.00 29.73 -4.73 (VIOLATED)
ANTENNA__067__A1/I 25.00 29.73 -4.73 (VIOLATED)
_102_/Q 25.00 29.73 -4.73 (VIOLATED)
ANTENNA__092__A1/I 25.00 29.50 -4.50 (VIOLATED)
_092_/A1 25.00 29.50 -4.50 (VIOLATED)
ANTENNA_output8_I/I 25.00 29.50 -4.50 (VIOLATED)
_113_/Q 25.00 29.50 -4.50 (VIOLATED)
output8/I 25.00 29.50 -4.50 (VIOLATED)
ANTENNA_output5_I/I 25.00 29.22 -4.22 (VIOLATED)
output5/I 25.00 29.22 -4.22 (VIOLATED)
ANTENNA__086__A1/I 25.00 29.21 -4.21 (VIOLATED)
ANTENNA__087__A1/I 25.00 29.21 -4.21 (VIOLATED)
_086_/A1 25.00 29.21 -4.21 (VIOLATED)
_087_/A1 25.00 29.21 -4.21 (VIOLATED)
_088_/A1 25.00 29.21 -4.21 (VIOLATED)
ANTENNA__088__A1/I 25.00 29.21 -4.21 (VIOLATED)
_089_/A1 25.00 29.21 -4.21 (VIOLATED)
ANTENNA__089__A1/I 25.00 29.21 -4.21 (VIOLATED)
_085_/A1 25.00 29.21 -4.21 (VIOLATED)
ANTENNA__085__A1/I 25.00 29.21 -4.21 (VIOLATED)
_110_/Q 25.00 29.21 -4.21 (VIOLATED)
ANTENNA_output3_I/I 25.00 28.12 -3.12 (VIOLATED)
output3/I 25.00 28.12 -3.12 (VIOLATED)
ANTENNA__079__B/I 25.00 28.12 -3.12 (VIOLATED)
_079_/B 25.00 28.12 -3.12 (VIOLATED)
_080_/A3 25.00 28.12 -3.12 (VIOLATED)
ANTENNA__080__A3/I 25.00 28.12 -3.12 (VIOLATED)
_108_/Q 25.00 28.12 -3.12 (VIOLATED)
ANTENNA__112__D/I 25.00 26.61 -1.61 (VIOLATED)
_091_/ZN 25.00 26.61 -1.61 (VIOLATED)
_112_/D 25.00 26.61 -1.61 (VIOLATED)
output17/I 25.00 25.59 -0.59 (VIOLATED)
ANTENNA_output17_I/I 25.00 25.59 -0.59 (VIOLATED)
_069_/A2 25.00 25.58 -0.58 (VIOLATED)
_068_/A2 25.00 25.58 -0.58 (VIOLATED)
ANTENNA__069__A2/I 25.00 25.58 -0.58 (VIOLATED)
ANTENNA__068__A2/I 25.00 25.58 -0.58 (VIOLATED)
_070_/A2 25.00 25.58 -0.58 (VIOLATED)
ANTENNA__070__A2/I 25.00 25.58 -0.58 (VIOLATED)
_071_/A2 25.00 25.58 -0.58 (VIOLATED)
ANTENNA__071__A2/I 25.00 25.58 -0.58 (VIOLATED)
_103_/Q 25.00 25.58 -0.58 (VIOLATED)
max capacitance
Pin Limit Cap Slack
------------------------------------------------------------
_076_/ZN 0.09 0.43 -0.35 (VIOLATED)
_095_/Q 0.39 0.53 -0.14 (VIOLATED)
_084_/ZN 0.09 0.23 -0.14 (VIOLATED)
_048_/ZN 0.09 0.23 -0.14 (VIOLATED)
_051_/ZN 0.09 0.22 -0.14 (VIOLATED)
_099_/Q 0.39 0.52 -0.13 (VIOLATED)
_069_/ZN 0.09 0.21 -0.12 (VIOLATED)
_082_/ZN 0.09 0.19 -0.10 (VIOLATED)
_064_/ZN 0.09 0.19 -0.10 (VIOLATED)
_060_/ZN 0.09 0.19 -0.10 (VIOLATED)
_075_/ZN 0.09 0.19 -0.10 (VIOLATED)
_102_/Q 0.39 0.47 -0.09 (VIOLATED)
_110_/Q 0.39 0.46 -0.08 (VIOLATED)
_057_/ZN 0.09 0.16 -0.08 (VIOLATED)
_108_/Q 0.39 0.45 -0.06 (VIOLATED)
_067_/ZN 0.09 0.14 -0.05 (VIOLATED)
_093_/ZN 0.09 0.14 -0.05 (VIOLATED)
_078_/ZN 0.09 0.13 -0.05 (VIOLATED)
_073_/ZN 0.09 0.13 -0.05 (VIOLATED)
_113_/Q 0.19 0.23 -0.04 (VIOLATED)
_055_/ZN 0.09 0.12 -0.03 (VIOLATED)
_103_/Q 0.39 0.41 -0.02 (VIOLATED)
_091_/ZN 0.09 0.10 -0.01 (VIOLATED)
_105_/Q 0.19 0.20 -0.00 (VIOLATED)
_058_/ZN 0.09 0.09 -0.00 (VIOLATED)
======================= Typical Corner ===================================
max slew
Pin Limit Slew Slack
------------------------------------------------------------
ANTENNA__106__D/I 8.60 18.95 -10.35 (VIOLATED)
_106_/D 8.60 18.95 -10.35 (VIOLATED)
_076_/ZN 8.60 18.95 -10.35 (VIOLATED)
_095_/D 8.60 10.03 -1.43 (VIOLATED)
ANTENNA__095__D/I 8.60 10.03 -1.43 (VIOLATED)
_051_/ZN 8.60 10.03 -1.43 (VIOLATED)
_109_/D 8.60 10.00 -1.40 (VIOLATED)
ANTENNA__109__D/I 8.60 10.00 -1.40 (VIOLATED)
_084_/ZN 8.60 10.00 -1.40 (VIOLATED)
_094_/D 8.60 9.99 -1.39 (VIOLATED)
ANTENNA__094__D/I 8.60 9.99 -1.39 (VIOLATED)
_048_/ZN 8.60 9.99 -1.39 (VIOLATED)
_103_/D 8.60 9.40 -0.80 (VIOLATED)
ANTENNA__103__D/I 8.60 9.40 -0.80 (VIOLATED)
_069_/ZN 8.60 9.40 -0.80 (VIOLATED)
max capacitance
Pin Limit Cap Slack
------------------------------------------------------------
_076_/ZN 0.18 0.43 -0.25 (VIOLATED)
_084_/ZN 0.18 0.23 -0.04 (VIOLATED)
_048_/ZN 0.18 0.23 -0.04 (VIOLATED)
_051_/ZN 0.18 0.22 -0.04 (VIOLATED)
_069_/ZN 0.18 0.21 -0.03 (VIOLATED)
_082_/ZN 0.18 0.19 -0.01 (VIOLATED)
_060_/ZN 0.18 0.19 -0.01 (VIOLATED)
_064_/ZN 0.18 0.19 -0.01 (VIOLATED)
_075_/ZN 0.18 0.19 -0.00 (VIOLATED)
======================= Fastest Corner ===================================
max slew
Pin Limit Slew Slack
------------------------------------------------------------
_106_/D 2.60 7.87 -5.27 (VIOLATED)
ANTENNA__106__D/I 2.60 7.87 -5.27 (VIOLATED)
_076_/ZN 2.60 7.86 -5.26 (VIOLATED)
_095_/D 2.60 4.18 -1.58 (VIOLATED)
ANTENNA__095__D/I 2.60 4.18 -1.58 (VIOLATED)
_051_/ZN 2.60 4.18 -1.58 (VIOLATED)
_109_/D 2.60 4.17 -1.57 (VIOLATED)
ANTENNA__109__D/I 2.60 4.17 -1.57 (VIOLATED)
_084_/ZN 2.60 4.16 -1.56 (VIOLATED)
_094_/D 2.60 4.15 -1.55 (VIOLATED)
ANTENNA__094__D/I 2.60 4.15 -1.55 (VIOLATED)
_048_/ZN 2.60 4.15 -1.55 (VIOLATED)
_103_/D 2.60 3.92 -1.32 (VIOLATED)
ANTENNA__103__D/I 2.60 3.92 -1.32 (VIOLATED)
_069_/ZN 2.60 3.92 -1.32 (VIOLATED)
_108_/D 2.60 3.53 -0.93 (VIOLATED)
ANTENNA__108__D/I 2.60 3.53 -0.93 (VIOLATED)
_082_/ZN 2.60 3.52 -0.92 (VIOLATED)
_099_/D 2.60 3.50 -0.90 (VIOLATED)
ANTENNA__099__D/I 2.60 3.50 -0.90 (VIOLATED)
_060_/ZN 2.60 3.50 -0.90 (VIOLATED)
_100_/D 2.60 3.46 -0.86 (VIOLATED)
ANTENNA__100__D/I 2.60 3.46 -0.86 (VIOLATED)
_064_/ZN 2.60 3.46 -0.86 (VIOLATED)
_105_/D 2.60 3.45 -0.85 (VIOLATED)
ANTENNA__105__D/I 2.60 3.45 -0.85 (VIOLATED)
_075_/ZN 2.60 3.45 -0.85 (VIOLATED)
_097_/D 2.60 3.02 -0.42 (VIOLATED)
ANTENNA__097__D/I 2.60 3.02 -0.42 (VIOLATED)
_057_/ZN 2.60 3.02 -0.42 (VIOLATED)
output10/I 2.60 2.83 -0.23 (VIOLATED)
ANTENNA_output10_I/I 2.60 2.83 -0.23 (VIOLATED)
_053_/A2 2.60 2.81 -0.21 (VIOLATED)
_050_/A2 2.60 2.81 -0.21 (VIOLATED)
ANTENNA__053__A2/I 2.60 2.81 -0.21 (VIOLATED)
ANTENNA__050__A2/I 2.60 2.81 -0.21 (VIOLATED)
_052_/A2 2.60 2.81 -0.21 (VIOLATED)
ANTENNA__052__A2/I 2.60 2.81 -0.21 (VIOLATED)
_051_/A2 2.60 2.81 -0.21 (VIOLATED)
ANTENNA__051__A2/I 2.60 2.81 -0.21 (VIOLATED)
_062_/A2 2.60 2.79 -0.19 (VIOLATED)
ANTENNA__062__A2/I 2.60 2.79 -0.19 (VIOLATED)
_061_/A2 2.60 2.79 -0.19 (VIOLATED)
ANTENNA__061__A2/I 2.60 2.79 -0.19 (VIOLATED)
_059_/A2 2.60 2.79 -0.19 (VIOLATED)
ANTENNA__059__A2/I 2.60 2.79 -0.19 (VIOLATED)
ANTENNA__060__A2/I 2.60 2.79 -0.19 (VIOLATED)
_060_/A2 2.60 2.79 -0.19 (VIOLATED)
output13/I 2.60 2.79 -0.19 (VIOLATED)
ANTENNA_output13_I/I 2.60 2.79 -0.19 (VIOLATED)
_095_/Q 2.60 2.79 -0.19 (VIOLATED)
_099_/Q 2.60 2.78 -0.18 (VIOLATED)
max capacitance
Pin Limit Cap Slack
------------------------------------------------------------
_076_/ZN 0.13 0.43 -0.30 (VIOLATED)
_084_/ZN 0.13 0.23 -0.10 (VIOLATED)
_048_/ZN 0.13 0.23 -0.10 (VIOLATED)
_051_/ZN 0.13 0.22 -0.09 (VIOLATED)
_069_/ZN 0.13 0.21 -0.08 (VIOLATED)
_082_/ZN 0.13 0.19 -0.06 (VIOLATED)
_095_/Q 0.47 0.53 -0.06 (VIOLATED)
_064_/ZN 0.13 0.19 -0.06 (VIOLATED)
_060_/ZN 0.13 0.19 -0.06 (VIOLATED)
_075_/ZN 0.13 0.19 -0.06 (VIOLATED)
_099_/Q 0.47 0.52 -0.05 (VIOLATED)
_057_/ZN 0.13 0.16 -0.03 (VIOLATED)
_067_/ZN 0.13 0.14 -0.01 (VIOLATED)
_102_/Q 0.47 0.47 -0.01 (VIOLATED)
_093_/ZN 0.13 0.14 -0.01 (VIOLATED)
_078_/ZN 0.13 0.13 -0.00 (VIOLATED)
_073_/ZN 0.13 0.13 -0.00 (VIOLATED)
_113_/Q 0.23 0.23 -0.00 (VIOLATED)
===========================================================================
max slew violation count 119
max fanout violation count 0
max cap violation count 25
============================================================================
check_slew_end
tns_report
===========================================================================
report_tns
============================================================================
tns -198.89
tns_report_end
wns_report
===========================================================================
report_wns
============================================================================
wns -48.38
wns_report_end
worst_slack
===========================================================================
report_worst_slack -max (Setup)
============================================================================
worst slack -48.38
===========================================================================
report_worst_slack -min (Hold)
============================================================================
worst slack 1.50
worst_slack_end
clock_skew
===========================================================================
report_clock_skew
============================================================================
======================== Slowest Corner ==================================
Clock wb_clk_i
Latency CRPR Skew
_106_/CLK ^
4.44
_107_/CLK ^
3.90 -0.24 0.30
======================= Typical Corner ===================================
Clock wb_clk_i
Latency CRPR Skew
_106_/CLK ^
0.86
_107_/CLK ^
0.75 -0.05 0.06
======================= Fastest Corner ===================================
Clock wb_clk_i
Latency CRPR Skew
_106_/CLK ^
0.40
_107_/CLK ^
0.36 -0.02 0.03
clock_skew_end
power_report
===========================================================================
report_power
============================================================================
======================= Slowest Corner =================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
Sequential 1.91e-05 1.41e-05 3.38e-09 3.32e-05 39.7%
Combinational 1.73e-05 2.04e-05 1.27e-05 5.04e-05 60.3%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 3.64e-05 3.45e-05 1.27e-05 8.36e-05 100.0%
43.5% 41.3% 15.2%
======================= Typical Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
Sequential 7.17e-05 5.86e-05 1.98e-09 1.30e-04 44.9%
Combinational 7.29e-05 8.57e-05 1.28e-06 1.60e-04 55.1%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 1.45e-04 1.44e-04 1.28e-06 2.90e-04 100.0%
49.8% 49.7% 0.4%
======================= Fastest Corner =================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
Sequential 2.09e-04 1.63e-04 4.84e-09 3.72e-04 42.6%
Combinational 2.61e-04 2.37e-04 3.55e-06 5.02e-04 57.4%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 4.70e-04 4.00e-04 3.56e-06 8.74e-04 100.0%
53.8% 45.8% 0.4%
power_report_end
area_report
===========================================================================
report_design_area
============================================================================
Design area 68288 u^2 3% utilization.
area_report_end
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing SDF files for all corners...
Writing SDF for the ff corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.ff.sdf...
Writing SDF for the ss corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.ss.sdf...
Writing SDF for the tt corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.tt.sdf...
Writing timing models for all corners...
Writing timing models for the ff corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.ff.lib...
Writing timing models for the ss corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.ss.lib...
Writing timing models for the tt corner to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.tt.lib...