| OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| min_report |
| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.22 0.10 0.10 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.08 clknet_1_0__leaf_wb_clk_i (net) |
| 0.19 0.00 0.77 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 1.35 1.72 2.49 v _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 10 0.22 net6 (net) |
| 1.36 0.06 2.55 v _086_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.47 0.58 3.13 ^ _086_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.01 _042_ (net) |
| 0.47 0.00 3.13 ^ _087_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1.55 1.04 4.17 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 2 0.08 _017_ (net) |
| 1.55 0.01 4.19 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 4.19 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.22 0.11 0.11 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.08 clknet_1_0__leaf_wb_clk_i (net) |
| 0.19 0.00 0.85 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.25 1.10 clock uncertainty |
| -0.08 1.02 clock reconvergence pessimism |
| -0.29 0.73 library hold time |
| 0.73 data required time |
| ----------------------------------------------------------------------------- |
| 0.73 data required time |
| -4.19 data arrival time |
| ----------------------------------------------------------------------------- |
| 3.46 slack (MET) |
| |
| |
| Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.22 0.10 0.10 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.08 clknet_1_0__leaf_wb_clk_i (net) |
| 0.19 0.00 0.77 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.36 1.66 2.43 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.11 net7 (net) |
| 1.36 0.03 2.46 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.81 0.74 3.19 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 2 0.02 _043_ (net) |
| 0.81 0.00 3.19 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1.70 1.19 4.38 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.10 _018_ (net) |
| 1.70 0.02 4.40 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4.40 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.22 0.11 0.11 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.08 clknet_1_0__leaf_wb_clk_i (net) |
| 0.19 0.00 0.85 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 1.10 clock uncertainty |
| -0.08 1.02 clock reconvergence pessimism |
| -0.35 0.67 library hold time |
| 0.67 data required time |
| ----------------------------------------------------------------------------- |
| 0.67 data required time |
| -4.40 data arrival time |
| ----------------------------------------------------------------------------- |
| 3.73 slack (MET) |
| |
| |
| Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.22 0.10 0.10 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.19 0.34 0.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.08 clknet_1_0__leaf_wb_clk_i (net) |
| 0.19 0.00 0.77 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 1.44 1.79 2.56 v _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 12 0.23 net2 (net) |
| 1.44 0.04 2.60 v _058_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 4.10 2.67 5.27 ^ _058_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.09 _004_ (net) |
| 4.10 0.02 5.29 ^ _098_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 5.29 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.22 0.11 0.11 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.47 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.19 0.38 0.85 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.08 clknet_1_0__leaf_wb_clk_i (net) |
| 0.19 0.00 0.85 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.25 1.10 clock uncertainty |
| -0.08 1.02 clock reconvergence pessimism |
| 0.30 1.32 library hold time |
| 1.32 data required time |
| ----------------------------------------------------------------------------- |
| 1.32 data required time |
| -5.29 data arrival time |
| ----------------------------------------------------------------------------- |
| 3.97 slack (MET) |
| |
| |
| Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.22 0.10 0.10 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.06 clknet_1_1__leaf_wb_clk_i (net) |
| 0.17 0.00 0.75 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.08 2.05 2.81 v _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4 0.17 net15 (net) |
| 2.08 0.04 2.84 v _065_/A1 (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 0.47 0.78 3.63 ^ _065_/Z (gf180mcu_fd_sc_mcu7t5v0__xor2_1) |
| 1 0.01 _031_ (net) |
| 0.47 0.00 3.63 ^ _066_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1.57 1.05 4.68 v _066_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.09 _007_ (net) |
| 1.57 0.02 4.70 v _101_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 4.70 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.22 0.11 0.11 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.06 clknet_1_1__leaf_wb_clk_i (net) |
| 0.17 0.00 0.83 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.25 1.08 clock uncertainty |
| -0.08 1.00 clock reconvergence pessimism |
| -0.33 0.68 library hold time |
| 0.68 data required time |
| ----------------------------------------------------------------------------- |
| 0.68 data required time |
| -4.70 data arrival time |
| ----------------------------------------------------------------------------- |
| 4.02 slack (MET) |
| |
| |
| Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.22 0.10 0.10 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 0.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.33 0.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.17 0.32 0.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.06 clknet_1_1__leaf_wb_clk_i (net) |
| 0.17 0.00 0.75 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 1.24 1.65 2.41 v _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 10 0.20 net21 (net) |
| 1.25 0.07 2.47 v _077_/A2 (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 0.44 0.51 2.98 ^ _077_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.01 _037_ (net) |
| 0.44 0.00 2.98 ^ _078_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 2.61 1.64 4.63 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 2 0.13 _013_ (net) |
| 2.61 0.04 4.66 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 4.66 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.22 0.11 0.11 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 0.11 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.37 0.47 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.47 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.17 0.36 0.83 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.06 clknet_1_1__leaf_wb_clk_i (net) |
| 0.17 0.00 0.83 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.25 1.08 clock uncertainty |
| -0.08 1.00 clock reconvergence pessimism |
| -0.56 0.44 library hold time |
| 0.44 data required time |
| ----------------------------------------------------------------------------- |
| 0.44 data required time |
| -4.66 data arrival time |
| ----------------------------------------------------------------------------- |
| 4.22 slack (MET) |
| |
| |
| min_report_end |
| max_report |
| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 13.00 13.00 ^ input external delay |
| 0.19 0.07 13.07 ^ wb_rst_i (in) |
| 2 0.00 wb_rst_i (net) |
| 0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.12 net1 (net) |
| 2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3) |
| 1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3) |
| 20 0.18 _020_ (net) |
| 1.63 0.02 16.44 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 18.95 11.96 28.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.43 _012_ (net) |
| 18.95 0.12 28.52 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 28.52 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock source latency |
| 0.22 0.10 65.10 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.08 clknet_1_0__leaf_wb_clk_i (net) |
| 0.19 0.00 65.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| -0.25 65.52 clock uncertainty |
| 0.00 65.52 clock reconvergence pessimism |
| 1.23 66.75 library setup time |
| 66.75 data required time |
| ----------------------------------------------------------------------------- |
| 66.75 data required time |
| -28.52 data arrival time |
| ----------------------------------------------------------------------------- |
| 38.23 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 13.00 13.00 ^ input external delay |
| 0.19 0.07 13.07 ^ wb_rst_i (in) |
| 2 0.00 wb_rst_i (net) |
| 0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.12 net1 (net) |
| 2.79 0.03 15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 1.63 1.30 16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 20 0.14 _021_ (net) |
| 1.63 0.00 16.32 ^ _050_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1.44 0.51 16.84 v _050_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 2 0.02 _022_ (net) |
| 1.44 0.00 16.84 v _051_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 10.03 6.54 23.38 ^ _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 2 0.22 _001_ (net) |
| 10.03 0.07 23.45 ^ _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 23.45 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock source latency |
| 0.22 0.10 65.10 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 65.43 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.17 0.32 65.75 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 18 0.06 clknet_1_1__leaf_wb_clk_i (net) |
| 0.17 0.00 65.75 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| -0.25 65.50 clock uncertainty |
| 0.00 65.50 clock reconvergence pessimism |
| 0.26 65.77 library setup time |
| 65.77 data required time |
| ----------------------------------------------------------------------------- |
| 65.77 data required time |
| -23.45 data arrival time |
| ----------------------------------------------------------------------------- |
| 42.32 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _109_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 13.00 13.00 ^ input external delay |
| 0.19 0.07 13.07 ^ wb_rst_i (in) |
| 2 0.00 wb_rst_i (net) |
| 0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.12 net1 (net) |
| 2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3) |
| 1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3) |
| 20 0.18 _020_ (net) |
| 1.62 0.02 16.44 v _084_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 10.00 6.59 23.02 ^ _084_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.23 _015_ (net) |
| 10.00 0.08 23.10 ^ _109_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 23.10 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock source latency |
| 0.22 0.10 65.10 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.08 clknet_1_0__leaf_wb_clk_i (net) |
| 0.19 0.00 65.77 ^ _109_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| -0.25 65.52 clock uncertainty |
| 0.00 65.52 clock reconvergence pessimism |
| 0.27 65.79 library setup time |
| 65.79 data required time |
| ----------------------------------------------------------------------------- |
| 65.79 data required time |
| -23.10 data arrival time |
| ----------------------------------------------------------------------------- |
| 42.69 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 13.00 13.00 ^ input external delay |
| 0.19 0.07 13.07 ^ wb_rst_i (in) |
| 2 0.00 wb_rst_i (net) |
| 0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.12 net1 (net) |
| 2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3) |
| 1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3) |
| 20 0.18 _020_ (net) |
| 1.63 0.02 16.45 v _048_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 9.99 6.50 22.95 ^ _048_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.23 _000_ (net) |
| 9.99 0.05 23.00 ^ _094_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 23.00 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock source latency |
| 0.22 0.10 65.10 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.08 clknet_1_0__leaf_wb_clk_i (net) |
| 0.19 0.00 65.77 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| -0.25 65.52 clock uncertainty |
| 0.00 65.52 clock reconvergence pessimism |
| 0.27 65.79 library setup time |
| 65.79 data required time |
| ----------------------------------------------------------------------------- |
| 65.79 data required time |
| -23.00 data arrival time |
| ----------------------------------------------------------------------------- |
| 42.79 slack (MET) |
| |
| |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _103_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 13.00 13.00 ^ input external delay |
| 0.19 0.07 13.07 ^ wb_rst_i (in) |
| 2 0.00 wb_rst_i (net) |
| 0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.12 net1 (net) |
| 2.79 0.03 15.02 ^ _049_/I (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 1.63 1.30 16.32 ^ _049_/Z (gf180mcu_fd_sc_mcu7t5v0__buf_2) |
| 20 0.14 _021_ (net) |
| 1.63 0.01 16.33 ^ _068_/B (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1.03 0.36 16.69 v _068_/ZN (gf180mcu_fd_sc_mcu7t5v0__oai21_1) |
| 1 0.01 _032_ (net) |
| 1.03 0.00 16.69 v _069_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 9.40 6.08 22.77 ^ _069_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 2 0.21 _009_ (net) |
| 9.40 0.06 22.83 ^ _103_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 22.83 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock source latency |
| 0.22 0.10 65.10 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.08 clknet_1_0__leaf_wb_clk_i (net) |
| 0.19 0.00 65.77 ^ _103_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| -0.25 65.52 clock uncertainty |
| 0.00 65.52 clock reconvergence pessimism |
| 0.20 65.73 library setup time |
| 65.73 data required time |
| ----------------------------------------------------------------------------- |
| 65.73 data required time |
| -22.83 data arrival time |
| ----------------------------------------------------------------------------- |
| 42.90 slack (MET) |
| |
| |
| max_report_end |
| check_report |
| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: wb_rst_i (input port clocked by wb_clk_i) |
| Endpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (propagated) |
| 13.00 13.00 ^ input external delay |
| 0.19 0.07 13.07 ^ wb_rst_i (in) |
| 2 0.00 wb_rst_i (net) |
| 0.19 0.00 13.07 ^ input1/I (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 2.79 1.92 14.99 ^ input1/Z (gf180mcu_fd_sc_mcu7t5v0__buf_1) |
| 4 0.12 net1 (net) |
| 2.79 0.03 15.02 ^ _047_/I (gf180mcu_fd_sc_mcu7t5v0__clkinv_3) |
| 1.62 1.40 16.42 v _047_/ZN (gf180mcu_fd_sc_mcu7t5v0__clkinv_3) |
| 20 0.18 _020_ (net) |
| 1.63 0.02 16.44 v _076_/A2 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 18.95 11.96 28.41 ^ _076_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 2 0.43 _012_ (net) |
| 18.95 0.12 28.52 ^ _106_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 28.52 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock source latency |
| 0.22 0.10 65.10 ^ wb_clk_i (in) |
| 2 0.03 wb_clk_i (net) |
| 0.22 0.00 65.10 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.33 65.43 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.05 clknet_0_wb_clk_i (net) |
| 0.15 0.00 65.43 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.19 0.34 65.77 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 22 0.08 clknet_1_0__leaf_wb_clk_i (net) |
| 0.19 0.00 65.77 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| -0.25 65.52 clock uncertainty |
| 0.00 65.52 clock reconvergence pessimism |
| 1.23 66.75 library setup time |
| 66.75 data required time |
| ----------------------------------------------------------------------------- |
| 66.75 data required time |
| -28.52 data arrival time |
| ----------------------------------------------------------------------------- |
| 38.23 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
| check_report_end |
| check_slew |
| |
| =========================================================================== |
| report_check_types -max_slew -max_cap -max_fanout -violators |
| ============================================================================ |
| max slew |
| |
| Pin Limit Slew Slack |
| ------------------------------------------------------------ |
| ANTENNA__106__D/I 8.60 18.95 -10.35 (VIOLATED) |
| _106_/D 8.60 18.95 -10.35 (VIOLATED) |
| _076_/ZN 8.60 18.95 -10.35 (VIOLATED) |
| _095_/D 8.60 10.03 -1.43 (VIOLATED) |
| ANTENNA__095__D/I 8.60 10.03 -1.43 (VIOLATED) |
| _051_/ZN 8.60 10.03 -1.43 (VIOLATED) |
| _109_/D 8.60 10.00 -1.40 (VIOLATED) |
| ANTENNA__109__D/I 8.60 10.00 -1.40 (VIOLATED) |
| _084_/ZN 8.60 10.00 -1.40 (VIOLATED) |
| _094_/D 8.60 9.99 -1.39 (VIOLATED) |
| ANTENNA__094__D/I 8.60 9.99 -1.39 (VIOLATED) |
| _048_/ZN 8.60 9.99 -1.39 (VIOLATED) |
| _103_/D 8.60 9.40 -0.80 (VIOLATED) |
| ANTENNA__103__D/I 8.60 9.40 -0.80 (VIOLATED) |
| _069_/ZN 8.60 9.40 -0.80 (VIOLATED) |
| |
| max capacitance |
| |
| Pin Limit Cap Slack |
| ------------------------------------------------------------ |
| _076_/ZN 0.18 0.43 -0.25 (VIOLATED) |
| _084_/ZN 0.18 0.23 -0.04 (VIOLATED) |
| _048_/ZN 0.18 0.23 -0.04 (VIOLATED) |
| _051_/ZN 0.18 0.22 -0.04 (VIOLATED) |
| _069_/ZN 0.18 0.21 -0.03 (VIOLATED) |
| _082_/ZN 0.18 0.19 -0.01 (VIOLATED) |
| _060_/ZN 0.18 0.19 -0.01 (VIOLATED) |
| _064_/ZN 0.18 0.19 -0.01 (VIOLATED) |
| _075_/ZN 0.18 0.19 -0.00 (VIOLATED) |
| |
| |
| =========================================================================== |
| max slew violation count 15 |
| max fanout violation count 0 |
| max cap violation count 9 |
| ============================================================================ |
| check_slew_end |
| tns_report |
| |
| =========================================================================== |
| report_tns |
| ============================================================================ |
| tns 0.00 |
| tns_report_end |
| wns_report |
| |
| =========================================================================== |
| report_wns |
| ============================================================================ |
| wns 0.00 |
| wns_report_end |
| worst_slack |
| |
| =========================================================================== |
| report_worst_slack -max (Setup) |
| ============================================================================ |
| worst slack 38.23 |
| |
| =========================================================================== |
| report_worst_slack -min (Hold) |
| ============================================================================ |
| worst slack 3.46 |
| worst_slack_end |
| clock_skew |
| |
| =========================================================================== |
| report_clock_skew |
| ============================================================================ |
| Clock wb_clk_i |
| Latency CRPR Skew |
| _106_/CLK ^ |
| 0.86 |
| _107_/CLK ^ |
| 0.75 -0.05 0.06 |
| |
| clock_skew_end |
| power_report |
| |
| =========================================================================== |
| report_power |
| ============================================================================ |
| Group Internal Switching Leakage Total |
| Power Power Power Power (Watts) |
| ---------------------------------------------------------------- |
| Sequential 7.17e-05 5.86e-05 1.98e-09 1.30e-04 44.9% |
| Combinational 7.29e-05 8.57e-05 1.28e-06 1.60e-04 55.1% |
| Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| ---------------------------------------------------------------- |
| Total 1.45e-04 1.44e-04 1.28e-06 2.90e-04 100.0% |
| 49.8% 49.7% 0.4% |
| power_report_end |
| area_report |
| |
| =========================================================================== |
| report_design_area |
| ============================================================================ |
| Design area 68288 u^2 3% utilization. |
| area_report_end |
| Setting global connections for newly added cells... |
| [WARNING] Did not save OpenROAD database! |
| Writing SDF to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.sdf... |
| Writing timing model to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/routing/mca/process_corner_nom/cntr_example.lib... |
