| OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO ODB-0222] Reading LEF file: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef |
| [INFO ODB-0223] Created 13 technology layers |
| [INFO ODB-0224] Created 60 technology vias |
| [INFO ODB-0225] Created 229 library cells |
| [INFO ODB-0226] Finished LEF file: /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/merged.nom.lef |
| Reading netlist... |
| [INFO]: Setting output delay to: 13.0 |
| [INFO]: Setting input delay to: 13.0 |
| [INFO]: Setting load to: 0.07291 |
| [INFO]: Setting clock uncertainty to: 0.25 |
| [INFO]: Setting clock transition to: 0.15 |
| [INFO]: Setting timing derate to: 0.5 % |
| min_report |
| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _096_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.05 1.46 1.46 v _096_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.08 io_out[18] (net) |
| 1.05 0.00 1.46 v _052_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.47 0.44 1.90 ^ _052_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _023_ (net) |
| 0.47 0.00 1.90 ^ _055_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.17 0.14 2.03 v _055_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.00 _002_ (net) |
| 0.17 0.00 2.03 v _096_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.03 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _096_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.07 0.32 library hold time |
| 0.32 data required time |
| ----------------------------------------------------------------------------- |
| 0.32 data required time |
| -2.03 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.72 slack (MET) |
| |
| |
| Startpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _100_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.05 1.46 1.46 v _100_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.08 io_out[2] (net) |
| 1.05 0.00 1.46 v _061_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.47 0.44 1.90 ^ _061_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _028_ (net) |
| 0.47 0.00 1.90 ^ _064_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.17 0.14 2.03 v _064_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.00 _006_ (net) |
| 0.17 0.00 2.03 v _100_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.03 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _100_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.07 0.32 library hold time |
| 0.32 data required time |
| ----------------------------------------------------------------------------- |
| 0.32 data required time |
| -2.03 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.72 slack (MET) |
| |
| |
| Startpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _104_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.05 1.46 1.46 v _104_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.08 io_out[6] (net) |
| 1.05 0.00 1.46 v _070_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.47 0.44 1.90 ^ _070_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _033_ (net) |
| 0.47 0.00 1.90 ^ _073_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.17 0.14 2.03 v _073_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.00 _010_ (net) |
| 0.17 0.00 2.03 v _104_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.03 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _104_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.07 0.32 library hold time |
| 0.32 data required time |
| ----------------------------------------------------------------------------- |
| 0.32 data required time |
| -2.03 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.72 slack (MET) |
| |
| |
| Startpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _108_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.05 1.46 1.46 v _108_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.08 io_out[10] (net) |
| 1.05 0.00 1.46 v _079_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.47 0.44 1.90 ^ _079_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _038_ (net) |
| 0.47 0.00 1.90 ^ _082_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.17 0.14 2.03 v _082_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.00 _014_ (net) |
| 0.17 0.00 2.03 v _108_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.03 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _108_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.07 0.32 library hold time |
| 0.32 data required time |
| ----------------------------------------------------------------------------- |
| 0.32 data required time |
| -2.03 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.72 slack (MET) |
| |
| |
| Startpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _112_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 1.05 1.46 1.46 v _112_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 3 0.08 io_out[14] (net) |
| 1.05 0.00 1.46 v _088_/B (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.47 0.44 1.90 ^ _088_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.00 _043_ (net) |
| 0.47 0.00 1.90 ^ _091_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.17 0.14 2.03 v _091_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.00 _018_ (net) |
| 0.17 0.00 2.03 v _112_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.03 data arrival time |
| |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _112_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.07 0.32 library hold time |
| 0.32 data required time |
| ----------------------------------------------------------------------------- |
| 0.32 data required time |
| -2.03 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.72 slack (MET) |
| |
| |
| min_report_end |
| max_report |
| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[0] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.35 2.41 2.41 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.10 io_out[0] (net) |
| 2.35 0.00 2.41 ^ io_out[0] (out) |
| 2.41 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -2.41 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.34 slack (MET) |
| |
| |
| Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[12] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.35 2.41 2.41 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.10 io_out[12] (net) |
| 2.35 0.00 2.41 ^ io_out[12] (out) |
| 2.41 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -2.41 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.34 slack (MET) |
| |
| |
| Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[16] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.35 2.41 2.41 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.10 io_out[16] (net) |
| 2.35 0.00 2.41 ^ io_out[16] (out) |
| 2.41 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -2.41 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.34 slack (MET) |
| |
| |
| Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[4] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.35 2.41 2.41 ^ _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.10 io_out[4] (net) |
| 2.35 0.00 2.41 ^ io_out[4] (out) |
| 2.41 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -2.41 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.34 slack (MET) |
| |
| |
| Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[8] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.35 2.41 2.41 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.10 io_out[8] (net) |
| 2.35 0.00 2.41 ^ io_out[8] (out) |
| 2.41 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -2.41 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.34 slack (MET) |
| |
| |
| max_report_end |
| check_report |
| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[0] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2.35 2.41 2.41 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 6 0.10 io_out[0] (net) |
| 2.35 0.00 2.41 ^ io_out[0] (out) |
| 2.41 data arrival time |
| |
| 0.15 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (ideal) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -2.41 data arrival time |
| ----------------------------------------------------------------------------- |
| 49.34 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
| check_report_end |
| check_slew |
| |
| =========================================================================== |
| report_check_types -max_slew -max_cap -max_fanout -violators |
| ============================================================================ |
| |
| =========================================================================== |
| max slew violation count 0 |
| max fanout violation count 0 |
| max cap violation count 0 |
| ============================================================================ |
| check_slew_end |
| tns_report |
| |
| =========================================================================== |
| report_tns |
| ============================================================================ |
| tns 0.00 |
| tns_report_end |
| wns_report |
| |
| =========================================================================== |
| report_wns |
| ============================================================================ |
| wns 0.00 |
| wns_report_end |
| worst_slack |
| |
| =========================================================================== |
| report_worst_slack -max (Setup) |
| ============================================================================ |
| worst slack 49.34 |
| |
| =========================================================================== |
| report_worst_slack -min (Hold) |
| ============================================================================ |
| worst slack 1.72 |
| worst_slack_end |
| clock_skew |
| |
| =========================================================================== |
| report_clock_skew |
| ============================================================================ |
| Clock wb_clk_i |
| Latency CRPR Skew |
| _094_/CLK ^ |
| 0.23 |
| _094_/CLK ^ |
| 0.21 0.00 0.02 |
| |
| clock_skew_end |
| power_report |
| |
| =========================================================================== |
| report_power |
| ============================================================================ |
| Group Internal Switching Leakage Total |
| Power Power Power Power (Watts) |
| ---------------------------------------------------------------- |
| Sequential 6.99e-05 1.61e-05 1.89e-09 8.60e-05 92.8% |
| Combinational 4.47e-06 2.19e-06 2.66e-09 6.66e-06 7.2% |
| Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| ---------------------------------------------------------------- |
| Total 7.43e-05 1.83e-05 4.55e-09 9.26e-05 100.0% |
| 80.2% 19.8% 0.0% |
| power_report_end |
| area_report |
| |
| =========================================================================== |
| report_design_area |
| ============================================================================ |
| Design area 2178 u^2 100% utilization. |
| area_report_end |
| [WARNING] Did not save OpenROAD database! |
| Writing SDF to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/results/synthesis/cntr_example.sdf... |
