| OpenROAD 7f00621cb612fd94e15b35790afe744c89d433a7 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO]: Setting RC values... |
| [INFO RSZ-0033] No hold violations found. |
| Placement Analysis |
| --------------------------------- |
| total displacement 0.0 u |
| average displacement 0.0 u |
| max displacement 0.0 u |
| original HPWL 60457.6 u |
| legalized HPWL 60593.7 u |
| delta HPWL 0 % |
| |
| [INFO DPL-0020] Mirrored 63 instances |
| [INFO DPL-0021] HPWL before 60593.7 u |
| [INFO DPL-0022] HPWL after 60457.6 u |
| [INFO DPL-0023] HPWL delta -0.2 % |
| Setting global connections for newly added cells... |
| Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.odb... |
| Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.nl.v... |
| Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.pnl.v... |
| Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.def... |
| Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.sdc... |
| min_report |
| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _102_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.13 0.00 0.70 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.40 1.14 1.84 v _102_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 6 0.05 net16 (net) |
| 0.40 0.01 1.85 v _067_/A1 (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 0.60 0.44 2.29 ^ _067_/ZN (gf180mcu_fd_sc_mcu7t5v0__nor2_1) |
| 1 0.01 _008_ (net) |
| 0.60 0.00 2.29 ^ _102_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 2.29 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.13 0.00 0.77 ^ _102_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.25 1.02 clock uncertainty |
| -0.07 0.95 clock reconvergence pessimism |
| 0.02 0.97 library hold time |
| 0.97 data required time |
| ----------------------------------------------------------------------------- |
| 0.97 data required time |
| -2.29 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.32 slack (MET) |
| |
| |
| Startpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _107_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.13 0.00 0.70 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.55 1.30 2.00 ^ _107_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 5 0.04 net21 (net) |
| 0.56 0.02 2.02 ^ _078_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.38 0.30 2.31 v _078_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _013_ (net) |
| 0.38 0.00 2.32 v _107_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 2.32 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.13 0.00 0.77 ^ _107_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.25 1.02 clock uncertainty |
| -0.07 0.95 clock reconvergence pessimism |
| 0.03 0.97 library hold time |
| 0.97 data required time |
| ----------------------------------------------------------------------------- |
| 0.97 data required time |
| -2.32 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.34 slack (MET) |
| |
| |
| Startpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _111_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.40 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.14 0.31 0.71 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.14 0.00 0.71 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.57 1.31 2.02 ^ _111_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 5 0.04 net6 (net) |
| 0.57 0.01 2.03 ^ _087_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.39 0.30 2.33 v _087_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _017_ (net) |
| 0.39 0.00 2.34 v _111_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 2.34 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.14 0.00 0.78 ^ _111_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.25 1.03 clock uncertainty |
| -0.07 0.96 clock reconvergence pessimism |
| 0.02 0.98 library hold time |
| 0.98 data required time |
| ----------------------------------------------------------------------------- |
| 0.98 data required time |
| -2.34 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.36 slack (MET) |
| |
| |
| Startpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _095_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.13 0.00 0.70 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.57 1.31 2.01 ^ _095_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 5 0.04 net10 (net) |
| 0.58 0.01 2.03 ^ _051_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.40 0.31 2.33 v _051_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _001_ (net) |
| 0.40 0.00 2.34 v _095_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 2.34 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.13 0.00 0.77 ^ _095_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.25 1.02 clock uncertainty |
| -0.07 0.95 clock reconvergence pessimism |
| 0.02 0.97 library hold time |
| 0.97 data required time |
| ----------------------------------------------------------------------------- |
| 0.97 data required time |
| -2.34 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.37 slack (MET) |
| |
| |
| Startpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: _099_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.32 0.40 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.40 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.13 0.30 0.70 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.13 0.00 0.70 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.63 1.35 2.05 ^ _099_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 5 0.05 net13 (net) |
| 0.63 0.01 2.06 ^ _060_/A2 (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 0.38 0.29 2.35 v _060_/ZN (gf180mcu_fd_sc_mcu7t5v0__aoi21_1) |
| 1 0.01 _005_ (net) |
| 0.38 0.00 2.36 v _099_/D (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 2.36 data arrival time |
| |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.13 0.00 0.77 ^ _099_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.25 1.02 clock uncertainty |
| -0.07 0.95 clock reconvergence pessimism |
| 0.03 0.97 library hold time |
| 0.97 data required time |
| ----------------------------------------------------------------------------- |
| 0.97 data required time |
| -2.36 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.38 slack (MET) |
| |
| |
| min_report_end |
| max_report |
| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[16] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.14 0.00 0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.71 1.54 2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 6 0.06 net9 (net) |
| 0.71 0.03 2.34 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 0.48 0.72 3.06 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 1 0.07 io_out[16] (net) |
| 0.48 0.00 3.06 ^ io_out[16] (out) |
| 3.06 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -3.06 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.69 slack (MET) |
| |
| |
| Startpoint: _110_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[12] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.13 0.00 0.77 ^ _110_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.71 1.54 2.31 ^ _110_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 6 0.06 net5 (net) |
| 0.72 0.03 2.34 ^ output5/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 0.48 0.72 3.05 ^ output5/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 1 0.07 io_out[12] (net) |
| 0.48 0.00 3.05 ^ io_out[12] (out) |
| 3.05 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -3.05 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.70 slack (MET) |
| |
| |
| Startpoint: _101_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[3] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.44 ^ clkbuf_1_1__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.13 0.33 0.77 ^ clkbuf_1_1__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 9 0.03 clknet_1_1__leaf_wb_clk_i (net) |
| 0.13 0.00 0.77 ^ _101_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 0.83 1.51 2.28 ^ _101_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_1) |
| 2 0.03 net15 (net) |
| 0.83 0.01 2.30 ^ output15/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 0.48 0.73 3.03 ^ output15/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 1 0.07 io_out[3] (net) |
| 0.48 0.00 3.03 ^ io_out[3] (out) |
| 3.03 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -3.03 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.72 slack (MET) |
| |
| |
| Startpoint: _106_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[8] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.14 0.00 0.78 ^ _106_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.66 1.51 2.29 ^ _106_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 6 0.05 net20 (net) |
| 0.66 0.02 2.31 ^ output20/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 0.48 0.71 3.02 ^ output20/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 1 0.07 io_out[8] (net) |
| 0.48 0.00 3.02 ^ io_out[8] (out) |
| 3.02 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -3.02 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.73 slack (MET) |
| |
| |
| Startpoint: _098_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[0] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.14 0.00 0.78 ^ _098_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.65 1.51 2.29 ^ _098_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 6 0.05 net2 (net) |
| 0.65 0.00 2.29 ^ output2/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 0.48 0.70 2.99 ^ output2/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 1 0.07 io_out[0] (net) |
| 0.48 0.00 2.99 ^ io_out[0] (out) |
| 2.99 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -2.99 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.76 slack (MET) |
| |
| |
| max_report_end |
| check_report |
| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: _094_ (rising edge-triggered flip-flop clocked by wb_clk_i) |
| Endpoint: io_out[16] (output port clocked by wb_clk_i) |
| Path Group: wb_clk_i |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.00 0.00 clock wb_clk_i (rise edge) |
| 0.00 0.00 clock source latency |
| 0.18 0.08 0.08 ^ wb_clk_i (in) |
| 1 0.02 wb_clk_i (net) |
| 0.18 0.00 0.08 ^ clkbuf_0_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.15 0.36 0.44 ^ clkbuf_0_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 2 0.04 clknet_0_wb_clk_i (net) |
| 0.15 0.00 0.44 ^ clkbuf_1_0__f_wb_clk_i/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 0.14 0.34 0.78 ^ clkbuf_1_0__f_wb_clk_i/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_16) |
| 11 0.04 clknet_1_0__leaf_wb_clk_i (net) |
| 0.14 0.00 0.78 ^ _094_/CLK (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 0.71 1.54 2.32 ^ _094_/Q (gf180mcu_fd_sc_mcu7t5v0__dffq_2) |
| 6 0.06 net9 (net) |
| 0.71 0.03 2.34 ^ output9/I (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 0.48 0.72 3.06 ^ output9/Z (gf180mcu_fd_sc_mcu7t5v0__clkbuf_4) |
| 1 0.07 io_out[16] (net) |
| 0.48 0.00 3.06 ^ io_out[16] (out) |
| 3.06 data arrival time |
| |
| 65.00 65.00 clock wb_clk_i (rise edge) |
| 0.00 65.00 clock network delay (propagated) |
| -0.25 64.75 clock uncertainty |
| 0.00 64.75 clock reconvergence pessimism |
| -13.00 51.75 output external delay |
| 51.75 data required time |
| ----------------------------------------------------------------------------- |
| 51.75 data required time |
| -3.06 data arrival time |
| ----------------------------------------------------------------------------- |
| 48.69 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
| check_report_end |
| check_slew |
| |
| =========================================================================== |
| report_check_types -max_slew -max_cap -max_fanout -violators |
| ============================================================================ |
| |
| =========================================================================== |
| max slew violation count 0 |
| max fanout violation count 0 |
| max cap violation count 0 |
| ============================================================================ |
| check_slew_end |
| tns_report |
| |
| =========================================================================== |
| report_tns |
| ============================================================================ |
| tns 0.00 |
| tns_report_end |
| wns_report |
| |
| =========================================================================== |
| report_wns |
| ============================================================================ |
| wns 0.00 |
| wns_report_end |
| worst_slack |
| |
| =========================================================================== |
| report_worst_slack -max (Setup) |
| ============================================================================ |
| worst slack 48.69 |
| |
| =========================================================================== |
| report_worst_slack -min (Hold) |
| ============================================================================ |
| worst slack 1.32 |
| worst_slack_end |
| clock_skew |
| |
| =========================================================================== |
| report_clock_skew |
| ============================================================================ |
| Clock wb_clk_i |
| Latency CRPR Skew |
| _106_/CLK ^ |
| 0.78 |
| _108_/CLK ^ |
| 0.70 -0.04 0.04 |
| |
| clock_skew_end |
| power_report |
| |
| =========================================================================== |
| report_power |
| ============================================================================ |
| Group Internal Switching Leakage Total |
| Power Power Power Power (Watts) |
| ---------------------------------------------------------------- |
| Sequential 7.07e-05 7.86e-06 1.98e-09 7.86e-05 42.6% |
| Combinational 6.84e-05 3.72e-05 3.25e-07 1.06e-04 57.4% |
| Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| ---------------------------------------------------------------- |
| Total 1.39e-04 4.50e-05 3.27e-07 1.85e-04 100.0% |
| 75.4% 24.4% 0.2% |
| power_report_end |
| area_report |
| |
| =========================================================================== |
| report_design_area |
| ============================================================================ |
| Design area 67586 u^2 3% utilization. |
| area_report_end |
| Setting global connections for newly added cells... |
| Writing OpenROAD database to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.odb... |
| Writing netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.nl.v... |
| Writing powered netlist to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.pnl.v... |
| Writing layout to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.def... |
| Writing timing constraints to /home/htf6ry/gf180-demo-fiveguys/openlane/cntr_example/runs/22_12_03_21_36/tmp/cts/11-cntr_example.resized.sdc... |
