rtc integration
diff --git a/.gitmodules b/.gitmodules
index 5426bcd..df1d438 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -13,3 +13,6 @@
[submodule "verilog/rtl/fpu"]
path = verilog/rtl/fpu
url = https://github.com/dineshannayya/fpu
+[submodule "verilog/rtl/rtc"]
+ path = verilog/rtl/rtc
+ url = https://github.com/dineshannayya/rtc
diff --git a/Makefile b/Makefile
index dc5ba38..38de28b 100644
--- a/Makefile
+++ b/Makefile
@@ -110,7 +110,7 @@
# Install DV setup
.PHONY: simenv
simenv:
- docker pull riscduino/dv_setup:mpw6
+ docker pull riscduino/dv_setup:mpw7
.PHONY: setup
setup: install check-env install_mcw openlane pdk-with-volare setup-timing-scripts
@@ -132,7 +132,7 @@
-e TOOLS=/opt/riscv32i \
-e DESIGNS=$(TARGET_PATH) \
-e GCC_PREFIX=riscv32-unknown-elf \
- -u $$(id -u $$USER):$$(id -g $$USER) riscduino/dv_setup:mpw6 \
+ -u $$(id -u $$USER):$$(id -g $$USER) riscduino/dv_setup:mpw7 \
sh -c $(verify_command)
@@ -327,3 +327,11 @@
@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast
@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow
@echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
+
+#Added by Dinesh-A for Klayout Based DRC check
+.PHONY: run-drc
+run-drc:
+ @echo "run kalyout DRC checks"
+ mkdir -p signoff/user_project_wrapper/openlane-signoff/drc
+ docker run -ti --rm -v $(PROJECT_ROOT):/project riscduino/openlane:mpw7 sh -c "cd /project && ./scripts/drc/run.sh user_project_wrapper "
+
diff --git a/README.md b/README.md
index 05a57bf..9b7552f 100644
--- a/README.md
+++ b/README.md
@@ -74,6 +74,9 @@
* 3 x Timer (16 Bit), 1us/1ms/1second resolution
* 2 x ws281x driver
* 16 Hardware Semaphore
+ * FPU (SP) Core
+ * AES 128 Bit Core
+ * RTC Core
* Pin Compatbible to arduino uno
* Wishbone compatible design
* Written in System Verilog
@@ -410,16 +413,16 @@
- flow automatically pull the required docker based on MPW version.
- RTL to gds docker is hardcoded inside File: openlane/Makefile
```bash
- OPENLANE_TAG = mpw6
+ OPENLANE_TAG = mpw7
OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)
```
## Note-1.1: View the RTL to GDS Docker content
- - for MPW-6 caravel pdk and openlane avaible inside riscduino/openlane:mpw6 docker
+ - for MPW-7 caravel pdk and openlane avaible inside riscduino/openlane:mpw7 docker
- caravel, openlane and pdk envionment are automatically pointed to internal docker pointer
- To view the docker contents
```bash
- docker run -ti --rm riscduino/openlane:mpw6 bash
- cd /opt/pdk_mpw6 - pdk folder
+ docker run -ti --rm riscduino/openlane:mpw7 bash
+ cd /opt/pdk_mpw7 - pdk folder
cd /opt/caravel - caravel folder
cd /openlane - openlane folder
env - Show the internally defined env's
@@ -436,12 +439,12 @@
docker pull riscduino/dv_setup:mpw6
## Note-2.1: View the RTL Simulation Docker content
- - for MPW-6 caravel and pdk avaible inside riscduino/dv_setup:mpw6 docker this is used for RTL to gds flows
+ - for MPW-7 caravel and pdk avaible inside riscduino/dv_setup:mpw7 docker this is used for RTL to gds flows
- caravel and pdk envionment are automatically pointed to internal docker pointer
- To view the docker contents
```bash
- docker run -ti --rm riscduino/dv_setup:mpw6 bash
- cd /opt/pdk_mpw6 - pdk folder
+ docker run -ti --rm riscduino/dv_setup:mpw7 bash
+ cd /opt/pdk_mpw7 - pdk folder
cd /opt/caravel - caravel folder
env - Show the internally defined env's
CARAVEL_ROOT=/opt/caravel
@@ -471,7 +474,10 @@
* **15.user_cache_bypass** - Riscv Boot without icache and dcache
* **16.user_pwm** -Standalone pwm Test
* **17.user_sema** -Standalone validation of hardware Semaphore function
-* **18.riscv_regress** - Standalone riscv compliance and regression test suite
+* **18.riscv_regress** -Standalone riscv compliance and regression test suite
+* **19.user_rtc** -Standalone RTC core test
+* **20.user_aes_core** -Standalone AES Core test
+* **21.user_fpu_core** -Standalone FPU(SP) Core test
## Caravel+RISCDUINO Integrated Specific Test case
* **1.wb_port** - Complete caravel User Wishbone validation
@@ -662,7 +668,7 @@
We are looking for community help in following activity, interested user can ping me in efabless slack platform
* **Analog Design** - ADC, DAC, PLL,
-* **Digital Design** - New IP Integration, Encription,DSP, Floating point functions
+* **Digital Design** - New IP Integration, Encription,DSP, DMA controller, 10Mb MAC, Floating point functions
* **Verification** - Improving the Verification flow
* **Linux Porting** - Build Root integration
* **Arudino Software Update** - Tool Customisation for Riscduino, Adding additional plug-in and Riscv compilation support
diff --git a/docs/source/_static/Riscduino_Soc.png b/docs/source/_static/Riscduino_Soc.png
index 135f686..5dae5ff 100644
--- a/docs/source/_static/Riscduino_Soc.png
+++ b/docs/source/_static/Riscduino_Soc.png
Binary files differ
diff --git a/env/spef-mapping.tcl b/env/spef-mapping.tcl
index 02a1561..adf75f3 100644
--- a/env/spef-mapping.tcl
+++ b/env/spef-mapping.tcl
@@ -2,6 +2,7 @@
set spef_mapping(mprj/u_aes) "$::env(PROJECT_ROOT)/signoff/aes_top/openlane-signoff/spef/aes_top.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/u_fpu) "$::env(PROJECT_ROOT)/signoff/fpu_wrapper/openlane-signoff/spef/fpu_wrapper.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/u_intercon) "$::env(PROJECT_ROOT)/signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_peri) "$::env(PROJECT_ROOT)/signoff/peri_top/openlane-signoff/spef/peri_top.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/u_pinmux) "$::env(PROJECT_ROOT)/signoff/pinmux_top/openlane-signoff/spef/pinmux_top.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/u_pll) "$::env(PROJECT_ROOT)/signoff/dg_pll/openlane-signoff/spef/dg_pll.$::env(RCX_CORNER).spef"
set spef_mapping(mprj/u_qspi_master) "$::env(PROJECT_ROOT)/signoff/qspim_top/openlane-signoff/spef/qspim_top.$::env(RCX_CORNER).spef"
diff --git a/openlane/bus_rep_north/config.tcl b/openlane/bus_rep_north/config.tcl
index 4168921..e66bac5 100755
--- a/openlane/bus_rep_north/config.tcl
+++ b/openlane/bus_rep_north/config.tcl
@@ -49,7 +49,8 @@
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=27 "
+set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=27 \
+ BUS_BUF_WD=42 "
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
#set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
diff --git a/openlane/bus_rep_north/pin_order.cfg b/openlane/bus_rep_north/pin_order.cfg
index d6472e3..3fc1b58 100644
--- a/openlane/bus_rep_north/pin_order.cfg
+++ b/openlane/bus_rep_north/pin_order.cfg
@@ -32,7 +32,95 @@
ch_in\[26\]
#S
-ch_in\[0\] 2000 0 64
+buf_in\[0\] 0100 0 4
+buf_out\[1\]
+buf_out\[2\]
+buf_in\[3\]
+buf_out\[4\]
+buf_out\[5\]
+buf_in\[6\]
+buf_out\[7\]
+buf_out\[8\]
+buf_in\[9\]
+buf_out\[10\]
+buf_out\[11\]
+buf_in\[12\]
+buf_out\[13\]
+buf_out\[14\]
+buf_in\[15\]
+buf_out\[16\]
+buf_out\[17\]
+buf_in\[18\]
+buf_out\[19\]
+buf_out\[20\]
+buf_in\[21\]
+buf_out\[22\]
+buf_out\[23\]
+buf_in\[24\]
+buf_out\[25\]
+buf_out\[26\]
+buf_in\[27\]
+buf_out\[28\]
+buf_out\[29\]
+buf_in\[30\]
+buf_out\[31\]
+buf_out\[32\]
+buf_in\[33\]
+buf_out\[34\]
+buf_out\[35\]
+buf_in\[36\]
+buf_out\[37\]
+buf_out\[38\]
+buf_in\[39\]
+buf_out\[40\]
+buf_out\[41\]
+
+buf_in\[41\] 2000 0 4
+buf_in\[40\]
+buf_out\[39\]
+buf_in\[38\]
+buf_in\[37\]
+buf_out\[36\]
+buf_in\[35\]
+buf_in\[34\]
+buf_out\[33\]
+buf_in\[32\]
+buf_in\[31\]
+buf_out\[30\]
+buf_in\[29\]
+buf_in\[28\]
+buf_out\[27\]
+buf_in\[26\]
+buf_in\[25\]
+buf_out\[24\]
+buf_in\[23\]
+buf_in\[22\]
+buf_out\[21\]
+buf_in\[20\]
+buf_in\[19\]
+buf_out\[18\]
+buf_in\[17\]
+buf_in\[16\]
+buf_out\[15\]
+buf_in\[14\]
+buf_in\[13\]
+buf_out\[12\]
+buf_in\[11\]
+buf_in\[10\]
+buf_out\[9\]
+buf_in\[8\]
+buf_in\[7\]
+buf_out\[6\]
+buf_in\[5\]
+buf_in\[4\]
+buf_out\[3\]
+buf_in\[2\]
+buf_in\[1\]
+buf_out\[0\]
+
+
+
+ch_in\[0\] 2400 0 16
ch_in\[1\]
ch_out\[2\]
ch_in\[3\]
diff --git a/openlane/fpu_wrapper/base.sdc b/openlane/fpu_wrapper/base.sdc
new file mode 100644
index 0000000..9a5897d
--- /dev/null
+++ b/openlane/fpu_wrapper/base.sdc
@@ -0,0 +1,271 @@
+###############################################################################
+# Created by write_sdc
+# Mon Nov 7 16:29:34 2022
+###############################################################################
+current_design fpu_wrapper
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[0]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[1]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[2]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[3]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {rst_n}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_clk_int}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_clk_out}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[1]}]
+
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_cmd}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[1]}]
+
+
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[1]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[1]}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_out}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[0]}]
+
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/openlane/fpu_wrapper/config.tcl b/openlane/fpu_wrapper/config.tcl
new file mode 100755
index 0000000..8c0d4db
--- /dev/null
+++ b/openlane/fpu_wrapper/config.tcl
@@ -0,0 +1,126 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+
+set ::env(DESIGN_NAME) fpu_wrapper
+
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "mclk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/fpu_wrapper/src/fpu_wrapper.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/fpu_wrapper/src/fpu_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_mul.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_div.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_add.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_f2i.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_i2f.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
+ "
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 550 550"
+
+set ::env(GRT_ADJUSTMENT) 0.2
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.43"
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+set ::env(FP_IO_VEXTEND) 2
+set ::env(FP_IO_HEXTEND) 2
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
+
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
+
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/fpu_wrapper/pin_order.cfg b/openlane/fpu_wrapper/pin_order.cfg
new file mode 100644
index 0000000..1ad7fde
--- /dev/null
+++ b/openlane/fpu_wrapper/pin_order.cfg
@@ -0,0 +1,93 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+
+#S
+
+rst_n 00 0 2
+cfg_cska\[3\]
+cfg_cska\[2\]
+cfg_cska\[1\]
+cfg_cska\[0\]
+wbd_clk_out
+mclk
+
+
+wbd_clk_int 050 0 2
+dmem_req_ack
+dmem_req
+dmem_cmd
+dmem_width\[1\]
+dmem_width\[0\]
+dmem_addr\[4\]
+dmem_addr\[3\]
+dmem_addr\[2\]
+dmem_addr\[1\]
+dmem_addr\[0\]
+dmem_wdata\[31\]
+dmem_wdata\[30\]
+dmem_wdata\[29\]
+dmem_wdata\[28\]
+dmem_wdata\[27\]
+dmem_wdata\[26\]
+dmem_wdata\[25\]
+dmem_wdata\[24\]
+dmem_wdata\[23\]
+dmem_wdata\[22\]
+dmem_wdata\[21\]
+dmem_wdata\[20\]
+dmem_wdata\[19\]
+dmem_wdata\[18\]
+dmem_wdata\[17\]
+dmem_wdata\[16\]
+dmem_wdata\[15\]
+dmem_wdata\[14\]
+dmem_wdata\[13\]
+dmem_wdata\[12\]
+dmem_wdata\[11\]
+dmem_wdata\[10\]
+dmem_wdata\[9\]
+dmem_wdata\[8\]
+dmem_wdata\[7\]
+dmem_wdata\[6\]
+dmem_wdata\[5\]
+dmem_wdata\[4\]
+dmem_wdata\[3\]
+dmem_wdata\[2\]
+dmem_wdata\[1\]
+dmem_wdata\[0\]
+dmem_rdata\[31\]
+dmem_rdata\[30\]
+dmem_rdata\[29\]
+dmem_rdata\[28\]
+dmem_rdata\[27\]
+dmem_rdata\[26\]
+dmem_rdata\[25\]
+dmem_rdata\[24\]
+dmem_rdata\[23\]
+dmem_rdata\[22\]
+dmem_rdata\[21\]
+dmem_rdata\[20\]
+dmem_rdata\[19\]
+dmem_rdata\[18\]
+dmem_rdata\[17\]
+dmem_rdata\[16\]
+dmem_rdata\[15\]
+dmem_rdata\[14\]
+dmem_rdata\[13\]
+dmem_rdata\[12\]
+dmem_rdata\[11\]
+dmem_rdata\[10\]
+dmem_rdata\[9\]
+dmem_rdata\[8\]
+dmem_rdata\[7\]
+dmem_rdata\[6\]
+dmem_rdata\[5\]
+dmem_rdata\[4\]
+dmem_rdata\[3\]
+dmem_rdata\[2\]
+dmem_rdata\[1\]
+dmem_rdata\[0\]
+dmem_resp\[1\]
+dmem_resp\[0\]
diff --git a/openlane/peri_top/base.sdc b/openlane/peri_top/base.sdc
new file mode 100644
index 0000000..d55cd9f
--- /dev/null
+++ b/openlane/peri_top/base.sdc
@@ -0,0 +1,214 @@
+###############################################################################
+# Created by write_sdc
+# Wed Dec 7 16:59:07 2022
+###############################################################################
+current_design peri_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+create_clock -name rtc_clk -period 100.0000 [get_ports {rtc_clk}]
+
+set_clock_groups \
+ -name clock_group \
+ -logically_exclusive \
+ -group [get_clocks {mclk}]\
+ -group [get_clocks {rtc_clk}]\
+ -comment {Async Clock group}
+
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty 0.2500 [all_clocks]
+set_propagated_clock [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+### ClkSkew Adjust
+set_case_analysis 0 [get_ports {cfg_cska_peri[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[3]}]
+
+set_max_delay 3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay 2 -to [get_ports {wbd_clk_peri}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_peri
+
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {s_reset_n}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {s_reset_n}]
+
+## RTC - Sys Clk
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
+
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+
+
+### DAC I/F
+
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac0_mux_sel[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac1_mux_sel[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac2_mux_sel[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac3_mux_sel[*]}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac0_mux_sel[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac1_mux_sel[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac2_mux_sel[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac3_mux_sel[*]}]
+
+### RTC clock domain
+set_output_delay -max 6.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {inc_date_d}]
+set_output_delay -max 6.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {inc_time_s}]
+set_output_delay -max 6.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {rtc_intr}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {inc_date_d}]
+set_output_delay -min 1.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {inc_time_s}]
+set_output_delay -min 1.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {rtc_intr}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {inc_date_d}]
+set_load -pin_load 0.0334 [get_ports {inc_time_s}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {rtc_intr}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_peri}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/openlane/peri_top/config.tcl b/openlane/peri_top/config.tcl
new file mode 100755
index 0000000..0b3f35f
--- /dev/null
+++ b/openlane/peri_top/config.tcl
@@ -0,0 +1,138 @@
+# SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+
+set ::env(DESIGN_NAME) peri_top
+
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "mclk rtc_clk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/rtc/verilog/rtl/core/rtc_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/rtc/verilog/rtl/core/rtc_core.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/rtc/verilog/rtl/core/rtc_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/peripheral/src/peri_top.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/dig2ana/src/dig2ana_reg.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_reg_bus.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+ "
+
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/ ]
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 400 200"
+
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.35"
+set ::env(CELL_PAD) "8"
+#set ::env(GRT_ADJUSTMENT) {0.2}
+
+
+######################################################################################
+# Metal-2/3 Signal are Routed near to block boundary is creating DRC violation at Top-level
+# during pad connectivity
+
+#set ::env(GRT_OBS) " \
+# met2 0 2 500 3, \
+# met2 0 747 500 748, \
+# met3 2 0 3 750, \
+# met3 497 0 498 750"
+
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "1"
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+
+#Lef
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
+
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
+
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/peri_top/pin_order.cfg b/openlane/peri_top/pin_order.cfg
new file mode 100644
index 0000000..2f23b77
--- /dev/null
+++ b/openlane/peri_top/pin_order.cfg
@@ -0,0 +1,142 @@
+#BUS_SORT
+#MANUAL_PLACE
+
+#W
+s_reset_n
+mclk
+wbd_clk_int
+wbd_clk_peri
+cfg_cska_peri\[3\]
+cfg_cska_peri\[2\]
+cfg_cska_peri\[1\]
+cfg_cska_peri\[0\]
+
+cfg_dac3_mux_sel\[7\]
+cfg_dac3_mux_sel\[6\]
+cfg_dac3_mux_sel\[5\]
+cfg_dac3_mux_sel\[4\]
+cfg_dac3_mux_sel\[3\]
+cfg_dac3_mux_sel\[2\]
+cfg_dac3_mux_sel\[1\]
+cfg_dac3_mux_sel\[0\]
+
+cfg_dac2_mux_sel\[7\]
+cfg_dac2_mux_sel\[6\]
+cfg_dac2_mux_sel\[5\]
+cfg_dac2_mux_sel\[4\]
+cfg_dac2_mux_sel\[3\]
+cfg_dac2_mux_sel\[2\]
+cfg_dac2_mux_sel\[1\]
+cfg_dac2_mux_sel\[0\]
+
+cfg_dac1_mux_sel\[7\]
+cfg_dac1_mux_sel\[6\]
+cfg_dac1_mux_sel\[5\]
+cfg_dac1_mux_sel\[4\]
+cfg_dac1_mux_sel\[3\]
+cfg_dac1_mux_sel\[2\]
+cfg_dac1_mux_sel\[1\]
+cfg_dac1_mux_sel\[0\]
+
+cfg_dac0_mux_sel\[7\]
+cfg_dac0_mux_sel\[6\]
+cfg_dac0_mux_sel\[5\]
+cfg_dac0_mux_sel\[4\]
+cfg_dac0_mux_sel\[3\]
+cfg_dac0_mux_sel\[2\]
+cfg_dac0_mux_sel\[1\]
+cfg_dac0_mux_sel\[0\]
+
+
+#S
+rtc_clk 200 0 2
+rtc_intr
+inc_date_d
+inc_time_s
+
+
+reg_cs 250 0 2
+reg_wr
+reg_addr\[10\]
+reg_addr\[9\]
+reg_addr\[8\]
+reg_addr\[7\]
+reg_addr\[6\]
+reg_addr\[5\]
+reg_addr\[4\]
+reg_addr\[3\]
+reg_addr\[2\]
+reg_addr\[1\]
+reg_addr\[0\]
+reg_be\[3\]
+reg_be\[2\]
+reg_be\[1\]
+reg_be\[0\]
+reg_wdata\[31\]
+reg_wdata\[30\]
+reg_wdata\[29\]
+reg_wdata\[28\]
+reg_wdata\[27\]
+reg_wdata\[26\]
+reg_wdata\[25\]
+reg_wdata\[24\]
+reg_wdata\[23\]
+reg_wdata\[22\]
+reg_wdata\[21\]
+reg_wdata\[20\]
+reg_wdata\[19\]
+reg_wdata\[18\]
+reg_wdata\[17\]
+reg_wdata\[16\]
+reg_wdata\[15\]
+reg_wdata\[14\]
+reg_wdata\[13\]
+reg_wdata\[12\]
+reg_wdata\[11\]
+reg_wdata\[10\]
+reg_wdata\[9\]
+reg_wdata\[8\]
+reg_wdata\[7\]
+reg_wdata\[6\]
+reg_wdata\[5\]
+reg_wdata\[4\]
+reg_wdata\[3\]
+reg_wdata\[2\]
+reg_wdata\[1\]
+reg_wdata\[0\]
+reg_rdata\[31\]
+reg_rdata\[30\]
+reg_rdata\[29\]
+reg_rdata\[28\]
+reg_rdata\[27\]
+reg_rdata\[26\]
+reg_rdata\[25\]
+reg_rdata\[24\]
+reg_rdata\[23\]
+reg_rdata\[22\]
+reg_rdata\[21\]
+reg_rdata\[20\]
+reg_rdata\[19\]
+reg_rdata\[18\]
+reg_rdata\[17\]
+reg_rdata\[16\]
+reg_rdata\[15\]
+reg_rdata\[14\]
+reg_rdata\[13\]
+reg_rdata\[12\]
+reg_rdata\[11\]
+reg_rdata\[10\]
+reg_rdata\[9\]
+reg_rdata\[8\]
+reg_rdata\[7\]
+reg_rdata\[6\]
+reg_rdata\[5\]
+reg_rdata\[4\]
+reg_rdata\[3\]
+reg_rdata\[2\]
+reg_rdata\[1\]
+reg_rdata\[0\]
+reg_ack
+
+
+
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg
index fff23e7..bcdbeb5 100644
--- a/openlane/pinmux_top/pin_order.cfg
+++ b/openlane/pinmux_top/pin_order.cfg
@@ -69,7 +69,6 @@
int_pll_clock
xtal_clk
s_reset_n
-rtc_clk
usb_clk
pinmux_debug\[0\] 0300 0 2
@@ -226,6 +225,7 @@
reg_cs 260 0 2
reg_wr
+reg_addr\[10\]
reg_addr\[9\]
reg_addr\[8\]
reg_addr\[7\]
@@ -308,44 +308,7 @@
#N
-
-cfg_dac3_mux_sel\[7\]
-cfg_dac3_mux_sel\[6\]
-cfg_dac3_mux_sel\[5\]
-cfg_dac3_mux_sel\[4\]
-cfg_dac3_mux_sel\[3\]
-cfg_dac3_mux_sel\[2\]
-cfg_dac3_mux_sel\[1\]
-cfg_dac3_mux_sel\[0\]
-
-cfg_dac2_mux_sel\[7\]
-cfg_dac2_mux_sel\[6\]
-cfg_dac2_mux_sel\[5\]
-cfg_dac2_mux_sel\[4\]
-cfg_dac2_mux_sel\[3\]
-cfg_dac2_mux_sel\[2\]
-cfg_dac2_mux_sel\[1\]
-cfg_dac2_mux_sel\[0\]
-
-cfg_dac1_mux_sel\[7\]
-cfg_dac1_mux_sel\[6\]
-cfg_dac1_mux_sel\[5\]
-cfg_dac1_mux_sel\[4\]
-cfg_dac1_mux_sel\[3\]
-cfg_dac1_mux_sel\[2\]
-cfg_dac1_mux_sel\[1\]
-cfg_dac1_mux_sel\[0\]
-
-cfg_dac0_mux_sel\[7\]
-cfg_dac0_mux_sel\[6\]
-cfg_dac0_mux_sel\[5\]
-cfg_dac0_mux_sel\[4\]
-cfg_dac0_mux_sel\[3\]
-cfg_dac0_mux_sel\[2\]
-cfg_dac0_mux_sel\[1\]
-cfg_dac0_mux_sel\[0\]
-
-digital_io_oen\[37\] 100 0 4
+digital_io_oen\[37\] 000 0 2
digital_io_out\[37\]
digital_io_in\[37\]
digital_io_oen\[36\]
@@ -374,9 +337,109 @@
digital_io_in\[29\]
digital_io_oen\[28\]
digital_io_out\[28\]
+digital_io_in\[28\]
+digital_io_oen\[27\]
+digital_io_out\[27\]
+digital_io_in\[27\]
+digital_io_oen\[26\]
+digital_io_out\[26\]
+digital_io_in\[26\]
+digital_io_oen\[25\]
+digital_io_out\[25\]
+digital_io_in\[25\]
+digital_io_oen\[24\]
+digital_io_out\[24\]
+digital_io_in\[24\]
+
+rtc_clk 150 0 2
+rtc_intr
+
+reg_peri_cs 200 0 2
+reg_peri_wr
+reg_peri_addr\[10\]
+reg_peri_addr\[9\]
+reg_peri_addr\[8\]
+reg_peri_addr\[7\]
+reg_peri_addr\[6\]
+reg_peri_addr\[5\]
+reg_peri_addr\[4\]
+reg_peri_addr\[3\]
+reg_peri_addr\[2\]
+reg_peri_addr\[1\]
+reg_peri_addr\[0\]
+reg_peri_be\[3\]
+reg_peri_be\[2\]
+reg_peri_be\[1\]
+reg_peri_be\[0\]
+reg_peri_wdata\[31\]
+reg_peri_wdata\[30\]
+reg_peri_wdata\[29\]
+reg_peri_wdata\[28\]
+reg_peri_wdata\[27\]
+reg_peri_wdata\[26\]
+reg_peri_wdata\[25\]
+reg_peri_wdata\[24\]
+reg_peri_wdata\[23\]
+reg_peri_wdata\[22\]
+reg_peri_wdata\[21\]
+reg_peri_wdata\[20\]
+reg_peri_wdata\[19\]
+reg_peri_wdata\[18\]
+reg_peri_wdata\[17\]
+reg_peri_wdata\[16\]
+reg_peri_wdata\[15\]
+reg_peri_wdata\[14\]
+reg_peri_wdata\[13\]
+reg_peri_wdata\[12\]
+reg_peri_wdata\[11\]
+reg_peri_wdata\[10\]
+reg_peri_wdata\[9\]
+reg_peri_wdata\[8\]
+reg_peri_wdata\[7\]
+reg_peri_wdata\[6\]
+reg_peri_wdata\[5\]
+reg_peri_wdata\[4\]
+reg_peri_wdata\[3\]
+reg_peri_wdata\[2\]
+reg_peri_wdata\[1\]
+reg_peri_wdata\[0\]
+reg_peri_rdata\[31\]
+reg_peri_rdata\[30\]
+reg_peri_rdata\[29\]
+reg_peri_rdata\[28\]
+reg_peri_rdata\[27\]
+reg_peri_rdata\[26\]
+reg_peri_rdata\[25\]
+reg_peri_rdata\[24\]
+reg_peri_rdata\[23\]
+reg_peri_rdata\[22\]
+reg_peri_rdata\[21\]
+reg_peri_rdata\[20\]
+reg_peri_rdata\[19\]
+reg_peri_rdata\[18\]
+reg_peri_rdata\[17\]
+reg_peri_rdata\[16\]
+reg_peri_rdata\[15\]
+reg_peri_rdata\[14\]
+reg_peri_rdata\[13\]
+reg_peri_rdata\[12\]
+reg_peri_rdata\[11\]
+reg_peri_rdata\[10\]
+reg_peri_rdata\[9\]
+reg_peri_rdata\[8\]
+reg_peri_rdata\[7\]
+reg_peri_rdata\[6\]
+reg_peri_rdata\[5\]
+reg_peri_rdata\[4\]
+reg_peri_rdata\[3\]
+reg_peri_rdata\[2\]
+reg_peri_rdata\[1\]
+reg_peri_rdata\[0\]
+reg_peri_ack
-cfg_dco_mode 0200 0 2
+
+cfg_dco_mode 0300 0 2
cfg_pll_enb
pll_ref_clk
cfg_pll_fed_div\[4\]
@@ -411,19 +474,6 @@
cfg_dc_trim\[1\]
cfg_dc_trim\[0\]
-digital_io_in\[28\] 0300 0 2
-digital_io_oen\[27\]
-digital_io_out\[27\]
-digital_io_in\[27\]
-digital_io_oen\[26\]
-digital_io_out\[26\]
-digital_io_in\[26\]
-digital_io_oen\[25\]
-digital_io_out\[25\]
-digital_io_in\[25\]
-digital_io_oen\[24\]
-digital_io_out\[24\]
-digital_io_in\[24\]
digital_io_in\[23\] 400 0
@@ -474,7 +524,7 @@
sflash_di\[2\]
sflash_di\[3\]
-digital_io_in\[0\] 0200 0 4
+digital_io_in\[0\] 0300 0 4
digital_io_out\[0\]
digital_io_oen\[0\]
digital_io_in\[1\]
diff --git a/openlane/qspim_top/pin_order.cfg b/openlane/qspim_top/pin_order.cfg
index 8c81d46..afea1d2 100644
--- a/openlane/qspim_top/pin_order.cfg
+++ b/openlane/qspim_top/pin_order.cfg
@@ -23,7 +23,7 @@
#W
-cfg_cska_sp_co\[3\] 0200 0 2
+cfg_cska_sp_co\[3\] 0300 0 2
cfg_cska_sp_co\[2\]
cfg_cska_sp_co\[1\]
cfg_cska_sp_co\[0\]
@@ -35,7 +35,7 @@
wbd_clk_spi
mclk
-wbd_stb_i 0300 0 2
+wbd_stb_i 0350 0 2
wbd_we_i
wbd_adr_i\[31\]
wbd_adr_i\[30\]
@@ -161,7 +161,7 @@
strap_flash\[1\]
strap_flash\[0\]
-spi_debug\[0\] 0200 0 2
+spi_debug\[0\] 0050 0 2
spi_debug\[1\]
spi_debug\[2\]
spi_debug\[3\]
diff --git a/openlane/uart_i2c_usb_spi_top/pin_order.cfg b/openlane/uart_i2c_usb_spi_top/pin_order.cfg
index b518404..cbc75a4 100644
--- a/openlane/uart_i2c_usb_spi_top/pin_order.cfg
+++ b/openlane/uart_i2c_usb_spi_top/pin_order.cfg
@@ -2,7 +2,7 @@
#MANUAL_PLACE
#W
-cfg_cska_uart\[3\] 0200 0 2
+cfg_cska_uart\[3\] 0300 0 2
cfg_cska_uart\[2\]
cfg_cska_uart\[1\]
cfg_cska_uart\[0\]
@@ -10,7 +10,7 @@
wbd_clk_uart
app_clk
-reg_cs 0300 0 2
+reg_cs 0400 0 2
reg_wr
reg_addr\[8\]
reg_addr\[7\]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index f26769b..486f13f 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -82,6 +82,7 @@
$::env(DESIGN_DIR)/../../verilog/gl/bus_rep_north.v \
$::env(DESIGN_DIR)/../../verilog/gl/bus_rep_east.v \
$::env(DESIGN_DIR)/../../verilog/gl/bus_rep_west.v \
+ $::env(DESIGN_DIR)/../../verilog/gl/peri_top.v \
"
set ::env(EXTRA_LEFS) "\
@@ -102,6 +103,7 @@
$lef_root/bus_rep_north.lef \
$lef_root/bus_rep_east.lef \
$lef_root/bus_rep_west.lef \
+ $lef_root/peri_top.lef \
"
set ::env(EXTRA_GDS_FILES) "\
@@ -122,6 +124,7 @@
$gds_root/bus_rep_north.gds \
$gds_root/bus_rep_east.gds \
$gds_root/bus_rep_west.gds \
+ $gds_root/peri_top.gds \
"
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -202,7 +205,8 @@
u_rp_south vccd1 vssd1 vccd1 vssd1,\
u_rp_north vccd1 vssd1 vccd1 vssd1,\
u_rp_east vccd1 vssd1 vccd1 vssd1,\
- u_rp_west vccd1 vssd1 vccd1 vssd1
+ u_rp_west vccd1 vssd1 vccd1 vssd1,\
+ u_peri vccd1 vssd1 vccd1 vssd1
"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 3a3500f..36306e2 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,14 +1,15 @@
-u_4x8bit_dac 1850 2500 N
-u_qspi_master 2250 450 N
-u_uart_i2c_usb_spi 2250 1100 N
-u_pinmux 2250 2000 N
-u_pll 2500 3028 N
+u_4x8bit_dac 1850 2500 N
+u_qspi_master 2250 350 N
+u_uart_i2c_usb_spi 2250 1000 N
+u_pinmux 2250 1900 N
+u_peri 2200 3000 N
+u_pll 2650 3000 N
u_fpu 1100 2600 N
u_aes 150 2600 N
u_riscv_top.i_core_top_0 150 1400 N
u_riscv_top.i_core_top_1 1200 1400 FN
-u_riscv_top.u_connect 733 1400 N
+u_riscv_top.u_connect 740 1400 N
u_riscv_top.u_intf 950 650 N
u_dcache_2kb 150 130 N
u_icache_2kb 950 130 N
@@ -16,7 +17,7 @@
u_intercon 1850 650 N
-u_wb_host 1750 150 N
+u_wb_host 1750 100 N
u_rp_south 100 20 N
u_rp_north 100 3400 N
u_rp_east 2820 50 E
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl
index b317190..84ea810 100644
--- a/openlane/user_project_wrapper/pdn_cfg.tcl
+++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -158,7 +158,7 @@
define_pdn_grid \
-macro \
-name macro_1 \
- -instances "u_pll u_intercon u_pinmux u_qspi_master u_tsram0_2kb u_icache_2kb u_dcache_2kb u_uart_i2c_usb_spi u_wb_host u_riscv_top.i_core_top_0 u_riscv_top.i_core_top_1 u_riscv_top.u_connect u_riscv_top.u_intf u_4x8bit_dac u_aes u_fpu" \
+ -instances "u_pll u_intercon u_pinmux u_qspi_master u_tsram0_2kb u_icache_2kb u_dcache_2kb u_uart_i2c_usb_spi u_wb_host u_riscv_top.i_core_top_0 u_riscv_top.i_core_top_1 u_riscv_top.u_connect u_riscv_top.u_intf u_4x8bit_dac u_aes u_fpu u_peri" \
-starts_with POWER \
-halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 8ac589d..60315f0 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -153,12 +153,8 @@
#N
-cfg_clk_skew_ctrl1\[31\] 0000 0 2
-cfg_clk_skew_ctrl1\[30\]
-cfg_clk_skew_ctrl1\[29\]
-cfg_clk_skew_ctrl1\[28\]
-cfg_clk_skew_ctrl1\[7\]
+cfg_clk_skew_ctrl1\[7\] 0000 0 2
cfg_cska_wh\[3\]
cfg_clk_skew_ctrl1\[6\]
cfg_cska_wh\[2\]
@@ -335,7 +331,12 @@
wbs_cyc_o
-cfg_clk_skew_ctrl2\[31\] 325 0 2
+cfg_clk_skew_ctrl1\[31\] 325 0 2
+cfg_clk_skew_ctrl1\[30\]
+cfg_clk_skew_ctrl1\[29\]
+cfg_clk_skew_ctrl1\[28\]
+
+cfg_clk_skew_ctrl2\[31\]
cfg_clk_skew_ctrl2\[30\]
cfg_clk_skew_ctrl2\[29\]
cfg_clk_skew_ctrl2\[28\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index a87255c..743d701 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -54,8 +54,8 @@
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
-set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=14\
- CH_DATA_WD=154 \
+set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=8\
+ CH_DATA_WD=158 \
"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index 51bfa57..af8e9cf 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -3,16 +3,9 @@
#MANUAL_PLACE
#S
-ch_clk_in\[13\] 000 0 2
-ch_clk_in\[12\]
-ch_clk_in\[11\]
-ch_clk_in\[10\]
-ch_clk_in\[9\]
-ch_clk_in\[8\]
-ch_clk_in\[7\]
+ch_clk_in\[7\] 000 0 2
ch_clk_in\[6\]
ch_clk_in\[5\]
-ch_clk_in\[4\]
rst_n 020 0 2
@@ -66,6 +59,7 @@
cfg_cska_wi\[1\]
cfg_cska_wi\[0\]
+ch_clk_in\[4\]
ch_clk_in\[3\]
ch_clk_in\[2\]
ch_clk_in\[1\]
@@ -182,7 +176,13 @@
m0_wbd_err_o
m0_wbd_cyc_i
-ch_data_in\[153\] 225 0 2
+
+ch_data_in\[157\] 225 0 2
+ch_data_in\[156\]
+ch_data_in\[155\]
+ch_data_in\[154\]
+
+ch_data_in\[153\]
ch_data_in\[152\]
ch_data_in\[151\]
ch_data_in\[150\]
@@ -272,7 +272,7 @@
ch_data_out\[22\]
ch_data_out\[21\]
ch_data_out\[20\]
-ch_clk_out\[4\]
+ch_clk_out\[5\]
ch_data_out\[3\] 050 0 2
ch_data_out\[2\]
@@ -600,33 +600,29 @@
ch_data_out\[42\]
ch_data_out\[41\]
ch_data_out\[40\]
-ch_clk_out\[9\]
ch_data_out\[39\]
ch_data_out\[38\]
ch_data_out\[37\]
ch_data_out\[36\]
-ch_clk_out\[8\]
ch_data_out\[35\]
ch_data_out\[34\]
ch_data_out\[33\]
ch_data_out\[32\]
-ch_clk_out\[7\]
ch_data_out\[31\]
ch_data_out\[30\]
ch_data_out\[29\]
ch_data_out\[28\]
-ch_clk_out\[6\]
ch_data_out\[27\] 750 0 2
ch_data_out\[26\]
ch_data_out\[25\]
ch_data_out\[24\]
-ch_clk_out\[5\]
+ch_clk_out\[6\]
ch_data_out\[76\] 1600 0 2
ch_data_out\[75\]
@@ -666,13 +662,11 @@
ch_data_out\[148\]
ch_data_out\[147\]
ch_data_out\[146\]
-ch_clk_out\[10\]
ch_data_out\[153\] 1750 0 2
ch_data_out\[152\]
ch_data_out\[151\]
ch_data_out\[150\]
-ch_clk_out\[11\]
#E
ch_data_out\[19\] 0000 0 2
@@ -685,7 +679,7 @@
ch_data_out\[4\]
ch_clk_out\[1\]
-s0_wbd_stb_o 0100 0 2
+s0_wbd_stb_o 0050 0 2
s0_wbd_we_o
s0_wbd_adr_o\[31\]
s0_wbd_adr_o\[30\]
@@ -892,7 +886,9 @@
s1_wbd_cyc_o
-ch_data_in\[145\] 1350 0 2
+
+
+ch_data_in\[145\] 1250 0 2
ch_data_in\[144\]
ch_data_in\[143\]
ch_data_in\[142\]
@@ -966,7 +962,7 @@
ch_data_out\[78\]
ch_data_out\[77\]
-ch_data_in\[76\] 1550 0 2
+ch_data_in\[76\] 1450 0 2
ch_data_in\[75\]
ch_data_in\[74\]
ch_data_in\[73\]
@@ -1006,8 +1002,9 @@
ch_data_out\[12\]
ch_clk_out\[3\]
-s2_wbd_stb_o 1610 0 2
+s2_wbd_stb_o 1510 0 2
s2_wbd_we_o
+s2_wbd_adr_o\[10\]
s2_wbd_adr_o\[9\]
s2_wbd_adr_o\[8\]
s2_wbd_adr_o\[7\]
@@ -1089,6 +1086,10 @@
s2_wbd_ack_i
s2_wbd_cyc_o
-ch_clk_out\[12\]
-ch_clk_out\[13\]
+ch_clk_out\[7\]
+ch_clk_out\[4\] 1750 0 2
+ch_data_out\[154\]
+ch_data_out\[155\]
+ch_data_out\[156\]
+ch_data_out\[157\]
diff --git a/openlane/ycr2_iconnect/pin_order.cfg b/openlane/ycr2_iconnect/pin_order.cfg
index 48f9639..4eda6fe 100644
--- a/openlane/ycr2_iconnect/pin_order.cfg
+++ b/openlane/ycr2_iconnect/pin_order.cfg
@@ -128,7 +128,8 @@
sram0_dout1\[1\]
sram0_dout1\[0\]
-core0_uid\[1\] 0200 00 2
+core0_clk 0200 00 2
+core0_uid\[1\]
core0_uid\[0\]
core0_imem_req_ack
core0_imem_req
@@ -827,7 +828,8 @@
core_clk_skew
core_clk
-core1_uid\[1\] 0200 00 2
+core1_clk 0200 00 2
+core1_uid\[1\]
core1_uid\[0\]
core1_imem_req_ack
core1_imem_req
@@ -1198,6 +1200,7 @@
#N
+cpu_clk_aes
aes_dmem_req_ack
aes_dmem_req
aes_dmem_cmd
@@ -1278,8 +1281,8 @@
aes_dmem_resp\[0\]
-
-fpu_dmem_req_ack 0200 0 2
+cpu_clk_fpu 0200 0 2
+fpu_dmem_req_ack
fpu_dmem_req
fpu_dmem_cmd
fpu_dmem_width\[1\]
diff --git a/openlane/ycr_core_top/pin_order.cfg b/openlane/ycr_core_top/pin_order.cfg
index f3daaa8..54bb33f 100644
--- a/openlane/ycr_core_top/pin_order.cfg
+++ b/openlane/ycr_core_top/pin_order.cfg
@@ -1,22 +1,21 @@
#BUS_SORT
#MANUAL_PLACE
#E
-pwrup_rst_n
+pwrup_rst_n 0000 00 2
rst_n
-
-cfg_ccska\[3\]
-cfg_ccska\[2\]
-cfg_ccska\[1\]
-cfg_ccska\[0\]
-core_clk_int
-core_clk_skew
-
-clk
-clk_o
core_rst_n_o
core_rdc_qlfy_o
-core_uid\[1\] 0200 00 2
+cfg_ccska\[3\] 0180 00 2
+cfg_ccska\[2\]
+cfg_ccska\[1\]
+cfg_ccska\[0\]
+core_clk_skew
+clk
+clk_o
+
+core_clk_int 0200 00 2
+core_uid\[1\]
core_uid\[0\]
imem2core_req_ack_i
core2imem_req_o
diff --git a/sdc/.caravel.sdc.swp b/sdc/.caravel.sdc.swp
new file mode 100644
index 0000000..92143b4
--- /dev/null
+++ b/sdc/.caravel.sdc.swp
Binary files differ
diff --git a/sdc/aes_top.sdc b/sdc/aes_top.sdc
new file mode 100644
index 0000000..ffe02f5
--- /dev/null
+++ b/sdc/aes_top.sdc
@@ -0,0 +1,277 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 07:49:06 2022
+###############################################################################
+current_design aes_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[5]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[6]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_cmd}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_cmd}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_req}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_req}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_width[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_width[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_width[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_width[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {rst_n}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {rst_n}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {wbd_clk_int}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {wbd_clk_int}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_req_ack}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_resp[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_resp[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {wbd_clk_out}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {wbd_clk_out}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_out}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/bus_rep_east.sdc b/sdc/bus_rep_east.sdc
new file mode 100644
index 0000000..ef1b316
--- /dev/null
+++ b/sdc/bus_rep_east.sdc
@@ -0,0 +1,199 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 10:21:05 2022
+###############################################################################
+current_design bus_rep_east
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[42]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[43]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[44]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[42]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[43]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[44]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {ch_out[44]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[43]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[42]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[41]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[40]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[39]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[38]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[37]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[36]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[35]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[34]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[33]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[32]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[31]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[30]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[29]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[28]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[27]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[26]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[25]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[24]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[23]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[22]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[21]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[20]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[19]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[18]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[17]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[16]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[15]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[14]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[13]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[12]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[11]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[10]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[9]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[8]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/bus_rep_north.sdc b/sdc/bus_rep_north.sdc
new file mode 100644
index 0000000..17f2323
--- /dev/null
+++ b/sdc/bus_rep_north.sdc
@@ -0,0 +1,295 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 10:20:58 2022
+###############################################################################
+current_design bus_rep_north
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[9]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {buf_out[41]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[40]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[39]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[38]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[37]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[36]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[35]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[34]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[33]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[32]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[31]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[30]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[29]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[28]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[27]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[26]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[25]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[24]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[23]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[22]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[21]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[20]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[19]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[18]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[17]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[16]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[15]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[14]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[13]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[12]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[11]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[10]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[9]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[8]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[7]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[6]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[5]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[4]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[3]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[2]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[1]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[0]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[26]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[25]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[24]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[23]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[22]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[21]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[20]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[19]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[18]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[17]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[16]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[15]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[14]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[13]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[12]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[11]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[10]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[9]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[8]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/bus_rep_south.sdc b/sdc/bus_rep_south.sdc
new file mode 100644
index 0000000..07489c0
--- /dev/null
+++ b/sdc/bus_rep_south.sdc
@@ -0,0 +1,1031 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 10:21:25 2022
+###############################################################################
+current_design bus_rep_south
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[100]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[101]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[102]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[103]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[104]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[105]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[106]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[107]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[108]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[109]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[110]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[111]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[112]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[113]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[114]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[115]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[116]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[117]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[118]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[119]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[120]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[121]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[122]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[123]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[124]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[125]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[126]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[127]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[128]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[129]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[130]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[131]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[132]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[133]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[134]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[135]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[136]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[137]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[138]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[139]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[140]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[141]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[142]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[143]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[144]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[145]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[146]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[147]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[148]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[149]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[150]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[151]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[152]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[153]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[154]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[155]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[156]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[157]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[158]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[159]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[160]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[161]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[162]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[163]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[164]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[165]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[166]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[167]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[168]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[169]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[170]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[171]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[172]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[173]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[174]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[175]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[176]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[177]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[178]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[179]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[180]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[181]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[182]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[183]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[184]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[185]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[186]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[187]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[188]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[189]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[190]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[191]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[192]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[193]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[194]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[195]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[196]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[197]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[198]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[199]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[200]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[201]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[202]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[203]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[204]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[205]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[206]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[207]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[208]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[209]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[210]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[211]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[212]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[213]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[214]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[215]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[216]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[217]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[218]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[219]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[220]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[221]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[222]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[223]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[224]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[225]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[226]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[227]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[228]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[229]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[230]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[231]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[232]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[233]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[234]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[235]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[236]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[237]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[238]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[239]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[240]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[241]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[242]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[243]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[244]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[245]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[246]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[247]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[248]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[249]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[250]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[251]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[252]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[42]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[43]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[44]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[45]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[46]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[47]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[48]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[49]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[50]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[51]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[52]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[53]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[54]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[55]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[56]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[57]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[58]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[59]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[60]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[61]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[62]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[63]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[64]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[65]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[66]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[67]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[68]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[69]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[70]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[71]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[72]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[73]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[74]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[75]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[76]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[77]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[78]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[79]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[80]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[81]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[82]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[83]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[84]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[85]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[86]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[87]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[88]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[89]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[90]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[91]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[92]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[93]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[94]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[95]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[96]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[97]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[98]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[99]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[100]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[101]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[102]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[103]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[104]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[105]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[106]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[107]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[108]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[109]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[110]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[111]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[112]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[113]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[114]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[115]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[116]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[117]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[118]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[119]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[120]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[121]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[122]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[123]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[124]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[125]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[126]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[127]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[128]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[129]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[130]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[131]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[132]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[133]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[134]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[135]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[136]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[137]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[138]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[139]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[140]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[141]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[142]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[143]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[144]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[145]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[146]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[147]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[148]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[149]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[150]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[151]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[152]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[153]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[154]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[155]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[156]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[157]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[158]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[159]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[160]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[161]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[162]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[163]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[164]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[165]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[166]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[167]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[168]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[169]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[170]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[171]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[172]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[173]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[174]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[175]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[176]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[177]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[178]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[179]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[180]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[181]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[182]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[183]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[184]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[185]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[186]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[187]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[188]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[189]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[190]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[191]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[192]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[193]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[194]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[195]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[196]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[197]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[198]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[199]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[200]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[201]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[202]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[203]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[204]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[205]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[206]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[207]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[208]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[209]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[210]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[211]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[212]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[213]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[214]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[215]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[216]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[217]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[218]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[219]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[220]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[221]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[222]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[223]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[224]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[225]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[226]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[227]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[228]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[229]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[230]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[231]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[232]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[233]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[234]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[235]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[236]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[237]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[238]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[239]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[240]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[241]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[242]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[243]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[244]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[245]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[246]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[247]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[248]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[249]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[250]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[251]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[252]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[42]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[43]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[44]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[45]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[46]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[47]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[48]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[49]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[50]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[51]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[52]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[53]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[54]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[55]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[56]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[57]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[58]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[59]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[60]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[61]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[62]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[63]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[64]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[65]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[66]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[67]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[68]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[69]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[70]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[71]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[72]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[73]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[74]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[75]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[76]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[77]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[78]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[79]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[80]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[81]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[82]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[83]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[84]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[85]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[86]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[87]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[88]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[89]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[90]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[91]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[92]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[93]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[94]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[95]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[96]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[97]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[98]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[99]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {ch_out[252]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[251]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[250]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[249]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[248]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[247]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[246]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[245]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[244]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[243]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[242]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[241]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[240]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[239]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[238]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[237]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[236]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[235]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[234]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[233]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[232]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[231]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[230]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[229]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[228]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[227]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[226]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[225]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[224]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[223]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[222]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[221]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[220]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[219]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[218]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[217]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[216]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[215]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[214]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[213]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[212]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[211]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[210]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[209]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[208]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[207]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[206]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[205]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[204]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[203]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[202]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[201]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[200]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[199]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[198]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[197]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[196]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[195]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[194]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[193]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[192]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[191]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[190]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[189]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[188]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[187]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[186]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[185]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[184]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[183]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[182]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[181]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[180]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[179]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[178]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[177]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[176]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[175]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[174]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[173]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[172]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[171]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[170]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[169]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[168]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[167]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[166]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[165]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[164]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[163]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[162]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[161]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[160]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[159]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[158]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[157]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[156]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[155]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[154]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[153]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[152]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[151]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[150]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[149]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[148]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[147]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[146]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[145]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[144]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[143]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[142]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[141]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[140]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[139]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[138]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[137]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[136]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[135]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[134]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[133]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[132]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[131]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[130]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[129]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[128]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[127]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[126]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[125]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[124]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[123]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[122]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[121]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[120]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[119]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[118]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[117]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[116]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[115]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[114]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[113]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[112]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[111]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[110]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[109]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[108]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[107]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[106]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[105]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[104]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[103]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[102]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[101]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[100]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[99]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[98]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[97]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[96]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[95]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[94]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[93]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[92]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[91]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[90]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[89]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[88]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[87]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[86]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[85]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[84]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[83]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[82]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[81]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[80]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[79]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[78]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[77]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[76]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[75]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[74]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[73]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[72]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[71]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[70]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[69]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[68]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[67]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[66]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[65]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[64]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[63]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[62]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[61]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[60]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[59]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[58]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[57]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[56]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[55]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[54]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[53]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[52]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[51]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[50]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[49]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[48]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[47]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[46]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[45]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[44]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[43]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[42]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[41]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[40]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[39]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[38]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[37]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[36]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[35]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[34]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[33]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[32]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[31]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[30]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[29]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[28]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[27]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[26]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[25]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[24]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[23]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[22]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[21]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[20]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[19]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[18]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[17]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[16]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[15]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[14]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[13]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[12]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[11]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[10]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[9]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[8]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[252]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[251]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[250]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[249]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[248]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[247]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[246]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[245]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[244]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[243]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[242]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[241]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[240]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[239]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[238]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[237]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[236]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[235]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[234]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[233]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[232]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[231]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[230]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[229]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[228]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[227]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[226]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[225]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[224]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[223]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[222]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[221]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[220]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[219]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[218]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[217]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[216]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[215]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[214]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[213]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[212]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[211]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[210]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[209]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[208]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[207]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[206]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[205]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[204]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[203]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[202]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[201]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[200]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[199]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[198]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[197]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[196]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[195]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[194]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[193]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[192]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[191]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[190]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[189]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[188]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[187]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[186]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[185]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[184]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[183]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[182]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[181]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[180]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[179]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[178]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[177]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[176]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[175]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[174]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[173]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[172]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[171]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[170]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[169]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[168]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[167]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[166]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[165]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[164]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[163]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[162]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[161]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[160]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[159]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[158]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[157]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[156]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[155]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[154]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[153]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[152]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[151]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[150]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[149]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[148]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[147]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[146]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[145]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[144]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[143]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[142]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[141]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[140]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[139]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[138]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[137]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[136]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[135]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[134]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[133]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[132]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[131]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[130]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[129]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[128]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[124]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[123]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[122]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[121]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[120]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[119]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[118]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[117]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[116]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[115]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[114]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[113]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[112]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[111]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[110]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[109]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[108]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[107]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[106]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[105]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[104]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[103]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[102]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[101]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[100]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[99]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[98]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[97]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[96]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[95]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[94]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[93]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[92]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[91]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[90]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[89]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[88]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[87]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[86]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[85]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[84]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[83]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[82]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[81]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[80]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[79]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[78]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[77]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[76]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[75]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[74]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[73]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[72]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[71]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[70]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[69]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[68]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[67]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[66]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[65]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[64]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[63]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[62]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[61]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[60]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[59]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[58]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[57]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[56]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[55]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[54]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[53]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[52]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[51]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[50]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[49]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/bus_rep_west.sdc b/sdc/bus_rep_west.sdc
new file mode 100644
index 0000000..b8e774e
--- /dev/null
+++ b/sdc/bus_rep_west.sdc
@@ -0,0 +1,187 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 10:21:17 2022
+###############################################################################
+current_design bus_rep_west
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {ch_out[41]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[40]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[39]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[38]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[37]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[36]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[35]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[34]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[33]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[32]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[31]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[30]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[29]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[28]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[27]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[26]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[25]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[24]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[23]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[22]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[21]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[20]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[19]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[18]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[17]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[16]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[15]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[14]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[13]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[12]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[11]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[10]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[9]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[8]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/caravel.sdc b/sdc/caravel.sdc
new file mode 100644
index 0000000..9ddeee6
--- /dev/null
+++ b/sdc/caravel.sdc
@@ -0,0 +1,364 @@
+### Caravel Signoff SDC
+### Rev 3
+### Date: 28/10/2022
+### Reference SDC: $CARAVEL_ROOT/signoff/caravel/caravel.sdc
+
+## MASTER CLOCKS
+## Reduce the clock speed from 25ns 40ns
+create_clock -name clk -period 40 [get_ports {clock}]
+
+create_clock -name hkspi_clk -period 100 [get_pins {housekeeping/mgmt_gpio_in[4]} ]
+create_clock -name hk_serial_clk -period 50 [get_pins {housekeeping/serial_clock}]
+create_clock -name hk_serial_load -period 1000 [get_pins {housekeeping/serial_load}]
+# hk_serial_clk period is x2 core clock
+
+### User Project Clocks
+create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clk] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i]
+create_clock -name int_pll_clock -period 5.0000 [get_pins {mprj/u_pinmux/int_pll_clock}]
+
+create_clock -name wbs_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_reg.u_wbs_ref_clkbuf.u_buf/X}]
+create_clock -name wbs_clk_i -period 26.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}]
+
+create_clock -name cpu_ref_clk -period 5.0000 [get_pins {mprj/u_wb_host/u_reg.u_cpu_ref_clkbuf.u_buf/X}]
+create_clock -name cpu_clk -period 40.0000 [get_pins {mprj/u_wb_host/cpu_clk}]
+
+create_clock -name rtc_ref_clk -period 50.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_rtc_ref_clkbuf.u_buf/X}]
+create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_rtc.u_buf/X}]
+
+create_clock -name pll_ref_clk -period 20.0000 [get_pins {mprj/u_pinmux/pll_ref_clk}]
+create_clock -name pll_clk_0 -period 12.0000 [get_pins {mprj/u_pll/ringosc.ibufp01/Y}]
+
+create_clock -name usb_ref_clk -period 6.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_usb_ref_clkbuf.u_buf/X}]
+create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_usb.u_buf/X}]
+create_clock -name uarts0_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uarts1_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
+create_clock -name dbg_ref_clk -period 12.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_dbg_ref.u_buf/X}]
+
+set_clock_uncertainty 0.1000 [all_clocks]
+
+set_clock_groups \
+ -name clock_group \
+ -logically_exclusive \
+ -group [get_clocks {wb_clk clk}]\
+ -group [get_clocks {hk_serial_clk}]\
+ -group [get_clocks {hk_serial_load}]\
+ -group [get_clocks {hkspi_clk}]\
+ -group [get_clocks {int_pll_clock}]\
+ -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {wbs_ref_clk}]\
+ -group [get_clocks {cpu_clk}]\
+ -group [get_clocks {cpu_ref_clk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {usb_ref_clk}]\
+ -group [get_clocks {pll_ref_clk}]\
+ -group [get_clocks {pll_clk_0}]\
+ -group [get_clocks {usb_clk}]\
+ -group [get_clocks {uarts0_clk}]\
+ -group [get_clocks {uarts1_clk}]\
+ -group [get_clocks {uartm_clk}]\
+ -group [get_clocks {dbg_ref_clk}]\
+ -group [get_clocks {rtc_ref_clk}]\
+ -comment {Async Clock group}
+
+# clock <-> hk_serial_clk/load no paths
+# future note: CDC stuff
+# clock <-> hkspi_clk no paths with careful methods (clock is off)
+
+set_propagated_clock [all_clocks]
+
+## INPUT/OUTPUT DELAYS
+set input_delay_value 4
+set output_delay_value 4
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {gpio}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[0]}]
+
+#set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[1]}]
+
+set_input_delay $input_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[2]}]
+set_input_delay $input_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[3]}]
+
+#set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[4]}]
+
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[5]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[6]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[7]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[8]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[9]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[10]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[11]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[12]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[13]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[14]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[15]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[16]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[17]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[18]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[19]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[20]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[21]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[22]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[23]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[24]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[25]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[26]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[27]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[28]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[29]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[30]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[31]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[32]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[33]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[34]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[35]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[36]}]
+set_input_delay $input_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[37]}]
+
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_csb}]
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_clk}]
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io0}]
+set_output_delay $output_delay_value -clock [get_clocks {clk}] -add_delay [get_ports {flash_io1}]
+
+# set_output_delay $output_delay_value -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[1]}]
+
+set_max_fanout 12 [current_design]
+# synthesis max fanout should be less than 12 (7 maybe)
+
+## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled
+set_case_analysis 0 [get_pins housekeeping/_3936_/S]
+set_case_analysis 0 [get_pins housekeeping/_3937_/S]
+
+# Add case analysis for pads DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 to be outputs
+
+set_case_analysis 1 [get_pins padframe/*_pad*/DM[2]]
+set_case_analysis 1 [get_pins padframe/*_pad*/DM[1]]
+set_case_analysis 0 [get_pins padframe/*_pad*/DM[0]]
+set_case_analysis 0 [get_pins padframe/*_pad*/SLOW]
+set_case_analysis 0 [get_pins padframe/*_pad*/ANALOG_EN]
+
+# the following pads are set as inputs
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[2]]
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[1]]
+set_case_analysis 1 [get_pins padframe/*area1_io_pad[4]/DM[0]]
+
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[2]]
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[1]]
+set_case_analysis 1 [get_pins padframe/*area1_io_pad[2]/DM[0]]
+
+
+set_case_analysis 0 [get_pins padframe/clock_pad/DM[2]]
+set_case_analysis 0 [get_pins padframe/clock_pad/DM[1]]
+set_case_analysis 1 [get_pins padframe/clock_pad/DM[0]]
+
+#################################################################
+## User Case analysis
+#################################################################
+set_case_analysis 0 [get_pins {mprj/u_peri/cfg_cska_peri[3]}]
+set_case_analysis 1 [get_pins {mprj/u_peri/cfg_cska_peri[2]}]
+set_case_analysis 0 [get_pins {mprj/u_peri/cfg_cska_peri[1]}]
+set_case_analysis 0 [get_pins {mprj/u_peri/cfg_cska_peri[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[3]}]
+set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}]
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}]
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}]
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}]
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}]
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}]
+set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}]
+set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}]
+
+# clock skew cntrl-2
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_fpu/cfg_cska[2]}]
+set_case_analysis 1 [get_pins {mprj/u_fpu/cfg_cska[1]}]
+set_case_analysis 1 [get_pins {mprj/u_fpu/cfg_cska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_aes/cfg_cska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[0]}]
+
+#set_case_analysis 1 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[3]}]
+#set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[2]}]
+#set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[1]}]
+#set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[0]}]
+
+#set_case_analysis 1 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[3]}]
+#set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[2]}]
+#set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[1]}]
+#set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[0]}]
+
+
+
+
+#Keept the SRAM clock driving edge at pos edge
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[1]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[1]}]
+
+
+## FALSE PATHS (ASYNCHRONOUS INPUTS)
+set_false_path -from [get_ports {resetb}]
+
+## Async USB/I2C Interrupt, Double Sync added inside glbl block
+set_false_path -through [get_pins {mprj/u_pinmux/usb_intr}]
+set_false_path -through [get_pins {mprj/u_pinmux/i2cm_intr}]
+
+## UART RXD is async signal
+set_false_path -through [get_pins {mprj/u_wb_host/uartm_rxd}]
+
+##SPI Slave Interface Signal (SCLK/SSN) are double sync with wb_clk
+set_false_path -through [get_pins {mprj/u_wb_host/sclk}]
+set_false_path -through [get_pins {mprj/u_wb_host/ssn}]
+## SDIN sampled on negedge SCLK
+set_false_path -through [get_pins {mprj/u_wb_host/sdin}]
+
+
+# set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_in[*]]
+# reset_path -from [get_ports mprj_io[4]]
+# reset_path -from [get_ports mprj_io[2]]
+#reset_path is not supported in PT read_sdc ^
+
+set_false_path -from [get_ports mprj_io[0]] -through [get_pins housekeeping/mgmt_gpio_in[0]]
+set_false_path -from [get_ports mprj_io[1]] -through [get_pins housekeeping/mgmt_gpio_in[1]]
+set_false_path -from [get_ports mprj_io[3]] -through [get_pins housekeeping/mgmt_gpio_in[3]]
+set_false_path -from [get_ports mprj_io[5]] -through [get_pins housekeeping/mgmt_gpio_in[5]]
+set_false_path -from [get_ports mprj_io[6]] -through [get_pins housekeeping/mgmt_gpio_in[6]]
+set_false_path -from [get_ports mprj_io[7]] -through [get_pins housekeeping/mgmt_gpio_in[7]]
+set_false_path -from [get_ports mprj_io[8]] -through [get_pins housekeeping/mgmt_gpio_in[8]]
+set_false_path -from [get_ports mprj_io[9]] -through [get_pins housekeeping/mgmt_gpio_in[9]]
+set_false_path -from [get_ports mprj_io[10]] -through [get_pins housekeeping/mgmt_gpio_in[10]]
+set_false_path -from [get_ports mprj_io[11]] -through [get_pins housekeeping/mgmt_gpio_in[11]]
+set_false_path -from [get_ports mprj_io[12]] -through [get_pins housekeeping/mgmt_gpio_in[12]]
+set_false_path -from [get_ports mprj_io[13]] -through [get_pins housekeeping/mgmt_gpio_in[13]]
+set_false_path -from [get_ports mprj_io[14]] -through [get_pins housekeeping/mgmt_gpio_in[14]]
+set_false_path -from [get_ports mprj_io[15]] -through [get_pins housekeeping/mgmt_gpio_in[15]]
+set_false_path -from [get_ports mprj_io[16]] -through [get_pins housekeeping/mgmt_gpio_in[16]]
+set_false_path -from [get_ports mprj_io[17]] -through [get_pins housekeeping/mgmt_gpio_in[17]]
+set_false_path -from [get_ports mprj_io[18]] -through [get_pins housekeeping/mgmt_gpio_in[18]]
+set_false_path -from [get_ports mprj_io[19]] -through [get_pins housekeeping/mgmt_gpio_in[19]]
+set_false_path -from [get_ports mprj_io[20]] -through [get_pins housekeeping/mgmt_gpio_in[20]]
+set_false_path -from [get_ports mprj_io[21]] -through [get_pins housekeeping/mgmt_gpio_in[21]]
+set_false_path -from [get_ports mprj_io[22]] -through [get_pins housekeeping/mgmt_gpio_in[22]]
+set_false_path -from [get_ports mprj_io[23]] -through [get_pins housekeeping/mgmt_gpio_in[23]]
+set_false_path -from [get_ports mprj_io[24]] -through [get_pins housekeeping/mgmt_gpio_in[24]]
+set_false_path -from [get_ports mprj_io[25]] -through [get_pins housekeeping/mgmt_gpio_in[25]]
+set_false_path -from [get_ports mprj_io[26]] -through [get_pins housekeeping/mgmt_gpio_in[26]]
+set_false_path -from [get_ports mprj_io[27]] -through [get_pins housekeeping/mgmt_gpio_in[27]]
+set_false_path -from [get_ports mprj_io[28]] -through [get_pins housekeeping/mgmt_gpio_in[28]]
+set_false_path -from [get_ports mprj_io[29]] -through [get_pins housekeeping/mgmt_gpio_in[29]]
+set_false_path -from [get_ports mprj_io[30]] -through [get_pins housekeeping/mgmt_gpio_in[30]]
+set_false_path -from [get_ports mprj_io[31]] -through [get_pins housekeeping/mgmt_gpio_in[31]]
+set_false_path -from [get_ports mprj_io[32]] -through [get_pins housekeeping/mgmt_gpio_in[32]]
+set_false_path -from [get_ports mprj_io[33]] -through [get_pins housekeeping/mgmt_gpio_in[33]]
+set_false_path -from [get_ports mprj_io[34]] -through [get_pins housekeeping/mgmt_gpio_in[34]]
+set_false_path -from [get_ports mprj_io[35]] -through [get_pins housekeeping/mgmt_gpio_in[35]]
+set_false_path -from [get_ports mprj_io[36]] -through [get_pins housekeeping/mgmt_gpio_in[36]]
+set_false_path -from [get_ports mprj_io[37]] -through [get_pins housekeeping/mgmt_gpio_in[37]]
+
+set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_out[*]]
+set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_oeb[*]]
+set_false_path -from [get_ports gpio]
+
+#### LA Input to wb_host are false path
+set_false_path -through [get_pins mprj/u_wb_host/la_data_in[*] ]
+
+### These reset has reset synchronozation
+set_false_path -through [get_pins mprj/u_uart_i2c_usb_spi/i2c_rstn ]
+set_false_path -through [get_pins mprj/u_uart_i2c_usb_spi/spi_rstn ]
+set_false_path -through [get_pins mprj/u_uart_i2c_usb_spi/usb_rstn ]
+set_false_path -through [get_pins mprj/u_uart_i2c_usb_spi/uart_rstn[*] ]
+
+
+
+# add loads for output ports (pads)
+set min_cap 5
+set max_cap 10
+puts "\[INFO\]: Cap load range: $min_cap : $max_cap"
+# set_load 10 [all_outputs]
+set_load -min $min_cap [all_outputs]
+set_load -max $max_cap [all_outputs]
+
+#add input transition for the inputs ports (pads)
+# set_input_transition 2 [all_inputs]
+#add exception for power pads as 2ns on them results in max_tran violations (false viol)
+# set_input_transition 2 [remove_from_collection [all_inputs] [get_ports v*]]
+# remove_from_collection is not supported in PT read_sdc ^
+# set_input_transition 2 [all_inputs]
+# set_input_transition 0 [get_ports v*]
+
+set min_in_tran 1
+set max_in_tran 4
+puts "\[INFO\]: Input transition range: $min_in_tran : $max_in_tran"
+set_input_transition -min $min_in_tran [all_inputs]
+set_input_transition -min 0 [get_ports v*]
+set_input_transition -max $max_in_tran [all_inputs]
+set_input_transition -max 0 [get_ports v*]
+
+# check ocv table (not provided) -- maybe try 8%
+set derate 0.0375
+puts "\[INFO\]: Setting derate factor to: [expr $derate * 100] %"
+set_timing_derate -early [expr 1-$derate]
+set_timing_derate -late [expr 1+$derate]
+
+# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
+# apply the constraint to hd cells at the ss corner only
+# if {$::env(PROC_CORNER) == "s"} {
+# set max_tran 1.5
+# set_max_transition $max_tran [get_pins -of_objects [get_cells -filter {ref_name=~sky130_fd_sc_hd*}]]
+# set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
+# set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
+# puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
+# }
+# -filter not supported in PT read_sdc ^
diff --git a/sdc/dg_pll.sdc b/sdc/dg_pll.sdc
new file mode 100644
index 0000000..ee6b582
--- /dev/null
+++ b/sdc/dg_pll.sdc
@@ -0,0 +1,61 @@
+###############################################################################
+# Created by write_sdc
+# Tue Nov 22 06:29:19 2022
+###############################################################################
+current_design dg_pll
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name pll_control_clock -period 6.6667 [get_pins {ringosc.ibufp01/Y}]
+set_clock_transition 0.1500 [get_clocks {pll_control_clock}]
+set_clock_uncertainty -setup 0.5000 pll_control_clock
+set_clock_uncertainty -hold 0.2500 pll_control_clock
+set_propagated_clock [get_clocks {pll_control_clock}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {clockp[1]}]
+set_load -pin_load 0.0334 [get_ports {clockp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dco}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {enable}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {osc}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetb}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/digital_pll.sdc b/sdc/digital_pll.sdc
new file mode 100644
index 0000000..d56c67f
--- /dev/null
+++ b/sdc/digital_pll.sdc
@@ -0,0 +1,97 @@
+###############################################################################
+# Created by write_sdc
+# Fri Sep 16 17:32:50 2022
+###############################################################################
+current_design digital_pll
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name pll_control_clock -period 6.6667 [get_pins {ringosc.ibufp01/Y}]
+set_clock_transition 0.1500 [get_clocks {pll_control_clock}]
+set_clock_uncertainty 0.2500 pll_control_clock
+set_propagated_clock [get_clocks {pll_control_clock}]
+set_input_delay 2.0000 -add_delay [get_ports {dco}]
+set_input_delay 2.0000 -add_delay [get_ports {div[0]}]
+set_input_delay 2.0000 -add_delay [get_ports {div[1]}]
+set_input_delay 2.0000 -add_delay [get_ports {div[2]}]
+set_input_delay 2.0000 -add_delay [get_ports {div[3]}]
+set_input_delay 2.0000 -add_delay [get_ports {div[4]}]
+set_input_delay 2.0000 -add_delay [get_ports {enable}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[0]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[10]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[11]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[12]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[13]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[14]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[15]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[16]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[17]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[18]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[19]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[1]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[20]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[21]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[22]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[23]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[24]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[25]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[2]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[3]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[4]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[5]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[6]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[7]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[8]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[9]}]
+set_input_delay 2.0000 -add_delay [get_ports {osc}]
+set_input_delay 2.0000 -add_delay [get_ports {resetb}]
+set_output_delay 2.0000 -add_delay [get_ports {clockp[0]}]
+set_output_delay 2.0000 -add_delay [get_ports {clockp[1]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {clockp[1]}]
+set_load -pin_load 0.0334 [get_ports {clockp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dco}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {enable}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {osc}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetb}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/fpu_wrapper.sdc b/sdc/fpu_wrapper.sdc
new file mode 100644
index 0000000..d8cab24
--- /dev/null
+++ b/sdc/fpu_wrapper.sdc
@@ -0,0 +1,271 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 08:53:56 2022
+###############################################################################
+current_design fpu_wrapper
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_cmd}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_cmd}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_req}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_req}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_width[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_width[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_width[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_width[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {rst_n}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {rst_n}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {wbd_clk_int}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {wbd_clk_int}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_req_ack}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_resp[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_resp[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {wbd_clk_out}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {wbd_clk_out}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_out}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/peri_top.sdc b/sdc/peri_top.sdc
new file mode 100644
index 0000000..9c549e3
--- /dev/null
+++ b/sdc/peri_top.sdc
@@ -0,0 +1,401 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 10:44:09 2022
+###############################################################################
+current_design peri_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+create_clock -name rtc_clk -period 100.0000 [get_ports {rtc_clk}]
+set_clock_transition 0.1500 [get_clocks {rtc_clk}]
+set_clock_uncertainty 0.2500 rtc_clk
+set_propagated_clock [get_clocks {rtc_clk}]
+set_clock_groups -name clock_group -logically_exclusive \
+ -group [get_clocks {mclk}]\
+ -group [get_clocks {rtc_clk}] -comment {Async Clock group}
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[10]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[9]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_cs}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_cs}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wr}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wr}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {s_reset_n}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {s_reset_n}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {rtc_clk}] -min -add_delay [get_ports {inc_date_d}]
+set_output_delay 6.0000 -clock [get_clocks {rtc_clk}] -max -add_delay [get_ports {inc_date_d}]
+set_output_delay 1.0000 -clock [get_clocks {rtc_clk}] -min -add_delay [get_ports {inc_time_s}]
+set_output_delay 6.0000 -clock [get_clocks {rtc_clk}] -max -add_delay [get_ports {inc_time_s}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_ack}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_ack}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {rtc_clk}] -min -add_delay [get_ports {rtc_intr}]
+set_output_delay 6.0000 -clock [get_clocks {rtc_clk}] -max -add_delay [get_ports {rtc_intr}]
+set_max_delay\
+ -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+ -from [get_ports {wbd_clk_int}]\
+ -to [get_ports {wbd_clk_peri}] 3.5000
+set_max_delay\
+ -to [get_ports {wbd_clk_peri}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {inc_date_d}]
+set_load -pin_load 0.0334 [get_ports {inc_time_s}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {rtc_intr}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_peri}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/pinmux.sdc b/sdc/pinmux.sdc
new file mode 100644
index 0000000..79cbc0d
--- /dev/null
+++ b/sdc/pinmux.sdc
@@ -0,0 +1,520 @@
+###############################################################################
+# Created by write_sdc
+# Sun Aug 14 14:58:56 2022
+###############################################################################
+current_design pinmux
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty -setup 0.5000 mclk
+set_clock_uncertainty -hold 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {h_reset_n}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_cs}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_cs}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wr}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wr}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {qspim_rst_n}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {qspim_rst_n}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_ack}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_ack}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[9]}]
+set_max_delay\
+ -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+ -from [get_ports {wbd_clk_int}]\
+ -to [get_ports {wbd_clk_pinmux}] 3.5000
+set_max_delay\
+ -to [get_ports {wbd_clk_pinmux}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {cpu_intf_rst_n}]
+set_load -pin_load 0.0334 [get_ports {i2cm_clk_i}]
+set_load -pin_load 0.0334 [get_ports {i2cm_data_i}]
+set_load -pin_load 0.0334 [get_ports {i2cm_rst_n}]
+set_load -pin_load 0.0334 [get_ports {pulse1m_mclk}]
+set_load -pin_load 0.0334 [get_ports {qspim_rst_n}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {soft_irq}]
+set_load -pin_load 0.0334 [get_ports {spim_mosi}]
+set_load -pin_load 0.0334 [get_ports {spis_mosi}]
+set_load -pin_load 0.0334 [get_ports {spis_sck}]
+set_load -pin_load 0.0334 [get_ports {spis_ssn}]
+set_load -pin_load 0.0334 [get_ports {sspim_rst_n}]
+set_load -pin_load 0.0334 [get_ports {uartm_rxd}]
+set_load -pin_load 0.0334 [get_ports {usb_dn_i}]
+set_load -pin_load 0.0334 [get_ports {usb_dp_i}]
+set_load -pin_load 0.0334 [get_ports {usb_rst_n}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_pinmux}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[0]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[1]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[0]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[37]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[36]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[35]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[34]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[33]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[32]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[31]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[30]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[29]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[28]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[27]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[26]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[25]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[24]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[23]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[22]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[21]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[20]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[19]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[18]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[17]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[16]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[15]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[14]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[13]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[12]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[11]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[10]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[9]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[8]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[7]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[6]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[5]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[4]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[3]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[2]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[1]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[0]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[15]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[14]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[13]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[12]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[11]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[10]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[9]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[8]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[7]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[6]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[5]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[4]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[3]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[2]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[1]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[0]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[3]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[2]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[1]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_rst_n[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_rst_n[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_rxd[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_rxd[0]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_clk_mon}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {h_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_clk_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_clk_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_sck}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_miso}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_sck}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spis_miso}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uartm_txd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_dn_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_dp_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_txd[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_txd[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/sdc/pinmux_top.sdc b/sdc/pinmux_top.sdc
new file mode 100644
index 0000000..4d80b95
--- /dev/null
+++ b/sdc/pinmux_top.sdc
@@ -0,0 +1,783 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 06:19:01 2022
+###############################################################################
+current_design pinmux_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty -setup 0.5000 mclk
+set_clock_uncertainty -hold 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+create_clock -name user_clock1 -period 10.0000 [get_ports {user_clock1}]
+set_clock_transition 0.1500 [get_clocks {user_clock1}]
+set_clock_uncertainty -setup 0.5000 user_clock1
+set_clock_uncertainty -hold 0.2500 user_clock1
+set_propagated_clock [get_clocks {user_clock1}]
+create_clock -name user_clock2 -period 10.0000 [get_ports {user_clock2}]
+set_clock_transition 0.1500 [get_clocks {user_clock2}]
+set_clock_uncertainty -setup 0.5000 user_clock2
+set_clock_uncertainty -hold 0.2500 user_clock2
+set_propagated_clock [get_clocks {user_clock2}]
+create_clock -name int_pll_clock -period 5.0000
+set_clock_uncertainty -setup 0.5000 int_pll_clock
+set_clock_uncertainty -hold 0.2500 int_pll_clock
+create_clock -name rtc_ref_clk -period 50.0000 [get_pins {u_glbl_reg.u_rtc_ref_clkbuf.u_buf/X}]
+set_clock_transition 0.1500 [get_clocks {rtc_ref_clk}]
+set_clock_uncertainty -setup 0.5000 rtc_ref_clk
+set_clock_uncertainty -hold 0.2500 rtc_ref_clk
+set_propagated_clock [get_clocks {rtc_ref_clk}]
+create_clock -name rtc_clk -period 50.0000 [get_pins {u_glbl_reg.u_clkbuf_rtc.u_buf/X}]
+set_clock_transition 0.1500 [get_clocks {rtc_clk}]
+set_clock_uncertainty -setup 0.5000 rtc_clk
+set_clock_uncertainty -hold 0.2500 rtc_clk
+set_propagated_clock [get_clocks {rtc_clk}]
+create_clock -name usb_ref_clk -period 5.0000 [get_pins {u_glbl_reg.u_usb_ref_clkbuf.u_buf/X}]
+set_clock_transition 0.1500 [get_clocks {usb_ref_clk}]
+set_clock_uncertainty -setup 0.5000 usb_ref_clk
+set_clock_uncertainty -hold 0.2500 usb_ref_clk
+set_propagated_clock [get_clocks {usb_ref_clk}]
+create_clock -name dbg_ref_clk -period 10.0000 [get_pins {u_glbl_reg.u_clkbuf_dbg_ref.u_buf/X}]
+set_clock_transition 0.1500 [get_clocks {dbg_ref_clk}]
+set_clock_uncertainty -setup 0.5000 dbg_ref_clk
+set_clock_uncertainty -hold 0.2500 dbg_ref_clk
+set_propagated_clock [get_clocks {dbg_ref_clk}]
+set_clock_groups -name clock_group -logically_exclusive \
+ -group [get_clocks {dbg_ref_clk}]\
+ -group [get_clocks {int_pll_clock}]\
+ -group [get_clocks {mclk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {rtc_ref_clk}]\
+ -group [get_clocks {usb_ref_clk}]\
+ -group [get_clocks {user_clock1}]\
+ -group [get_clocks {user_clock2}] -comment {Async Clock group}
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[10]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[9]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_cs}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_cs}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wr}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wr}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {qspim_rst_n}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {qspim_rst_n}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_ack}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_ack}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[9]}]
+set_max_delay\
+ -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+ -from [get_ports {wbd_clk_int}]\
+ -to [get_ports {wbd_clk_pinmux}] 3.5000
+set_max_delay\
+ -to [get_ports {wbd_clk_pinmux}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {cfg_dco_mode}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_enb}]
+set_load -pin_load 0.0334 [get_ports {cpu_intf_rst_n}]
+set_load -pin_load 0.0334 [get_ports {i2cm_clk_i}]
+set_load -pin_load 0.0334 [get_ports {i2cm_data_i}]
+set_load -pin_load 0.0334 [get_ports {i2cm_rst_n}]
+set_load -pin_load 0.0334 [get_ports {pll_ref_clk}]
+set_load -pin_load 0.0334 [get_ports {pulse1m_mclk}]
+set_load -pin_load 0.0334 [get_ports {qspim_rst_n}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_cs}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wr}]
+set_load -pin_load 0.0334 [get_ports {rtc_clk}]
+set_load -pin_load 0.0334 [get_ports {soft_irq}]
+set_load -pin_load 0.0334 [get_ports {spim_mosi}]
+set_load -pin_load 0.0334 [get_ports {spis_mosi}]
+set_load -pin_load 0.0334 [get_ports {spis_sck}]
+set_load -pin_load 0.0334 [get_ports {spis_ssn}]
+set_load -pin_load 0.0334 [get_ports {sspim_rst_n}]
+set_load -pin_load 0.0334 [get_ports {uartm_rxd}]
+set_load -pin_load 0.0334 [get_ports {usb_clk}]
+set_load -pin_load 0.0334 [get_ports {usb_dn_i}]
+set_load -pin_load 0.0334 [get_ports {usb_dp_i}]
+set_load -pin_load 0.0334 [get_ports {usb_rst_n}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_pinmux}]
+set_load -pin_load 0.0334 [get_ports {xtal_clk}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[25]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[24]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[23]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[22]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[21]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[20]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[19]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[18]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[17]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[16]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[0]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[3]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[2]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[1]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[0]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[37]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[36]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[35]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[34]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[33]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[32]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[31]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[30]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[29]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[28]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[27]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[26]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[25]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[24]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[23]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[22]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[21]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[20]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[19]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[18]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[17]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[16]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[15]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[14]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[13]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[12]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[11]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[10]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[9]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[8]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[7]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[6]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[5]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[4]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[3]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[2]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[1]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[0]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[31]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[30]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[29]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[28]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[27]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[26]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[25]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[24]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[23]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[22]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[21]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[20]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[19]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[18]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[17]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[16]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[15]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[14]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[13]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[12]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[11]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[10]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[9]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[8]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[7]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[6]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[5]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[4]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[3]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[2]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[1]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[0]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[3]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[2]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[1]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[0]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[31]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[30]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[29]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[28]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[27]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[26]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[25]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[24]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[23]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[22]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[21]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[20]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[19]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[18]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[17]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[16]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[15]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[14]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[13]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[12]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[11]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[10]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[9]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[8]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[7]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[6]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[5]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[4]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[3]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[2]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[1]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[0]}]
+set_load -pin_load 0.0334 [get_ports {strap_uartm[1]}]
+set_load -pin_load 0.0334 [get_ports {strap_uartm[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_rst_n[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_rst_n[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_rxd[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_rxd[0]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_strap_pad_ctrl}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cpu_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {e_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_clk_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_clk_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {int_pll_clock}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {p_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_ack}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_sck}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_miso}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_sck}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spis_miso}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uartm_txd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_dn_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_dp_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock1}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_txd[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_txd[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/qspim_top.sdc b/sdc/qspim_top.sdc
new file mode 100644
index 0000000..7e6c99e
--- /dev/null
+++ b/sdc/qspim_top.sdc
@@ -0,0 +1,532 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 07:01:53 2022
+###############################################################################
+current_design qspim_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty -setup 0.5000 mclk
+set_clock_uncertainty -hold 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+create_generated_clock -name spiclk -add -source [get_ports {mclk}] -master_clock [get_clocks {mclk}] -divide_by 2 -comment {SPI Clock Out} [get_ports {spi_clk}]
+set_clock_transition 0.1500 [get_clocks {spiclk}]
+set_clock_uncertainty -setup 0.5000 spiclk
+set_clock_uncertainty -hold 0.2500 spiclk
+set_propagated_clock [get_clocks {spiclk}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {rst_n}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {rst_n}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[0]}]
+set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[0]}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[1]}]
+set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[1]}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[2]}]
+set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[2]}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[3]}]
+set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[3]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[0]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[10]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[11]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[12]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[13]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[14]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[15]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[16]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[17]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[18]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[19]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[1]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[20]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[21]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[22]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[23]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[24]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[25]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[26]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[27]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[28]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[29]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[2]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[30]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[31]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[3]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[4]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[5]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[6]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[7]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[8]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[9]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[0]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[10]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[11]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[12]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[13]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[14]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[15]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[16]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[17]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[18]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[19]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[1]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[20]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[21]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[22]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[23]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[24]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[25]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[26]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[27]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[28]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[29]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[2]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[30]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[31]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[3]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[4]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[5]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[6]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[7]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[8]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[9]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[0]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[1]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[2]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[3]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_stb_i}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_stb_i}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_we_i}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_we_i}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[0]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[0]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[1]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[1]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[2]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[2]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[3]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[3]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[0]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[0]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[1]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[1]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[2]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[2]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[3]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[3]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[0]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[0]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[1]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[1]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[2]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[2]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[3]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[3]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_ack_o}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_ack_o}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[0]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[10]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[10]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[11]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[11]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[12]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[12]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[13]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[13]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[14]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[14]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[15]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[15]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[16]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[16]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[17]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[17]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[18]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[18]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[19]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[19]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[1]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[20]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[20]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[21]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[21]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[22]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[22]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[23]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[23]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[24]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[24]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[25]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[25]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[26]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[26]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[27]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[27]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[28]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[28]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[29]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[29]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[2]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[30]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[30]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[31]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[31]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[3]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[4]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[5]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[6]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[7]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[8]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[8]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[9]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[9]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_err_o}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_err_o}]
+set_max_delay\
+ -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+ -from [get_ports {wbd_clk_int}]\
+ -to [get_ports {wbd_clk_spi}] 3.5000
+set_max_delay\
+ -to [get_ports {spi_debug[0]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[10]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[11]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[12]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[13]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[14]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[15]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[16]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[17]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[18]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[19]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[1]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[20]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[21]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[22]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[23]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[24]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[25]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[26]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[27]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[28]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[29]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[2]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[30]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[31]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[3]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[4]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[5]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[6]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[7]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[8]}] 10.0000
+set_max_delay\
+ -to [get_ports {spi_debug[9]}] 10.0000
+set_max_delay\
+ -to [get_ports {wbd_clk_spi}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {spi_clk}]
+set_load -pin_load 0.0334 [get_ports {wbd_ack_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_spi}]
+set_load -pin_load 0.0334 [get_ports {wbd_err_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_lack_o}]
+set_load -pin_load 0.0334 [get_ports {spi_csn[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_csn[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_csn[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_csn[0]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[0]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_init_bypass}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_pre_sram}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sram}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bry_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_flash[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_flash[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[3]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/uart_i2c_usb_spi_top.sdc b/sdc/uart_i2c_usb_spi_top.sdc
new file mode 100644
index 0000000..fa4c4a4
--- /dev/null
+++ b/sdc/uart_i2c_usb_spi_top.sdc
@@ -0,0 +1,425 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 07:47:01 2022
+###############################################################################
+current_design uart_i2c_usb_spi_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name app_clk -period 10.0000 [get_ports {app_clk}]
+set_clock_transition 0.1500 [get_clocks {app_clk}]
+set_clock_uncertainty -setup 0.5000 app_clk
+set_clock_uncertainty -hold 0.2500 app_clk
+set_propagated_clock [get_clocks {app_clk}]
+create_clock -name uart0_baud_clk -period 100.0000 [get_pins {u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}]
+set_clock_transition 0.1500 [get_clocks {uart0_baud_clk}]
+set_clock_uncertainty -setup 0.5000 uart0_baud_clk
+set_clock_uncertainty -hold 0.2500 uart0_baud_clk
+set_propagated_clock [get_clocks {uart0_baud_clk}]
+create_clock -name uart1_baud_clk -period 100.0000 [get_pins {u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}]
+set_clock_transition 0.1500 [get_clocks {uart1_baud_clk}]
+set_clock_uncertainty -setup 0.5000 uart1_baud_clk
+set_clock_uncertainty -hold 0.2500 uart1_baud_clk
+set_propagated_clock [get_clocks {uart1_baud_clk}]
+create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}]
+set_clock_transition 0.1500 [get_clocks {usb_clk}]
+set_clock_uncertainty -setup 0.5000 usb_clk
+set_clock_uncertainty -hold 0.2500 usb_clk
+set_propagated_clock [get_clocks {usb_clk}]
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {app_clk}]\
+ -group [get_clocks {uart0_baud_clk}]\
+ -group [get_clocks {uart1_baud_clk}]\
+ -group [get_clocks {usb_clk}] -comment {Async Clock group}
+set_input_delay 1.5000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {i2c_rstn}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {i2c_rstn}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[0]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[0]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[1]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[1]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[2]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[2]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[3]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[3]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_cs}]
+set_input_delay 5.7500 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_cs}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wr}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wr}]
+set_input_delay 1.5000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {uart_rstn[0]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {uart_rstn[0]}]
+set_input_delay 1.5000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {uart_rstn[1]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {uart_rstn[1]}]
+set_input_delay 1.5000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {usb_rstn}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {usb_rstn}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[9]}]
+set_multicycle_path -hold\
+ -from [list [get_ports {reg_addr[0]}]\
+ [get_ports {reg_addr[1]}]\
+ [get_ports {reg_addr[2]}]\
+ [get_ports {reg_addr[3]}]\
+ [get_ports {reg_addr[4]}]\
+ [get_ports {reg_addr[5]}]\
+ [get_ports {reg_addr[6]}]\
+ [get_ports {reg_addr[7]}]\
+ [get_ports {reg_addr[8]}]]\
+ -to [list [get_ports {reg_ack}]\
+ [get_ports {reg_rdata[0]}]\
+ [get_ports {reg_rdata[10]}]\
+ [get_ports {reg_rdata[11]}]\
+ [get_ports {reg_rdata[12]}]\
+ [get_ports {reg_rdata[13]}]\
+ [get_ports {reg_rdata[14]}]\
+ [get_ports {reg_rdata[15]}]\
+ [get_ports {reg_rdata[16]}]\
+ [get_ports {reg_rdata[17]}]\
+ [get_ports {reg_rdata[18]}]\
+ [get_ports {reg_rdata[19]}]\
+ [get_ports {reg_rdata[1]}]\
+ [get_ports {reg_rdata[20]}]\
+ [get_ports {reg_rdata[21]}]\
+ [get_ports {reg_rdata[22]}]\
+ [get_ports {reg_rdata[23]}]\
+ [get_ports {reg_rdata[24]}]\
+ [get_ports {reg_rdata[25]}]\
+ [get_ports {reg_rdata[26]}]\
+ [get_ports {reg_rdata[27]}]\
+ [get_ports {reg_rdata[28]}]\
+ [get_ports {reg_rdata[29]}]\
+ [get_ports {reg_rdata[2]}]\
+ [get_ports {reg_rdata[30]}]\
+ [get_ports {reg_rdata[31]}]\
+ [get_ports {reg_rdata[3]}]\
+ [get_ports {reg_rdata[4]}]\
+ [get_ports {reg_rdata[5]}]\
+ [get_ports {reg_rdata[6]}]\
+ [get_ports {reg_rdata[7]}]\
+ [get_ports {reg_rdata[8]}]\
+ [get_ports {reg_rdata[9]}]] 1
+set_multicycle_path -setup\
+ -from [list [get_ports {reg_addr[0]}]\
+ [get_ports {reg_addr[1]}]\
+ [get_ports {reg_addr[2]}]\
+ [get_ports {reg_addr[3]}]\
+ [get_ports {reg_addr[4]}]\
+ [get_ports {reg_addr[5]}]\
+ [get_ports {reg_addr[6]}]\
+ [get_ports {reg_addr[7]}]\
+ [get_ports {reg_addr[8]}]]\
+ -to [list [get_ports {reg_ack}]\
+ [get_ports {reg_rdata[0]}]\
+ [get_ports {reg_rdata[10]}]\
+ [get_ports {reg_rdata[11]}]\
+ [get_ports {reg_rdata[12]}]\
+ [get_ports {reg_rdata[13]}]\
+ [get_ports {reg_rdata[14]}]\
+ [get_ports {reg_rdata[15]}]\
+ [get_ports {reg_rdata[16]}]\
+ [get_ports {reg_rdata[17]}]\
+ [get_ports {reg_rdata[18]}]\
+ [get_ports {reg_rdata[19]}]\
+ [get_ports {reg_rdata[1]}]\
+ [get_ports {reg_rdata[20]}]\
+ [get_ports {reg_rdata[21]}]\
+ [get_ports {reg_rdata[22]}]\
+ [get_ports {reg_rdata[23]}]\
+ [get_ports {reg_rdata[24]}]\
+ [get_ports {reg_rdata[25]}]\
+ [get_ports {reg_rdata[26]}]\
+ [get_ports {reg_rdata[27]}]\
+ [get_ports {reg_rdata[28]}]\
+ [get_ports {reg_rdata[29]}]\
+ [get_ports {reg_rdata[2]}]\
+ [get_ports {reg_rdata[30]}]\
+ [get_ports {reg_rdata[31]}]\
+ [get_ports {reg_rdata[3]}]\
+ [get_ports {reg_rdata[4]}]\
+ [get_ports {reg_rdata[5]}]\
+ [get_ports {reg_rdata[6]}]\
+ [get_ports {reg_rdata[7]}]\
+ [get_ports {reg_rdata[8]}]\
+ [get_ports {reg_rdata[9]}]] 2
+set_max_delay\
+ -from [get_ports {wbd_clk_int}] 5.0000
+set_max_delay\
+ -from [get_ports {wbd_clk_int}]\
+ -to [get_ports {wbd_clk_uart}] 5.0000
+set_max_delay\
+ -to [get_ports {wbd_clk_uart}] 5.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {i2cm_intr_o}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {scl_pad_o}]
+set_load -pin_load 0.0334 [get_ports {scl_pad_oen_o}]
+set_load -pin_load 0.0334 [get_ports {sda_pad_o}]
+set_load -pin_load 0.0334 [get_ports {sda_padoen_o}]
+set_load -pin_load 0.0334 [get_ports {sspim_sck}]
+set_load -pin_load 0.0334 [get_ports {sspim_so}]
+set_load -pin_load 0.0334 [get_ports {usb_intr_o}]
+set_load -pin_load 0.0334 [get_ports {usb_out_dn}]
+set_load -pin_load 0.0334 [get_ports {usb_out_dp}]
+set_load -pin_load 0.0334 [get_ports {usb_out_tx_oen}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_uart}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {sspim_ssn[3]}]
+set_load -pin_load 0.0334 [get_ports {sspim_ssn[2]}]
+set_load -pin_load 0.0334 [get_ports {sspim_ssn[1]}]
+set_load -pin_load 0.0334 [get_ports {sspim_ssn[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_txd[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_txd[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {app_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2c_rstn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scl_pad_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sda_pad_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_rstn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sspim_si}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_in_dn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_in_dp}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_rstn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rstn[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rstn[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rxd[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rxd[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
new file mode 100644
index 0000000..b2b6e86
--- /dev/null
+++ b/sdc/user_project_wrapper.sdc
@@ -0,0 +1,987 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 15:27:39 2022
+###############################################################################
+current_design user_project_wrapper
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name user_clock2 -period 100.0000 [get_ports {user_clock2}]
+set_propagated_clock [get_clocks {user_clock2}]
+create_clock -name wbm_clk_i -period 10.0000 [get_ports {wb_clk_i}]
+set_propagated_clock [get_clocks {wbm_clk_i}]
+create_clock -name wbs_clk_i -period 10.0000 [get_pins {u_wb_host/wbs_clk_out}]
+set_propagated_clock [get_clocks {wbs_clk_i}]
+create_clock -name cpu_clk -period 20.0000 [get_pins {u_wb_host/cpu_clk}]
+set_propagated_clock [get_clocks {cpu_clk}]
+create_clock -name rtc_clk -period 50.0000
+create_clock -name usb_clk -period 20.0000
+create_clock -name line_clk -period 100.0000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -setup 0.2000
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {cpu_clk}]\
+ -group [get_clocks {line_clk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {usb_clk}]\
+ -group [get_clocks {wbm_clk_i}]\
+ -group [get_clocks {wbs_clk_i}] -comment {Async Clock group}
+set_input_delay 2.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wb_rst_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[0]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[0]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[10]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[10]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[11]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[11]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[12]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[12]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[13]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[13]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[14]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[14]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[15]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[15]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[16]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[16]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[17]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[17]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[18]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[18]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[19]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[19]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[1]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[1]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[20]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[20]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[21]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[21]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[22]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[22]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[23]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[23]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[24]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[24]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[25]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[25]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[26]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[26]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[27]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[27]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[28]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[28]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[29]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[29]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[2]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[2]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[30]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[30]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[31]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[31]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[3]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[3]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[4]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[4]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[5]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[5]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[6]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[6]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[7]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[7]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[8]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[8]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[9]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[9]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_sel_i[0]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_sel_i[0]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_sel_i[1]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_sel_i[1]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_sel_i[2]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_sel_i[2]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_sel_i[3]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_sel_i[3]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_stb_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_stb_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_we_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_we_i}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_ack_o}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_ack_o}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[9]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {wbs_ack_o}]
+set_load -pin_load 0.0334 [get_ports {analog_io[28]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[27]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[26]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[25]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[24]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[23]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[22]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[21]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[20]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[19]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[18]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[17]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[16]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[15]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[14]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[13]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[12]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[11]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[10]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[9]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[8]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[7]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[6]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[5]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[4]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[3]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[2]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[1]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[0]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
+set_load -pin_load 0.0334 [get_ports {io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[127]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[126]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[125]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[124]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[123]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[122]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[121]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[120]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[119]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[118]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[117]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[116]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[115]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[114]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[113]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[112]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[111]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[110]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[109]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[108]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[107]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[106]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[105]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[104]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[103]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[102]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[101]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[100]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[99]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[98]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[97]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[96]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[95]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[94]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[93]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[92]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[91]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[90]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[89]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[88]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[87]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[86]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[85]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[84]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[83]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[82]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[81]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[80]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[79]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[78]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[77]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[76]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[75]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[74]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[73]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[72]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[71]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[70]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[69]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[68]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[67]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[66]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[65]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[64]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[63]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[62]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[61]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[60]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[59]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[58]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[57]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[56]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[55]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[54]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[53]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[52]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[51]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[50]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[49]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[48]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[47]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[46]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[45]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[44]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[43]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[42]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[41]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[40]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[39]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[38]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[37]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[36]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[35]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[34]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[33]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[32]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[31]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[30]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[29]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[28]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[27]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[26]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[25]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[24]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[23]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[22]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[21]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[20]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[19]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[18]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[17]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[16]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[15]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[14]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[13]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[12]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[11]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[10]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[9]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[8]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[7]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[6]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[5]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[4]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[3]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[2]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[1]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[0]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[123]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[122]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[121]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[120]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[119]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[118]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[117]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[116]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[115]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[114]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[113]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[112]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[111]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[110]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[109]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[108]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[107]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[106]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[105]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[104]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[103]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[102]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[101]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[100]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[99]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[98]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[97]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[96]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[95]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[94]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[93]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[92]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[91]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[90]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[89]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[88]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[87]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[86]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[85]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[84]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[83]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[82]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[81]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[80]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[79]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[78]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[77]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[76]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[75]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[74]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[73]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[72]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[71]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[70]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[69]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[68]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[67]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[66]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[65]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[64]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[63]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[62]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[61]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[60]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[59]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[58]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[57]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[56]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[55]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[54]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[53]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[52]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[51]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[50]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[49]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[124]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[123]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[122]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[121]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[120]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[119]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[118]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[117]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[116]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[115]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[114]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[113]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[112]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[111]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[110]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[109]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[108]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[107]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[106]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[105]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[104]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[103]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[102]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[101]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[100]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[99]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[98]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[97]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[96]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[95]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[94]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[93]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[92]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[91]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[90]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[89]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[88]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[87]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[86]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[85]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[84]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[83]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[82]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[81]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[80]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[79]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[78]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[77]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[76]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[75]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[74]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[73]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[72]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[71]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[70]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[69]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[68]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[67]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[66]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[65]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[64]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[63]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[62]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[61]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[60]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[59]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[58]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[57]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[56]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[55]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[54]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[53]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[52]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[51]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[50]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[49]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[0]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[1]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[2]}]
+set_case_analysis 1 [get_pins {u_intercon/cfg_cska_wi[3]}]
+set_case_analysis 0 [get_pins {u_pinmux/cfg_cska_pinmux[0]}]
+set_case_analysis 1 [get_pins {u_pinmux/cfg_cska_pinmux[1]}]
+set_case_analysis 1 [get_pins {u_pinmux/cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_pins {u_pinmux/cfg_cska_pinmux[3]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[0]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[3]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_spi[0]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_spi[1]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_spi[2]}]
+set_case_analysis 1 [get_pins {u_qspi_master/cfg_cska_spi[3]}]
+set_case_analysis 0 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[0]}]
+set_case_analysis 0 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[1]}]
+set_case_analysis 0 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[2]}]
+set_case_analysis 1 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[0]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[1]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 1 [get_pins {u_wb_host/cfg_cska_wh[3]}]
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/sdc/wb_host.sdc b/sdc/wb_host.sdc
new file mode 100644
index 0000000..8a35241
--- /dev/null
+++ b/sdc/wb_host.sdc
@@ -0,0 +1,873 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 14:48:44 2022
+###############################################################################
+current_design wb_host
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wbm_clk_i -period 10.0000 [get_ports {wbm_clk_i}]
+set_clock_transition 0.1500 [get_clocks {wbm_clk_i}]
+set_clock_uncertainty -setup 0.5000 wbm_clk_i
+set_clock_uncertainty -hold 0.2500 wbm_clk_i
+set_propagated_clock [get_clocks {wbm_clk_i}]
+create_clock -name wbs_clk_i -period 10.0000 [get_ports {wbs_clk_i}]
+set_clock_transition 0.1500 [get_clocks {wbs_clk_i}]
+set_clock_uncertainty -setup 0.5000 wbs_clk_i
+set_clock_uncertainty -hold 0.2500 wbs_clk_i
+set_propagated_clock [get_clocks {wbs_clk_i}]
+create_clock -name uart_clk -period 100.0000 [get_pins {u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
+set_clock_transition 0.1500 [get_clocks {uart_clk}]
+set_clock_uncertainty -setup 0.5000 uart_clk
+set_clock_uncertainty -hold 0.2500 uart_clk
+set_propagated_clock [get_clocks {uart_clk}]
+create_clock -name int_pll_clock -period 10.0000
+set_clock_uncertainty -setup 0.5000 int_pll_clock
+set_clock_uncertainty -hold 0.2500 int_pll_clock
+create_clock -name wbs_ref_clk -period 10.0000
+set_clock_uncertainty -setup 0.5000 wbs_ref_clk
+set_clock_uncertainty -hold 0.2500 wbs_ref_clk
+create_clock -name cpu_ref_clk -period 10.0000
+set_clock_uncertainty -setup 0.5000 cpu_ref_clk
+set_clock_uncertainty -hold 0.2500 cpu_ref_clk
+create_clock -name usb_ref_clk -period 10.0000
+set_clock_uncertainty -setup 0.5000 usb_ref_clk
+set_clock_uncertainty -hold 0.2500 usb_ref_clk
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {cpu_ref_clk}]\
+ -group [get_clocks {int_pll_clock}]\
+ -group [get_clocks {uart_clk}]\
+ -group [get_clocks {usb_ref_clk}]\
+ -group [get_clocks {wbm_clk_i}]\
+ -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {wbs_ref_clk}] -comment {Async Clock group}
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_rst_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_rst_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_stb_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_stb_i}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_ack_i}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[9]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_ack_o}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_ack_o}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[0]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[0]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[10]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[10]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[11]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[11]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[12]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[12]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[13]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[13]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[14]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[14]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[15]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[15]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[16]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[16]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[17]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[17]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[18]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[18]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[19]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[19]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[1]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[1]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[20]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[20]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[21]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[21]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[22]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[22]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[23]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[23]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[24]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[24]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[25]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[25]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[26]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[26]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[27]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[27]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[28]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[28]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[29]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[29]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[2]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[2]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[30]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[30]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[31]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[31]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[3]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[3]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[4]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[4]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[5]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[5]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[6]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[6]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[7]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[7]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[8]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[8]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[9]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[9]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_err_o}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_err_o}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[0]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[0]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[10]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[10]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[11]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[11]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[12]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[12]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[13]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[13]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[14]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[14]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[15]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[15]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[16]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[16]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[17]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[17]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[18]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[18]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[19]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[19]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[1]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[1]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[20]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[20]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[21]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[21]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[22]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[22]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[23]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[23]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[24]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[24]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[25]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[25]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[26]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[26]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[27]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[27]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[28]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[28]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[29]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[29]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[2]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[2]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[30]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[30]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[31]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[31]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[3]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[3]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[4]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[4]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[5]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[5]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[6]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[6]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[7]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[7]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[8]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[8]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[9]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[9]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[9]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[9]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_sel_o[0]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_sel_o[0]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_sel_o[1]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_sel_o[1]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_sel_o[2]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_sel_o[2]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_sel_o[3]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_sel_o[3]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_stb_o}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_stb_o}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_we_o}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_we_o}]
+set_multicycle_path -hold\
+ -from [list [get_ports {wbm_adr_i[0]}]\
+ [get_ports {wbm_adr_i[10]}]\
+ [get_ports {wbm_adr_i[11]}]\
+ [get_ports {wbm_adr_i[12]}]\
+ [get_ports {wbm_adr_i[13]}]\
+ [get_ports {wbm_adr_i[14]}]\
+ [get_ports {wbm_adr_i[15]}]\
+ [get_ports {wbm_adr_i[16]}]\
+ [get_ports {wbm_adr_i[17]}]\
+ [get_ports {wbm_adr_i[18]}]\
+ [get_ports {wbm_adr_i[19]}]\
+ [get_ports {wbm_adr_i[1]}]\
+ [get_ports {wbm_adr_i[20]}]\
+ [get_ports {wbm_adr_i[21]}]\
+ [get_ports {wbm_adr_i[22]}]\
+ [get_ports {wbm_adr_i[23]}]\
+ [get_ports {wbm_adr_i[24]}]\
+ [get_ports {wbm_adr_i[25]}]\
+ [get_ports {wbm_adr_i[26]}]\
+ [get_ports {wbm_adr_i[27]}]\
+ [get_ports {wbm_adr_i[28]}]\
+ [get_ports {wbm_adr_i[29]}]\
+ [get_ports {wbm_adr_i[2]}]\
+ [get_ports {wbm_adr_i[30]}]\
+ [get_ports {wbm_adr_i[31]}]\
+ [get_ports {wbm_adr_i[3]}]\
+ [get_ports {wbm_adr_i[4]}]\
+ [get_ports {wbm_adr_i[5]}]\
+ [get_ports {wbm_adr_i[6]}]\
+ [get_ports {wbm_adr_i[7]}]\
+ [get_ports {wbm_adr_i[8]}]\
+ [get_ports {wbm_adr_i[9]}]\
+ [get_ports {wbm_cyc_i}]\
+ [get_ports {wbm_dat_i[0]}]\
+ [get_ports {wbm_dat_i[10]}]\
+ [get_ports {wbm_dat_i[11]}]\
+ [get_ports {wbm_dat_i[12]}]\
+ [get_ports {wbm_dat_i[13]}]\
+ [get_ports {wbm_dat_i[14]}]\
+ [get_ports {wbm_dat_i[15]}]\
+ [get_ports {wbm_dat_i[16]}]\
+ [get_ports {wbm_dat_i[17]}]\
+ [get_ports {wbm_dat_i[18]}]\
+ [get_ports {wbm_dat_i[19]}]\
+ [get_ports {wbm_dat_i[1]}]\
+ [get_ports {wbm_dat_i[20]}]\
+ [get_ports {wbm_dat_i[21]}]\
+ [get_ports {wbm_dat_i[22]}]\
+ [get_ports {wbm_dat_i[23]}]\
+ [get_ports {wbm_dat_i[24]}]\
+ [get_ports {wbm_dat_i[25]}]\
+ [get_ports {wbm_dat_i[26]}]\
+ [get_ports {wbm_dat_i[27]}]\
+ [get_ports {wbm_dat_i[28]}]\
+ [get_ports {wbm_dat_i[29]}]\
+ [get_ports {wbm_dat_i[2]}]\
+ [get_ports {wbm_dat_i[30]}]\
+ [get_ports {wbm_dat_i[31]}]\
+ [get_ports {wbm_dat_i[3]}]\
+ [get_ports {wbm_dat_i[4]}]\
+ [get_ports {wbm_dat_i[5]}]\
+ [get_ports {wbm_dat_i[6]}]\
+ [get_ports {wbm_dat_i[7]}]\
+ [get_ports {wbm_dat_i[8]}]\
+ [get_ports {wbm_dat_i[9]}]\
+ [get_ports {wbm_sel_i[0]}]\
+ [get_ports {wbm_sel_i[1]}]\
+ [get_ports {wbm_sel_i[2]}]\
+ [get_ports {wbm_sel_i[3]}]\
+ [get_ports {wbm_we_i}]] 2
+set_multicycle_path -setup\
+ -from [list [get_ports {wbm_adr_i[0]}]\
+ [get_ports {wbm_adr_i[10]}]\
+ [get_ports {wbm_adr_i[11]}]\
+ [get_ports {wbm_adr_i[12]}]\
+ [get_ports {wbm_adr_i[13]}]\
+ [get_ports {wbm_adr_i[14]}]\
+ [get_ports {wbm_adr_i[15]}]\
+ [get_ports {wbm_adr_i[16]}]\
+ [get_ports {wbm_adr_i[17]}]\
+ [get_ports {wbm_adr_i[18]}]\
+ [get_ports {wbm_adr_i[19]}]\
+ [get_ports {wbm_adr_i[1]}]\
+ [get_ports {wbm_adr_i[20]}]\
+ [get_ports {wbm_adr_i[21]}]\
+ [get_ports {wbm_adr_i[22]}]\
+ [get_ports {wbm_adr_i[23]}]\
+ [get_ports {wbm_adr_i[24]}]\
+ [get_ports {wbm_adr_i[25]}]\
+ [get_ports {wbm_adr_i[26]}]\
+ [get_ports {wbm_adr_i[27]}]\
+ [get_ports {wbm_adr_i[28]}]\
+ [get_ports {wbm_adr_i[29]}]\
+ [get_ports {wbm_adr_i[2]}]\
+ [get_ports {wbm_adr_i[30]}]\
+ [get_ports {wbm_adr_i[31]}]\
+ [get_ports {wbm_adr_i[3]}]\
+ [get_ports {wbm_adr_i[4]}]\
+ [get_ports {wbm_adr_i[5]}]\
+ [get_ports {wbm_adr_i[6]}]\
+ [get_ports {wbm_adr_i[7]}]\
+ [get_ports {wbm_adr_i[8]}]\
+ [get_ports {wbm_adr_i[9]}]\
+ [get_ports {wbm_cyc_i}]\
+ [get_ports {wbm_dat_i[0]}]\
+ [get_ports {wbm_dat_i[10]}]\
+ [get_ports {wbm_dat_i[11]}]\
+ [get_ports {wbm_dat_i[12]}]\
+ [get_ports {wbm_dat_i[13]}]\
+ [get_ports {wbm_dat_i[14]}]\
+ [get_ports {wbm_dat_i[15]}]\
+ [get_ports {wbm_dat_i[16]}]\
+ [get_ports {wbm_dat_i[17]}]\
+ [get_ports {wbm_dat_i[18]}]\
+ [get_ports {wbm_dat_i[19]}]\
+ [get_ports {wbm_dat_i[1]}]\
+ [get_ports {wbm_dat_i[20]}]\
+ [get_ports {wbm_dat_i[21]}]\
+ [get_ports {wbm_dat_i[22]}]\
+ [get_ports {wbm_dat_i[23]}]\
+ [get_ports {wbm_dat_i[24]}]\
+ [get_ports {wbm_dat_i[25]}]\
+ [get_ports {wbm_dat_i[26]}]\
+ [get_ports {wbm_dat_i[27]}]\
+ [get_ports {wbm_dat_i[28]}]\
+ [get_ports {wbm_dat_i[29]}]\
+ [get_ports {wbm_dat_i[2]}]\
+ [get_ports {wbm_dat_i[30]}]\
+ [get_ports {wbm_dat_i[31]}]\
+ [get_ports {wbm_dat_i[3]}]\
+ [get_ports {wbm_dat_i[4]}]\
+ [get_ports {wbm_dat_i[5]}]\
+ [get_ports {wbm_dat_i[6]}]\
+ [get_ports {wbm_dat_i[7]}]\
+ [get_ports {wbm_dat_i[8]}]\
+ [get_ports {wbm_dat_i[9]}]\
+ [get_ports {wbm_sel_i[0]}]\
+ [get_ports {wbm_sel_i[1]}]\
+ [get_ports {wbm_sel_i[2]}]\
+ [get_ports {wbm_sel_i[3]}]\
+ [get_ports {wbm_we_i}]] 2
+set_max_delay\
+ -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+ -from [get_ports {wbd_clk_int}]\
+ -to [get_ports {wbd_clk_wh}] 3.5000
+set_max_delay\
+ -to [get_ports {wbd_clk_wh}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {cfg_strap_pad_ctrl}]
+set_load -pin_load 0.0334 [get_ports {cpu_clk}]
+set_load -pin_load 0.0334 [get_ports {e_reset_n}]
+set_load -pin_load 0.0334 [get_ports {p_reset_n}]
+set_load -pin_load 0.0334 [get_ports {s_reset_n}]
+set_load -pin_load 0.0334 [get_ports {sdout}]
+set_load -pin_load 0.0334 [get_ports {sdout_oen}]
+set_load -pin_load 0.0334 [get_ports {uartm_txd}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_wh}]
+set_load -pin_load 0.0334 [get_ports {wbd_int_rst_n}]
+set_load -pin_load 0.0334 [get_ports {wbd_pll_rst_n}]
+set_load -pin_load 0.0334 [get_ports {wbm_ack_o}]
+set_load -pin_load 0.0334 [get_ports {wbm_err_o}]
+set_load -pin_load 0.0334 [get_ports {wbs_clk_out}]
+set_load -pin_load 0.0334 [get_ports {wbs_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {wbs_stb_o}]
+set_load -pin_load 0.0334 [get_ports {wbs_we_o}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[31]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[30]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[29]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[28]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[27]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[26]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[25]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[24]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[23]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[22]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[21]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[20]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[19]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[18]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[17]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[16]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[31]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[30]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[29]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[28]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[27]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[26]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[25]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[24]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[23]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[22]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[21]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[20]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[19]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[18]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[17]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[16]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[0]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[31]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[30]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[29]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[28]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[27]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[26]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[25]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[24]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[23]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[22]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[21]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[20]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[19]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[18]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[17]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[16]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[15]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[14]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[13]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[12]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[11]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[10]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[9]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[8]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[7]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[6]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[5]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[4]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[3]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[2]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[1]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[0]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_sel_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {int_pll_clock}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sdin}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ssn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uartm_rxd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock1}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_rst_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_err_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {xtal_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_uartm[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_uartm[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.
