| #BUS_SORT |
| #MANUAL_PLACE |
| #E |
| pwrup_rst_n 0000 00 2 |
| rst_n |
| core_rst_n_o |
| core_rdc_qlfy_o |
| |
| cfg_ccska\[3\] 0180 00 2 |
| cfg_ccska\[2\] |
| cfg_ccska\[1\] |
| cfg_ccska\[0\] |
| core_clk_skew |
| clk |
| clk_o |
| |
| core_clk_int 0200 00 2 |
| core_uid\[1\] |
| core_uid\[0\] |
| imem2core_req_ack_i |
| core2imem_req_o |
| core2imem_cmd_o |
| core2imem_addr_o\[31\] |
| core2imem_addr_o\[30\] |
| core2imem_addr_o\[29\] |
| core2imem_addr_o\[28\] |
| core2imem_addr_o\[27\] |
| core2imem_addr_o\[26\] |
| core2imem_addr_o\[25\] |
| core2imem_addr_o\[24\] |
| core2imem_addr_o\[23\] |
| core2imem_addr_o\[22\] |
| core2imem_addr_o\[21\] |
| core2imem_addr_o\[20\] |
| core2imem_addr_o\[19\] |
| core2imem_addr_o\[18\] |
| core2imem_addr_o\[17\] |
| core2imem_addr_o\[16\] |
| core2imem_addr_o\[15\] |
| core2imem_addr_o\[14\] |
| core2imem_addr_o\[13\] |
| core2imem_addr_o\[12\] |
| core2imem_addr_o\[11\] |
| core2imem_addr_o\[10\] |
| core2imem_addr_o\[9\] |
| core2imem_addr_o\[8\] |
| core2imem_addr_o\[7\] |
| core2imem_addr_o\[6\] |
| core2imem_addr_o\[5\] |
| core2imem_addr_o\[4\] |
| core2imem_addr_o\[3\] |
| core2imem_addr_o\[2\] |
| core2imem_addr_o\[1\] |
| core2imem_addr_o\[0\] |
| core2imem_bl_o\[2\] |
| core2imem_bl_o\[1\] |
| core2imem_bl_o\[0\] |
| imem2core_rdata_i\[31\] |
| imem2core_rdata_i\[30\] |
| imem2core_rdata_i\[29\] |
| imem2core_rdata_i\[28\] |
| imem2core_rdata_i\[27\] |
| imem2core_rdata_i\[26\] |
| imem2core_rdata_i\[25\] |
| imem2core_rdata_i\[24\] |
| imem2core_rdata_i\[23\] |
| imem2core_rdata_i\[22\] |
| imem2core_rdata_i\[21\] |
| imem2core_rdata_i\[20\] |
| imem2core_rdata_i\[19\] |
| imem2core_rdata_i\[18\] |
| imem2core_rdata_i\[17\] |
| imem2core_rdata_i\[16\] |
| imem2core_rdata_i\[15\] |
| imem2core_rdata_i\[14\] |
| imem2core_rdata_i\[13\] |
| imem2core_rdata_i\[12\] |
| imem2core_rdata_i\[11\] |
| imem2core_rdata_i\[10\] |
| imem2core_rdata_i\[9\] |
| imem2core_rdata_i\[8\] |
| imem2core_rdata_i\[7\] |
| imem2core_rdata_i\[6\] |
| imem2core_rdata_i\[5\] |
| imem2core_rdata_i\[4\] |
| imem2core_rdata_i\[3\] |
| imem2core_rdata_i\[2\] |
| imem2core_rdata_i\[1\] |
| imem2core_rdata_i\[0\] |
| imem2core_resp_i\[1\] |
| imem2core_resp_i\[0\] |
| |
| dmem2core_req_ack_i 0350 0 2 |
| core2dmem_req_o |
| core2dmem_cmd_o |
| core2dmem_width_o\[1\] |
| core2dmem_width_o\[0\] |
| core2dmem_addr_o\[31\] |
| core2dmem_addr_o\[30\] |
| core2dmem_addr_o\[29\] |
| core2dmem_addr_o\[28\] |
| core2dmem_addr_o\[27\] |
| core2dmem_addr_o\[26\] |
| core2dmem_addr_o\[25\] |
| core2dmem_addr_o\[24\] |
| core2dmem_addr_o\[23\] |
| core2dmem_addr_o\[22\] |
| core2dmem_addr_o\[21\] |
| core2dmem_addr_o\[20\] |
| core2dmem_addr_o\[19\] |
| core2dmem_addr_o\[18\] |
| core2dmem_addr_o\[17\] |
| core2dmem_addr_o\[16\] |
| core2dmem_addr_o\[15\] |
| core2dmem_addr_o\[14\] |
| core2dmem_addr_o\[13\] |
| core2dmem_addr_o\[12\] |
| core2dmem_addr_o\[11\] |
| core2dmem_addr_o\[10\] |
| core2dmem_addr_o\[9\] |
| core2dmem_addr_o\[8\] |
| core2dmem_addr_o\[7\] |
| core2dmem_addr_o\[6\] |
| core2dmem_addr_o\[5\] |
| core2dmem_addr_o\[4\] |
| core2dmem_addr_o\[3\] |
| core2dmem_addr_o\[2\] |
| core2dmem_addr_o\[1\] |
| core2dmem_addr_o\[0\] |
| core2dmem_wdata_o\[31\] |
| core2dmem_wdata_o\[30\] |
| core2dmem_wdata_o\[29\] |
| core2dmem_wdata_o\[28\] |
| core2dmem_wdata_o\[27\] |
| core2dmem_wdata_o\[26\] |
| core2dmem_wdata_o\[25\] |
| core2dmem_wdata_o\[24\] |
| core2dmem_wdata_o\[23\] |
| core2dmem_wdata_o\[22\] |
| core2dmem_wdata_o\[21\] |
| core2dmem_wdata_o\[20\] |
| core2dmem_wdata_o\[19\] |
| core2dmem_wdata_o\[18\] |
| core2dmem_wdata_o\[17\] |
| core2dmem_wdata_o\[16\] |
| core2dmem_wdata_o\[15\] |
| core2dmem_wdata_o\[14\] |
| core2dmem_wdata_o\[13\] |
| core2dmem_wdata_o\[12\] |
| core2dmem_wdata_o\[11\] |
| core2dmem_wdata_o\[10\] |
| core2dmem_wdata_o\[9\] |
| core2dmem_wdata_o\[8\] |
| core2dmem_wdata_o\[7\] |
| core2dmem_wdata_o\[6\] |
| core2dmem_wdata_o\[5\] |
| core2dmem_wdata_o\[4\] |
| core2dmem_wdata_o\[3\] |
| core2dmem_wdata_o\[2\] |
| core2dmem_wdata_o\[1\] |
| core2dmem_wdata_o\[0\] |
| dmem2core_rdata_i\[31\] |
| dmem2core_rdata_i\[30\] |
| dmem2core_rdata_i\[29\] |
| dmem2core_rdata_i\[28\] |
| dmem2core_rdata_i\[27\] |
| dmem2core_rdata_i\[26\] |
| dmem2core_rdata_i\[25\] |
| dmem2core_rdata_i\[24\] |
| dmem2core_rdata_i\[23\] |
| dmem2core_rdata_i\[22\] |
| dmem2core_rdata_i\[21\] |
| dmem2core_rdata_i\[20\] |
| dmem2core_rdata_i\[19\] |
| dmem2core_rdata_i\[18\] |
| dmem2core_rdata_i\[17\] |
| dmem2core_rdata_i\[16\] |
| dmem2core_rdata_i\[15\] |
| dmem2core_rdata_i\[14\] |
| dmem2core_rdata_i\[13\] |
| dmem2core_rdata_i\[12\] |
| dmem2core_rdata_i\[11\] |
| dmem2core_rdata_i\[10\] |
| dmem2core_rdata_i\[9\] |
| dmem2core_rdata_i\[8\] |
| dmem2core_rdata_i\[7\] |
| dmem2core_rdata_i\[6\] |
| dmem2core_rdata_i\[5\] |
| dmem2core_rdata_i\[4\] |
| dmem2core_rdata_i\[3\] |
| dmem2core_rdata_i\[2\] |
| dmem2core_rdata_i\[1\] |
| dmem2core_rdata_i\[0\] |
| dmem2core_resp_i\[1\] |
| dmem2core_resp_i\[0\] |
| |
| core_debug\[48\] 0500 0 2 |
| core_debug\[47\] |
| core_debug\[46\] |
| core_debug\[45\] |
| core_debug\[44\] |
| core_debug\[43\] |
| core_debug\[42\] |
| core_debug\[41\] |
| core_debug\[40\] |
| core_debug\[39\] |
| core_debug\[38\] |
| core_debug\[37\] |
| core_debug\[36\] |
| core_debug\[35\] |
| core_debug\[34\] |
| core_debug\[33\] |
| core_debug\[32\] |
| core_debug\[31\] |
| core_debug\[30\] |
| core_debug\[29\] |
| core_debug\[28\] |
| core_debug\[27\] |
| core_debug\[26\] |
| core_debug\[25\] |
| core_debug\[24\] |
| core_debug\[23\] |
| core_debug\[22\] |
| core_debug\[21\] |
| core_debug\[20\] |
| core_debug\[19\] |
| core_debug\[18\] |
| core_debug\[17\] |
| core_debug\[16\] |
| core_debug\[15\] |
| core_debug\[14\] |
| core_debug\[13\] |
| core_debug\[12\] |
| core_debug\[11\] |
| core_debug\[10\] |
| core_debug\[9\] |
| core_debug\[8\] |
| core_debug\[7\] |
| core_debug\[6\] |
| core_debug\[5\] |
| core_debug\[4\] |
| core_debug\[3\] |
| core_debug\[2\] |
| core_debug\[1\] |
| core_debug\[0\] |
| |
| core_irq_mtimer_i 0600 0 2 |
| core_mtimer_val_i\[63\] |
| core_mtimer_val_i\[62\] |
| core_mtimer_val_i\[61\] |
| core_mtimer_val_i\[60\] |
| core_mtimer_val_i\[59\] |
| core_mtimer_val_i\[58\] |
| core_mtimer_val_i\[57\] |
| core_mtimer_val_i\[56\] |
| core_mtimer_val_i\[55\] |
| core_mtimer_val_i\[54\] |
| core_mtimer_val_i\[53\] |
| core_mtimer_val_i\[52\] |
| core_mtimer_val_i\[51\] |
| core_mtimer_val_i\[50\] |
| core_mtimer_val_i\[49\] |
| core_mtimer_val_i\[48\] |
| core_mtimer_val_i\[47\] |
| core_mtimer_val_i\[46\] |
| core_mtimer_val_i\[45\] |
| core_mtimer_val_i\[44\] |
| core_mtimer_val_i\[43\] |
| core_mtimer_val_i\[42\] |
| core_mtimer_val_i\[41\] |
| core_mtimer_val_i\[40\] |
| core_mtimer_val_i\[39\] |
| core_mtimer_val_i\[38\] |
| core_mtimer_val_i\[37\] |
| core_mtimer_val_i\[36\] |
| core_mtimer_val_i\[35\] |
| core_mtimer_val_i\[34\] |
| core_mtimer_val_i\[33\] |
| core_mtimer_val_i\[32\] |
| core_mtimer_val_i\[31\] |
| core_mtimer_val_i\[30\] |
| core_mtimer_val_i\[29\] |
| core_mtimer_val_i\[28\] |
| core_mtimer_val_i\[27\] |
| core_mtimer_val_i\[26\] |
| core_mtimer_val_i\[25\] |
| core_mtimer_val_i\[24\] |
| core_mtimer_val_i\[23\] |
| core_mtimer_val_i\[22\] |
| core_mtimer_val_i\[21\] |
| core_mtimer_val_i\[20\] |
| core_mtimer_val_i\[19\] |
| core_mtimer_val_i\[18\] |
| core_mtimer_val_i\[17\] |
| core_mtimer_val_i\[16\] |
| core_mtimer_val_i\[15\] |
| core_mtimer_val_i\[14\] |
| core_mtimer_val_i\[13\] |
| core_mtimer_val_i\[12\] |
| core_mtimer_val_i\[11\] |
| core_mtimer_val_i\[10\] |
| core_mtimer_val_i\[9\] |
| core_mtimer_val_i\[8\] |
| core_mtimer_val_i\[7\] |
| core_mtimer_val_i\[6\] |
| core_mtimer_val_i\[5\] |
| core_mtimer_val_i\[4\] |
| core_mtimer_val_i\[3\] |
| core_mtimer_val_i\[2\] |
| core_mtimer_val_i\[1\] |
| core_mtimer_val_i\[0\] |
| |
| core_irq_lines_i\[31\] |
| core_irq_lines_i\[30\] |
| core_irq_lines_i\[29\] |
| core_irq_lines_i\[28\] |
| core_irq_lines_i\[27\] |
| core_irq_lines_i\[26\] |
| core_irq_lines_i\[25\] |
| core_irq_lines_i\[24\] |
| core_irq_lines_i\[23\] |
| core_irq_lines_i\[22\] |
| core_irq_lines_i\[21\] |
| core_irq_lines_i\[20\] |
| core_irq_lines_i\[19\] |
| core_irq_lines_i\[18\] |
| core_irq_lines_i\[17\] |
| core_irq_lines_i\[16\] |
| core_irq_lines_i\[15\] |
| core_irq_lines_i\[14\] |
| core_irq_lines_i\[13\] |
| core_irq_lines_i\[12\] |
| core_irq_lines_i\[11\] |
| core_irq_lines_i\[10\] |
| core_irq_lines_i\[9\] |
| core_irq_lines_i\[8\] |
| core_irq_lines_i\[7\] |
| core_irq_lines_i\[6\] |
| core_irq_lines_i\[5\] |
| core_irq_lines_i\[4\] |
| core_irq_lines_i\[3\] |
| core_irq_lines_i\[2\] |
| core_irq_lines_i\[1\] |
| core_irq_lines_i\[0\] |
| core_irq_soft_i |
| cpu_rst_n |
| |