diff --git a/.gitmodules b/.gitmodules
index 5426bcd..df1d438 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -13,3 +13,6 @@
 [submodule "verilog/rtl/fpu"]
 	path = verilog/rtl/fpu
 	url = https://github.com/dineshannayya/fpu
+[submodule "verilog/rtl/rtc"]
+	path = verilog/rtl/rtc
+	url = https://github.com/dineshannayya/rtc
diff --git a/Makefile b/Makefile
index dc5ba38..38de28b 100644
--- a/Makefile
+++ b/Makefile
@@ -110,7 +110,7 @@
 # Install DV setup
 .PHONY: simenv
 simenv:
-	docker pull riscduino/dv_setup:mpw6
+	docker pull riscduino/dv_setup:mpw7
 
 .PHONY: setup
 setup: install check-env install_mcw openlane pdk-with-volare setup-timing-scripts
@@ -132,7 +132,7 @@
 		-e TOOLS=/opt/riscv32i \
 		-e DESIGNS=$(TARGET_PATH) \
 		-e GCC_PREFIX=riscv32-unknown-elf \
-		-u $$(id -u $$USER):$$(id -g $$USER) riscduino/dv_setup:mpw6 \
+		-u $$(id -u $$USER):$$(id -g $$USER) riscduino/dv_setup:mpw7 \
 		sh -c $(verify_command)
 
 
@@ -327,3 +327,11 @@
 	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast
 	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow
 	@echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
+
+#Added by Dinesh-A for Klayout Based DRC check
+.PHONY: run-drc
+run-drc: 
+	@echo "run kalyout DRC checks"
+	mkdir -p signoff/user_project_wrapper/openlane-signoff/drc
+	docker run -ti --rm  -v $(PROJECT_ROOT):/project riscduino/openlane:mpw7  sh -c "cd /project && ./scripts/drc/run.sh user_project_wrapper "
+
diff --git a/README.md b/README.md
index 05a57bf..9b7552f 100644
--- a/README.md
+++ b/README.md
@@ -74,6 +74,9 @@
     * 3 x Timer (16 Bit), 1us/1ms/1second resolution
     * 2 x ws281x driver
     * 16 Hardware Semaphore
+    * FPU (SP) Core
+    * AES 128 Bit Core
+    * RTC Core
     * Pin Compatbible to arduino uno
     * Wishbone compatible design
     * Written in System Verilog
@@ -410,16 +413,16 @@
     - flow automatically pull the required docker based on MPW version.
     - RTL to gds docker is hardcoded inside File: openlane/Makefile
 ```bash
-     OPENLANE_TAG = mpw6
+     OPENLANE_TAG = mpw7
      OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)
 ```
 ## Note-1.1: View the RTL to GDS Docker content
-    - for MPW-6 caravel pdk and openlane avaible inside riscduino/openlane:mpw6 docker 
+    - for MPW-7 caravel pdk and openlane avaible inside riscduino/openlane:mpw7 docker 
     - caravel, openlane and pdk envionment are automatically pointed to internal docker pointer
     - To view the docker contents
 ```bash
-    docker run -ti --rm riscduino/openlane:mpw6  bash
-    cd /opt/pdk_mpw6     -  pdk folder
+    docker run -ti --rm riscduino/openlane:mpw7  bash
+    cd /opt/pdk_mpw7     -  pdk folder
     cd /opt/caravel      -  caravel folder 
     cd /openlane         -  openlane folder
     env   - Show the internally defined env's
@@ -436,12 +439,12 @@
 	    docker pull riscduino/dv_setup:mpw6
 
 ## Note-2.1: View the RTL Simulation Docker content
-    - for MPW-6 caravel and pdk avaible inside riscduino/dv_setup:mpw6 docker this is used for RTL to gds flows
+    - for MPW-7 caravel and pdk avaible inside riscduino/dv_setup:mpw7 docker this is used for RTL to gds flows
     - caravel and pdk envionment are automatically pointed to internal docker pointer
     - To view the docker contents
 ```bash
-    docker run -ti --rm riscduino/dv_setup:mpw6  bash
-    cd /opt/pdk_mpw6     -  pdk folder
+    docker run -ti --rm riscduino/dv_setup:mpw7  bash
+    cd /opt/pdk_mpw7     -  pdk folder
     cd /opt/caravel      -  caravel folder 
     env   - Show the internally defined env's
         CARAVEL_ROOT=/opt/caravel
@@ -471,7 +474,10 @@
 * **15.user_cache_bypass**  - Riscv Boot without icache and dcache
 * **16.user_pwm**            -Standalone pwm Test
 * **17.user_sema**           -Standalone validation of hardware Semaphore function
-* **18.riscv_regress**       - Standalone riscv compliance and regression test suite
+* **18.riscv_regress**       -Standalone riscv compliance and regression test suite
+* **19.user_rtc**            -Standalone RTC core test
+* **20.user_aes_core**       -Standalone AES Core test
+* **21.user_fpu_core**       -Standalone FPU(SP) Core test
 
 ## Caravel+RISCDUINO Integrated Specific Test case 
 * **1.wb_port**             - Complete caravel User Wishbone validation
@@ -662,7 +668,7 @@
 We are looking for community help in following activity, interested user can ping me in efabless slack platform
 
 *  **Analog Design**           - ADC, DAC, PLL,
-*  **Digital Design**          - New IP Integration, Encription,DSP, Floating point functions
+*  **Digital Design**          - New IP Integration, Encription,DSP, DMA controller, 10Mb MAC, Floating point functions
 *  **Verification**            - Improving the Verification flow
 *  **Linux Porting**           - Build Root integration
 *  **Arudino Software Update** - Tool Customisation for Riscduino, Adding additional plug-in and Riscv compilation support
diff --git a/docs/source/_static/Riscduino_Soc.png b/docs/source/_static/Riscduino_Soc.png
index 135f686..5dae5ff 100644
--- a/docs/source/_static/Riscduino_Soc.png
+++ b/docs/source/_static/Riscduino_Soc.png
Binary files differ
diff --git a/env/spef-mapping.tcl b/env/spef-mapping.tcl
index 02a1561..adf75f3 100644
--- a/env/spef-mapping.tcl
+++ b/env/spef-mapping.tcl
@@ -2,6 +2,7 @@
 set spef_mapping(mprj/u_aes) "$::env(PROJECT_ROOT)/signoff/aes_top/openlane-signoff/spef/aes_top.$::env(RCX_CORNER).spef"
 set spef_mapping(mprj/u_fpu) "$::env(PROJECT_ROOT)/signoff/fpu_wrapper/openlane-signoff/spef/fpu_wrapper.$::env(RCX_CORNER).spef"
 set spef_mapping(mprj/u_intercon) "$::env(PROJECT_ROOT)/signoff/wb_interconnect/openlane-signoff/spef/wb_interconnect.$::env(RCX_CORNER).spef"
+set spef_mapping(mprj/u_peri) "$::env(PROJECT_ROOT)/signoff/peri_top/openlane-signoff/spef/peri_top.$::env(RCX_CORNER).spef"
 set spef_mapping(mprj/u_pinmux) "$::env(PROJECT_ROOT)/signoff/pinmux_top/openlane-signoff/spef/pinmux_top.$::env(RCX_CORNER).spef"
 set spef_mapping(mprj/u_pll) "$::env(PROJECT_ROOT)/signoff/dg_pll/openlane-signoff/spef/dg_pll.$::env(RCX_CORNER).spef"
 set spef_mapping(mprj/u_qspi_master) "$::env(PROJECT_ROOT)/signoff/qspim_top/openlane-signoff/spef/qspim_top.$::env(RCX_CORNER).spef"
diff --git a/openlane/bus_rep_north/config.tcl b/openlane/bus_rep_north/config.tcl
index 4168921..e66bac5 100755
--- a/openlane/bus_rep_north/config.tcl
+++ b/openlane/bus_rep_north/config.tcl
@@ -49,7 +49,8 @@
 
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 
-set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=27 "
+set ::env(SYNTH_PARAMETERS) "BUS_REP_WD=27 \ 
+                             BUS_BUF_WD=42 "
 
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 #set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
diff --git a/openlane/bus_rep_north/pin_order.cfg b/openlane/bus_rep_north/pin_order.cfg
index d6472e3..3fc1b58 100644
--- a/openlane/bus_rep_north/pin_order.cfg
+++ b/openlane/bus_rep_north/pin_order.cfg
@@ -32,7 +32,95 @@
 ch_in\[26\]
 
 #S
-ch_in\[0\]    2000 0 64
+buf_in\[0\]    0100 0 4
+buf_out\[1\]
+buf_out\[2\]
+buf_in\[3\]    
+buf_out\[4\]
+buf_out\[5\]
+buf_in\[6\]    
+buf_out\[7\]
+buf_out\[8\]
+buf_in\[9\]    
+buf_out\[10\]
+buf_out\[11\]
+buf_in\[12\]    
+buf_out\[13\]
+buf_out\[14\]
+buf_in\[15\]    
+buf_out\[16\]
+buf_out\[17\]
+buf_in\[18\]    
+buf_out\[19\]
+buf_out\[20\]
+buf_in\[21\]    
+buf_out\[22\]
+buf_out\[23\]
+buf_in\[24\]    
+buf_out\[25\]
+buf_out\[26\]
+buf_in\[27\]    
+buf_out\[28\]
+buf_out\[29\]
+buf_in\[30\]    
+buf_out\[31\]
+buf_out\[32\]
+buf_in\[33\]    
+buf_out\[34\]
+buf_out\[35\]
+buf_in\[36\]    
+buf_out\[37\]
+buf_out\[38\]
+buf_in\[39\]    
+buf_out\[40\]
+buf_out\[41\]
+
+buf_in\[41\]  2000 0 4
+buf_in\[40\]
+buf_out\[39\]    
+buf_in\[38\]
+buf_in\[37\]
+buf_out\[36\]    
+buf_in\[35\]
+buf_in\[34\]
+buf_out\[33\]    
+buf_in\[32\]
+buf_in\[31\]
+buf_out\[30\]    
+buf_in\[29\]
+buf_in\[28\]
+buf_out\[27\]    
+buf_in\[26\]
+buf_in\[25\]
+buf_out\[24\]    
+buf_in\[23\]
+buf_in\[22\]
+buf_out\[21\]    
+buf_in\[20\]
+buf_in\[19\]
+buf_out\[18\]    
+buf_in\[17\]
+buf_in\[16\]
+buf_out\[15\]    
+buf_in\[14\]
+buf_in\[13\]
+buf_out\[12\]    
+buf_in\[11\]
+buf_in\[10\]
+buf_out\[9\]    
+buf_in\[8\]
+buf_in\[7\]
+buf_out\[6\]    
+buf_in\[5\]
+buf_in\[4\]
+buf_out\[3\]    
+buf_in\[2\]
+buf_in\[1\]
+buf_out\[0\]    
+
+
+
+ch_in\[0\]    2400 0 16
 ch_in\[1\]
 ch_out\[2\]
 ch_in\[3\]    
diff --git a/openlane/fpu_wrapper/base.sdc b/openlane/fpu_wrapper/base.sdc
new file mode 100644
index 0000000..9a5897d
--- /dev/null
+++ b/openlane/fpu_wrapper/base.sdc
@@ -0,0 +1,271 @@
+###############################################################################
+# Created by write_sdc
+# Mon Nov  7 16:29:34 2022
+###############################################################################
+current_design fpu_wrapper
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[0]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[1]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[2]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_cska[3]}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {rst_n}]
+set_input_delay -max 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_clk_int}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_clk_out}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[1]}]
+
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_cmd}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_width[1]}]
+
+
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[1]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {dmem_resp[1]}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_out}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[0]}]
+
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/openlane/fpu_wrapper/config.tcl b/openlane/fpu_wrapper/config.tcl
new file mode 100755
index 0000000..8c0d4db
--- /dev/null
+++ b/openlane/fpu_wrapper/config.tcl
@@ -0,0 +1,126 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+
+set ::env(DESIGN_NAME) fpu_wrapper
+
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "mclk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu_wrapper/src/fpu_wrapper.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu_wrapper/src/fpu_reg.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_top.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_mul.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_div.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_add.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_f2i.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/fpu/verilog/rtl/fpu_sp_i2f.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+        $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
+        $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \
+	"
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 550 550"
+
+set ::env(GRT_ADJUSTMENT) 0.2
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.43"
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
+
+set ::env(FP_IO_VEXTEND) 2
+set ::env(FP_IO_HEXTEND) 2
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+
+#Lef 
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
+
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
+
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/fpu_wrapper/pin_order.cfg b/openlane/fpu_wrapper/pin_order.cfg
new file mode 100644
index 0000000..1ad7fde
--- /dev/null
+++ b/openlane/fpu_wrapper/pin_order.cfg
@@ -0,0 +1,93 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+
+#S
+
+rst_n             00 0 2
+cfg_cska\[3\]
+cfg_cska\[2\]
+cfg_cska\[1\]
+cfg_cska\[0\]
+wbd_clk_out
+mclk               
+
+
+wbd_clk_int     050 0 2
+dmem_req_ack    
+dmem_req         
+dmem_cmd  
+dmem_width\[1\]
+dmem_width\[0\]
+dmem_addr\[4\]     
+dmem_addr\[3\]     
+dmem_addr\[2\]     
+dmem_addr\[1\]     
+dmem_addr\[0\]   
+dmem_wdata\[31\]
+dmem_wdata\[30\]
+dmem_wdata\[29\]
+dmem_wdata\[28\]
+dmem_wdata\[27\]
+dmem_wdata\[26\]
+dmem_wdata\[25\]
+dmem_wdata\[24\]
+dmem_wdata\[23\]
+dmem_wdata\[22\]
+dmem_wdata\[21\]
+dmem_wdata\[20\]
+dmem_wdata\[19\]
+dmem_wdata\[18\]
+dmem_wdata\[17\]
+dmem_wdata\[16\]
+dmem_wdata\[15\]
+dmem_wdata\[14\]
+dmem_wdata\[13\]
+dmem_wdata\[12\]
+dmem_wdata\[11\]
+dmem_wdata\[10\]
+dmem_wdata\[9\]
+dmem_wdata\[8\]
+dmem_wdata\[7\]
+dmem_wdata\[6\]
+dmem_wdata\[5\]
+dmem_wdata\[4\]
+dmem_wdata\[3\]
+dmem_wdata\[2\]
+dmem_wdata\[1\]
+dmem_wdata\[0\]
+dmem_rdata\[31\]
+dmem_rdata\[30\]
+dmem_rdata\[29\]
+dmem_rdata\[28\]
+dmem_rdata\[27\]
+dmem_rdata\[26\]
+dmem_rdata\[25\]
+dmem_rdata\[24\]
+dmem_rdata\[23\]
+dmem_rdata\[22\]
+dmem_rdata\[21\]
+dmem_rdata\[20\]
+dmem_rdata\[19\]
+dmem_rdata\[18\]
+dmem_rdata\[17\]
+dmem_rdata\[16\]
+dmem_rdata\[15\]
+dmem_rdata\[14\]
+dmem_rdata\[13\]
+dmem_rdata\[12\]
+dmem_rdata\[11\]
+dmem_rdata\[10\]
+dmem_rdata\[9\]
+dmem_rdata\[8\]
+dmem_rdata\[7\]
+dmem_rdata\[6\]
+dmem_rdata\[5\]
+dmem_rdata\[4\]
+dmem_rdata\[3\]
+dmem_rdata\[2\]
+dmem_rdata\[1\]
+dmem_rdata\[0\]
+dmem_resp\[1\]
+dmem_resp\[0\]
diff --git a/openlane/peri_top/base.sdc b/openlane/peri_top/base.sdc
new file mode 100644
index 0000000..d55cd9f
--- /dev/null
+++ b/openlane/peri_top/base.sdc
@@ -0,0 +1,214 @@
+###############################################################################
+# Created by write_sdc
+# Wed Dec  7 16:59:07 2022
+###############################################################################
+current_design peri_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+create_clock -name rtc_clk -period 100.0000 [get_ports {rtc_clk}]
+
+set_clock_groups \
+   -name clock_group \
+   -logically_exclusive \
+   -group [get_clocks {mclk}]\
+   -group [get_clocks {rtc_clk}]\
+   -comment {Async Clock group}
+
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty 0.2500 [all_clocks]
+set_propagated_clock [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+### ClkSkew Adjust
+set_case_analysis 0 [get_ports {cfg_cska_peri[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[3]}]
+
+set_max_delay   3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay   2 -to   [get_ports {wbd_clk_peri}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_peri
+
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {s_reset_n}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {s_reset_n}]
+
+## RTC - Sys Clk
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
+
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}]
+
+
+### DAC I/F
+
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac0_mux_sel[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac1_mux_sel[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac2_mux_sel[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac3_mux_sel[*]}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac0_mux_sel[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac1_mux_sel[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac2_mux_sel[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_dac3_mux_sel[*]}]
+
+### RTC clock domain
+set_output_delay -max 6.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {inc_date_d}]
+set_output_delay -max 6.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {inc_time_s}]
+set_output_delay -max 6.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {rtc_intr}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {inc_date_d}]
+set_output_delay -min 1.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {inc_time_s}]
+set_output_delay -min 1.0000 -clock [get_clocks {rtc_clk}] -add_delay [get_ports {rtc_intr}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {inc_date_d}]
+set_load -pin_load 0.0334 [get_ports {inc_time_s}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {rtc_intr}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_peri}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/openlane/peri_top/config.tcl b/openlane/peri_top/config.tcl
new file mode 100755
index 0000000..0b3f35f
--- /dev/null
+++ b/openlane/peri_top/config.tcl
@@ -0,0 +1,138 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+# Global
+# ------
+
+set script_dir [file dirname [file normalize [info script]]]
+# Name
+
+set ::env(DESIGN_NAME) peri_top
+
+set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
+
+# Timing configuration
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "mclk rtc_clk"
+
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) {0}
+
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
+# Sources
+# -------
+
+# Local sources + no2usb sources
+set ::env(VERILOG_FILES) "\
+     $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \
+     $::env(DESIGN_DIR)/../../verilog/rtl/rtc/verilog/rtl/core/rtc_top.sv \
+     $::env(DESIGN_DIR)/../../verilog/rtl/rtc/verilog/rtl/core/rtc_core.sv \
+     $::env(DESIGN_DIR)/../../verilog/rtl/rtc/verilog/rtl/core/rtc_reg.sv \
+     $::env(DESIGN_DIR)/../../verilog/rtl/peripheral/src/peri_top.sv \
+     $::env(DESIGN_DIR)/../../verilog/rtl/dig2ana/src/dig2ana_reg.sv \
+     $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv     \
+     $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv     \
+     $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_reg_bus.sv \
+     $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \
+     "
+
+set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/ ]
+
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+set ::env(LEC_ENABLE) 0
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+
+
+# Floorplanning
+# -------------
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 400 200"
+
+
+# If you're going to use multiple power domains, then keep this disabled.
+set ::env(RUN_CVC) 0
+
+#set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+
+set ::env(PL_TIME_DRIVEN) 1
+set ::env(PL_TARGET_DENSITY) "0.35"
+set ::env(CELL_PAD) "8"
+#set ::env(GRT_ADJUSTMENT) {0.2}
+
+
+######################################################################################
+# Metal-2/3 Signal are Routed near to block boundary is creating DRC violation at Top-level 
+# during pad connectivity
+
+#set ::env(GRT_OBS) "                        \
+#                    met2  0    2   500  3,  \
+#                    met2  0    747 500  748, \
+#                    met3  2    0   3    750, \
+#                    met3  497  0 498    750"
+
+
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "1"
+
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
+
+set ::env(FP_PDN_VPITCH) 100
+set ::env(FP_PDN_HPITCH) 100
+set ::env(FP_PDN_VWIDTH) 6.2
+set ::env(FP_PDN_HWIDTH) 6.2
+
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
+
+#Lef 
+set ::env(MAGIC_GENERATE_LEF) {1}
+set ::env(MAGIC_WRITE_FULL_LEF) {0}
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {1.5}
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {1.5}
+
+set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {0.25}
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) {0.25}
+
+set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {500}
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {500}
+
+set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
+set ::env(QUIT_ON_LVS_ERROR) "1"
+set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/peri_top/pin_order.cfg b/openlane/peri_top/pin_order.cfg
new file mode 100644
index 0000000..2f23b77
--- /dev/null
+++ b/openlane/peri_top/pin_order.cfg
@@ -0,0 +1,142 @@
+#BUS_SORT
+#MANUAL_PLACE
+
+#W
+s_reset_n
+mclk
+wbd_clk_int
+wbd_clk_peri
+cfg_cska_peri\[3\]
+cfg_cska_peri\[2\]
+cfg_cska_peri\[1\]
+cfg_cska_peri\[0\]
+
+cfg_dac3_mux_sel\[7\]
+cfg_dac3_mux_sel\[6\]
+cfg_dac3_mux_sel\[5\]
+cfg_dac3_mux_sel\[4\]
+cfg_dac3_mux_sel\[3\]
+cfg_dac3_mux_sel\[2\]
+cfg_dac3_mux_sel\[1\]
+cfg_dac3_mux_sel\[0\]
+
+cfg_dac2_mux_sel\[7\]
+cfg_dac2_mux_sel\[6\]
+cfg_dac2_mux_sel\[5\]
+cfg_dac2_mux_sel\[4\]
+cfg_dac2_mux_sel\[3\]
+cfg_dac2_mux_sel\[2\]
+cfg_dac2_mux_sel\[1\]
+cfg_dac2_mux_sel\[0\]
+
+cfg_dac1_mux_sel\[7\]
+cfg_dac1_mux_sel\[6\]
+cfg_dac1_mux_sel\[5\]
+cfg_dac1_mux_sel\[4\]
+cfg_dac1_mux_sel\[3\]
+cfg_dac1_mux_sel\[2\]
+cfg_dac1_mux_sel\[1\]
+cfg_dac1_mux_sel\[0\]
+
+cfg_dac0_mux_sel\[7\]
+cfg_dac0_mux_sel\[6\]
+cfg_dac0_mux_sel\[5\]
+cfg_dac0_mux_sel\[4\]
+cfg_dac0_mux_sel\[3\]
+cfg_dac0_mux_sel\[2\]
+cfg_dac0_mux_sel\[1\]
+cfg_dac0_mux_sel\[0\]
+
+
+#S
+rtc_clk                200 0 2
+rtc_intr
+inc_date_d
+inc_time_s
+
+
+reg_cs            250 0  2
+reg_wr           
+reg_addr\[10\]    
+reg_addr\[9\]    
+reg_addr\[8\]    
+reg_addr\[7\]    
+reg_addr\[6\]    
+reg_addr\[5\]    
+reg_addr\[4\]    
+reg_addr\[3\]    
+reg_addr\[2\]    
+reg_addr\[1\]    
+reg_addr\[0\]    
+reg_be\[3\]    
+reg_be\[2\]    
+reg_be\[1\]    
+reg_be\[0\]    
+reg_wdata\[31\]   
+reg_wdata\[30\]   
+reg_wdata\[29\]   
+reg_wdata\[28\]   
+reg_wdata\[27\]   
+reg_wdata\[26\]   
+reg_wdata\[25\]   
+reg_wdata\[24\]   
+reg_wdata\[23\]   
+reg_wdata\[22\]   
+reg_wdata\[21\]   
+reg_wdata\[20\]   
+reg_wdata\[19\]   
+reg_wdata\[18\]   
+reg_wdata\[17\]   
+reg_wdata\[16\]   
+reg_wdata\[15\]   
+reg_wdata\[14\]   
+reg_wdata\[13\]   
+reg_wdata\[12\]  
+reg_wdata\[11\]  
+reg_wdata\[10\]  
+reg_wdata\[9\]   
+reg_wdata\[8\]   
+reg_wdata\[7\]   
+reg_wdata\[6\]   
+reg_wdata\[5\]   
+reg_wdata\[4\]   
+reg_wdata\[3\]   
+reg_wdata\[2\]   
+reg_wdata\[1\]   
+reg_wdata\[0\]   
+reg_rdata\[31\]  
+reg_rdata\[30\]  
+reg_rdata\[29\]  
+reg_rdata\[28\]  
+reg_rdata\[27\]  
+reg_rdata\[26\]  
+reg_rdata\[25\]  
+reg_rdata\[24\]  
+reg_rdata\[23\]  
+reg_rdata\[22\]  
+reg_rdata\[21\]  
+reg_rdata\[20\]  
+reg_rdata\[19\]  
+reg_rdata\[18\]  
+reg_rdata\[17\]  
+reg_rdata\[16\]  
+reg_rdata\[15\]  
+reg_rdata\[14\]  
+reg_rdata\[13\]  
+reg_rdata\[12\]  
+reg_rdata\[11\]  
+reg_rdata\[10\]  
+reg_rdata\[9\]  
+reg_rdata\[8\]  
+reg_rdata\[7\]  
+reg_rdata\[6\]  
+reg_rdata\[5\]  
+reg_rdata\[4\]  
+reg_rdata\[3\]  
+reg_rdata\[2\]  
+reg_rdata\[1\]  
+reg_rdata\[0\]  
+reg_ack       
+
+
+
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg
index fff23e7..bcdbeb5 100644
--- a/openlane/pinmux_top/pin_order.cfg
+++ b/openlane/pinmux_top/pin_order.cfg
@@ -69,7 +69,6 @@
 int_pll_clock
 xtal_clk
 s_reset_n
-rtc_clk
 usb_clk
 
 pinmux_debug\[0\] 0300 0  2
@@ -226,6 +225,7 @@
 
 reg_cs            260 0  2
 reg_wr           
+reg_addr\[10\]    
 reg_addr\[9\]    
 reg_addr\[8\]    
 reg_addr\[7\]    
@@ -308,44 +308,7 @@
 
 
 #N
-
-cfg_dac3_mux_sel\[7\]
-cfg_dac3_mux_sel\[6\]
-cfg_dac3_mux_sel\[5\]
-cfg_dac3_mux_sel\[4\]
-cfg_dac3_mux_sel\[3\]
-cfg_dac3_mux_sel\[2\]
-cfg_dac3_mux_sel\[1\]
-cfg_dac3_mux_sel\[0\]
-
-cfg_dac2_mux_sel\[7\]
-cfg_dac2_mux_sel\[6\]
-cfg_dac2_mux_sel\[5\]
-cfg_dac2_mux_sel\[4\]
-cfg_dac2_mux_sel\[3\]
-cfg_dac2_mux_sel\[2\]
-cfg_dac2_mux_sel\[1\]
-cfg_dac2_mux_sel\[0\]
-
-cfg_dac1_mux_sel\[7\]
-cfg_dac1_mux_sel\[6\]
-cfg_dac1_mux_sel\[5\]
-cfg_dac1_mux_sel\[4\]
-cfg_dac1_mux_sel\[3\]
-cfg_dac1_mux_sel\[2\]
-cfg_dac1_mux_sel\[1\]
-cfg_dac1_mux_sel\[0\]
-
-cfg_dac0_mux_sel\[7\]
-cfg_dac0_mux_sel\[6\]
-cfg_dac0_mux_sel\[5\]
-cfg_dac0_mux_sel\[4\]
-cfg_dac0_mux_sel\[3\]
-cfg_dac0_mux_sel\[2\]
-cfg_dac0_mux_sel\[1\]
-cfg_dac0_mux_sel\[0\]
-
-digital_io_oen\[37\]  100 0 4
+digital_io_oen\[37\]  000 0 2
 digital_io_out\[37\]
 digital_io_in\[37\]
 digital_io_oen\[36\]
@@ -374,9 +337,109 @@
 digital_io_in\[29\]
 digital_io_oen\[28\]
 digital_io_out\[28\]
+digital_io_in\[28\]  
+digital_io_oen\[27\]
+digital_io_out\[27\]
+digital_io_in\[27\]
+digital_io_oen\[26\]
+digital_io_out\[26\]
+digital_io_in\[26\]
+digital_io_oen\[25\]
+digital_io_out\[25\]
+digital_io_in\[25\]
+digital_io_oen\[24\]
+digital_io_out\[24\]
+digital_io_in\[24\]
+
+rtc_clk               150 0 2
+rtc_intr              
+
+reg_peri_cs            200 0  2
+reg_peri_wr           
+reg_peri_addr\[10\]    
+reg_peri_addr\[9\]    
+reg_peri_addr\[8\]    
+reg_peri_addr\[7\]    
+reg_peri_addr\[6\]    
+reg_peri_addr\[5\]    
+reg_peri_addr\[4\]    
+reg_peri_addr\[3\]    
+reg_peri_addr\[2\]    
+reg_peri_addr\[1\]    
+reg_peri_addr\[0\]    
+reg_peri_be\[3\]    
+reg_peri_be\[2\]    
+reg_peri_be\[1\]    
+reg_peri_be\[0\]    
+reg_peri_wdata\[31\]   
+reg_peri_wdata\[30\]   
+reg_peri_wdata\[29\]   
+reg_peri_wdata\[28\]   
+reg_peri_wdata\[27\]   
+reg_peri_wdata\[26\]   
+reg_peri_wdata\[25\]   
+reg_peri_wdata\[24\]   
+reg_peri_wdata\[23\]   
+reg_peri_wdata\[22\]   
+reg_peri_wdata\[21\]   
+reg_peri_wdata\[20\]   
+reg_peri_wdata\[19\]   
+reg_peri_wdata\[18\]   
+reg_peri_wdata\[17\]   
+reg_peri_wdata\[16\]   
+reg_peri_wdata\[15\]   
+reg_peri_wdata\[14\]   
+reg_peri_wdata\[13\]   
+reg_peri_wdata\[12\]  
+reg_peri_wdata\[11\]  
+reg_peri_wdata\[10\]  
+reg_peri_wdata\[9\]   
+reg_peri_wdata\[8\]   
+reg_peri_wdata\[7\]   
+reg_peri_wdata\[6\]   
+reg_peri_wdata\[5\]   
+reg_peri_wdata\[4\]   
+reg_peri_wdata\[3\]   
+reg_peri_wdata\[2\]   
+reg_peri_wdata\[1\]   
+reg_peri_wdata\[0\]   
+reg_peri_rdata\[31\]  
+reg_peri_rdata\[30\]  
+reg_peri_rdata\[29\]  
+reg_peri_rdata\[28\]  
+reg_peri_rdata\[27\]  
+reg_peri_rdata\[26\]  
+reg_peri_rdata\[25\]  
+reg_peri_rdata\[24\]  
+reg_peri_rdata\[23\]  
+reg_peri_rdata\[22\]  
+reg_peri_rdata\[21\]  
+reg_peri_rdata\[20\]  
+reg_peri_rdata\[19\]  
+reg_peri_rdata\[18\]  
+reg_peri_rdata\[17\]  
+reg_peri_rdata\[16\]  
+reg_peri_rdata\[15\]  
+reg_peri_rdata\[14\]  
+reg_peri_rdata\[13\]  
+reg_peri_rdata\[12\]  
+reg_peri_rdata\[11\]  
+reg_peri_rdata\[10\]  
+reg_peri_rdata\[9\]  
+reg_peri_rdata\[8\]  
+reg_peri_rdata\[7\]  
+reg_peri_rdata\[6\]  
+reg_peri_rdata\[5\]  
+reg_peri_rdata\[4\]  
+reg_peri_rdata\[3\]  
+reg_peri_rdata\[2\]  
+reg_peri_rdata\[1\]  
+reg_peri_rdata\[0\]  
+reg_peri_ack       
 
 
-cfg_dco_mode         0200 0 2
+
+cfg_dco_mode         0300 0 2
 cfg_pll_enb
 pll_ref_clk
 cfg_pll_fed_div\[4\]
@@ -411,19 +474,6 @@
 cfg_dc_trim\[1\]
 cfg_dc_trim\[0\]
 
-digital_io_in\[28\]  0300 0 2
-digital_io_oen\[27\]
-digital_io_out\[27\]
-digital_io_in\[27\]
-digital_io_oen\[26\]
-digital_io_out\[26\]
-digital_io_in\[26\]
-digital_io_oen\[25\]
-digital_io_out\[25\]
-digital_io_in\[25\]
-digital_io_oen\[24\]
-digital_io_out\[24\]
-digital_io_in\[24\]
 
 
 digital_io_in\[23\]     400  0
@@ -474,7 +524,7 @@
 sflash_di\[2\]      
 sflash_di\[3\]      
 
-digital_io_in\[0\]   0200 0 4
+digital_io_in\[0\]   0300 0 4
 digital_io_out\[0\]
 digital_io_oen\[0\]
 digital_io_in\[1\]
diff --git a/openlane/qspim_top/pin_order.cfg b/openlane/qspim_top/pin_order.cfg
index 8c81d46..afea1d2 100644
--- a/openlane/qspim_top/pin_order.cfg
+++ b/openlane/qspim_top/pin_order.cfg
@@ -23,7 +23,7 @@
 
 
 #W
-cfg_cska_sp_co\[3\]   0200 0 2
+cfg_cska_sp_co\[3\]   0300 0 2
 cfg_cska_sp_co\[2\]
 cfg_cska_sp_co\[1\]
 cfg_cska_sp_co\[0\]
@@ -35,7 +35,7 @@
 wbd_clk_spi
 mclk                   
 
-wbd_stb_i              0300 0 2
+wbd_stb_i              0350 0 2
 wbd_we_i               
 wbd_adr_i\[31\]        
 wbd_adr_i\[30\]        
@@ -161,7 +161,7 @@
 strap_flash\[1\]
 strap_flash\[0\]
 
-spi_debug\[0\]        0200 0  2
+spi_debug\[0\]        0050 0  2
 spi_debug\[1\]        
 spi_debug\[2\]        
 spi_debug\[3\]        
diff --git a/openlane/uart_i2c_usb_spi_top/pin_order.cfg b/openlane/uart_i2c_usb_spi_top/pin_order.cfg
index b518404..cbc75a4 100644
--- a/openlane/uart_i2c_usb_spi_top/pin_order.cfg
+++ b/openlane/uart_i2c_usb_spi_top/pin_order.cfg
@@ -2,7 +2,7 @@
 #MANUAL_PLACE
 
 #W
-cfg_cska_uart\[3\]     0200 0  2
+cfg_cska_uart\[3\]     0300 0  2
 cfg_cska_uart\[2\]
 cfg_cska_uart\[1\]
 cfg_cska_uart\[0\]
@@ -10,7 +10,7 @@
 wbd_clk_uart
 app_clk                
 
-reg_cs                 0300 0  2
+reg_cs                 0400 0  2
 reg_wr                 
 reg_addr\[8\]          
 reg_addr\[7\]          
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index f26769b..486f13f 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -82,6 +82,7 @@
 	    $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_north.v \
 	    $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_east.v \
 	    $::env(DESIGN_DIR)/../../verilog/gl/bus_rep_west.v \
+	    $::env(DESIGN_DIR)/../../verilog/gl/peri_top.v \
 	    "
 
 set ::env(EXTRA_LEFS) "\
@@ -102,6 +103,7 @@
 	$lef_root/bus_rep_north.lef \
 	$lef_root/bus_rep_east.lef \
 	$lef_root/bus_rep_west.lef \
+	$lef_root/peri_top.lef \
 	"
 
 set ::env(EXTRA_GDS_FILES) "\
@@ -122,6 +124,7 @@
 	$gds_root/bus_rep_north.gds \
 	$gds_root/bus_rep_east.gds \
 	$gds_root/bus_rep_west.gds \
+	$gds_root/peri_top.gds \
 	"
 
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -202,7 +205,8 @@
 	u_rp_south                  vccd1 vssd1 vccd1 vssd1,\
 	u_rp_north                  vccd1 vssd1 vccd1 vssd1,\
 	u_rp_east                   vccd1 vssd1 vccd1 vssd1,\
-	u_rp_west                   vccd1 vssd1 vccd1 vssd1
+	u_rp_west                   vccd1 vssd1 vccd1 vssd1,\
+	u_peri                      vccd1 vssd1 vccd1 vssd1
       	"
 
 
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 3a3500f..36306e2 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,14 +1,15 @@
-u_4x8bit_dac                 1850            2500            N
-u_qspi_master                2250             450           N
-u_uart_i2c_usb_spi           2250            1100           N
-u_pinmux                     2250            2000           N
-u_pll                        2500            3028           N
+u_4x8bit_dac                 1850            2500        N
+u_qspi_master                2250             350        N
+u_uart_i2c_usb_spi           2250            1000        N
+u_pinmux                     2250            1900        N
+u_peri                       2200            3000        N
+u_pll                        2650            3000        N
 
 u_fpu                       1100            2600           N
 u_aes                       150             2600           N
 u_riscv_top.i_core_top_0    150	     1400 	     N
 u_riscv_top.i_core_top_1    1200	     1400	     FN
-u_riscv_top.u_connect       733	     1400	     N
+u_riscv_top.u_connect       740	     1400	     N
 u_riscv_top.u_intf          950 	     650	     N
 u_dcache_2kb                150             130            N
 u_icache_2kb                950             130            N
@@ -16,7 +17,7 @@
 
 
 u_intercon                  1850            650          N
-u_wb_host                   1750            150          N
+u_wb_host                   1750            100          N
 u_rp_south                   100            20           N
 u_rp_north                   100            3400         N
 u_rp_east                   2820            50           E
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl
index b317190..84ea810 100644
--- a/openlane/user_project_wrapper/pdn_cfg.tcl
+++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -158,7 +158,7 @@
 define_pdn_grid \
     -macro \
     -name macro_1 \
-    -instances "u_pll u_intercon u_pinmux u_qspi_master u_tsram0_2kb u_icache_2kb u_dcache_2kb u_uart_i2c_usb_spi u_wb_host u_riscv_top.i_core_top_0 u_riscv_top.i_core_top_1 u_riscv_top.u_connect u_riscv_top.u_intf u_4x8bit_dac u_aes u_fpu" \
+    -instances "u_pll u_intercon u_pinmux u_qspi_master u_tsram0_2kb u_icache_2kb u_dcache_2kb u_uart_i2c_usb_spi u_wb_host u_riscv_top.i_core_top_0 u_riscv_top.i_core_top_1 u_riscv_top.u_connect u_riscv_top.u_intf u_4x8bit_dac u_aes u_fpu u_peri" \
     -starts_with POWER \
     -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
 
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 8ac589d..60315f0 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -153,12 +153,8 @@
 
 #N
 
-cfg_clk_skew_ctrl1\[31\]   0000 0 2
-cfg_clk_skew_ctrl1\[30\]
-cfg_clk_skew_ctrl1\[29\]
-cfg_clk_skew_ctrl1\[28\]
 
-cfg_clk_skew_ctrl1\[7\]
+cfg_clk_skew_ctrl1\[7\]      0000 0 2
 cfg_cska_wh\[3\]
 cfg_clk_skew_ctrl1\[6\]
 cfg_cska_wh\[2\]
@@ -335,7 +331,12 @@
 wbs_cyc_o      
 
 
-cfg_clk_skew_ctrl2\[31\]   325 0 2 
+cfg_clk_skew_ctrl1\[31\]   325 0 2
+cfg_clk_skew_ctrl1\[30\]
+cfg_clk_skew_ctrl1\[29\]
+cfg_clk_skew_ctrl1\[28\]
+
+cfg_clk_skew_ctrl2\[31\]   
 cfg_clk_skew_ctrl2\[30\]
 cfg_clk_skew_ctrl2\[29\]
 cfg_clk_skew_ctrl2\[28\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index a87255c..743d701 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -54,8 +54,8 @@
 
 set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 
-set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=14\
-	                 CH_DATA_WD=154 \
+set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=8\
+	                 CH_DATA_WD=158 \
 			 "
 
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index 51bfa57..af8e9cf 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg
@@ -3,16 +3,9 @@
 #MANUAL_PLACE
 
 #S
-ch_clk_in\[13\]  000 0 2
-ch_clk_in\[12\]
-ch_clk_in\[11\]
-ch_clk_in\[10\]
-ch_clk_in\[9\]
-ch_clk_in\[8\]
-ch_clk_in\[7\]
+ch_clk_in\[7\]  000 0 2
 ch_clk_in\[6\]
 ch_clk_in\[5\]
-ch_clk_in\[4\]
 
 
 rst_n                020  0 2
@@ -66,6 +59,7 @@
 cfg_cska_wi\[1\]     
 cfg_cska_wi\[0\] 
 
+ch_clk_in\[4\]
 ch_clk_in\[3\]
 ch_clk_in\[2\]
 ch_clk_in\[1\]
@@ -182,7 +176,13 @@
 m0_wbd_err_o        
 m0_wbd_cyc_i        
 
-ch_data_in\[153\]  225 0 2
+
+ch_data_in\[157\]  225 0 2
+ch_data_in\[156\]  
+ch_data_in\[155\]  
+ch_data_in\[154\]
+
+ch_data_in\[153\]  
 ch_data_in\[152\]  
 ch_data_in\[151\]  
 ch_data_in\[150\]
@@ -272,7 +272,7 @@
 ch_data_out\[22\] 
 ch_data_out\[21\] 
 ch_data_out\[20\] 
-ch_clk_out\[4\]
+ch_clk_out\[5\]
 
 ch_data_out\[3\]   050 0 2
 ch_data_out\[2\]
@@ -600,33 +600,29 @@
 ch_data_out\[42\] 
 ch_data_out\[41\] 
 ch_data_out\[40\] 
-ch_clk_out\[9\]
 
 ch_data_out\[39\] 
 ch_data_out\[38\] 
 ch_data_out\[37\] 
 ch_data_out\[36\] 
-ch_clk_out\[8\]
 
 ch_data_out\[35\] 
 ch_data_out\[34\] 
 ch_data_out\[33\] 
 ch_data_out\[32\] 
 
-ch_clk_out\[7\]
 
 ch_data_out\[31\] 
 ch_data_out\[30\] 
 ch_data_out\[29\] 
 ch_data_out\[28\] 
 
-ch_clk_out\[6\]
 
 ch_data_out\[27\]  750 0 2
 ch_data_out\[26\] 
 ch_data_out\[25\] 
 ch_data_out\[24\] 
-ch_clk_out\[5\]
+ch_clk_out\[6\]
 
 ch_data_out\[76\]   1600 0 2
 ch_data_out\[75\] 
@@ -666,13 +662,11 @@
 ch_data_out\[148\]  
 ch_data_out\[147\]  
 ch_data_out\[146\]  
-ch_clk_out\[10\]
 
 ch_data_out\[153\]  1750 0 2
 ch_data_out\[152\]  
 ch_data_out\[151\]  
 ch_data_out\[150\]  
-ch_clk_out\[11\]
 
 #E
 ch_data_out\[19\]   0000 0  2  
@@ -685,7 +679,7 @@
 ch_data_out\[4\]
 ch_clk_out\[1\]
 
-s0_wbd_stb_o         0100 0 2
+s0_wbd_stb_o         0050 0 2
 s0_wbd_we_o         
 s0_wbd_adr_o\[31\]  
 s0_wbd_adr_o\[30\]  
@@ -892,7 +886,9 @@
 s1_wbd_cyc_o  
 
 
-ch_data_in\[145\]  1350 0 2
+
+
+ch_data_in\[145\]  1250 0 2
 ch_data_in\[144\]  
 ch_data_in\[143\]  
 ch_data_in\[142\]  
@@ -966,7 +962,7 @@
 ch_data_out\[78\]  
 ch_data_out\[77\]  
 
-ch_data_in\[76\]  1550 0 2
+ch_data_in\[76\]  1450 0 2
 ch_data_in\[75\]  
 ch_data_in\[74\]  
 ch_data_in\[73\]  
@@ -1006,8 +1002,9 @@
 ch_data_out\[12\]
 ch_clk_out\[3\]
 
-s2_wbd_stb_o         1610 0 2
+s2_wbd_stb_o         1510 0 2
 s2_wbd_we_o         
+s2_wbd_adr_o\[10\]   
 s2_wbd_adr_o\[9\]   
 s2_wbd_adr_o\[8\]   
 s2_wbd_adr_o\[7\]   
@@ -1089,6 +1086,10 @@
 s2_wbd_ack_i        
 s2_wbd_cyc_o        
 
-ch_clk_out\[12\]
-ch_clk_out\[13\]
+ch_clk_out\[7\]
 
+ch_clk_out\[4\]           1750 0 2
+ch_data_out\[154\]
+ch_data_out\[155\]
+ch_data_out\[156\]
+ch_data_out\[157\]
diff --git a/openlane/ycr2_iconnect/pin_order.cfg b/openlane/ycr2_iconnect/pin_order.cfg
index 48f9639..4eda6fe 100644
--- a/openlane/ycr2_iconnect/pin_order.cfg
+++ b/openlane/ycr2_iconnect/pin_order.cfg
@@ -128,7 +128,8 @@
 sram0_dout1\[1\]
 sram0_dout1\[0\]
 
-core0_uid\[1\]   0200 00 2
+core0_clk        0200 00 2
+core0_uid\[1\]   
 core0_uid\[0\]   
 core0_imem_req_ack
 core0_imem_req
@@ -827,7 +828,8 @@
 core_clk_skew
 core_clk          
 
-core1_uid\[1\]      0200 00 2
+core1_clk           0200 00 2
+core1_uid\[1\]      
 core1_uid\[0\]   
 core1_imem_req_ack
 core1_imem_req
@@ -1198,6 +1200,7 @@
 
 
 #N
+cpu_clk_aes
 aes_dmem_req_ack
 aes_dmem_req
 aes_dmem_cmd
@@ -1278,8 +1281,8 @@
 aes_dmem_resp\[0\]
 
 
-
-fpu_dmem_req_ack 0200 0 2
+cpu_clk_fpu      0200 0 2
+fpu_dmem_req_ack 
 fpu_dmem_req
 fpu_dmem_cmd
 fpu_dmem_width\[1\]
diff --git a/openlane/ycr_core_top/pin_order.cfg b/openlane/ycr_core_top/pin_order.cfg
index f3daaa8..54bb33f 100644
--- a/openlane/ycr_core_top/pin_order.cfg
+++ b/openlane/ycr_core_top/pin_order.cfg
@@ -1,22 +1,21 @@
 #BUS_SORT
 #MANUAL_PLACE
 #E
-pwrup_rst_n       
+pwrup_rst_n               0000 00 2
 rst_n
-
-cfg_ccska\[3\]
-cfg_ccska\[2\]
-cfg_ccska\[1\]
-cfg_ccska\[0\]
-core_clk_int
-core_clk_skew
-
-clk
-clk_o
 core_rst_n_o
 core_rdc_qlfy_o
 
-core_uid\[1\]              0200 00 2
+cfg_ccska\[3\]             0180 00 2
+cfg_ccska\[2\]
+cfg_ccska\[1\]
+cfg_ccska\[0\]
+core_clk_skew
+clk
+clk_o
+
+core_clk_int               0200 00 2
+core_uid\[1\]              
 core_uid\[0\]   
 imem2core_req_ack_i
 core2imem_req_o
diff --git a/sdc/.caravel.sdc.swp b/sdc/.caravel.sdc.swp
new file mode 100644
index 0000000..92143b4
--- /dev/null
+++ b/sdc/.caravel.sdc.swp
Binary files differ
diff --git a/sdc/aes_top.sdc b/sdc/aes_top.sdc
new file mode 100644
index 0000000..ffe02f5
--- /dev/null
+++ b/sdc/aes_top.sdc
@@ -0,0 +1,277 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 07:49:06 2022
+###############################################################################
+current_design aes_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[5]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[6]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_cmd}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_cmd}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_req}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_req}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_width[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_width[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_width[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_width[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {rst_n}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {rst_n}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {wbd_clk_int}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {wbd_clk_int}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_req_ack}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_resp[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_resp[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {wbd_clk_out}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {wbd_clk_out}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_out}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/bus_rep_east.sdc b/sdc/bus_rep_east.sdc
new file mode 100644
index 0000000..ef1b316
--- /dev/null
+++ b/sdc/bus_rep_east.sdc
@@ -0,0 +1,199 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 10:21:05 2022
+###############################################################################
+current_design bus_rep_east
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000 
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[42]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[43]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[44]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[42]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[43]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[44]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {ch_out[44]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[43]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[42]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[41]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[40]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[39]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[38]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[37]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[36]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[35]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[34]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[33]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[32]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[31]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[30]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[29]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[28]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[27]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[26]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[25]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[24]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[23]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[22]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[21]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[20]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[19]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[18]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[17]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[16]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[15]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[14]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[13]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[12]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[11]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[10]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[9]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[8]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/bus_rep_north.sdc b/sdc/bus_rep_north.sdc
new file mode 100644
index 0000000..17f2323
--- /dev/null
+++ b/sdc/bus_rep_north.sdc
@@ -0,0 +1,295 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 10:20:58 2022
+###############################################################################
+current_design bus_rep_north
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000 
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_in[9]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {buf_out[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {buf_out[41]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[40]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[39]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[38]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[37]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[36]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[35]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[34]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[33]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[32]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[31]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[30]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[29]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[28]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[27]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[26]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[25]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[24]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[23]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[22]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[21]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[20]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[19]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[18]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[17]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[16]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[15]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[14]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[13]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[12]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[11]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[10]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[9]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[8]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[7]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[6]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[5]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[4]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[3]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[2]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[1]}]
+set_load -pin_load 0.0334 [get_ports {buf_out[0]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[26]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[25]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[24]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[23]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[22]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[21]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[20]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[19]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[18]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[17]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[16]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[15]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[14]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[13]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[12]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[11]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[10]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[9]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[8]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {buf_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/bus_rep_south.sdc b/sdc/bus_rep_south.sdc
new file mode 100644
index 0000000..07489c0
--- /dev/null
+++ b/sdc/bus_rep_south.sdc
@@ -0,0 +1,1031 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 10:21:25 2022
+###############################################################################
+current_design bus_rep_south
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000 
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[100]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[101]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[102]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[103]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[104]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[105]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[106]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[107]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[108]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[109]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[110]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[111]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[112]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[113]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[114]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[115]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[116]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[117]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[118]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[119]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[120]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[121]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[122]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[123]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[124]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[125]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[126]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[127]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[128]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[129]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[130]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[131]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[132]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[133]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[134]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[135]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[136]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[137]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[138]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[139]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[140]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[141]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[142]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[143]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[144]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[145]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[146]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[147]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[148]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[149]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[150]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[151]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[152]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[153]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[154]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[155]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[156]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[157]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[158]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[159]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[160]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[161]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[162]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[163]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[164]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[165]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[166]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[167]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[168]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[169]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[170]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[171]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[172]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[173]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[174]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[175]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[176]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[177]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[178]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[179]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[180]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[181]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[182]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[183]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[184]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[185]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[186]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[187]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[188]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[189]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[190]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[191]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[192]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[193]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[194]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[195]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[196]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[197]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[198]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[199]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[200]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[201]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[202]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[203]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[204]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[205]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[206]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[207]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[208]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[209]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[210]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[211]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[212]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[213]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[214]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[215]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[216]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[217]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[218]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[219]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[220]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[221]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[222]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[223]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[224]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[225]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[226]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[227]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[228]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[229]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[230]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[231]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[232]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[233]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[234]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[235]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[236]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[237]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[238]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[239]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[240]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[241]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[242]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[243]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[244]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[245]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[246]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[247]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[248]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[249]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[250]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[251]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[252]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[42]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[43]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[44]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[45]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[46]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[47]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[48]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[49]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[50]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[51]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[52]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[53]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[54]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[55]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[56]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[57]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[58]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[59]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[60]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[61]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[62]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[63]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[64]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[65]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[66]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[67]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[68]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[69]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[70]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[71]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[72]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[73]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[74]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[75]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[76]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[77]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[78]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[79]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[80]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[81]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[82]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[83]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[84]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[85]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[86]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[87]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[88]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[89]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[90]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[91]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[92]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[93]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[94]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[95]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[96]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[97]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[98]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[99]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[100]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[101]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[102]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[103]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[104]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[105]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[106]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[107]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[108]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[109]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[110]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[111]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[112]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[113]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[114]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[115]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[116]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[117]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[118]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[119]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[120]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[121]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[122]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[123]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[124]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[125]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[126]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[127]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[128]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[129]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[130]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[131]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[132]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[133]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[134]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[135]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[136]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[137]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[138]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[139]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[140]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[141]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[142]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[143]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[144]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[145]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[146]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[147]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[148]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[149]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[150]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[151]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[152]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[153]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[154]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[155]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[156]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[157]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[158]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[159]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[160]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[161]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[162]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[163]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[164]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[165]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[166]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[167]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[168]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[169]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[170]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[171]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[172]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[173]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[174]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[175]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[176]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[177]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[178]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[179]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[180]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[181]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[182]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[183]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[184]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[185]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[186]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[187]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[188]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[189]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[190]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[191]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[192]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[193]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[194]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[195]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[196]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[197]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[198]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[199]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[200]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[201]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[202]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[203]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[204]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[205]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[206]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[207]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[208]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[209]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[210]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[211]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[212]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[213]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[214]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[215]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[216]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[217]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[218]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[219]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[220]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[221]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[222]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[223]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[224]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[225]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[226]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[227]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[228]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[229]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[230]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[231]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[232]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[233]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[234]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[235]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[236]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[237]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[238]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[239]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[240]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[241]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[242]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[243]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[244]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[245]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[246]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[247]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[248]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[249]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[250]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[251]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[252]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[42]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[43]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[44]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[45]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[46]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[47]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[48]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[49]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[50]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[51]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[52]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[53]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[54]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[55]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[56]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[57]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[58]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[59]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[60]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[61]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[62]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[63]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[64]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[65]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[66]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[67]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[68]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[69]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[70]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[71]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[72]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[73]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[74]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[75]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[76]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[77]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[78]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[79]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[80]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[81]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[82]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[83]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[84]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[85]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[86]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[87]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[88]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[89]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[90]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[91]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[92]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[93]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[94]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[95]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[96]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[97]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[98]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[99]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {ch_out[252]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[251]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[250]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[249]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[248]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[247]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[246]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[245]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[244]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[243]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[242]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[241]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[240]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[239]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[238]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[237]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[236]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[235]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[234]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[233]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[232]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[231]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[230]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[229]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[228]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[227]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[226]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[225]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[224]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[223]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[222]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[221]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[220]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[219]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[218]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[217]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[216]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[215]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[214]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[213]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[212]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[211]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[210]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[209]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[208]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[207]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[206]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[205]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[204]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[203]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[202]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[201]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[200]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[199]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[198]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[197]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[196]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[195]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[194]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[193]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[192]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[191]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[190]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[189]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[188]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[187]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[186]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[185]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[184]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[183]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[182]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[181]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[180]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[179]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[178]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[177]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[176]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[175]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[174]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[173]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[172]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[171]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[170]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[169]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[168]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[167]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[166]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[165]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[164]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[163]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[162]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[161]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[160]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[159]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[158]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[157]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[156]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[155]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[154]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[153]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[152]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[151]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[150]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[149]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[148]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[147]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[146]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[145]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[144]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[143]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[142]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[141]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[140]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[139]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[138]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[137]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[136]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[135]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[134]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[133]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[132]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[131]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[130]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[129]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[128]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[127]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[126]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[125]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[124]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[123]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[122]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[121]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[120]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[119]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[118]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[117]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[116]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[115]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[114]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[113]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[112]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[111]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[110]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[109]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[108]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[107]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[106]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[105]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[104]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[103]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[102]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[101]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[100]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[99]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[98]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[97]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[96]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[95]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[94]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[93]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[92]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[91]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[90]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[89]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[88]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[87]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[86]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[85]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[84]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[83]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[82]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[81]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[80]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[79]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[78]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[77]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[76]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[75]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[74]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[73]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[72]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[71]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[70]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[69]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[68]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[67]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[66]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[65]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[64]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[63]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[62]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[61]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[60]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[59]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[58]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[57]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[56]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[55]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[54]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[53]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[52]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[51]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[50]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[49]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[48]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[47]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[46]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[45]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[44]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[43]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[42]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[41]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[40]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[39]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[38]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[37]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[36]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[35]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[34]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[33]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[32]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[31]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[30]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[29]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[28]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[27]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[26]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[25]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[24]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[23]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[22]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[21]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[20]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[19]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[18]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[17]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[16]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[15]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[14]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[13]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[12]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[11]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[10]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[9]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[8]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[252]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[251]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[250]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[249]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[248]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[247]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[246]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[245]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[244]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[243]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[242]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[241]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[240]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[239]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[238]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[237]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[236]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[235]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[234]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[233]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[232]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[231]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[230]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[229]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[228]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[227]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[226]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[225]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[224]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[223]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[222]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[221]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[220]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[219]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[218]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[217]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[216]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[215]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[214]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[213]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[212]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[211]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[210]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[209]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[208]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[207]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[206]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[203]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[202]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[200]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[199]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[198]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[197]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[196]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[195]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[194]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[193]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[192]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[191]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[190]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[189]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[188]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[187]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[186]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[185]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[184]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[183]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[182]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[181]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[180]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[179]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[178]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[177]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[176]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[175]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[174]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[173]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[172]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[171]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[170]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[169]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[168]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[167]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[166]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[165]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[164]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[163]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[162]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[161]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[160]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[159]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[158]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[157]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[156]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[155]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[154]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[153]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[152]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[151]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[150]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[149]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[148]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[147]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[146]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[145]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[144]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[143]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[142]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[141]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[140]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[139]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[138]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[137]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[136]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[135]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[134]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[133]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[132]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[131]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[130]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[129]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[128]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[124]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[123]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[122]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[121]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[120]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[119]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[118]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[117]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[116]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[115]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[114]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[113]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[112]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[111]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[110]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[109]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[108]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[107]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[106]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[105]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[104]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[103]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[102]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[101]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[100]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[99]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[98]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[97]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[96]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[95]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[94]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[93]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[92]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[91]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[90]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[89]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[88]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[87]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[86]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[85]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[84]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[83]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[82]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[81]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[80]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[79]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[78]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[77]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[76]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[75]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[74]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[73]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[72]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[71]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[70]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[69]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[68]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[67]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[66]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[65]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[64]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[63]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[62]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[61]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[60]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[59]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[58]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[57]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[56]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[55]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[54]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[53]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[52]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[51]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[50]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[49]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/bus_rep_west.sdc b/sdc/bus_rep_west.sdc
new file mode 100644
index 0000000..b8e774e
--- /dev/null
+++ b/sdc/bus_rep_west.sdc
@@ -0,0 +1,187 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 10:21:17 2022
+###############################################################################
+current_design bus_rep_west
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name __VIRTUAL_CLK__ -period 10.0000 
+set_clock_uncertainty 0.2500 __VIRTUAL_CLK__
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[0]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[10]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[11]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[12]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[13]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[14]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[15]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[16]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[17]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[18]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[19]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[1]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[20]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[21]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[22]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[23]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[24]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[25]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[26]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[27]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[28]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[29]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[2]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[30]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[31]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[32]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[33]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[34]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[35]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[36]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[37]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[38]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[39]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[3]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[40]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[41]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[4]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[5]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[6]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[7]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[8]}]
+set_input_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_in[9]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[0]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[10]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[11]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[12]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[13]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[14]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[15]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[16]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[17]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[18]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[19]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[1]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[20]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[21]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[22]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[23]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[24]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[25]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[26]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[27]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[28]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[29]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[2]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[30]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[31]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[32]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[33]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[34]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[35]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[36]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[37]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[38]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[39]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[3]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[40]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[41]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[4]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[5]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[6]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[7]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[8]}]
+set_output_delay 2.0000 -clock [get_clocks {__VIRTUAL_CLK__}] -add_delay [get_ports {ch_out[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {ch_out[41]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[40]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[39]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[38]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[37]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[36]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[35]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[34]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[33]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[32]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[31]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[30]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[29]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[28]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[27]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[26]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[25]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[24]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[23]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[22]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[21]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[20]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[19]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[18]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[17]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[16]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[15]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[14]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[13]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[12]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[11]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[10]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[9]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[8]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_out[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_in[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/caravel.sdc b/sdc/caravel.sdc
new file mode 100644
index 0000000..9ddeee6
--- /dev/null
+++ b/sdc/caravel.sdc
@@ -0,0 +1,364 @@
+### Caravel Signoff SDC
+### Rev 3
+### Date: 28/10/2022
+### Reference SDC: $CARAVEL_ROOT/signoff/caravel/caravel.sdc
+
+## MASTER CLOCKS
+## Reduce the clock speed from 25ns 40ns
+create_clock -name clk -period 40 [get_ports {clock}] 
+
+create_clock -name hkspi_clk -period 100 [get_pins {housekeeping/mgmt_gpio_in[4]} ] 
+create_clock -name hk_serial_clk -period 50 [get_pins {housekeeping/serial_clock}]
+create_clock -name hk_serial_load -period 1000 [get_pins {housekeeping/serial_load}]
+# hk_serial_clk period is x2 core clock
+
+### User Project Clocks
+create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clk] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i]
+create_clock -name int_pll_clock -period 5.0000  [get_pins {mprj/u_pinmux/int_pll_clock}]
+
+create_clock -name wbs_ref_clk -period 5.0000   [get_pins {mprj/u_wb_host/u_reg.u_wbs_ref_clkbuf.u_buf/X}]
+create_clock -name wbs_clk_i   -period 26.0000  [get_pins {mprj/u_wb_host/wbs_clk_out}]
+
+create_clock -name cpu_ref_clk -period 5.0000   [get_pins {mprj/u_wb_host/u_reg.u_cpu_ref_clkbuf.u_buf/X}]
+create_clock -name cpu_clk     -period 40.0000  [get_pins {mprj/u_wb_host/cpu_clk}]
+
+create_clock -name rtc_ref_clk -period 50.0000  [get_pins {mprj/u_pinmux/u_glbl_reg.u_rtc_ref_clkbuf.u_buf/X}]
+create_clock -name rtc_clk     -period 50.0000  [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_rtc.u_buf/X}]
+
+create_clock -name pll_ref_clk -period 20.0000  [get_pins {mprj/u_pinmux/pll_ref_clk}]
+create_clock -name pll_clk_0   -period 12.0000   [get_pins {mprj/u_pll/ringosc.ibufp01/Y}]
+
+create_clock -name usb_ref_clk -period 6.0000   [get_pins {mprj/u_pinmux/u_glbl_reg.u_usb_ref_clkbuf.u_buf/X}]
+create_clock -name usb_clk     -period 20.0000  [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_usb.u_buf/X}]
+create_clock -name uarts0_clk  -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uarts1_clk  -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}]
+create_clock -name uartm_clk   -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
+create_clock -name dbg_ref_clk -period 12.0000 [get_pins {mprj/u_pinmux/u_glbl_reg.u_clkbuf_dbg_ref.u_buf/X}]
+
+set_clock_uncertainty 0.1000 [all_clocks]
+
+set_clock_groups \
+   -name clock_group \
+   -logically_exclusive \
+   -group [get_clocks {wb_clk clk}]\
+   -group [get_clocks {hk_serial_clk}]\
+   -group [get_clocks {hk_serial_load}]\
+   -group [get_clocks {hkspi_clk}]\
+   -group [get_clocks {int_pll_clock}]\
+   -group [get_clocks {wbs_clk_i}]\
+   -group [get_clocks {wbs_ref_clk}]\
+   -group [get_clocks {cpu_clk}]\
+   -group [get_clocks {cpu_ref_clk}]\
+   -group [get_clocks {rtc_clk}]\
+   -group [get_clocks {usb_ref_clk}]\
+   -group [get_clocks {pll_ref_clk}]\
+   -group [get_clocks {pll_clk_0}]\
+   -group [get_clocks {usb_clk}]\
+   -group [get_clocks {uarts0_clk}]\
+   -group [get_clocks {uarts1_clk}]\
+   -group [get_clocks {uartm_clk}]\
+   -group [get_clocks {dbg_ref_clk}]\
+   -group [get_clocks {rtc_ref_clk}]\
+   -comment {Async Clock group}
+
+# clock <-> hk_serial_clk/load no paths
+# future note: CDC stuff
+# clock <-> hkspi_clk no paths with careful methods (clock is off)
+
+set_propagated_clock [all_clocks]
+
+## INPUT/OUTPUT DELAYS
+set input_delay_value 4
+set output_delay_value 4
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {gpio}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[0]}]
+
+#set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[1]}]
+
+set_input_delay $input_delay_value  -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[2]}]
+set_input_delay $input_delay_value  -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[3]}]
+
+#set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[4]}]
+
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[5]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[6]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[7]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[8]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[9]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[10]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[11]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[12]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[13]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[14]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[15]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[16]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[17]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[18]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[19]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[20]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[21]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[22]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[23]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[24]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[25]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[26]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[27]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[28]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[29]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[30]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[31]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[32]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[33]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[34]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[35]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[36]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {mprj_io[37]}]
+
+set_output_delay $output_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {flash_csb}]
+set_output_delay $output_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {flash_clk}]
+set_output_delay $output_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {flash_io0}]
+set_output_delay $output_delay_value  -clock [get_clocks {clk}] -add_delay [get_ports {flash_io1}]
+
+# set_output_delay $output_delay_value  -clock [get_clocks {hkspi_clk}] -add_delay [get_ports {mprj_io[1]}]
+
+set_max_fanout 12 [current_design]
+# synthesis max fanout should be less than 12 (7 maybe)
+
+## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled 
+set_case_analysis 0 [get_pins housekeeping/_3936_/S]
+set_case_analysis 0 [get_pins housekeeping/_3937_/S]
+
+# Add case analysis for pads DM[2]==1'b1 & DM[1]==1'b1 & DM[0]==1'b0 to be outputs
+
+set_case_analysis 1 [get_pins padframe/*_pad*/DM[2]]
+set_case_analysis 1 [get_pins padframe/*_pad*/DM[1]]
+set_case_analysis 0 [get_pins padframe/*_pad*/DM[0]]
+set_case_analysis 0 [get_pins padframe/*_pad*/SLOW]
+set_case_analysis 0 [get_pins padframe/*_pad*/ANALOG_EN]
+
+# the following pads are set as inputs
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[2]]
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[4]/DM[1]]
+set_case_analysis 1 [get_pins padframe/*area1_io_pad[4]/DM[0]]
+
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[2]]
+set_case_analysis 0 [get_pins padframe/*area1_io_pad[2]/DM[1]]
+set_case_analysis 1 [get_pins padframe/*area1_io_pad[2]/DM[0]]
+
+
+set_case_analysis 0 [get_pins padframe/clock_pad/DM[2]]
+set_case_analysis 0 [get_pins padframe/clock_pad/DM[1]]
+set_case_analysis 1 [get_pins padframe/clock_pad/DM[0]]
+
+#################################################################
+## User Case analysis
+#################################################################
+set_case_analysis 0 [get_pins {mprj/u_peri/cfg_cska_peri[3]}]
+set_case_analysis 1 [get_pins {mprj/u_peri/cfg_cska_peri[2]}]
+set_case_analysis 0 [get_pins {mprj/u_peri/cfg_cska_peri[1]}]
+set_case_analysis 0 [get_pins {mprj/u_peri/cfg_cska_peri[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[3]}]
+set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}]
+set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}]
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}]
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}]
+set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}]
+set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_wcska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}]
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}]
+set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}]
+set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}]
+
+# clock skew cntrl-2
+set_case_analysis 0 [get_pins {mprj/u_fpu/cfg_cska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_fpu/cfg_cska[2]}]
+set_case_analysis 1 [get_pins {mprj/u_fpu/cfg_cska[1]}]
+set_case_analysis 1 [get_pins {mprj/u_fpu/cfg_cska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_aes/cfg_cska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_aes/cfg_cska[0]}]
+
+#set_case_analysis 1 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[3]}]
+#set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[2]}]
+#set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[1]}]
+#set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_3/cfg_ccska[0]}]
+
+#set_case_analysis 1 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[3]}]
+#set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[2]}]
+#set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[1]}]
+#set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_2/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_1/cfg_ccska[0]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.i_core_top_0/cfg_ccska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[3]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[2]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_ccska[0]}]
+
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[3]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_ccska[0]}]
+
+
+
+
+#Keept the SRAM clock driving edge at pos edge
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[1]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[1]}]
+
+
+## FALSE PATHS (ASYNCHRONOUS INPUTS)
+set_false_path -from [get_ports {resetb}]
+
+## Async USB/I2C Interrupt, Double Sync added inside glbl block
+set_false_path -through [get_pins {mprj/u_pinmux/usb_intr}]
+set_false_path -through [get_pins {mprj/u_pinmux/i2cm_intr}]
+
+## UART RXD is async signal
+set_false_path -through [get_pins {mprj/u_wb_host/uartm_rxd}]
+
+##SPI Slave Interface Signal (SCLK/SSN) are double sync with wb_clk
+set_false_path -through [get_pins {mprj/u_wb_host/sclk}]
+set_false_path -through [get_pins {mprj/u_wb_host/ssn}]
+## SDIN sampled on negedge SCLK
+set_false_path -through [get_pins {mprj/u_wb_host/sdin}]
+
+
+# set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_in[*]]
+# reset_path -from [get_ports mprj_io[4]] 
+# reset_path -from [get_ports mprj_io[2]] 
+#reset_path is not supported in PT read_sdc ^
+
+set_false_path -from [get_ports mprj_io[0]] -through [get_pins housekeeping/mgmt_gpio_in[0]]
+set_false_path -from [get_ports mprj_io[1]] -through [get_pins housekeeping/mgmt_gpio_in[1]]
+set_false_path -from [get_ports mprj_io[3]] -through [get_pins housekeeping/mgmt_gpio_in[3]]
+set_false_path -from [get_ports mprj_io[5]] -through [get_pins housekeeping/mgmt_gpio_in[5]]
+set_false_path -from [get_ports mprj_io[6]] -through [get_pins housekeeping/mgmt_gpio_in[6]]
+set_false_path -from [get_ports mprj_io[7]] -through [get_pins housekeeping/mgmt_gpio_in[7]]
+set_false_path -from [get_ports mprj_io[8]] -through [get_pins housekeeping/mgmt_gpio_in[8]]
+set_false_path -from [get_ports mprj_io[9]] -through [get_pins housekeeping/mgmt_gpio_in[9]]
+set_false_path -from [get_ports mprj_io[10]] -through [get_pins housekeeping/mgmt_gpio_in[10]]
+set_false_path -from [get_ports mprj_io[11]] -through [get_pins housekeeping/mgmt_gpio_in[11]]
+set_false_path -from [get_ports mprj_io[12]] -through [get_pins housekeeping/mgmt_gpio_in[12]]
+set_false_path -from [get_ports mprj_io[13]] -through [get_pins housekeeping/mgmt_gpio_in[13]]
+set_false_path -from [get_ports mprj_io[14]] -through [get_pins housekeeping/mgmt_gpio_in[14]]
+set_false_path -from [get_ports mprj_io[15]] -through [get_pins housekeeping/mgmt_gpio_in[15]]
+set_false_path -from [get_ports mprj_io[16]] -through [get_pins housekeeping/mgmt_gpio_in[16]]
+set_false_path -from [get_ports mprj_io[17]] -through [get_pins housekeeping/mgmt_gpio_in[17]]
+set_false_path -from [get_ports mprj_io[18]] -through [get_pins housekeeping/mgmt_gpio_in[18]]
+set_false_path -from [get_ports mprj_io[19]] -through [get_pins housekeeping/mgmt_gpio_in[19]]
+set_false_path -from [get_ports mprj_io[20]] -through [get_pins housekeeping/mgmt_gpio_in[20]]
+set_false_path -from [get_ports mprj_io[21]] -through [get_pins housekeeping/mgmt_gpio_in[21]]
+set_false_path -from [get_ports mprj_io[22]] -through [get_pins housekeeping/mgmt_gpio_in[22]]
+set_false_path -from [get_ports mprj_io[23]] -through [get_pins housekeeping/mgmt_gpio_in[23]]
+set_false_path -from [get_ports mprj_io[24]] -through [get_pins housekeeping/mgmt_gpio_in[24]]
+set_false_path -from [get_ports mprj_io[25]] -through [get_pins housekeeping/mgmt_gpio_in[25]]
+set_false_path -from [get_ports mprj_io[26]] -through [get_pins housekeeping/mgmt_gpio_in[26]]
+set_false_path -from [get_ports mprj_io[27]] -through [get_pins housekeeping/mgmt_gpio_in[27]]
+set_false_path -from [get_ports mprj_io[28]] -through [get_pins housekeeping/mgmt_gpio_in[28]]
+set_false_path -from [get_ports mprj_io[29]] -through [get_pins housekeeping/mgmt_gpio_in[29]]
+set_false_path -from [get_ports mprj_io[30]] -through [get_pins housekeeping/mgmt_gpio_in[30]]
+set_false_path -from [get_ports mprj_io[31]] -through [get_pins housekeeping/mgmt_gpio_in[31]]
+set_false_path -from [get_ports mprj_io[32]] -through [get_pins housekeeping/mgmt_gpio_in[32]]
+set_false_path -from [get_ports mprj_io[33]] -through [get_pins housekeeping/mgmt_gpio_in[33]]
+set_false_path -from [get_ports mprj_io[34]] -through [get_pins housekeeping/mgmt_gpio_in[34]]
+set_false_path -from [get_ports mprj_io[35]] -through [get_pins housekeeping/mgmt_gpio_in[35]]
+set_false_path -from [get_ports mprj_io[36]] -through [get_pins housekeeping/mgmt_gpio_in[36]]
+set_false_path -from [get_ports mprj_io[37]] -through [get_pins housekeeping/mgmt_gpio_in[37]]
+
+set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_out[*]]
+set_false_path -from [get_ports mprj_io[*]] -through [get_pins housekeeping/mgmt_gpio_oeb[*]]
+set_false_path -from [get_ports gpio]
+
+#### LA Input to wb_host are false path
+set_false_path -through [get_pins mprj/u_wb_host/la_data_in[*] ]
+
+### These reset has reset synchronozation
+set_false_path -through [get_pins mprj/u_uart_i2c_usb_spi/i2c_rstn ]
+set_false_path -through [get_pins mprj/u_uart_i2c_usb_spi/spi_rstn ]
+set_false_path -through [get_pins mprj/u_uart_i2c_usb_spi/usb_rstn ]
+set_false_path -through [get_pins mprj/u_uart_i2c_usb_spi/uart_rstn[*] ]
+
+
+
+# add loads for output ports (pads)
+set min_cap 5
+set max_cap 10
+puts "\[INFO\]: Cap load range: $min_cap : $max_cap"
+# set_load 10 [all_outputs]
+set_load -min $min_cap [all_outputs] 
+set_load -max $max_cap [all_outputs] 
+
+#add input transition for the inputs ports (pads)
+# set_input_transition 2 [all_inputs]
+#add exception for power pads as 2ns on them results in max_tran violations (false viol)
+# set_input_transition 2 [remove_from_collection [all_inputs] [get_ports v*]] 
+# remove_from_collection is not supported in PT read_sdc ^
+# set_input_transition 2 [all_inputs] 
+# set_input_transition 0 [get_ports v*]
+
+set min_in_tran 1
+set max_in_tran 4
+puts "\[INFO\]: Input transition range: $min_in_tran : $max_in_tran"
+set_input_transition -min $min_in_tran [all_inputs] 
+set_input_transition -min 0 [get_ports v*]
+set_input_transition -max $max_in_tran [all_inputs]
+set_input_transition -max 0 [get_ports v*]
+
+# check ocv table (not provided) -- maybe try 8% 
+set derate 0.0375
+puts "\[INFO\]: Setting derate factor to: [expr $derate * 100] %"
+set_timing_derate -early [expr 1-$derate]
+set_timing_derate -late [expr 1+$derate]
+
+# add max_tran constraint as the default max_tran of the ss hd SCL is 10 so the violations are not caught in ss corners
+# apply the constraint to hd cells at the ss corner only
+# if {$::env(PROC_CORNER) == "s"} {
+#    set max_tran 1.5
+#    set_max_transition $max_tran [get_pins -of_objects [get_cells -filter {ref_name=~sky130_fd_sc_hd*}]]
+#    set_max_transition $max_tran [get_pins -of_objects [get_cells */* -filter {ref_name=~sky130_fd_sc_hd*}]]
+#    set_max_transition $max_tran [get_pins -of_objects [get_cells */*/* -filter {ref_name=~sky130_fd_sc_hd*}]]
+#    puts "\[INFO\]: Setting maximum transition of HD cells in slow process corner to: $max_tran"
+# }
+# -filter not supported in PT read_sdc ^
diff --git a/sdc/dg_pll.sdc b/sdc/dg_pll.sdc
new file mode 100644
index 0000000..ee6b582
--- /dev/null
+++ b/sdc/dg_pll.sdc
@@ -0,0 +1,61 @@
+###############################################################################
+# Created by write_sdc
+# Tue Nov 22 06:29:19 2022
+###############################################################################
+current_design dg_pll
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name pll_control_clock -period 6.6667 [get_pins {ringosc.ibufp01/Y}]
+set_clock_transition 0.1500 [get_clocks {pll_control_clock}]
+set_clock_uncertainty -setup 0.5000 pll_control_clock
+set_clock_uncertainty -hold 0.2500 pll_control_clock
+set_propagated_clock [get_clocks {pll_control_clock}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {clockp[1]}]
+set_load -pin_load 0.0334 [get_ports {clockp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dco}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {enable}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {osc}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetb}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/digital_pll.sdc b/sdc/digital_pll.sdc
new file mode 100644
index 0000000..d56c67f
--- /dev/null
+++ b/sdc/digital_pll.sdc
@@ -0,0 +1,97 @@
+###############################################################################
+# Created by write_sdc
+# Fri Sep 16 17:32:50 2022
+###############################################################################
+current_design digital_pll
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name pll_control_clock -period 6.6667 [get_pins {ringosc.ibufp01/Y}]
+set_clock_transition 0.1500 [get_clocks {pll_control_clock}]
+set_clock_uncertainty 0.2500 pll_control_clock
+set_propagated_clock [get_clocks {pll_control_clock}]
+set_input_delay 2.0000 -add_delay [get_ports {dco}]
+set_input_delay 2.0000 -add_delay [get_ports {div[0]}]
+set_input_delay 2.0000 -add_delay [get_ports {div[1]}]
+set_input_delay 2.0000 -add_delay [get_ports {div[2]}]
+set_input_delay 2.0000 -add_delay [get_ports {div[3]}]
+set_input_delay 2.0000 -add_delay [get_ports {div[4]}]
+set_input_delay 2.0000 -add_delay [get_ports {enable}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[0]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[10]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[11]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[12]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[13]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[14]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[15]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[16]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[17]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[18]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[19]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[1]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[20]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[21]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[22]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[23]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[24]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[25]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[2]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[3]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[4]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[5]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[6]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[7]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[8]}]
+set_input_delay 2.0000 -add_delay [get_ports {ext_trim[9]}]
+set_input_delay 2.0000 -add_delay [get_ports {osc}]
+set_input_delay 2.0000 -add_delay [get_ports {resetb}]
+set_output_delay 2.0000 -add_delay [get_ports {clockp[0]}]
+set_output_delay 2.0000 -add_delay [get_ports {clockp[1]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {clockp[1]}]
+set_load -pin_load 0.0334 [get_ports {clockp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dco}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {enable}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {osc}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetb}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/fpu_wrapper.sdc b/sdc/fpu_wrapper.sdc
new file mode 100644
index 0000000..d8cab24
--- /dev/null
+++ b/sdc/fpu_wrapper.sdc
@@ -0,0 +1,271 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 08:53:56 2022
+###############################################################################
+current_design fpu_wrapper
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {cfg_cska[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {cfg_cska[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_addr[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_cmd}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_cmd}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_req}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_req}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[10]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[11]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[12]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[13]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[14]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[15]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[16]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[17]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[18]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[19]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[20]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[21]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[22]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[23]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[24]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[25]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[26]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[27]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[28]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[29]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[30]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[31]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[5]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[6]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[7]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[8]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_wdata[9]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_width[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_width[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_width[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_width[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {rst_n}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {rst_n}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {wbd_clk_int}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {wbd_clk_int}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_req_ack}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_resp[0]}]
+set_output_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {dmem_resp[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {dmem_resp[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -rise -max -add_delay [get_ports {wbd_clk_out}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -fall -max -add_delay [get_ports {wbd_clk_out}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_out}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {dmem_resp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem_width[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/peri_top.sdc b/sdc/peri_top.sdc
new file mode 100644
index 0000000..9c549e3
--- /dev/null
+++ b/sdc/peri_top.sdc
@@ -0,0 +1,401 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 10:44:09 2022
+###############################################################################
+current_design peri_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+create_clock -name rtc_clk -period 100.0000 [get_ports {rtc_clk}]
+set_clock_transition 0.1500 [get_clocks {rtc_clk}]
+set_clock_uncertainty 0.2500 rtc_clk
+set_propagated_clock [get_clocks {rtc_clk}]
+set_clock_groups -name clock_group -logically_exclusive \
+ -group [get_clocks {mclk}]\
+ -group [get_clocks {rtc_clk}] -comment {Async Clock group}
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[10]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[9]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_cs}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_cs}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wr}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wr}]
+set_input_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {s_reset_n}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {s_reset_n}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac0_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac0_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac1_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac1_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac2_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac2_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {cfg_dac3_mux_sel[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {cfg_dac3_mux_sel[7]}]
+set_output_delay 1.0000 -clock [get_clocks {rtc_clk}] -min -add_delay [get_ports {inc_date_d}]
+set_output_delay 6.0000 -clock [get_clocks {rtc_clk}] -max -add_delay [get_ports {inc_date_d}]
+set_output_delay 1.0000 -clock [get_clocks {rtc_clk}] -min -add_delay [get_ports {inc_time_s}]
+set_output_delay 6.0000 -clock [get_clocks {rtc_clk}] -max -add_delay [get_ports {inc_time_s}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_ack}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_ack}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {rtc_clk}] -min -add_delay [get_ports {rtc_intr}]
+set_output_delay 6.0000 -clock [get_clocks {rtc_clk}] -max -add_delay [get_ports {rtc_intr}]
+set_max_delay\
+    -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+    -from [get_ports {wbd_clk_int}]\
+    -to [get_ports {wbd_clk_peri}] 3.5000
+set_max_delay\
+    -to [get_ports {wbd_clk_peri}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {inc_date_d}]
+set_load -pin_load 0.0334 [get_ports {inc_time_s}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {rtc_intr}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_peri}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac0_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac1_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac2_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dac3_mux_sel[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_peri[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_peri[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]
diff --git a/sdc/pinmux.sdc b/sdc/pinmux.sdc
new file mode 100644
index 0000000..79cbc0d
--- /dev/null
+++ b/sdc/pinmux.sdc
@@ -0,0 +1,520 @@
+###############################################################################
+# Created by write_sdc
+# Sun Aug 14 14:58:56 2022
+###############################################################################
+current_design pinmux
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty -setup 0.5000 mclk
+set_clock_uncertainty -hold 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {h_reset_n}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_cs}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_cs}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wr}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wr}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {qspim_rst_n}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {qspim_rst_n}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_ack}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_ack}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[9]}]
+set_max_delay\
+    -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+    -from [get_ports {wbd_clk_int}]\
+    -to [get_ports {wbd_clk_pinmux}] 3.5000
+set_max_delay\
+    -to [get_ports {wbd_clk_pinmux}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {cpu_intf_rst_n}]
+set_load -pin_load 0.0334 [get_ports {i2cm_clk_i}]
+set_load -pin_load 0.0334 [get_ports {i2cm_data_i}]
+set_load -pin_load 0.0334 [get_ports {i2cm_rst_n}]
+set_load -pin_load 0.0334 [get_ports {pulse1m_mclk}]
+set_load -pin_load 0.0334 [get_ports {qspim_rst_n}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {soft_irq}]
+set_load -pin_load 0.0334 [get_ports {spim_mosi}]
+set_load -pin_load 0.0334 [get_ports {spis_mosi}]
+set_load -pin_load 0.0334 [get_ports {spis_sck}]
+set_load -pin_load 0.0334 [get_ports {spis_ssn}]
+set_load -pin_load 0.0334 [get_ports {sspim_rst_n}]
+set_load -pin_load 0.0334 [get_ports {uartm_rxd}]
+set_load -pin_load 0.0334 [get_ports {usb_dn_i}]
+set_load -pin_load 0.0334 [get_ports {usb_dp_i}]
+set_load -pin_load 0.0334 [get_ports {usb_rst_n}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_pinmux}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[0]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[1]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[0]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[37]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[36]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[35]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[34]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[33]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[32]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[31]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[30]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[29]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[28]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[27]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[26]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[25]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[24]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[23]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[22]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[21]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[20]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[19]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[18]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[17]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[16]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[15]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[14]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[13]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[12]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[11]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[10]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[9]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[8]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[7]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[6]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[5]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[4]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[3]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[2]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[1]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[0]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[15]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[14]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[13]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[12]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[11]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[10]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[9]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[8]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[7]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[6]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[5]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[4]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[3]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[2]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[1]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[0]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[3]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[2]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[1]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_rst_n[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_rst_n[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_rxd[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_rxd[0]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_clk_mon}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {h_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_clk_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_clk_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_sck}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_miso}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_sck}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spis_miso}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uartm_txd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_dn_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_dp_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_txd[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_txd[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/sdc/pinmux_top.sdc b/sdc/pinmux_top.sdc
new file mode 100644
index 0000000..4d80b95
--- /dev/null
+++ b/sdc/pinmux_top.sdc
@@ -0,0 +1,783 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 06:19:01 2022
+###############################################################################
+current_design pinmux_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty -setup 0.5000 mclk
+set_clock_uncertainty -hold 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+create_clock -name user_clock1 -period 10.0000 [get_ports {user_clock1}]
+set_clock_transition 0.1500 [get_clocks {user_clock1}]
+set_clock_uncertainty -setup 0.5000 user_clock1
+set_clock_uncertainty -hold 0.2500 user_clock1
+set_propagated_clock [get_clocks {user_clock1}]
+create_clock -name user_clock2 -period 10.0000 [get_ports {user_clock2}]
+set_clock_transition 0.1500 [get_clocks {user_clock2}]
+set_clock_uncertainty -setup 0.5000 user_clock2
+set_clock_uncertainty -hold 0.2500 user_clock2
+set_propagated_clock [get_clocks {user_clock2}]
+create_clock -name int_pll_clock -period 5.0000 
+set_clock_uncertainty -setup 0.5000 int_pll_clock
+set_clock_uncertainty -hold 0.2500 int_pll_clock
+create_clock -name rtc_ref_clk -period 50.0000 [get_pins {u_glbl_reg.u_rtc_ref_clkbuf.u_buf/X}]
+set_clock_transition 0.1500 [get_clocks {rtc_ref_clk}]
+set_clock_uncertainty -setup 0.5000 rtc_ref_clk
+set_clock_uncertainty -hold 0.2500 rtc_ref_clk
+set_propagated_clock [get_clocks {rtc_ref_clk}]
+create_clock -name rtc_clk -period 50.0000 [get_pins {u_glbl_reg.u_clkbuf_rtc.u_buf/X}]
+set_clock_transition 0.1500 [get_clocks {rtc_clk}]
+set_clock_uncertainty -setup 0.5000 rtc_clk
+set_clock_uncertainty -hold 0.2500 rtc_clk
+set_propagated_clock [get_clocks {rtc_clk}]
+create_clock -name usb_ref_clk -period 5.0000 [get_pins {u_glbl_reg.u_usb_ref_clkbuf.u_buf/X}]
+set_clock_transition 0.1500 [get_clocks {usb_ref_clk}]
+set_clock_uncertainty -setup 0.5000 usb_ref_clk
+set_clock_uncertainty -hold 0.2500 usb_ref_clk
+set_propagated_clock [get_clocks {usb_ref_clk}]
+create_clock -name dbg_ref_clk -period 10.0000 [get_pins {u_glbl_reg.u_clkbuf_dbg_ref.u_buf/X}]
+set_clock_transition 0.1500 [get_clocks {dbg_ref_clk}]
+set_clock_uncertainty -setup 0.5000 dbg_ref_clk
+set_clock_uncertainty -hold 0.2500 dbg_ref_clk
+set_propagated_clock [get_clocks {dbg_ref_clk}]
+set_clock_groups -name clock_group -logically_exclusive \
+ -group [get_clocks {dbg_ref_clk}]\
+ -group [get_clocks {int_pll_clock}]\
+ -group [get_clocks {mclk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {rtc_ref_clk}]\
+ -group [get_clocks {usb_ref_clk}]\
+ -group [get_clocks {user_clock1}]\
+ -group [get_clocks {user_clock2}] -comment {Async Clock group}
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[10]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[9]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_cs}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_cs}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wr}]
+set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wr}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {qspim_rst_n}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {qspim_rst_n}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_ack}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_ack}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[9]}]
+set_max_delay\
+    -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+    -from [get_ports {wbd_clk_int}]\
+    -to [get_ports {wbd_clk_pinmux}] 3.5000
+set_max_delay\
+    -to [get_ports {wbd_clk_pinmux}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {cfg_dco_mode}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_enb}]
+set_load -pin_load 0.0334 [get_ports {cpu_intf_rst_n}]
+set_load -pin_load 0.0334 [get_ports {i2cm_clk_i}]
+set_load -pin_load 0.0334 [get_ports {i2cm_data_i}]
+set_load -pin_load 0.0334 [get_ports {i2cm_rst_n}]
+set_load -pin_load 0.0334 [get_ports {pll_ref_clk}]
+set_load -pin_load 0.0334 [get_ports {pulse1m_mclk}]
+set_load -pin_load 0.0334 [get_ports {qspim_rst_n}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_cs}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wr}]
+set_load -pin_load 0.0334 [get_ports {rtc_clk}]
+set_load -pin_load 0.0334 [get_ports {soft_irq}]
+set_load -pin_load 0.0334 [get_ports {spim_mosi}]
+set_load -pin_load 0.0334 [get_ports {spis_mosi}]
+set_load -pin_load 0.0334 [get_ports {spis_sck}]
+set_load -pin_load 0.0334 [get_ports {spis_ssn}]
+set_load -pin_load 0.0334 [get_ports {sspim_rst_n}]
+set_load -pin_load 0.0334 [get_ports {uartm_rxd}]
+set_load -pin_load 0.0334 [get_ports {usb_clk}]
+set_load -pin_load 0.0334 [get_ports {usb_dn_i}]
+set_load -pin_load 0.0334 [get_ports {usb_dp_i}]
+set_load -pin_load 0.0334 [get_ports {usb_rst_n}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_pinmux}]
+set_load -pin_load 0.0334 [get_ports {xtal_clk}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[25]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[24]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[23]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[22]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[21]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[20]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[19]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[18]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[17]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[16]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_dc_trim[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_pll_fed_div[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[0]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[3]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[2]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[1]}]
+set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[0]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[37]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[36]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[35]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[34]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[33]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[32]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[31]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[30]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[29]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[28]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[27]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[26]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[25]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[24]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[23]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[22]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[21]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[20]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[19]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[18]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[17]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[16]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[15]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[14]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[13]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[12]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[11]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[10]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[9]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[8]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[7]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[6]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[5]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[4]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[3]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[2]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[1]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_oen[0]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {digital_io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[31]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[30]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[29]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[28]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[27]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[26]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[25]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[24]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[23]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[22]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[21]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[20]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[19]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[18]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[17]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[16]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[15]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[14]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[13]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[12]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[11]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[10]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[9]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[8]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[7]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[6]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[5]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[4]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[3]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[2]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[1]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[0]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {pinmux_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_addr[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_be[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_peri_wdata[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[3]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[2]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[1]}]
+set_load -pin_load 0.0334 [get_ports {sflash_di[0]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[31]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[30]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[29]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[28]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[27]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[26]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[25]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[24]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[23]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[22]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[21]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[20]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[19]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[18]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[17]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[16]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[15]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[14]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[13]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[12]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[11]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[10]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[9]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[8]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[7]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[6]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[5]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[4]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[3]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[2]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[1]}]
+set_load -pin_load 0.0334 [get_ports {strap_sticky[0]}]
+set_load -pin_load 0.0334 [get_ports {strap_uartm[1]}]
+set_load -pin_load 0.0334 [get_ports {strap_uartm[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_rst_n[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_rst_n[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_rxd[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_rxd[0]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_strap_pad_ctrl}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cpu_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {e_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_clk_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_clk_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {int_pll_clock}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {p_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_ack}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s_reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_sck}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_miso}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_sck}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spis_miso}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uartm_txd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_dn_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_dp_o}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_intr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_oen}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock1}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_peri_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {system_strap[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_txd[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_txd[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_pinmux[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/qspim_top.sdc b/sdc/qspim_top.sdc
new file mode 100644
index 0000000..7e6c99e
--- /dev/null
+++ b/sdc/qspim_top.sdc
@@ -0,0 +1,532 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 07:01:53 2022
+###############################################################################
+current_design qspim_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_transition 0.1500 [get_clocks {mclk}]
+set_clock_uncertainty -setup 0.5000 mclk
+set_clock_uncertainty -hold 0.2500 mclk
+set_propagated_clock [get_clocks {mclk}]
+create_generated_clock -name spiclk -add -source [get_ports {mclk}] -master_clock [get_clocks {mclk}] -divide_by 2 -comment {SPI Clock Out} [get_ports {spi_clk}]
+set_clock_transition 0.1500 [get_clocks {spiclk}]
+set_clock_uncertainty -setup 0.5000 spiclk
+set_clock_uncertainty -hold 0.2500 spiclk
+set_propagated_clock [get_clocks {spiclk}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {rst_n}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {rst_n}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[0]}]
+set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[0]}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[1]}]
+set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[1]}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[2]}]
+set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[2]}]
+set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[3]}]
+set_input_delay 5.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[3]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[0]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[10]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[11]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[12]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[13]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[14]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[15]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[16]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[17]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[18]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[19]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[1]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[20]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[21]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[22]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[23]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[24]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[25]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[26]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[27]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[28]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[29]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[2]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[30]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[31]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[3]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[4]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[5]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[6]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[7]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[8]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_adr_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_adr_i[9]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[0]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[10]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[11]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[12]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[13]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[14]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[15]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[16]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[17]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[18]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[19]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[1]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[20]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[21]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[22]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[23]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[24]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[25]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[26]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[27]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[28]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[29]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[2]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[30]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[31]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[3]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[4]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[5]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[6]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[7]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[8]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_i[9]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[0]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[1]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[2]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_sel_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_sel_i[3]}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_stb_i}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_stb_i}]
+set_input_delay 3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_we_i}]
+set_input_delay 6.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_we_i}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[0]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[0]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[1]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[1]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[2]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[2]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn[3]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn[3]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[0]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[0]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[1]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[1]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[2]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[2]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_oen[3]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_oen[3]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[0]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[0]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[1]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[1]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[2]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[2]}]
+set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[3]}]
+set_output_delay 4.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[3]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_ack_o}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_ack_o}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[0]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[0]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[10]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[10]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[11]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[11]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[12]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[12]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[13]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[13]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[14]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[14]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[15]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[15]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[16]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[16]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[17]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[17]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[18]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[18]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[19]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[19]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[1]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[1]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[20]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[20]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[21]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[21]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[22]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[22]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[23]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[23]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[24]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[24]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[25]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[25]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[26]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[26]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[27]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[27]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[28]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[28]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[29]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[29]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[2]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[2]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[30]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[30]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[31]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[31]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[3]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[3]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[4]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[4]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[5]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[5]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[6]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[6]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[7]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[7]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[8]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[8]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_dat_o[9]}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_dat_o[9]}]
+set_output_delay -2.7500 -clock [get_clocks {mclk}] -min -add_delay [get_ports {wbd_err_o}]
+set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {wbd_err_o}]
+set_max_delay\
+    -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+    -from [get_ports {wbd_clk_int}]\
+    -to [get_ports {wbd_clk_spi}] 3.5000
+set_max_delay\
+    -to [get_ports {spi_debug[0]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[10]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[11]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[12]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[13]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[14]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[15]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[16]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[17]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[18]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[19]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[1]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[20]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[21]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[22]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[23]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[24]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[25]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[26]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[27]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[28]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[29]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[2]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[30]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[31]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[3]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[4]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[5]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[6]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[7]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[8]}] 10.0000
+set_max_delay\
+    -to [get_ports {spi_debug[9]}] 10.0000
+set_max_delay\
+    -to [get_ports {wbd_clk_spi}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {spi_clk}]
+set_load -pin_load 0.0334 [get_ports {wbd_ack_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_spi}]
+set_load -pin_load 0.0334 [get_ports {wbd_err_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_lack_o}]
+set_load -pin_load 0.0334 [get_ports {spi_csn[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_csn[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_csn[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_csn[0]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_oen[0]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[3]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[2]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[1]}]
+set_load -pin_load 0.0334 [get_ports {spi_sdo[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dat_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_init_bypass}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_pre_sram}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sram}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bry_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_sdi[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_flash[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_flash[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_bl_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[3]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/uart_i2c_usb_spi_top.sdc b/sdc/uart_i2c_usb_spi_top.sdc
new file mode 100644
index 0000000..fa4c4a4
--- /dev/null
+++ b/sdc/uart_i2c_usb_spi_top.sdc
@@ -0,0 +1,425 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 07:47:01 2022
+###############################################################################
+current_design uart_i2c_usb_spi_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name app_clk -period 10.0000 [get_ports {app_clk}]
+set_clock_transition 0.1500 [get_clocks {app_clk}]
+set_clock_uncertainty -setup 0.5000 app_clk
+set_clock_uncertainty -hold 0.2500 app_clk
+set_propagated_clock [get_clocks {app_clk}]
+create_clock -name uart0_baud_clk -period 100.0000 [get_pins {u_uart0_core.u_lineclk_buf.genblk1.u_mux/X}]
+set_clock_transition 0.1500 [get_clocks {uart0_baud_clk}]
+set_clock_uncertainty -setup 0.5000 uart0_baud_clk
+set_clock_uncertainty -hold 0.2500 uart0_baud_clk
+set_propagated_clock [get_clocks {uart0_baud_clk}]
+create_clock -name uart1_baud_clk -period 100.0000 [get_pins {u_uart1_core.u_lineclk_buf.genblk1.u_mux/X}]
+set_clock_transition 0.1500 [get_clocks {uart1_baud_clk}]
+set_clock_uncertainty -setup 0.5000 uart1_baud_clk
+set_clock_uncertainty -hold 0.2500 uart1_baud_clk
+set_propagated_clock [get_clocks {uart1_baud_clk}]
+create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}]
+set_clock_transition 0.1500 [get_clocks {usb_clk}]
+set_clock_uncertainty -setup 0.5000 usb_clk
+set_clock_uncertainty -hold 0.2500 usb_clk
+set_propagated_clock [get_clocks {usb_clk}]
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {app_clk}]\
+ -group [get_clocks {uart0_baud_clk}]\
+ -group [get_clocks {uart1_baud_clk}]\
+ -group [get_clocks {usb_clk}] -comment {Async Clock group}
+set_input_delay 1.5000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {i2c_rstn}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {i2c_rstn}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 5.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[0]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[0]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[1]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[1]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[2]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[2]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[3]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[3]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_cs}]
+set_input_delay 5.7500 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_cs}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wr}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wr}]
+set_input_delay 1.5000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {uart_rstn[0]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {uart_rstn[0]}]
+set_input_delay 1.5000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {uart_rstn[1]}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {uart_rstn[1]}]
+set_input_delay 1.5000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {usb_rstn}]
+set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {usb_rstn}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay -2.7500 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay 1.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[9]}]
+set_multicycle_path -hold\
+    -from [list [get_ports {reg_addr[0]}]\
+           [get_ports {reg_addr[1]}]\
+           [get_ports {reg_addr[2]}]\
+           [get_ports {reg_addr[3]}]\
+           [get_ports {reg_addr[4]}]\
+           [get_ports {reg_addr[5]}]\
+           [get_ports {reg_addr[6]}]\
+           [get_ports {reg_addr[7]}]\
+           [get_ports {reg_addr[8]}]]\
+    -to [list [get_ports {reg_ack}]\
+           [get_ports {reg_rdata[0]}]\
+           [get_ports {reg_rdata[10]}]\
+           [get_ports {reg_rdata[11]}]\
+           [get_ports {reg_rdata[12]}]\
+           [get_ports {reg_rdata[13]}]\
+           [get_ports {reg_rdata[14]}]\
+           [get_ports {reg_rdata[15]}]\
+           [get_ports {reg_rdata[16]}]\
+           [get_ports {reg_rdata[17]}]\
+           [get_ports {reg_rdata[18]}]\
+           [get_ports {reg_rdata[19]}]\
+           [get_ports {reg_rdata[1]}]\
+           [get_ports {reg_rdata[20]}]\
+           [get_ports {reg_rdata[21]}]\
+           [get_ports {reg_rdata[22]}]\
+           [get_ports {reg_rdata[23]}]\
+           [get_ports {reg_rdata[24]}]\
+           [get_ports {reg_rdata[25]}]\
+           [get_ports {reg_rdata[26]}]\
+           [get_ports {reg_rdata[27]}]\
+           [get_ports {reg_rdata[28]}]\
+           [get_ports {reg_rdata[29]}]\
+           [get_ports {reg_rdata[2]}]\
+           [get_ports {reg_rdata[30]}]\
+           [get_ports {reg_rdata[31]}]\
+           [get_ports {reg_rdata[3]}]\
+           [get_ports {reg_rdata[4]}]\
+           [get_ports {reg_rdata[5]}]\
+           [get_ports {reg_rdata[6]}]\
+           [get_ports {reg_rdata[7]}]\
+           [get_ports {reg_rdata[8]}]\
+           [get_ports {reg_rdata[9]}]] 1
+set_multicycle_path -setup\
+    -from [list [get_ports {reg_addr[0]}]\
+           [get_ports {reg_addr[1]}]\
+           [get_ports {reg_addr[2]}]\
+           [get_ports {reg_addr[3]}]\
+           [get_ports {reg_addr[4]}]\
+           [get_ports {reg_addr[5]}]\
+           [get_ports {reg_addr[6]}]\
+           [get_ports {reg_addr[7]}]\
+           [get_ports {reg_addr[8]}]]\
+    -to [list [get_ports {reg_ack}]\
+           [get_ports {reg_rdata[0]}]\
+           [get_ports {reg_rdata[10]}]\
+           [get_ports {reg_rdata[11]}]\
+           [get_ports {reg_rdata[12]}]\
+           [get_ports {reg_rdata[13]}]\
+           [get_ports {reg_rdata[14]}]\
+           [get_ports {reg_rdata[15]}]\
+           [get_ports {reg_rdata[16]}]\
+           [get_ports {reg_rdata[17]}]\
+           [get_ports {reg_rdata[18]}]\
+           [get_ports {reg_rdata[19]}]\
+           [get_ports {reg_rdata[1]}]\
+           [get_ports {reg_rdata[20]}]\
+           [get_ports {reg_rdata[21]}]\
+           [get_ports {reg_rdata[22]}]\
+           [get_ports {reg_rdata[23]}]\
+           [get_ports {reg_rdata[24]}]\
+           [get_ports {reg_rdata[25]}]\
+           [get_ports {reg_rdata[26]}]\
+           [get_ports {reg_rdata[27]}]\
+           [get_ports {reg_rdata[28]}]\
+           [get_ports {reg_rdata[29]}]\
+           [get_ports {reg_rdata[2]}]\
+           [get_ports {reg_rdata[30]}]\
+           [get_ports {reg_rdata[31]}]\
+           [get_ports {reg_rdata[3]}]\
+           [get_ports {reg_rdata[4]}]\
+           [get_ports {reg_rdata[5]}]\
+           [get_ports {reg_rdata[6]}]\
+           [get_ports {reg_rdata[7]}]\
+           [get_ports {reg_rdata[8]}]\
+           [get_ports {reg_rdata[9]}]] 2
+set_max_delay\
+    -from [get_ports {wbd_clk_int}] 5.0000
+set_max_delay\
+    -from [get_ports {wbd_clk_int}]\
+    -to [get_ports {wbd_clk_uart}] 5.0000
+set_max_delay\
+    -to [get_ports {wbd_clk_uart}] 5.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {i2cm_intr_o}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {scl_pad_o}]
+set_load -pin_load 0.0334 [get_ports {scl_pad_oen_o}]
+set_load -pin_load 0.0334 [get_ports {sda_pad_o}]
+set_load -pin_load 0.0334 [get_ports {sda_padoen_o}]
+set_load -pin_load 0.0334 [get_ports {sspim_sck}]
+set_load -pin_load 0.0334 [get_ports {sspim_so}]
+set_load -pin_load 0.0334 [get_ports {usb_intr_o}]
+set_load -pin_load 0.0334 [get_ports {usb_out_dn}]
+set_load -pin_load 0.0334 [get_ports {usb_out_dp}]
+set_load -pin_load 0.0334 [get_ports {usb_out_tx_oen}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_uart}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {sspim_ssn[3]}]
+set_load -pin_load 0.0334 [get_ports {sspim_ssn[2]}]
+set_load -pin_load 0.0334 [get_ports {sspim_ssn[1]}]
+set_load -pin_load 0.0334 [get_ports {sspim_ssn[0]}]
+set_load -pin_load 0.0334 [get_ports {uart_txd[1]}]
+set_load -pin_load 0.0334 [get_ports {uart_txd[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {app_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2c_rstn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {scl_pad_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sda_pad_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spi_rstn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sspim_si}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_in_dn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_in_dp}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_rstn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rstn[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rstn[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rxd[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rxd[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/user_project_wrapper.sdc b/sdc/user_project_wrapper.sdc
new file mode 100644
index 0000000..b2b6e86
--- /dev/null
+++ b/sdc/user_project_wrapper.sdc
@@ -0,0 +1,987 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 15:27:39 2022
+###############################################################################
+current_design user_project_wrapper
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name user_clock2 -period 100.0000 [get_ports {user_clock2}]
+set_propagated_clock [get_clocks {user_clock2}]
+create_clock -name wbm_clk_i -period 10.0000 [get_ports {wb_clk_i}]
+set_propagated_clock [get_clocks {wbm_clk_i}]
+create_clock -name wbs_clk_i -period 10.0000 [get_pins {u_wb_host/wbs_clk_out}]
+set_propagated_clock [get_clocks {wbs_clk_i}]
+create_clock -name cpu_clk -period 20.0000 [get_pins {u_wb_host/cpu_clk}]
+set_propagated_clock [get_clocks {cpu_clk}]
+create_clock -name rtc_clk -period 50.0000 
+create_clock -name usb_clk -period 20.0000 
+create_clock -name line_clk -period 100.0000 
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -rise_to [get_clocks {cpu_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {cpu_clk}] -fall_to [get_clocks {cpu_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}]  -setup 0.2000
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {cpu_clk}]\
+ -group [get_clocks {line_clk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {usb_clk}]\
+ -group [get_clocks {wbm_clk_i}]\
+ -group [get_clocks {wbs_clk_i}] -comment {Async Clock group}
+set_input_delay 2.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wb_rst_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[0]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[0]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[10]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[10]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[11]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[11]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[12]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[12]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[13]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[13]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[14]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[14]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[15]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[15]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[16]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[16]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[17]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[17]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[18]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[18]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[19]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[19]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[1]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[1]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[20]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[20]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[21]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[21]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[22]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[22]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[23]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[23]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[24]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[24]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[25]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[25]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[26]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[26]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[27]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[27]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[28]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[28]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[29]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[29]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[2]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[2]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[30]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[30]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[31]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[31]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[3]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[3]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[4]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[4]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[5]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[5]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[6]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[6]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[7]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[7]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[8]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[8]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_adr_i[9]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_adr_i[9]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_sel_i[0]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_sel_i[0]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_sel_i[1]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_sel_i[1]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_sel_i[2]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_sel_i[2]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_sel_i[3]}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_sel_i[3]}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_stb_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_stb_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_we_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_we_i}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_ack_o}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_ack_o}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbs_dat_o[9]}]
+set_output_delay 4.5000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbs_dat_o[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {wbs_ack_o}]
+set_load -pin_load 0.0334 [get_ports {analog_io[28]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[27]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[26]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[25]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[24]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[23]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[22]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[21]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[20]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[19]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[18]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[17]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[16]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[15]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[14]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[13]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[12]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[11]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[10]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[9]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[8]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[7]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[6]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[5]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[4]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[3]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[2]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[1]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[0]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
+set_load -pin_load 0.0334 [get_ports {io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[127]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[126]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[125]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[124]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[123]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[122]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[121]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[120]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[119]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[118]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[117]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[116]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[115]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[114]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[113]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[112]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[111]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[110]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[109]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[108]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[107]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[106]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[105]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[104]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[103]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[102]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[101]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[100]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[99]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[98]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[97]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[96]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[95]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[94]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[93]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[92]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[91]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[90]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[89]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[88]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[87]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[86]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[85]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[84]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[83]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[82]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[81]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[80]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[79]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[78]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[77]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[76]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[75]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[74]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[73]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[72]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[71]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[70]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[69]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[68]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[67]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[66]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[65]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[64]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[63]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[62]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[61]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[60]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[59]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[58]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[57]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[56]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[55]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[54]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[53]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[52]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[51]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[50]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[49]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[48]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[47]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[46]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[45]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[44]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[43]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[42]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[41]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[40]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[39]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[38]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[37]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[36]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[35]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[34]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[33]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[32]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[31]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[30]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[29]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[28]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[27]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[26]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[25]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[24]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[23]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[22]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[21]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[20]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[19]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[18]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[17]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[16]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[15]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[14]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[13]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[12]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[11]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[10]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[9]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[8]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[7]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[6]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[5]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[4]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[3]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[2]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[1]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[0]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[123]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[122]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[121]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[120]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[119]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[118]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[117]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[116]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[115]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[114]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[113]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[112]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[111]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[110]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[109]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[108]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[107]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[106]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[105]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[104]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[103]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[102]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[101]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[100]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[99]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[98]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[97]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[96]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[95]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[94]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[93]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[92]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[91]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[90]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[89]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[88]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[87]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[86]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[85]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[84]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[83]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[82]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[81]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[80]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[8]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[127]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[79]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[78]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[76]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[75]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[74]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[73]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[72]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[71]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[70]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[69]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[67]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[44]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[26]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[0]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[1]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[2]}]
+set_case_analysis 1 [get_pins {u_intercon/cfg_cska_wi[3]}]
+set_case_analysis 0 [get_pins {u_pinmux/cfg_cska_pinmux[0]}]
+set_case_analysis 1 [get_pins {u_pinmux/cfg_cska_pinmux[1]}]
+set_case_analysis 1 [get_pins {u_pinmux/cfg_cska_pinmux[2]}]
+set_case_analysis 0 [get_pins {u_pinmux/cfg_cska_pinmux[3]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[0]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_sp_co[3]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_spi[0]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_spi[1]}]
+set_case_analysis 0 [get_pins {u_qspi_master/cfg_cska_spi[2]}]
+set_case_analysis 1 [get_pins {u_qspi_master/cfg_cska_spi[3]}]
+set_case_analysis 0 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[0]}]
+set_case_analysis 0 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[1]}]
+set_case_analysis 0 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[2]}]
+set_case_analysis 1 [get_pins {u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[0]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[1]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 1 [get_pins {u_wb_host/cfg_cska_wh[3]}]
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/sdc/wb_host.sdc b/sdc/wb_host.sdc
new file mode 100644
index 0000000..8a35241
--- /dev/null
+++ b/sdc/wb_host.sdc
@@ -0,0 +1,873 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 14:48:44 2022
+###############################################################################
+current_design wb_host
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wbm_clk_i -period 10.0000 [get_ports {wbm_clk_i}]
+set_clock_transition 0.1500 [get_clocks {wbm_clk_i}]
+set_clock_uncertainty -setup 0.5000 wbm_clk_i
+set_clock_uncertainty -hold 0.2500 wbm_clk_i
+set_propagated_clock [get_clocks {wbm_clk_i}]
+create_clock -name wbs_clk_i -period 10.0000 [get_ports {wbs_clk_i}]
+set_clock_transition 0.1500 [get_clocks {wbs_clk_i}]
+set_clock_uncertainty -setup 0.5000 wbs_clk_i
+set_clock_uncertainty -hold 0.2500 wbs_clk_i
+set_propagated_clock [get_clocks {wbs_clk_i}]
+create_clock -name uart_clk -period 100.0000 [get_pins {u_uart2wb.u_core.u_uart_clk.genblk1.u_mux/X}]
+set_clock_transition 0.1500 [get_clocks {uart_clk}]
+set_clock_uncertainty -setup 0.5000 uart_clk
+set_clock_uncertainty -hold 0.2500 uart_clk
+set_propagated_clock [get_clocks {uart_clk}]
+create_clock -name int_pll_clock -period 10.0000 
+set_clock_uncertainty -setup 0.5000 int_pll_clock
+set_clock_uncertainty -hold 0.2500 int_pll_clock
+create_clock -name wbs_ref_clk -period 10.0000 
+set_clock_uncertainty -setup 0.5000 wbs_ref_clk
+set_clock_uncertainty -hold 0.2500 wbs_ref_clk
+create_clock -name cpu_ref_clk -period 10.0000 
+set_clock_uncertainty -setup 0.5000 cpu_ref_clk
+set_clock_uncertainty -hold 0.2500 cpu_ref_clk
+create_clock -name usb_ref_clk -period 10.0000 
+set_clock_uncertainty -setup 0.5000 usb_ref_clk
+set_clock_uncertainty -hold 0.2500 usb_ref_clk
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {cpu_ref_clk}]\
+ -group [get_clocks {int_pll_clock}]\
+ -group [get_clocks {uart_clk}]\
+ -group [get_clocks {usb_ref_clk}]\
+ -group [get_clocks {wbm_clk_i}]\
+ -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {wbs_ref_clk}] -comment {Async Clock group}
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_rst_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_rst_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_stb_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_stb_i}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_ack_i}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_i[9]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_ack_o}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_ack_o}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[0]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[0]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[10]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[10]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[11]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[11]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[12]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[12]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[13]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[13]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[14]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[14]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[15]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[15]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[16]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[16]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[17]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[17]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[18]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[18]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[19]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[19]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[1]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[1]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[20]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[20]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[21]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[21]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[22]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[22]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[23]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[23]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[24]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[24]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[25]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[25]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[26]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[26]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[27]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[27]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[28]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[28]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[29]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[29]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[2]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[2]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[30]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[30]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[31]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[31]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[3]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[3]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[4]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[4]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[5]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[5]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[6]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[6]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[7]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[7]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[8]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[8]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_dat_o[9]}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_dat_o[9]}]
+set_output_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_err_o}]
+set_output_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_err_o}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[0]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[0]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[10]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[10]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[11]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[11]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[12]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[12]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[13]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[13]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[14]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[14]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[15]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[15]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[16]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[16]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[17]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[17]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[18]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[18]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[19]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[19]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[1]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[1]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[20]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[20]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[21]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[21]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[22]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[22]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[23]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[23]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[24]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[24]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[25]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[25]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[26]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[26]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[27]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[27]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[28]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[28]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[29]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[29]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[2]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[2]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[30]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[30]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[31]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[31]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[3]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[3]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[4]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[4]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[5]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[5]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[6]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[6]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[7]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[7]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[8]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[8]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_adr_o[9]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_adr_o[9]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_dat_o[9]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_dat_o[9]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_sel_o[0]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_sel_o[0]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_sel_o[1]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_sel_o[1]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_sel_o[2]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_sel_o[2]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_sel_o[3]}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_sel_o[3]}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_stb_o}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_stb_o}]
+set_output_delay -1.7500 -clock [get_clocks {wbs_clk_i}] -min -add_delay [get_ports {wbs_we_o}]
+set_output_delay 3.0000 -clock [get_clocks {wbs_clk_i}] -max -add_delay [get_ports {wbs_we_o}]
+set_multicycle_path -hold\
+    -from [list [get_ports {wbm_adr_i[0]}]\
+           [get_ports {wbm_adr_i[10]}]\
+           [get_ports {wbm_adr_i[11]}]\
+           [get_ports {wbm_adr_i[12]}]\
+           [get_ports {wbm_adr_i[13]}]\
+           [get_ports {wbm_adr_i[14]}]\
+           [get_ports {wbm_adr_i[15]}]\
+           [get_ports {wbm_adr_i[16]}]\
+           [get_ports {wbm_adr_i[17]}]\
+           [get_ports {wbm_adr_i[18]}]\
+           [get_ports {wbm_adr_i[19]}]\
+           [get_ports {wbm_adr_i[1]}]\
+           [get_ports {wbm_adr_i[20]}]\
+           [get_ports {wbm_adr_i[21]}]\
+           [get_ports {wbm_adr_i[22]}]\
+           [get_ports {wbm_adr_i[23]}]\
+           [get_ports {wbm_adr_i[24]}]\
+           [get_ports {wbm_adr_i[25]}]\
+           [get_ports {wbm_adr_i[26]}]\
+           [get_ports {wbm_adr_i[27]}]\
+           [get_ports {wbm_adr_i[28]}]\
+           [get_ports {wbm_adr_i[29]}]\
+           [get_ports {wbm_adr_i[2]}]\
+           [get_ports {wbm_adr_i[30]}]\
+           [get_ports {wbm_adr_i[31]}]\
+           [get_ports {wbm_adr_i[3]}]\
+           [get_ports {wbm_adr_i[4]}]\
+           [get_ports {wbm_adr_i[5]}]\
+           [get_ports {wbm_adr_i[6]}]\
+           [get_ports {wbm_adr_i[7]}]\
+           [get_ports {wbm_adr_i[8]}]\
+           [get_ports {wbm_adr_i[9]}]\
+           [get_ports {wbm_cyc_i}]\
+           [get_ports {wbm_dat_i[0]}]\
+           [get_ports {wbm_dat_i[10]}]\
+           [get_ports {wbm_dat_i[11]}]\
+           [get_ports {wbm_dat_i[12]}]\
+           [get_ports {wbm_dat_i[13]}]\
+           [get_ports {wbm_dat_i[14]}]\
+           [get_ports {wbm_dat_i[15]}]\
+           [get_ports {wbm_dat_i[16]}]\
+           [get_ports {wbm_dat_i[17]}]\
+           [get_ports {wbm_dat_i[18]}]\
+           [get_ports {wbm_dat_i[19]}]\
+           [get_ports {wbm_dat_i[1]}]\
+           [get_ports {wbm_dat_i[20]}]\
+           [get_ports {wbm_dat_i[21]}]\
+           [get_ports {wbm_dat_i[22]}]\
+           [get_ports {wbm_dat_i[23]}]\
+           [get_ports {wbm_dat_i[24]}]\
+           [get_ports {wbm_dat_i[25]}]\
+           [get_ports {wbm_dat_i[26]}]\
+           [get_ports {wbm_dat_i[27]}]\
+           [get_ports {wbm_dat_i[28]}]\
+           [get_ports {wbm_dat_i[29]}]\
+           [get_ports {wbm_dat_i[2]}]\
+           [get_ports {wbm_dat_i[30]}]\
+           [get_ports {wbm_dat_i[31]}]\
+           [get_ports {wbm_dat_i[3]}]\
+           [get_ports {wbm_dat_i[4]}]\
+           [get_ports {wbm_dat_i[5]}]\
+           [get_ports {wbm_dat_i[6]}]\
+           [get_ports {wbm_dat_i[7]}]\
+           [get_ports {wbm_dat_i[8]}]\
+           [get_ports {wbm_dat_i[9]}]\
+           [get_ports {wbm_sel_i[0]}]\
+           [get_ports {wbm_sel_i[1]}]\
+           [get_ports {wbm_sel_i[2]}]\
+           [get_ports {wbm_sel_i[3]}]\
+           [get_ports {wbm_we_i}]] 2
+set_multicycle_path -setup\
+    -from [list [get_ports {wbm_adr_i[0]}]\
+           [get_ports {wbm_adr_i[10]}]\
+           [get_ports {wbm_adr_i[11]}]\
+           [get_ports {wbm_adr_i[12]}]\
+           [get_ports {wbm_adr_i[13]}]\
+           [get_ports {wbm_adr_i[14]}]\
+           [get_ports {wbm_adr_i[15]}]\
+           [get_ports {wbm_adr_i[16]}]\
+           [get_ports {wbm_adr_i[17]}]\
+           [get_ports {wbm_adr_i[18]}]\
+           [get_ports {wbm_adr_i[19]}]\
+           [get_ports {wbm_adr_i[1]}]\
+           [get_ports {wbm_adr_i[20]}]\
+           [get_ports {wbm_adr_i[21]}]\
+           [get_ports {wbm_adr_i[22]}]\
+           [get_ports {wbm_adr_i[23]}]\
+           [get_ports {wbm_adr_i[24]}]\
+           [get_ports {wbm_adr_i[25]}]\
+           [get_ports {wbm_adr_i[26]}]\
+           [get_ports {wbm_adr_i[27]}]\
+           [get_ports {wbm_adr_i[28]}]\
+           [get_ports {wbm_adr_i[29]}]\
+           [get_ports {wbm_adr_i[2]}]\
+           [get_ports {wbm_adr_i[30]}]\
+           [get_ports {wbm_adr_i[31]}]\
+           [get_ports {wbm_adr_i[3]}]\
+           [get_ports {wbm_adr_i[4]}]\
+           [get_ports {wbm_adr_i[5]}]\
+           [get_ports {wbm_adr_i[6]}]\
+           [get_ports {wbm_adr_i[7]}]\
+           [get_ports {wbm_adr_i[8]}]\
+           [get_ports {wbm_adr_i[9]}]\
+           [get_ports {wbm_cyc_i}]\
+           [get_ports {wbm_dat_i[0]}]\
+           [get_ports {wbm_dat_i[10]}]\
+           [get_ports {wbm_dat_i[11]}]\
+           [get_ports {wbm_dat_i[12]}]\
+           [get_ports {wbm_dat_i[13]}]\
+           [get_ports {wbm_dat_i[14]}]\
+           [get_ports {wbm_dat_i[15]}]\
+           [get_ports {wbm_dat_i[16]}]\
+           [get_ports {wbm_dat_i[17]}]\
+           [get_ports {wbm_dat_i[18]}]\
+           [get_ports {wbm_dat_i[19]}]\
+           [get_ports {wbm_dat_i[1]}]\
+           [get_ports {wbm_dat_i[20]}]\
+           [get_ports {wbm_dat_i[21]}]\
+           [get_ports {wbm_dat_i[22]}]\
+           [get_ports {wbm_dat_i[23]}]\
+           [get_ports {wbm_dat_i[24]}]\
+           [get_ports {wbm_dat_i[25]}]\
+           [get_ports {wbm_dat_i[26]}]\
+           [get_ports {wbm_dat_i[27]}]\
+           [get_ports {wbm_dat_i[28]}]\
+           [get_ports {wbm_dat_i[29]}]\
+           [get_ports {wbm_dat_i[2]}]\
+           [get_ports {wbm_dat_i[30]}]\
+           [get_ports {wbm_dat_i[31]}]\
+           [get_ports {wbm_dat_i[3]}]\
+           [get_ports {wbm_dat_i[4]}]\
+           [get_ports {wbm_dat_i[5]}]\
+           [get_ports {wbm_dat_i[6]}]\
+           [get_ports {wbm_dat_i[7]}]\
+           [get_ports {wbm_dat_i[8]}]\
+           [get_ports {wbm_dat_i[9]}]\
+           [get_ports {wbm_sel_i[0]}]\
+           [get_ports {wbm_sel_i[1]}]\
+           [get_ports {wbm_sel_i[2]}]\
+           [get_ports {wbm_sel_i[3]}]\
+           [get_ports {wbm_we_i}]] 2
+set_max_delay\
+    -from [get_ports {wbd_clk_int}] 3.5000
+set_max_delay\
+    -from [get_ports {wbd_clk_int}]\
+    -to [get_ports {wbd_clk_wh}] 3.5000
+set_max_delay\
+    -to [get_ports {wbd_clk_wh}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {cfg_strap_pad_ctrl}]
+set_load -pin_load 0.0334 [get_ports {cpu_clk}]
+set_load -pin_load 0.0334 [get_ports {e_reset_n}]
+set_load -pin_load 0.0334 [get_ports {p_reset_n}]
+set_load -pin_load 0.0334 [get_ports {s_reset_n}]
+set_load -pin_load 0.0334 [get_ports {sdout}]
+set_load -pin_load 0.0334 [get_ports {sdout_oen}]
+set_load -pin_load 0.0334 [get_ports {uartm_txd}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_wh}]
+set_load -pin_load 0.0334 [get_ports {wbd_int_rst_n}]
+set_load -pin_load 0.0334 [get_ports {wbd_pll_rst_n}]
+set_load -pin_load 0.0334 [get_ports {wbm_ack_o}]
+set_load -pin_load 0.0334 [get_ports {wbm_err_o}]
+set_load -pin_load 0.0334 [get_ports {wbs_clk_out}]
+set_load -pin_load 0.0334 [get_ports {wbs_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {wbs_stb_o}]
+set_load -pin_load 0.0334 [get_ports {wbs_we_o}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[31]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[30]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[29]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[28]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[27]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[26]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[25]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[24]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[23]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[22]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[21]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[20]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[19]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[18]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[17]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[16]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl1[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[31]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[30]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[29]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[28]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[27]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[26]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[25]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[24]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[23]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[22]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[21]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[20]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[19]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[18]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[17]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[16]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[15]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[14]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[13]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_clk_skew_ctrl2[0]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[31]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[30]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[29]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[28]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[27]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[26]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[25]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[24]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[23]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[22]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[21]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[20]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[19]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[18]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[17]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[16]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[15]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[14]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[13]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[12]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[11]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[10]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[9]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[8]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[7]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[6]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[5]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[4]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[3]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[2]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[1]}]
+set_load -pin_load 0.0334 [get_ports {system_strap[0]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbm_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_sel_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {int_pll_clock}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sdin}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ssn}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uartm_rxd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock1}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_rst_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_err_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {xtal_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_sticky[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_uartm[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {strap_uartm[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_sel_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/wb_interconnect.sdc b/sdc/wb_interconnect.sdc
new file mode 100644
index 0000000..f05b185
--- /dev/null
+++ b/sdc/wb_interconnect.sdc
@@ -0,0 +1,2223 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 08:54:13 2022
+###############################################################################
+current_design wb_interconnect
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name clk_i -period 10.0000 [get_ports {clk_i}]
+set_clock_transition 0.1500 [get_clocks {clk_i}]
+set_clock_uncertainty -setup 0.5000 clk_i
+set_clock_uncertainty -hold 0.2500 clk_i
+set_propagated_clock [get_clocks {clk_i}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_adr_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_adr_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m0_wbd_sel_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m0_wbd_sel_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m0_wbd_sel_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m0_wbd_sel_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m0_wbd_sel_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m0_wbd_sel_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m0_wbd_sel_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m0_wbd_sel_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_adr_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_adr_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_sel_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_sel_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_sel_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_sel_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_sel_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_sel_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m1_wbd_sel_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m1_wbd_sel_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_adr_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_adr_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_sel_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_sel_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_sel_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_sel_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_sel_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_sel_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -min -add_delay [get_ports {m2_wbd_sel_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -min -add_delay [get_ports {m2_wbd_sel_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -rise -max -add_delay [get_ports {rst_n}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -fall -max -add_delay [get_ports {rst_n}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_ack_i}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_ack_i}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_ack_i}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[0]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[10]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[11]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[12]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[13]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[14]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[15]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[16]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[17]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[18]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[19]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[1]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[20]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[21]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[22]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[23]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[24]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[25]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[26]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[27]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[28]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[29]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[2]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[30]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[31]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[3]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[4]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[5]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[6]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[7]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[8]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_i[9]}]
+set_input_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_i[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_ack_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_ack_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_dat_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m0_wbd_err_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m0_wbd_err_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_ack_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_ack_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_dat_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m1_wbd_err_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m1_wbd_err_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_ack_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_ack_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_dat_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {m2_wbd_err_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {m2_wbd_err_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_adr_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_adr_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_cyc_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_cyc_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_dat_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_sel_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_sel_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_stb_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_stb_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s0_wbd_we_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s0_wbd_we_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_adr_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_adr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_cyc_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_cyc_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_dat_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_sel_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_sel_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_stb_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_stb_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s1_wbd_we_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s1_wbd_we_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_adr_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_adr_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_cyc_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_cyc_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[10]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[11]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[12]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[13]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[14]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[15]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[16]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[17]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[18]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[19]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[20]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[21]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[22]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[23]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[24]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[25]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[26]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[27]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[28]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[29]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[30]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[31]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[4]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[5]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[6]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[7]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[8]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_dat_o[9]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[0]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[1]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[2]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_sel_o[3]}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_sel_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_stb_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_stb_o}]
+set_output_delay 2.0000 -clock [get_clocks {clk_i}] -min -add_delay [get_ports {s2_wbd_we_o}]
+set_output_delay 4.0000 -clock [get_clocks {clk_i}] -max -add_delay [get_ports {s2_wbd_we_o}]
+set_max_delay\
+    -from [get_ports {wbd_clk_int}] 4.0000
+set_max_delay\
+    -from [get_ports {wbd_clk_int}]\
+    -to [get_ports {wbd_clk_wi}] 4.0000
+set_max_delay\
+    -to [get_ports {wbd_clk_wi}] 2.0000
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {m0_wbd_ack_o}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_err_o}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_lack_o}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_ack_o}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_err_o}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_lack_o}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_ack_o}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_err_o}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_lack_o}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_ack_o}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_err_o}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_lack_o}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bry_o}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_wi}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_clk_out[0]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[157]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[156]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[155]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[154]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[153]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[152]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[151]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[150]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[149]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[148]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[147]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[146]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[145]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[144]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[143]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[142]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[141]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[140]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[139]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[138]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[137]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[136]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[135]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[134]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[133]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[132]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[131]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[130]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[129]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[128]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[127]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[126]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[125]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[124]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[123]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[122]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[121]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[120]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[119]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[118]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[117]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[116]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[115]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[114]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[113]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[112]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[111]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[110]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[109]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[108]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[107]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[106]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[105]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[104]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[103]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[102]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[101]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[100]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[99]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[98]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[97]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[96]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[95]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[94]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[93]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[92]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[91]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[90]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[89]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[88]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[87]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[86]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[85]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[84]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[83]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[82]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[81]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[80]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[79]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[78]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[77]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[76]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[75]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[74]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[73]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[72]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[71]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[70]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[69]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[68]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[67]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[66]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[65]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[64]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[63]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[62]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[61]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[60]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[59]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[58]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[57]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[56]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[55]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[54]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[53]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[52]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[51]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[50]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[49]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[48]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[47]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[46]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[45]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[44]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[43]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[42]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[41]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[40]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[39]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[38]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[37]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[36]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[35]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[34]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[33]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[32]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[31]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[30]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[29]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[28]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[27]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[26]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[25]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[24]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[23]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[22]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[21]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[20]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[19]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[18]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[17]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[16]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[15]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[14]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[13]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[12]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[11]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[10]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[9]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[8]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[7]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[6]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[5]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[4]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[3]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[2]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[1]}]
+set_load -pin_load 0.0334 [get_ports {ch_data_out[0]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {m3_wbd_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[9]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[8]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[7]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[6]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[5]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[4]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_bl_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_bry_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bry_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bry_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_lack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_clk_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[157]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[156]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[155]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[154]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[153]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[152]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[151]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[150]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[149]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[148]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[147]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[146]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[145]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[144]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[143]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[142]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[141]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[140]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[139]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[138]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[137]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[136]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[135]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[134]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[133]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[132]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[131]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[130]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[129]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[128]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[124]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[123]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[122]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[121]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[120]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[119]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[118]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[117]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[116]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[115]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[114]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[113]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[112]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[111]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[110]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[109]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[108]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[107]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[106]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[105]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[104]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[103]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[102]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[101]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[100]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[99]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[98]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[97]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[96]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[95]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[94]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[93]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[92]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[91]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[90]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[89]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[88]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[87]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[86]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[85]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[84]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[83]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[82]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[81]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[80]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[79]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[78]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[77]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[76]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[75]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[74]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[73]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[72]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[71]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[70]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[69]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[68]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[67]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[66]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[65]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[64]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[63]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[62]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[61]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[60]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[59]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[58]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[57]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[56]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[55]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[54]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[53]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[52]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[51]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[50]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[49]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ch_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_bl_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_bl_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_bl_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_bl_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_bl_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m3_wbd_sel_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_wi[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_wi[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_wi[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_wi[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/ycr2_iconnect.sdc b/sdc/ycr2_iconnect.sdc
new file mode 100644
index 0000000..aae8274
--- /dev/null
+++ b/sdc/ycr2_iconnect.sdc
@@ -0,0 +1,2288 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 05:53:38 2022
+###############################################################################
+current_design ycr2_iconnect
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
+set_clock_transition 0.1500 [get_clocks {core_clk}]
+set_clock_uncertainty -setup 0.5000 core_clk
+set_clock_uncertainty -hold 0.2500 core_clk
+set_propagated_clock [get_clocks {core_clk}]
+create_generated_clock -name sram0_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {tcm clock0} [get_ports {sram0_clk0}]
+set_clock_transition 0.1500 [get_clocks {sram0_clk0}]
+set_clock_uncertainty -setup 0.5000 sram0_clk0
+set_clock_uncertainty -hold 0.2500 sram0_clk0
+set_propagated_clock [get_clocks {sram0_clk0}]
+create_generated_clock -name sram0_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {tcm clock1} [get_ports {sram0_clk1}]
+set_clock_transition 0.1500 [get_clocks {sram0_clk1}]
+set_clock_uncertainty -setup 0.5000 sram0_clk1
+set_clock_uncertainty -hold 0.2500 sram0_clk1
+set_propagated_clock [get_clocks {sram0_clk1}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_addr[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_req}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_req}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_wdata[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_width[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_width[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_width[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_width[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_addr[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_bl[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_bl[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_bl[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_bl[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_bl[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_bl[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_req}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_req}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_addr[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_cmd}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_cmd}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_req}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_req}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_wdata[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_width[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_width[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_width[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_width[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_addr[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_bl[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_bl[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_bl[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_bl[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_bl[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_bl[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_cmd}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_cmd}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_req}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_req}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[0]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[0]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[10]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[10]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[11]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[11]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[12]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[12]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[13]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[13]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[14]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[14]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[15]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[15]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[16]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[16]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[17]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[17]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[18]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[18]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[19]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[19]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[1]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[1]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[20]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[20]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[21]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[21]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[22]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[22]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[23]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[23]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[24]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[24]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[25]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[25]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[26]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[26]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[27]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[27]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[28]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[28]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[29]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[29]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[2]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[2]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[30]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[30]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[31]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[31]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[3]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[3]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[4]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[4]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[5]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[5]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[6]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[6]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[7]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[7]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[8]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[8]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_dout0[9]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_dout0[9]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[0]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[0]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[10]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[10]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[11]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[11]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[12]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[12]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[13]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[13]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[14]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[14]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[15]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[15]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[16]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[16]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[17]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[17]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[18]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[18]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[19]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[19]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[1]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[1]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[20]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[20]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[21]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[21]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[22]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[22]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[23]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[23]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[24]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[24]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[25]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[25]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[26]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[26]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[27]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[27]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[28]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[28]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[29]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[29]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[2]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[2]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[30]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[30]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[31]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[31]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[3]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[3]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[4]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[4]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[5]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[5]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[6]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[6]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[7]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[7]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[8]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[8]}]
+set_input_delay 2.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_dout1[9]}]
+set_input_delay 6.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_dout1[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[0]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[10]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[11]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[12]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[13]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[14]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[15]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[16]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[17]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[18]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[19]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[1]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[20]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[21]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[22]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[23]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[24]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[25]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[26]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[27]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[28]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[29]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[2]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[30]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[31]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[3]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[4]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[5]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[6]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[7]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[8]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_rdata[9]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_dmem_req_ack}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_dmem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[0]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[10]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[11]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[12]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[13]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[14]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[15]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[16]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[17]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[18]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[19]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[1]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[20]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[21]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[22]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[23]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[24]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[25]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[26]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[27]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[28]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[29]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[2]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[30]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[31]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[3]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[4]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[5]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[6]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[7]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[8]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_rdata[9]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core0_imem_req_ack}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core0_imem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[0]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[10]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[11]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[12]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[13]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[14]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[15]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[16]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[17]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[18]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[19]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[1]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[20]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[21]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[22]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[23]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[24]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[25]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[26]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[27]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[28]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[29]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[2]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[30]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[31]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[3]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[4]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[5]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[6]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[7]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[8]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_rdata[9]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_dmem_req_ack}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_dmem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[0]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[10]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[11]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[12]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[13]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[14]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[15]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[16]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[17]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[18]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[19]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[1]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[20]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[21]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[22]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[23]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[24]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[25]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[26]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[27]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[28]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[29]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[2]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[30]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[31]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[3]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[4]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[5]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[6]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[7]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[8]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_rdata[9]}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core1_imem_req_ack}]
+set_output_delay 4.5000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core1_imem_req_ack}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[0]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[1]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[2]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[3]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[4]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[4]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[5]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[5]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[6]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[6]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[7]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[7]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_addr0[8]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_addr0[8]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[0]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[0]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[1]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[1]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[2]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[2]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[3]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[3]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[4]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[4]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[5]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[5]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[6]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[6]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[7]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[7]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_addr1[8]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_addr1[8]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_csb0}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_csb0}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk1}] -min -add_delay [get_ports {sram0_csb1}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk1}] -max -add_delay [get_ports {sram0_csb1}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[0]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[10]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[10]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[11]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[11]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[12]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[12]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[13]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[13]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[14]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[14]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[15]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[15]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[16]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[16]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[17]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[17]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[18]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[18]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[19]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[19]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[1]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[20]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[20]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[21]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[21]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[22]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[22]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[23]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[23]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[24]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[24]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[25]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[25]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[26]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[26]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[27]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[27]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[28]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[28]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[29]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[29]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[2]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[30]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[30]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[31]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[31]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[3]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[4]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[4]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[5]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[5]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[6]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[6]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[7]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[7]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[8]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[8]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_din0[9]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_din0[9]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_web0}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_web0}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_wmask0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_wmask0[0]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_wmask0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_wmask0[1]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_wmask0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_wmask0[2]}]
+set_output_delay -1.0000 -clock [get_clocks {sram0_clk0}] -min -add_delay [get_ports {sram0_wmask0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {sram0_clk0}] -max -add_delay [get_ports {sram0_wmask0[3]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {aes_dmem_cmd}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_req}]
+set_load -pin_load 0.0334 [get_ports {cfg_dcache_force_flush}]
+set_load -pin_load 0.0334 [get_ports {core0_clk}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_soft}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_irq}]
+set_load -pin_load 0.0334 [get_ports {core1_clk}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_soft}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_irq}]
+set_load -pin_load 0.0334 [get_ports {core_clk_skew}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_cmd}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_req}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_cmd}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_req}]
+set_load -pin_load 0.0334 [get_ports {core_icache_cmd}]
+set_load -pin_load 0.0334 [get_ports {core_icache_req}]
+set_load -pin_load 0.0334 [get_ports {cpu_clk_aes}]
+set_load -pin_load 0.0334 [get_ports {cpu_clk_fpu}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_cmd}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_req}]
+set_load -pin_load 0.0334 [get_ports {sram0_clk0}]
+set_load -pin_load 0.0334 [get_ports {sram0_clk1}]
+set_load -pin_load 0.0334 [get_ports {sram0_csb0}]
+set_load -pin_load 0.0334 [get_ports {sram0_csb1}]
+set_load -pin_load 0.0334 [get_ports {sram0_web0}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_addr[6]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_addr[5]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_addr[4]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_addr[3]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_addr[2]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_addr[1]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_addr[0]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[31]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[30]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[29]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[28]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[27]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[26]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[25]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[24]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[23]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[22]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[21]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[20]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[19]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[18]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[17]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[16]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[15]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[14]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[13]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[12]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[11]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[10]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[9]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[8]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[7]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[6]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[5]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[4]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[3]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[2]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[1]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_wdata[0]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_width[1]}]
+set_load -pin_load 0.0334 [get_ports {aes_dmem_width[0]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core0_dmem_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core0_imem_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[31]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[30]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[29]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[28]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[27]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[26]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[25]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[24]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[23]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[22]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[21]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[20]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[19]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[18]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[17]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[16]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[15]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[14]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[13]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[12]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[11]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[10]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[9]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[8]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[7]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[6]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[5]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[4]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[3]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[2]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[1]}]
+set_load -pin_load 0.0334 [get_ports {core0_irq_lines[0]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[63]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[62]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[61]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[60]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[59]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[58]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[57]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[56]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[55]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[54]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[53]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[52]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[51]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[50]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[49]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[48]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[47]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[46]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[45]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[44]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[43]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[42]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[41]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[40]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[39]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[38]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[37]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[36]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[35]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[34]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[33]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[32]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[31]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[30]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[29]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[28]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[27]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[26]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[25]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[24]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[23]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[22]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[21]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[20]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[19]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[18]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[17]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[16]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[15]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[14]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[13]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[12]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[11]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[10]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[9]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[8]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[7]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[6]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[5]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[4]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[3]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[2]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[1]}]
+set_load -pin_load 0.0334 [get_ports {core0_timer_val[0]}]
+set_load -pin_load 0.0334 [get_ports {core0_uid[1]}]
+set_load -pin_load 0.0334 [get_ports {core0_uid[0]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core1_dmem_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core1_imem_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[31]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[30]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[29]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[28]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[27]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[26]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[25]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[24]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[23]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[22]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[21]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[20]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[19]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[18]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[17]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[16]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[15]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[14]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[13]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[12]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[11]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[10]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[9]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[8]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[7]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[6]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[5]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[4]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[3]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[2]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[1]}]
+set_load -pin_load 0.0334 [get_ports {core1_irq_lines[0]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[63]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[62]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[61]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[60]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[59]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[58]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[57]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[56]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[55]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[54]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[53]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[52]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[51]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[50]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[49]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[48]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[47]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[46]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[45]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[44]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[43]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[42]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[41]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[40]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[39]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[38]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[37]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[36]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[35]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[34]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[33]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[32]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[31]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[30]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[29]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[28]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[27]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[26]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[25]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[24]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[23]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[22]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[21]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[20]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[19]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[18]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[17]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[16]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[15]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[14]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[13]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[12]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[11]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[10]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[9]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[8]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[7]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[6]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[5]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[4]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[3]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[2]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[1]}]
+set_load -pin_load 0.0334 [get_ports {core1_timer_val[0]}]
+set_load -pin_load 0.0334 [get_ports {core1_uid[1]}]
+set_load -pin_load 0.0334 [get_ports {core1_uid[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[31]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[30]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[29]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[28]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[27]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[26]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[25]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[24]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[23]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[22]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[21]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[20]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[19]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[18]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[17]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[16]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[15]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[14]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[13]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[12]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[11]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[10]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[9]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[8]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[7]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[6]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[5]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[4]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[3]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[2]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_addr[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_wdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_width[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_width[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[31]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[30]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[29]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[28]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[27]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[26]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[25]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[24]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[23]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[22]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[21]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[20]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[19]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[18]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[17]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[16]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[15]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[14]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[13]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[12]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[11]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[10]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[9]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[8]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[7]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[6]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[5]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[4]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[3]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[2]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_addr[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_bl[2]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_bl[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_bl[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_wdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_width[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_width[0]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[31]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[30]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[29]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[28]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[27]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[26]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[25]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[24]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[23]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[22]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[21]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[20]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[19]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[18]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[17]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[16]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[15]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[14]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[13]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[12]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[11]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[10]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[9]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[8]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[7]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[6]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[5]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[4]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[3]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[2]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[1]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_addr[0]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_bl[2]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_bl[1]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_bl[0]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_width[1]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_width[0]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_addr[4]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_addr[3]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_addr[2]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_addr[1]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_addr[0]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[31]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[30]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[29]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[28]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[27]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[26]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[25]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[24]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[23]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[22]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[21]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[20]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[19]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[18]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[17]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[16]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[15]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[14]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[13]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[12]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[11]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[10]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[9]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[8]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[7]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[6]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[5]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[4]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[3]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[2]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[1]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_wdata[0]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_width[1]}]
+set_load -pin_load 0.0334 [get_ports {fpu_dmem_width[0]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[63]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[62]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[61]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[60]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[59]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[58]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[57]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[56]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[55]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[54]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[53]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[52]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[51]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[50]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[49]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[48]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[47]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[46]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[45]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[44]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[43]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[42]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[41]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[40]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[39]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[38]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[37]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[36]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[35]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[34]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[33]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[32]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {riscv_debug[0]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[8]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[7]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[6]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[5]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[4]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[3]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[2]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[1]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr0[0]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[8]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[7]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[6]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[5]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[4]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[3]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[2]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[1]}]
+set_load -pin_load 0.0334 [get_ports {sram0_addr1[0]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[31]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[30]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[29]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[28]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[27]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[26]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[25]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[24]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[23]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[22]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[21]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[20]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[19]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[18]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[17]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[16]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[15]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[14]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[13]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[12]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[11]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[10]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[9]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[8]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[7]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[6]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[5]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[4]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[3]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[2]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[1]}]
+set_load -pin_load 0.0334 [get_ports {sram0_din0[0]}]
+set_load -pin_load 0.0334 [get_ports {sram0_wmask0[3]}]
+set_load -pin_load 0.0334 [get_ports {sram0_wmask0[2]}]
+set_load -pin_load 0.0334 [get_ports {sram0_wmask0[1]}]
+set_load -pin_load 0.0334 [get_ports {sram0_wmask0[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_req_ack}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_bypass_dcache}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_bypass_icache}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_req_ack}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_req_ack}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_req_ack}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_soft_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cpu_intf_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_req_ack}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pwrup_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_resp[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {aes_dmem_resp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sram_lphase[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sram_lphase[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_debug[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_dmem_width[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_bl[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_bl[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core0_imem_bl[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_debug[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_dmem_width[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_bl[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_bl[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core1_imem_bl[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_resp[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_resp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_debug_sel[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_debug_sel[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_resp[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_resp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_resp[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_resp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_rdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_resp[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fpu_dmem_resp[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout0[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram0_dout1[0]}]
+set_case_analysis 0 [get_ports {cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_ports {cfg_sram_lphase[1]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/ycr_core_top.sdc b/sdc/ycr_core_top.sdc
new file mode 100644
index 0000000..09e3c36
--- /dev/null
+++ b/sdc/ycr_core_top.sdc
@@ -0,0 +1,711 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 05:57:39 2022
+###############################################################################
+current_design ycr_core_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 10.0000 [get_ports {clk}]
+set_clock_transition 0.1500 [get_clocks {core_clk}]
+set_clock_uncertainty -setup 0.5000 core_clk
+set_clock_uncertainty -hold 0.2500 core_clk
+set_propagated_clock [get_clocks {core_clk}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[0]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[10]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[11]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[12]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[13]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[14]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[15]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[16]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[17]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[18]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[19]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[1]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[20]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[21]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[22]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[23]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[24]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[25]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[26]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[27]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[28]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[29]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[2]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[30]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[31]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[3]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[4]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[5]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[6]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[7]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[8]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_rdata_i[9]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_rdata_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_req_ack_i}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_req_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_resp_i[0]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_resp_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {dmem2core_resp_i[1]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {dmem2core_resp_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[0]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[10]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[11]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[12]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[13]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[14]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[15]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[16]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[17]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[18]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[19]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[1]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[20]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[21]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[22]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[23]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[24]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[25]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[26]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[27]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[28]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[29]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[2]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[30]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[31]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[3]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[4]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[5]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[6]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[7]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[8]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_rdata_i[9]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_rdata_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_req_ack_i}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_req_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_resp_i[0]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_resp_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {imem2core_resp_i[1]}]
+set_input_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {imem2core_resp_i[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[0]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[10]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[11]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[12]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[13]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[14]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[15]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[16]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[17]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[18]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[19]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[1]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[20]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[21]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[22]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[23]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[24]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[25]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[26]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[27]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[28]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[29]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[2]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[30]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[31]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[3]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[4]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[5]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[6]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[7]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[8]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_addr_o[9]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_addr_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_req_o}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_req_o}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[0]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[10]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[11]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[12]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[13]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[14]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[15]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[16]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[17]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[18]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[19]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[1]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[20]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[21]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[22]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[23]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[24]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[25]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[26]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[27]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[28]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[29]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[2]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[30]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[31]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[3]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[4]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[5]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[6]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[7]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[8]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_wdata_o[9]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_wdata_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_width_o[0]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_width_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2dmem_width_o[1]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2dmem_width_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[0]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[10]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[11]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[12]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[13]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[14]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[15]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[16]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[17]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[18]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[19]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[1]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[20]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[21]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[22]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[23]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[24]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[25]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[26]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[27]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[28]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[29]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[2]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[30]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[31]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[3]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[4]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[5]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[6]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[7]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[8]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_addr_o[9]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_addr_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_bl_o[0]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_bl_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_bl_o[1]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_bl_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_bl_o[2]}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_bl_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_cmd_o}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_cmd_o}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core2imem_req_o}]
+set_output_delay 7.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core2imem_req_o}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {clk_o}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_cmd_o}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_req_o}]
+set_load -pin_load 0.0334 [get_ports {core2imem_cmd_o}]
+set_load -pin_load 0.0334 [get_ports {core2imem_req_o}]
+set_load -pin_load 0.0334 [get_ports {core_clk_skew}]
+set_load -pin_load 0.0334 [get_ports {core_rdc_qlfy_o}]
+set_load -pin_load 0.0334 [get_ports {core_rst_n_o}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_addr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[31]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[30]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[29]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[28]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[27]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[26]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[25]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[24]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[23]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[22]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[21]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[20]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[19]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[18]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[17]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[16]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[15]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[14]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[13]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[12]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[11]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[10]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[9]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[8]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[7]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[6]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[5]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[4]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[3]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[2]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[1]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_wdata_o[0]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_width_o[1]}]
+set_load -pin_load 0.0334 [get_ports {core2dmem_width_o[0]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_addr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_bl_o[2]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_bl_o[1]}]
+set_load -pin_load 0.0334 [get_ports {core2imem_bl_o[0]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[48]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[47]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[46]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[45]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[44]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[43]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[42]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[41]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[40]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[39]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[38]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[37]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[36]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[35]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[34]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[33]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[32]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[31]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[30]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[29]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[28]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[27]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[26]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[25]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[24]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[23]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[22]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[21]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[20]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[19]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[18]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[17]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[16]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[15]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[14]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[13]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[12]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[11]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[10]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[9]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[8]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[7]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[6]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[5]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[4]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[3]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[2]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[1]}]
+set_load -pin_load 0.0334 [get_ports {core_debug[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_mtimer_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_soft_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cpu_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_req_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_req_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pwrup_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_irq_lines_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[63]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[62]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[61]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[60]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[59]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[58]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[57]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[56]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[55]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[54]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[53]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[52]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[51]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[50]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[49]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[48]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[47]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[46]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[45]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[44]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[43]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[42]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[41]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[40]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[39]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[38]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_mtimer_val_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_uid[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_uid[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_rdata_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_resp_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dmem2core_resp_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_rdata_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_resp_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {imem2core_resp_i[0]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/sdc/ycr_intf.sdc b/sdc/ycr_intf.sdc
new file mode 100644
index 0000000..8d8052d
--- /dev/null
+++ b/sdc/ycr_intf.sdc
@@ -0,0 +1,2494 @@
+###############################################################################
+# Created by write_sdc
+# Sat Dec 10 05:54:02 2022
+###############################################################################
+current_design ycr_intf
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
+set_clock_transition 0.1500 [get_clocks {core_clk}]
+set_clock_uncertainty -setup 0.5000 core_clk
+set_clock_uncertainty -hold 0.2500 core_clk
+set_propagated_clock [get_clocks {core_clk}]
+create_clock -name rtc_clk -period 40.0000 
+set_clock_uncertainty -setup 0.5000 rtc_clk
+set_clock_uncertainty -hold 0.2500 rtc_clk
+create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
+set_clock_transition 0.1500 [get_clocks {wb_clk}]
+set_clock_uncertainty -setup 0.5000 wb_clk
+set_clock_uncertainty -hold 0.2500 wb_clk
+set_propagated_clock [get_clocks {wb_clk}]
+create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {dcache mem clock0} [get_ports {dcache_mem_clk0}]
+set_clock_transition 0.1500 [get_clocks {dcache_mem_clk0}]
+set_clock_uncertainty -setup 0.5000 dcache_mem_clk0
+set_clock_uncertainty -hold 0.2500 dcache_mem_clk0
+set_propagated_clock [get_clocks {dcache_mem_clk0}]
+create_generated_clock -name dcache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {dcache mem clock1} [get_ports {dcache_mem_clk1}]
+set_clock_transition 0.1500 [get_clocks {dcache_mem_clk1}]
+set_clock_uncertainty -setup 0.5000 dcache_mem_clk1
+set_clock_uncertainty -hold 0.2500 dcache_mem_clk1
+set_propagated_clock [get_clocks {dcache_mem_clk1}]
+create_generated_clock -name icache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {icache mem clock0} [get_ports {icache_mem_clk0}]
+set_clock_transition 0.1500 [get_clocks {icache_mem_clk0}]
+set_clock_uncertainty -setup 0.5000 icache_mem_clk0
+set_clock_uncertainty -hold 0.2500 icache_mem_clk0
+set_propagated_clock [get_clocks {icache_mem_clk0}]
+create_generated_clock -name icache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {icache mem clock1} [get_ports {icache_mem_clk1}]
+set_clock_transition 0.1500 [get_clocks {icache_mem_clk1}]
+set_clock_uncertainty -setup 0.5000 icache_mem_clk1
+set_clock_uncertainty -hold 0.2500 icache_mem_clk1
+set_propagated_clock [get_clocks {icache_mem_clk1}]
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {wb_clk}]\
+ -group [list [get_clocks {core_clk}]\
+           [get_clocks {dcache_mem_clk0}]\
+           [get_clocks {dcache_mem_clk1}]\
+           [get_clocks {icache_mem_clk0}]\
+           [get_clocks {icache_mem_clk1}]] -comment {Async Clock group}
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[0]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[10]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[11]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[12]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[13]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[14]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[15]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[16]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[17]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[18]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[19]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[1]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[20]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[21]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[22]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[23]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[24]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[25]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[26]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[27]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[28]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[29]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[2]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[30]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[31]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[3]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[4]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[5]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[6]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[7]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[8]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[9]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_cmd}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_cmd}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_req}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_req}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[0]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[10]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[11]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[12]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[13]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[14]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[15]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[16]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[17]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[18]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[19]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[1]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[20]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[21]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[22]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[23]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[24]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[25]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[26]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[27]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[28]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[29]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[2]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[30]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[31]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[3]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[4]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[5]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[6]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[7]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[8]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[9]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_width[0]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_width[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_width[1]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_width[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_cmd}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_cmd}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_req}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_req}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[10]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[10]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[11]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[11]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[12]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[12]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[13]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[13]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[14]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[14]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[15]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[15]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[16]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[16]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[17]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[17]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[18]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[18]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[19]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[19]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[1]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[20]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[20]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[21]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[21]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[22]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[22]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[23]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[23]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[24]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[24]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[25]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[25]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[26]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[26]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[27]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[27]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[28]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[28]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[29]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[29]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[2]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[2]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[30]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[30]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[31]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[31]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[3]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[3]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[4]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[4]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[5]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[5]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[6]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[6]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[7]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[7]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[8]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[8]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[9]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[9]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_width[0]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_width[0]}]
+set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_width[1]}]
+set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_width[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[0]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[10]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[10]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[11]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[11]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[12]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[12]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[13]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[13]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[14]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[14]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[15]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[15]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[16]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[16]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[17]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[17]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[18]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[18]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[19]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[19]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[1]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[20]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[20]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[21]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[21]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[22]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[22]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[23]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[23]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[24]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[24]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[25]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[25]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[26]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[26]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[27]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[27]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[28]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[28]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[29]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[29]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[2]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[30]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[30]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[31]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[31]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[3]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[3]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[4]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[4]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[5]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[5]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[6]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[6]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[7]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[7]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[8]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[8]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[9]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[9]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_bl[0]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_bl[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_bl[1]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_bl[1]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_bl[2]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_bl[2]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_cmd}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_cmd}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_req}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_req}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_width[0]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_width[0]}]
+set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_width[1]}]
+set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_width[1]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[0]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[0]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[10]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[10]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[11]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[11]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[12]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[12]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[13]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[13]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[14]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[14]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[15]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[15]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[16]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[16]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[17]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[17]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[18]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[18]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[19]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[19]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[1]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[1]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[20]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[20]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[21]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[21]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[22]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[22]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[23]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[23]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[24]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[24]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[25]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[25]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[26]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[26]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[27]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[27]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[28]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[28]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[29]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[29]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[2]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[2]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[30]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[30]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[31]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[31]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[3]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[3]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[4]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[4]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[5]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[5]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[6]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[6]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[7]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[7]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[8]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[8]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[9]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[9]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[0]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[0]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[10]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[10]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[11]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[11]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[12]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[12]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[13]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[13]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[14]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[14]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[15]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[15]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[16]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[16]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[17]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[17]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[18]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[18]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[19]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[19]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[1]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[1]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[20]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[20]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[21]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[21]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[22]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[22]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[23]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[23]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[24]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[24]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[25]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[25]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[26]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[26]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[27]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[27]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[28]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[28]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[29]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[29]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[2]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[2]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[30]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[30]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[31]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[31]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[3]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[3]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[4]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[4]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[5]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[5]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[6]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[6]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[7]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[7]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[8]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[8]}]
+set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[9]}]
+set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[9]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[0]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[0]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[10]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[10]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[11]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[11]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[12]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[12]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[13]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[13]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[14]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[14]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[15]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[15]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[16]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[16]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[17]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[17]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[18]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[18]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[19]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[19]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[1]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[1]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[20]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[20]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[21]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[21]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[22]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[22]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[23]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[23]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[24]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[24]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[25]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[25]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[26]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[26]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[27]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[27]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[28]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[28]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[29]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[29]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[2]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[2]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[30]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[30]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[31]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[31]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[3]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[3]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[4]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[4]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[5]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[5]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[6]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[6]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[7]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[7]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[8]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[8]}]
+set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[9]}]
+set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_ack_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_err_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_err_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_lack_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_lack_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_ack_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_err_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_err_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_lack_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_lack_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_ack_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_ack_i}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[0]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[0]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[10]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[10]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[11]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[11]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[12]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[12]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[13]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[13]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[14]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[14]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[15]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[15]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[16]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[16]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[17]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[17]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[18]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[18]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[19]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[19]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[1]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[1]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[20]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[20]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[21]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[21]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[22]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[22]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[23]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[23]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[24]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[24]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[25]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[25]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[26]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[26]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[27]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[27]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[28]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[28]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[29]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[29]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[2]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[2]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[30]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[30]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[31]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[31]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[3]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[3]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[4]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[4]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[5]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[5]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[6]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[6]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[7]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[7]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[8]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[8]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[9]}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[9]}]
+set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_err_i}]
+set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_err_i}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_req_ack}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_resp[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_resp[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_resp[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_resp[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_req_ack}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_resp[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_resp[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_resp[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_resp[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[10]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[10]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[11]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[11]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[12]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[12]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[13]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[13]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[14]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[14]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[15]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[15]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[16]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[16]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[17]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[17]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[18]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[18]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[19]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[19]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[1]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[20]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[20]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[21]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[21]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[22]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[22]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[23]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[23]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[24]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[24]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[25]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[25]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[26]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[26]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[27]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[27]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[28]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[28]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[29]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[29]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[2]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[2]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[30]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[30]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[31]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[31]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[3]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[3]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[4]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[4]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[5]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[5]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[6]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[6]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[7]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[7]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[8]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[8]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[9]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[9]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_req_ack}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_req_ack}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_resp[0]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_resp[0]}]
+set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_resp[1]}]
+set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_resp[1]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[0]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[1]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[2]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[3]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[4]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[4]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[5]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[5]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[6]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[6]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[7]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[7]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[8]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[8]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[0]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[0]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[1]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[1]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[2]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[2]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[3]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[3]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[4]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[4]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[5]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[5]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[6]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[6]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[7]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[7]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[8]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[8]}]
+set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_csb0}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_csb0}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_csb1}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_csb1}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[0]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[10]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[10]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[11]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[11]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[12]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[12]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[13]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[13]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[14]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[14]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[15]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[15]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[16]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[16]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[17]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[17]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[18]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[18]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[19]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[19]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[1]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[20]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[20]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[21]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[21]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[22]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[22]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[23]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[23]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[24]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[24]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[25]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[25]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[26]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[26]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[27]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[27]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[28]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[28]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[29]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[29]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[2]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[30]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[30]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[31]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[31]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[3]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[4]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[4]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[5]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[5]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[6]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[6]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[7]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[7]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[8]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[8]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[9]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[9]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_web0}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_web0}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_wmask0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_wmask0[0]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_wmask0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_wmask0[1]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_wmask0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_wmask0[2]}]
+set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_wmask0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_wmask0[3]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[0]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[1]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[2]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[3]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[4]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[4]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[5]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[5]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[6]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[6]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[7]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[7]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[8]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[8]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[0]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[0]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[1]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[1]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[2]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[2]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[3]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[3]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[4]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[4]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[5]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[5]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[6]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[6]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[7]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[7]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[8]}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[8]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_csb0}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_csb0}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_csb1}]
+set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_csb1}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[0]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[10]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[10]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[11]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[11]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[12]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[12]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[13]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[13]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[14]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[14]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[15]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[15]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[16]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[16]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[17]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[17]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[18]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[18]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[19]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[19]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[1]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[20]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[20]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[21]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[21]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[22]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[22]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[23]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[23]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[24]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[24]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[25]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[25]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[26]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[26]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[27]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[27]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[28]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[28]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[29]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[29]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[2]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[30]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[30]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[31]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[31]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[3]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[4]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[4]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[5]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[5]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[6]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[6]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[7]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[7]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[8]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[8]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[9]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[9]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_web0}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_web0}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_wmask0[0]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_wmask0[0]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_wmask0[1]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_wmask0[1]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_wmask0[2]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_wmask0[2]}]
+set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_wmask0[3]}]
+set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_wmask0[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[10]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[11]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[12]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[13]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[14]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[15]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[16]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[17]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[18]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[19]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[20]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[21]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[22]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[23]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[24]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[25]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[26]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[27]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[28]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[29]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[30]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[31]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bl_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bl_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_bry_o}]
+set_output_delay 5.5000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_bry_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_cyc_o}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_cyc_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[10]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[11]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[12]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[13]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[14]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[15]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[16]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[17]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[18]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[19]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[20]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[21]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[22]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[23]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[24]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[25]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[26]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[27]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[28]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[29]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[30]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[31]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_stb_o}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_stb_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_we_o}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_we_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[10]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[11]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[12]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[13]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[14]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[15]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[16]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[17]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[18]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[19]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[20]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[21]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[22]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[23]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[24]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[25]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[26]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[27]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[28]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[29]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[30]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[31]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_adr_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_adr_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bl_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bl_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_bry_o}]
+set_output_delay 2.5000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_bry_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_sel_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_sel_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_sel_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_sel_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_sel_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_sel_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_sel_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_sel_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_stb_o}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_stb_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_we_o}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_we_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[10]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[11]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[12]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[13]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[14]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[15]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[16]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[17]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[18]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[19]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[20]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[21]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[22]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[23]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[24]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[25]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[26]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[27]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[28]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[29]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[30]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[31]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_adr_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_adr_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[10]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[10]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[11]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[11]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[12]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[12]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[13]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[13]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[14]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[14]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[15]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[15]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[16]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[16]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[17]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[17]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[18]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[18]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[19]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[19]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[20]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[20]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[21]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[21]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[22]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[22]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[23]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[23]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[24]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[24]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[25]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[25]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[26]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[26]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[27]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[27]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[28]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[28]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[29]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[29]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[30]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[30]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[31]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[31]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[4]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[4]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[5]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[5]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[6]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[6]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[7]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[7]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[8]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[8]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_o[9]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_o[9]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_sel_o[0]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_sel_o[0]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_sel_o[1]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_sel_o[1]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_sel_o[2]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_sel_o[2]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_sel_o[3]}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_sel_o[3]}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_stb_o}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_stb_o}]
+set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_we_o}]
+set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_we_o}]
+set_false_path\
+    -from [list [get_ports {cfg_dcache_force_flush}]\
+           [get_ports {cfg_dcache_pfet_dis}]\
+           [get_ports {cfg_icache_ntag_pfet_dis}]\
+           [get_ports {cfg_icache_pfet_dis}]\
+           [get_ports {cfg_sram_lphase[0]}]\
+           [get_ports {cfg_sram_lphase[1]}]\
+           [get_ports {cpu_intf_rst_n}]\
+           [get_ports {pwrup_rst_n}]\
+           [get_ports {wb_rst_n}]]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {core_clk_skew}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_req_ack}]
+set_load -pin_load 0.0334 [get_ports {core_icache_req_ack}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_clk0}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_clk1}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_csb0}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_csb1}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_web0}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_clk0}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_clk1}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_csb0}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_csb1}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_web0}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bry_o}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_stb_o}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_we_o}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bry_o}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_stb_o}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_we_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_skew}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_bry_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_stb_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_we_o}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dcache_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core_dmem_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_resp[1]}]
+set_load -pin_load 0.0334 [get_ports {core_icache_resp[0]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[8]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[7]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[6]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[5]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[4]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[3]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[2]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[1]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr0[0]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[8]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[7]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[6]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[5]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[4]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[3]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[2]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[1]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_addr1[0]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[31]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[30]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[29]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[28]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[27]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[26]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[25]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[24]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[23]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[22]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[21]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[20]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[19]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[18]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[17]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[16]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[15]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[14]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[13]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[12]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[11]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[10]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[9]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[8]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[7]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[6]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[5]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[4]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[3]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[2]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[1]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_din0[0]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_wmask0[3]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_wmask0[2]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_wmask0[1]}]
+set_load -pin_load 0.0334 [get_ports {dcache_mem_wmask0[0]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[8]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[7]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[6]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[5]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[4]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[3]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[2]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[1]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr0[0]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[8]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[7]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[6]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[5]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[4]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[3]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[2]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[1]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_addr1[0]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[31]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[30]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[29]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[28]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[27]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[26]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[25]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[24]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[23]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[22]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[21]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[20]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[19]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[18]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[17]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[16]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[15]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[14]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[13]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[12]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[11]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[10]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[9]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[8]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[7]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[6]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[5]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[4]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[3]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[2]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[1]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_din0[0]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_wmask0[3]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_wmask0[2]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_wmask0[1]}]
+set_load -pin_load 0.0334 [get_ports {icache_mem_wmask0[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_bl_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wb_dcache_sel_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_bl_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wb_icache_sel_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_bl_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_bl_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_bl_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[0]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_bypass_dcache}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_bypass_icache}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_dcache_force_flush}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_dcache_pfet_dis}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_icache_ntag_pfet_dis}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_icache_pfet_dis}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_cmd}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_req}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cpu_intf_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pwrup_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_err_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_lack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_err_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_lack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_err_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_lack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_ccska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sram_lphase[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sram_lphase[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_wcska[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_wcska[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_wcska[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_wcska[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dcache_width[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_bl[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_bl[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_bl[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_dmem_width[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_bl[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_bl[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_bl[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_width[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_icache_width[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout0[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dcache_mem_dout1[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {icache_mem_dout1[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dcache_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_icache_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[0]}]
+set_case_analysis 0 [get_ports {cfg_ccska[0]}]
+set_case_analysis 0 [get_ports {cfg_ccska[1]}]
+set_case_analysis 0 [get_ports {cfg_ccska[2]}]
+set_case_analysis 0 [get_ports {cfg_ccska[3]}]
+set_case_analysis 0 [get_ports {cfg_wcska[0]}]
+set_case_analysis 0 [get_ports {cfg_wcska[1]}]
+set_case_analysis 0 [get_ports {cfg_wcska[2]}]
+set_case_analysis 0 [get_ports {cfg_wcska[3]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_transition 1.0000 [current_design]
+set_max_capacitance 0.2000 [current_design]
+set_max_fanout 10.0000 [current_design]
diff --git a/signoff/pinmux_top/OPENLANE_VERSION b/signoff/pinmux_top/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/pinmux_top/OPENLANE_VERSION
+++ b/signoff/pinmux_top/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/pinmux_top/PDK_SOURCES b/signoff/pinmux_top/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/pinmux_top/PDK_SOURCES
+++ b/signoff/pinmux_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/signoff/qspim_top/OPENLANE_VERSION b/signoff/qspim_top/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/qspim_top/OPENLANE_VERSION
+++ b/signoff/qspim_top/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/qspim_top/PDK_SOURCES b/signoff/qspim_top/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/qspim_top/PDK_SOURCES
+++ b/signoff/qspim_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/user_project_wrapper/OPENLANE_VERSION
+++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/user_project_wrapper/PDK_SOURCES
+++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/wb_host/OPENLANE_VERSION
+++ b/signoff/wb_host/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/wb_host/PDK_SOURCES
+++ b/signoff/wb_host/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/wb_interconnect/OPENLANE_VERSION
+++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/wb_interconnect/PDK_SOURCES
+++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/signoff/ycr2_iconnect/OPENLANE_VERSION b/signoff/ycr2_iconnect/OPENLANE_VERSION
index fabca1a..1888caa 100644
--- a/signoff/ycr2_iconnect/OPENLANE_VERSION
+++ b/signoff/ycr2_iconnect/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/ycr2_iconnect/PDK_SOURCES b/signoff/ycr2_iconnect/PDK_SOURCES
index ef91c87..3b6c758 100644
--- a/signoff/ycr2_iconnect/PDK_SOURCES
+++ b/signoff/ycr2_iconnect/PDK_SOURCES
@@ -1 +1 @@
-open_pdks 3af133706e554a740cfe60f21e773d9eaa41838c
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/ycr_core_top/OPENLANE_VERSION
+++ b/signoff/ycr_core_top/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/ycr_core_top/PDK_SOURCES
+++ b/signoff/ycr_core_top/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION
index 1234be5..1888caa 100644
--- a/signoff/ycr_intf/OPENLANE_VERSION
+++ b/signoff/ycr_intf/OPENLANE_VERSION
@@ -1 +1 @@
-OpenLane 7f0486c949c21042e0a670dd77d2d654ad189483
+OpenLane 73bc7f8a736d6f2a2d68168daea3e7718d4b6208
diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES
index f8d3b3a..3b6c758 100644
--- a/signoff/ycr_intf/PDK_SOURCES
+++ b/signoff/ycr_intf/PDK_SOURCES
@@ -1 +1 @@
-open_pdks a519523b0d9bc913a6f87a5eed083597ed9e2e93
+open_pdks b8c6129fb60851c452a3136c2b8c603bb92cb180
diff --git a/sta/scripts/ycr_intf.tcl b/sta/scripts/ycr_intf.tcl
new file mode 100644
index 0000000..8c444b1
--- /dev/null
+++ b/sta/scripts/ycr_intf.tcl
@@ -0,0 +1,50 @@
+
+    set ::env(USER_ROOT)    ".."
+    set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-7/caravel"
+
+    read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib	
+
+	# User project netlist
+    read_verilog $::env(USER_ROOT)/verilog/gl/ycr_intf.v
+
+
+	link_design ycr_intf
+
+
+	## User Project Spef
+    read_spef  $::env(USER_ROOT)/spef/ycr_intf.spef
+
+
+	read_sdc -echo ./sdc/ycr_intf.sdc	
+	set_propagated_clock [all_clocks]
+
+    report_annotated_check -list_annotated
+    report_annotated_check -list_not_annotated
+
+	check_setup  -verbose >  unconstraints.rpt
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_worst_slack -max 	
+	report_worst_slack -min 	
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10	
+	report_check_types -max_slew -max_capacitance -max_fanout -violators  > slew.cap.fanout.vio.rpt
+
+
+
diff --git a/sta/sdc/ycr_intf.sdc b/sta/sdc/ycr_intf.sdc
new file mode 100644
index 0000000..97c143c
--- /dev/null
+++ b/sta/sdc/ycr_intf.sdc
@@ -0,0 +1,260 @@
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
+create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
+
+create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache mem clock0} [get_ports dcache_mem_clk0]
+create_generated_clock -name dcache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache mem clock1} [get_ports dcache_mem_clk1]
+create_generated_clock -name icache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache mem clock0} [get_ports icache_mem_clk0]
+create_generated_clock -name icache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache mem clock1} [get_ports icache_mem_clk1]
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.5000 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {core_clk dcache_mem_clk0 dcache_mem_clk1 icache_mem_clk0 icache_mem_clk1}]\
+ -group [get_clocks {wb_clk}] -comment {Async Clock group}
+
+# Set case analysis
+set_case_analysis  0 [get_ports {cfg_ccska[3]}]
+set_case_analysis  0 [get_ports {cfg_ccska[2]}]
+set_case_analysis  0 [get_ports {cfg_ccska[1]}]
+set_case_analysis  0 [get_ports {cfg_ccska[0]}]
+
+set_case_analysis  0 [get_ports {cfg_wcska[3]}]
+set_case_analysis  0 [get_ports {cfg_wcska[2]}]
+set_case_analysis  0 [get_ports {cfg_wcska[1]}]
+set_case_analysis  0 [get_ports {cfg_wcska[0]}]
+
+#Assumed config are static
+set_false_path -from  [get_ports {cfg_dcache_force_flush}]
+set_false_path -from  [get_ports {cfg_dcache_pfet_dis}]
+set_false_path -from  [get_ports {cfg_icache_ntag_pfet_dis}]
+set_false_path -from  [get_ports {cfg_icache_pfet_dis}]
+
+
+set_false_path -from  [get_ports {cfg_sram_lphase[1]}]
+set_false_path -from  [get_ports {cfg_sram_lphase[0]}]
+
+#All reset has reset synchronization logic inside block ??
+set_false_path -from  [get_ports {cpu_intf_rst_n}]
+set_false_path -from  [get_ports {pwrup_rst_n}]
+set_false_path -from  [get_ports {wb_rst_n}]
+
+#CORE Instruction Memory Interface
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_resp[*]}]
+
+
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_cmd}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_addr[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_bl[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_width[*]}]
+
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_bl[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_icache_width[*]}]
+
+#Wishbone ICACHE I/F
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_sel_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_bl_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_bry_o}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_sel_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_bl_o[*]}]
+set_output_delay -max 2.5000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_bry_o}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_lack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_err_i}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_lack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_icache_err_i}]
+
+
+
+# CORE Data Memory Interface
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_resp[*]}]
+
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_cmd}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_width[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_addr[*]}]
+set_input_delay -min 4.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_wdata[*]}]
+
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_req}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_cmd}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_width[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_addr[*]}]
+set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dcache_wdata[*]}]
+
+
+# Data memory interface from router to WB bridge
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_resp[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_width[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_wdata[*]}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_width[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay  [get_ports {core_dmem_wdata[*]}]
+
+#WB Data Memory Interface
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_sel_o[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_dat_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_sel_o[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_err_i}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wbd_dmem_err_i}]
+
+
+## ICACHE PORT-0 SRAM Memory I/F
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_csb0}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_web0}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_addr0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_wmask0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_din0[*]}]
+
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_csb0}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_web0}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_addr0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_wmask0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay  [get_ports {icache_mem_din0[*]}]
+
+## ICACHE PORT-1 SRAM Memory I/F
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_csb1}]
+set_output_delay -min -1.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_addr1[*]}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_csb1}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_addr1[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_dout1[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay  [get_ports {icache_mem_dout1[*]}]
+
+
+# Wishbone DCACHE I/F
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bl_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bry_o}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_cyc_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bl_o[*]}]
+set_output_delay -max 5.5000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_bry_o}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_lack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_lack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay  [get_ports {wb_dcache_err_i}]
+
+## DCACHE PORT-0 SRAM I/F
+set_output_delay -min -1.2500 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_din0[*]}]
+
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_csb0}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_web0}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_addr0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_wmask0[*]}]
+set_output_delay -max 1.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_din0[*]}]
+
+set_input_delay  -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_dout0[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay  [get_ports {dcache_mem_dout0[*]}]
+
+
+## DCACHE PORT-1 SRAM I/F
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_csb1}]
+set_output_delay -min -1.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_addr1[*]}]
+
+set_output_delay -max 1.000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_csb1}]
+set_output_delay -max 1.000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_addr1[*]}]
+
+set_input_delay  -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_dout1[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay  [get_ports {dcache_mem_dout1[*]}]
+
+
+###############################################################################
+# Environment
+###############################################################################
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} [all_inputs]
+set cap_load 0.0334
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+set_max_transition 1.00 [current_design]
+set_max_capacitance 0.2 [current_design]
+set_max_fanout 10 [current_design]
+###############################################################################
+# Design Rules
+###############################################################################
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index a1faaf8..5441c46 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = user_basic user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_aes user_spi_isp user_timer user_uart_master user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 user_mcore_test1 user_mcore_test2 user_aes_core user_fpu_core
+PATTERNS = user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_basic user_spi_isp user_timer user_uart_master  user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master_test1 uart_master_test2 wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 user_mcore_test1 user_mcore_test2 user_aes_core user_fpu_core user_aes user_rtc
 
 all:  ${PATTERNS}
 	echo "################# RTL Test case Summary #####################" > regression.rpt
diff --git a/verilog/dv/common/agents/user_tasks.sv b/verilog/dv/common/agents/user_tasks.sv
index 75cd3e9..c9ba9f1 100644
--- a/verilog/dv/common/agents/user_tasks.sv
+++ b/verilog/dv/common/agents/user_tasks.sv
@@ -90,7 +90,7 @@
 begin
    // Run in Fast Sim Mode
    `ifdef GL
-       force u_top.u_wb_host._10252_.Q= 1'b1; 
+       force u_top.u_wb_host._10258_.Q= 1'b1; 
    `else
        force u_top.u_wb_host.u_reg.u_fastsim_buf.X = 1'b1; 
     `endif
diff --git a/verilog/dv/user_aes_core/Makefile b/verilog/dv/user_aes_core/Makefile
new file mode 100644
index 0000000..8dc518c
--- /dev/null
+++ b/verilog/dv/user_aes_core/Makefile
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+ 
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = user_aes_core
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+	${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  ${PATTERN}.c -o ${PATTERN}.o
+	${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  $(YIFIVE_FIRMWARE_PATH)/sc_print.c -o sc_print.o
+	${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
+	${GCC_PREFIX}-gcc -o ${PATTERN}.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld ${PATTERN}.o sc_print.o crt.o -nostartfiles -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+	${GCC_PREFIX}-objcopy -O verilog ${PATTERN}.elf ${PATTERN}.hex
+	${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump
+	rm crt.o ${PATTERN}.o
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+   endif
+else  
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
+endif
+
+%.vcd: %.vvp
+	vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_aes_core/user_aes_core.c b/verilog/dv/user_aes_core/user_aes_core.c
new file mode 100644
index 0000000..43b3dec
--- /dev/null
+++ b/verilog/dv/user_aes_core/user_aes_core.c
@@ -0,0 +1,196 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
+#define SC_SIM_OUTPORT (0xf0000000)
+
+
+#include <stdio.h>
+#include <string.h>
+#include <stdint.h>
+
+// Enable ECB, CTR and CBC mode. Note this can be done before including aes.h or at compile-time.
+// E.g. with GCC by using the -D flag: gcc -c aes.c -DCBC=0 -DCTR=1 -DECB=1
+#define CBC 1
+#define AES_BLOCKLEN 16
+
+//#include "aes.h"
+#include "int_reg_map.h"
+#include "common_misc.h"
+#include "common_bthread.h"
+
+static const uint8_t key[]      = { 0x44, 0x69, 0x6e, 0x65, 0x73, 0x68, 0x20, 0x20, 0x20, 0x41, 0x6e, 0x6e, 0x61, 0x79, 0x79, 0x61 };
+static const uint8_t enc_text[] = { 0xFE, 0x67, 0x23, 0x29, 0xDE, 0x2C, 0x41, 0xCE, 0x75, 0x79, 0x28, 0x12, 0xA0, 0x35, 0x66, 0xD0, 
+                                    0xC4, 0xBB, 0x67, 0x66, 0xAC, 0x09, 0x5B, 0xF7, 0xA9, 0xAF, 0x5D, 0x1C, 0xEC, 0xCE, 0x44, 0x54, 
+                                    0x44, 0x84, 0xCF, 0xBB, 0x0A, 0x37, 0x7A, 0xC4, 0x41, 0x3F, 0xD1, 0x86, 0x28, 0xBC, 0x18, 0x0C, 
+                                    0x8D, 0x08, 0xB4, 0xAB, 0x58, 0x88, 0xC0, 0xBF, 0x3D, 0xBC, 0xDD, 0x15, 0xB2, 0x31, 0x98, 0x66, 
+                                    0x00, 0xA9, 0x40, 0x2C, 0x88, 0x4C, 0xD4, 0x85, 0x1A, 0xF8, 0xD8, 0xB3, 0x42, 0xE4, 0xF3, 0x3D, 
+                                    0xBC, 0xB2, 0x2A, 0x5A, 0x6A, 0x24, 0x93, 0x24, 0xAC, 0xC1, 0x05, 0xE7, 0xAE, 0x75, 0xD1, 0xB2, 
+                                    0x90, 0x9A, 0xE8, 0xE5, 0xEF, 0x57, 0x24, 0x08, 0x74, 0xDA, 0x98, 0x85, 0x56, 0xF0, 0x38, 0xFB, 
+                                    0xF2, 0x04, 0xD1, 0xE9, 0x77, 0x2B, 0x9F, 0x62, 0x37, 0x0B, 0x08, 0x0F, 0x40, 0xC1, 0x70, 0xC1, 
+                                    0x11, 0x76, 0xC1, 0x61, 0xAF, 0x65, 0x57, 0x81, 0x31, 0x0C, 0xE9, 0x02, 0x9B, 0x75, 0x0F, 0x12 };
+
+static const uint8_t plain_text[]= { 0x52, 0x69, 0x73, 0x63, 0x64, 0x75, 0x69, 0x6e, 0x6f, 0x20, 0x69, 0x73, 0x20, 0x61, 0x20, 0x53, 
+                                    0x69, 0x6e, 0x67, 0x6c, 0x65, 0x20, 0x33, 0x32, 0x20, 0x62, 0x69, 0x74, 0x20, 0x52, 0x49, 0x53, 
+                                    0x43, 0x20, 0x56, 0x20, 0x62, 0x61, 0x73, 0x65, 0x64, 0x20, 0x53, 0x4f, 0x43, 0x20, 0x64, 0x65, 
+                                    0x73, 0x69, 0x67, 0x6e, 0x20, 0x70, 0x69, 0x6e, 0x20, 0x63, 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, 
+                                    0x62, 0x6c, 0x65, 0x20, 0x74, 0x6f, 0x20, 0x61, 0x72, 0x64, 0x75, 0x69, 0x6e, 0x6f, 0x20, 0x70, 
+                                    0x6c, 0x61, 0x74, 0x66, 0x6f, 0x72, 0x6d, 0x20, 0x61, 0x6e, 0x64, 0x20, 0x74, 0x68, 0x69, 0x73, 
+                                    0x20, 0x73, 0x6f, 0x63, 0x20, 0x74, 0x61, 0x72, 0x67, 0x65, 0x74, 0x65, 0x64, 0x20, 0x66, 0x6f, 
+                                    0x72, 0x20, 0x65, 0x66, 0x61, 0x62, 0x6c, 0x65, 0x73, 0x73, 0x20, 0x53, 0x68, 0x75, 0x74, 0x74 };
+
+static void phex(uint8_t* str,uint8_t len);
+static int test_encrypt(void);
+static int test_decrypt(void);
+
+int main(void)
+{
+    int exit;
+
+   //printf("\nTesting AES128\n\n");
+
+   reg_glbl_cfg0 |= 0x1F;       // Remove Reset for UART
+   reg_glbl_multi_func &=0x7FFFFFFF; // Disable UART Master Bit[31] = 0
+   reg_glbl_multi_func |=0x100; // Enable UART Multi func
+   reg_gpio_dsel  =0xFF00; // Enable PORT B As output
+   reg_uart0_ctrl = 0x07;       // Enable Uart Access {3'h0,2'b00,1'b1,1'b1,1'b1}
+
+   //// GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
+   //// bit[7:0]   - core-0
+   //// bit[15:8]  - core-1
+   //// bit[23:16] - core-2
+   //// bit[31:24] - core-3
+
+    reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main 
+
+    reg_gpio_odata  = 0x00000100; 
+    reg_glbl_soft_reg_0  = 0x00000000; 
+    exit = test_encrypt();
+    reg_gpio_odata  = 0x00000200; 
+
+    reg_glbl_soft_reg_0  = exit;
+    exit += test_decrypt();
+    reg_gpio_odata  = 0x00000300; 
+    reg_glbl_soft_reg_0  = exit;
+
+    if(exit == 0) {
+        reg_gpio_odata  = 0x00001800; 
+    } else {
+        reg_gpio_odata  = 0x0000A800; 
+    }
+
+    return exit;
+}
+
+
+// prints string as hex
+static void phex(uint8_t* str,uint8_t len )
+{
+
+    uint32_t iPayload;
+    unsigned char i,j;
+    for (i = 0; i < len; ++i)
+        printf("%.2x", str[i]);
+
+    printf("\n");
+
+    for (i = 0; i < len/4; ++i) {
+        iPayload = 0x00;
+        for (j = 0; j < 4; ++j) {
+           iPayload = (iPayload << 8) | str[(i*4)+j];
+        }
+        printf("%0x", iPayload);
+    }
+           
+    printf("\n");
+}
+
+static int test_decrypt(void)
+{
+
+    uint8_t ErrCnt = 0x00;
+    unsigned char i,j;
+
+
+   for (i = 0; i < 8; i += 1) {
+        // Write 16B Encryption Text and Key
+        for (j = 0; j < 16; ++j) {
+          *(&reg_aes_dec_key_bptr-j) = key[j];
+          *(&reg_aes_dec_text_in_bptr-j) = enc_text[(i*AES_BLOCKLEN)+j];
+
+        }
+        // Enable the Decrption Engine and Wait for completion
+        reg_aes_dec_ctrl = 0x1;
+        while(reg_aes_dec_ctrl);
+
+        // Validate the 16B of Encrypted Data
+        for (j = 0; j < 16; ++j) {
+           if(plain_text[(i*AES_BLOCKLEN)+j] != *(&reg_aes_dec_text_out_bptr-j)) {
+             ErrCnt++;
+           }
+
+        }
+   }
+   
+
+    if (ErrCnt == 0) {
+      //printf("SUCCESS!\n");
+	  return(0);
+    } else {
+      //printf("FAILURE!\n");
+	  return(1);
+    }
+}
+
+static int test_encrypt(void)
+{
+    uint8_t ErrCnt = 0x00;
+    unsigned char i,j;
+
+
+   for (i = 0; i < 8; i += 1) {
+        // Write 16B Plan Text and Key
+        for (j = 0; j < 16; ++j) {
+          *(&reg_aes_enc_key_bptr-j) = key[j];
+          *(&reg_aes_enc_text_in_bptr-j) = plain_text[(i*AES_BLOCKLEN)+j];
+
+        }
+        // Enable the Encryption Engine and Wait for completion
+        reg_aes_enc_ctrl = 0x1;
+        while(reg_aes_enc_ctrl);
+
+        // Validate the 16B of Encrypted Data
+        for (j = 0; j < 16; ++j) {
+           if(enc_text[(i*AES_BLOCKLEN)+j] != *(&reg_aes_enc_text_out_bptr-j)) {
+             ErrCnt++;
+           }
+
+        }
+     }
+
+    if (ErrCnt == 0) {
+        //printf("SUCCESS!\n");
+	return(0);
+    } else {
+        //printf("FAILURE!\n");
+	return(1);
+    }
+}
+
+
+
+
+
diff --git a/verilog/dv/user_aes_core/user_aes_core_tb.v b/verilog/dv/user_aes_core/user_aes_core_tb.v
new file mode 100644
index 0000000..fbb54f7
--- /dev/null
+++ b/verilog/dv/user_aes_core/user_aes_core_tb.v
@@ -0,0 +1,294 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Standalone User validation Test bench                       ////
+////                                                              ////
+////  This file is part of the Riscduino cores project            ////
+////                                                              ////
+////  Description                                                 ////
+////      To validate AES IP Encription & Decription              ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 7th Nov 2022, Dinesh A                              ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+module user_aes_core_tb;
+
+parameter real CLK1_PERIOD  = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
+
+`include "user_tasks.sv"
+
+
+//----------------------------------
+// Uart Configuration
+// ---------------------------------
+reg [1:0]  uart_data_bit        ;
+reg	       uart_stop_bits       ; // 0: 1 stop bit; 1: 2 stop bit;
+reg	       uart_stick_parity    ; // 1: force even parity
+reg	       uart_parity_en       ; // parity enable
+reg	       uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+reg [7:0]      uart_data            ;
+reg [15:0]     uart_divisor         ;	// divided by n * 16
+reg [15:0]     uart_timeout         ;// wait time limit
+
+reg [15:0]     uart_rx_nu           ;
+reg [15:0]     uart_tx_nu           ;
+reg [7:0]      uart_write_data [0:39];
+reg 	       uart_fifo_enable     ;	// fifo mode disable
+
+
+
+     /************* Port-B Mapping **********************************
+     *   Pin-14       PB0/CLKO/ICP1             digital_io[16]
+     *   Pin-15       PB1/SS[1]OC1A(PWM3)       digital_io[17]
+     *   Pin-16       PB2/SS[0]/OC1B(PWM4)      digital_io[18]
+     *   Pin-17       PB3/MOSI/OC2A(PWM5)       digital_io[19]
+     *   Pin-18       PB4/MISO                  digital_io[20]
+     *   Pin-19       PB5/SCK                   digital_io[21]
+     *   Pin-9        PB6/XTAL1/TOSC1           digital_io[11]
+     *   Pin-10       PB7/XTAL2/TOSC2           digital_io[12]
+     *   ********************************************************/
+
+     wire [7:0]  port_b_in = {   io_out[12],
+		                         io_out[11],
+		                         io_out[21],
+		                         io_out[20],
+			                     io_out[19],
+			                     io_out[18],
+		                         io_out[17],
+		                         io_out[16]
+			     };
+	initial begin
+		test_fail = 0;
+                wbd_ext_cyc_i ='h0;  // strobe/request
+                wbd_ext_stb_i ='h0;  // strobe/request
+                wbd_ext_adr_i ='h0;  // address
+                wbd_ext_we_i  ='h0;  // write
+                wbd_ext_dat_i ='h0;  // data output
+                wbd_ext_sel_i ='h0;  // byte enable
+	end
+
+	`ifdef WFDUMP
+	   initial begin
+	   	$dumpfile("simx.vcd");
+	   	$dumpvars(2, user_aes_core_tb);
+	   	$dumpvars(0, user_aes_core_tb.u_top.u_aes);
+	   	$dumpvars(0, user_aes_core_tb.u_top.u_riscv_top);
+	   	$dumpvars(0, user_aes_core_tb.u_top.u_pinmux);
+	   end
+       `endif
+
+	initial begin
+
+	       $value$plusargs("risc_core_id=%d", d_risc_id);
+           init();
+
+               uart_data_bit           = 2'b11;
+               uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
+               uart_stick_parity       = 0; // 1: force even parity
+               uart_parity_en          = 0; // parity enable
+               uart_even_odd_parity    = 1; // 0: odd parity; 1: even parity
+               uart_divisor            = 15;// divided by n * 16
+               uart_timeout            = 500;// wait time limit
+               uart_fifo_enable        = 0;	// fifo mode disable
+
+               #200; // Wait for reset removal
+               repeat (10) @(posedge clock);
+               $display("Monitor: Standalone User Uart Test Started");
+               
+               // Remove Wb Reset
+               //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+               // Enable UART Multi Functional Ports
+               wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h100);
+               
+                wait_riscv_boot();
+               repeat (2) @(posedge clock);
+               #1;
+		// Remove all the reset
+		if(d_risc_id == 0) begin
+		     $display("STATUS: Working with Risc core 0");
+                   //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+		end else if(d_risc_id == 1) begin
+		     $display("STATUS: Working with Risc core 1");
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+		end else if(d_risc_id == 2) begin
+		     $display("STATUS: Working with Risc core 2");
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+		end else if(d_risc_id == 3) begin
+		     $display("STATUS: Working with Risc core 3");
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+		end
+
+               repeat (100) @(posedge clock);  // wait for Processor Get Ready
+
+               tb_uart.uart_init;
+               wb_user_core_write(`ADDR_SPACE_UART0+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1});  
+               tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
+                                              uart_stick_parity, uart_timeout, uart_divisor);
+
+		// Set the PORT-B Direction as Output
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h0000FF00);
+		// Set the GPIO Output data: 0x00000000
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h0000000);
+   
+              fork
+	          begin
+                     repeat (1400000) @(posedge clock); 
+	          end
+	          begin
+                     wait(port_b_in == 8'h18 || port_b_in == 8'hA8);
+	          end
+	          begin
+                     while(1) begin
+                        wb_user_core_read(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,read_data);
+                        repeat (1000) @(posedge clock); 
+                     end
+	          end
+               join_any
+	
+	       wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h00000000);
+
+               $display("###################################################");
+               if(test_fail == 0) begin
+                  `ifdef GL
+                      $display("Monitor: %m (GL) Passed");
+                  `else
+                      $display("Monitor: %m (RTL) Passed");
+                  `endif
+               end else begin
+                   `ifdef GL
+                       $display("Monitor: %m (GL) Failed");
+                   `else
+                       $display("Monitor: %m (RTL) Failed");
+                   `endif
+                end
+               $display("###################################################");
+               #100
+               $finish;
+
+	end
+
+
+
+// SSPI Slave I/F
+assign io_in[5]  = 1'b1; // RESET
+assign io_in[21] = 1'b0 ; // SPIS SCK 
+
+
+//------------------------------------------------------
+//  Integrate the Serial flash with qurd support to
+//  user core using the gpio pads
+//  ----------------------------------------------------
+
+   wire flash_clk = io_out[28];
+   wire flash_csb = io_out[29];
+   // Creating Pad Delay
+   wire #1 io_oeb_29 = io_oeb[33];
+   wire #1 io_oeb_30 = io_oeb[34];
+   wire #1 io_oeb_31 = io_oeb[35];
+   wire #1 io_oeb_32 = io_oeb[36];
+   tri  #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
+   tri  #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
+   tri  #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
+   tri  #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+
+   assign io_in[33] = flash_io0;
+   assign io_in[34] = flash_io1;
+   assign io_in[35] = flash_io2;
+   assign io_in[36] = flash_io3;
+
+   // Quard flash
+     s25fl256s #(.mem_file_name("user_aes_core.hex"),
+	         .otp_file_name("none"),
+                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
+		 u_spi_flash_256mb (
+           // Data Inputs/Outputs
+       .SI      (flash_io0),
+       .SO      (flash_io1),
+       // Controls
+       .SCK     (flash_clk),
+       .CSNeg   (flash_csb),
+       .WPNeg   (flash_io2),
+       .HOLDNeg (flash_io3),
+       .RSTNeg  (!wb_rst_i)
+
+       );
+
+
+//---------------------------
+//  UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd   = io_out[7];
+assign io_in[6]  = uart_rxd ;
+ 
+uart_agent tb_uart(
+	.mclk                (clock              ),
+	.txd                 (uart_rxd           ),
+	.rxd                 (uart_txd           )
+	);
+
+
+
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 4f74553..826a0ef 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -173,7 +173,7 @@
                               (strap_skew == 2'b01) ?  CLK_SKEW1_RESET_VAL[27:24] + 2 :
                               (strap_skew == 2'b10) ?  CLK_SKEW1_RESET_VAL[27:24] + 4 : CLK_SKEW1_RESET_VAL[27:24]-4;
 
-assign skew_config[31:28] = 4'b0;
+assign skew_config[31:28] = CLK_SKEW1_RESET_VAL[31:28];
 
 //----------------------------------------------------------
 reg [3:0] cpu_clk_cfg,wbs_clk_cfg;
@@ -667,7 +667,7 @@
 input real exp_period;
 begin
    `ifdef GL
-   force clock_mon = u_top.u_wb_host._10366_.Q;
+   force clock_mon = u_top.u_wb_host._10372_.Q;
     `else
    force clock_mon = u_top.u_wb_host.u_uart2wb.u_core.line_clk_16x;
     `endif
diff --git a/verilog/dv/user_fpu_core/Makefile b/verilog/dv/user_fpu_core/Makefile
new file mode 100644
index 0000000..34afdb1
--- /dev/null
+++ b/verilog/dv/user_fpu_core/Makefile
@@ -0,0 +1,96 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+ 
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv32i/
+
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
+GCC_PREFIX?=riscv32-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = user_fpu_core
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+	${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  ${PATTERN}.c -o ${PATTERN}.o
+	${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  $(YIFIVE_FIRMWARE_PATH)/sc_print.c -o sc_print.o
+	${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
+	${GCC_PREFIX}-gcc -o ${PATTERN}.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld ${PATTERN}.o sc_print.o crt.o -nostartfiles -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+	${GCC_PREFIX}-objcopy -O verilog ${PATTERN}.elf ${PATTERN}.hex
+	${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump
+	rm crt.o ${PATTERN}.o
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+   endif
+else  
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
+endif
+
+%.vcd: %.vvp
+	vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_fpu_core/user_fpu_core.c b/verilog/dv/user_fpu_core/user_fpu_core.c
new file mode 100644
index 0000000..c5e6832
--- /dev/null
+++ b/verilog/dv/user_fpu_core/user_fpu_core.c
@@ -0,0 +1,226 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021, Dinesh Annayya
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
+// //////////////////////////////////////////////////////////////////////////
+#define SC_SIM_OUTPORT (0xf0000000)
+
+
+#include <stdio.h>
+#include <string.h>
+#include <stdint.h>
+
+#include "int_reg_map.h"
+#include "common_misc.h"
+#include "common_bthread.h"
+
+#define CMD_FPU_SP_ADD  0x1 // Single Precision (32 bit) Adder 
+#define CMD_FPU_SP_MUL  0x2 // Single Precision (32 bit) Multipler
+#define CMD_FPU_SP_DIV  0x3 // Single Precision (32 bit) Divider
+#define CMD_FPU_SP_F2I  0x4 // Single Precision (32 bit) Float to Integer
+#define CMD_FPU_SP_I2F  0x5 // Single Precision (32 bit) Integer to Float
+#define CMD_FPU_DP_ADD  0x9 // Double Precision (64 bit) Adder
+#define CMD_FPU_DP_MUL  0xA // Double Precision (64 bit) Multipler
+#define CMD_FPU_DP_DIV  0xB // Double Precision (64 bit) Divider
+
+int fpu_check(uint8_t Cmd, uint32_t Din1, uint32_t Din2, uint32_t Result);
+
+int main(void)
+{
+    int exit;
+
+   //printf("\nTesting FPU CORE LOGIC\n\n");
+
+   reg_glbl_cfg0 |= 0x1F;       // Remove Reset for UART
+   reg_glbl_multi_func &=0x7FFFFFFF; // Disable UART Master Bit[31] = 0
+   reg_glbl_multi_func |=0x100; // Enable UART Multi func
+   reg_gpio_dsel  =0xFF00; // Enable PORT B As output
+   reg_uart0_ctrl = 0x07;       // Enable Uart Access {3'h0,2'b00,1'b1,1'b1,1'b1}
+
+   //// GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
+   //// bit[7:0]   - core-0
+   //// bit[15:8]  - core-1
+   //// bit[23:16] - core-2
+   //// bit[31:24] - core-3
+
+    reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main 
+
+    reg_gpio_odata  = 0x00000100; 
+    reg_glbl_soft_reg_0  = 0x00000000; 
+    //--------------------------------------
+    // Floating Point Addition
+    //--------------------------------------
+
+    // TEST-1: Addition: Din1: 0.500000 Din2: 1.500000 Res: 2.000000
+    exit = fpu_check(CMD_FPU_SP_ADD,0x3f000000,0x3fc00000,0x40000000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-2: Addition: Din1: 0.500000 Din2: 1.250000 Res: 1.750000
+    exit += fpu_check(CMD_FPU_SP_ADD,0x3f000000,0x3fa00000,0x3fe00000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-3: Addition: Din1: 0.500000 Din2: 0.250000 Res: 0.750000
+    exit += fpu_check(CMD_FPU_SP_ADD,0x3f000000,0x3e800000,0x3f400000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-4: Addition: Din1: 2.000000 Din2: -2.000000 Res: 0.000000
+    exit += fpu_check(CMD_FPU_SP_ADD,0x40000000,0xc0000000,0x00000000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-5: Addition: Din1: -0.000000 Din2: 0.000000 Res: 0.000000
+    exit += fpu_check(CMD_FPU_SP_ADD,0x83e73d5c,0x1c800000,0x1c800000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-6: Addition: Din1: -1.211871 Din2: -2.889479 Res: -4.101350
+    exit += fpu_check(CMD_FPU_SP_ADD,0xbf9b1e94,0xc038ed3a,0xc0833e42);
+    reg_glbl_soft_reg_0  = exit;
+
+    //--------------------------------------
+    // Floating Point Multiplication
+    //--------------------------------------
+    // TEST-1: Multiplier: Din1: 0.500000 Din2: 1.500000 Res: 0.750000
+    exit += fpu_check(CMD_FPU_SP_MUL,0x3f000000,0x3fc00000,0x3f400000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-2: Multiplier: Din1: 0.500000 Din2: 1.250000 Res: 0.625000
+    exit += fpu_check(CMD_FPU_SP_MUL,0x3f000000,0x3fa00000,0x3f200000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-3: Multiplier: Din1: 0.500000 Din2: 0.250000 Res: 0.125000
+    exit += fpu_check(CMD_FPU_SP_MUL,0x3f000000,0x3e800000,0x3e000000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-4: Multiplier: Din1: 0.000000 Din2: -0.000000 Res: -0.000000
+    exit += fpu_check(CMD_FPU_SP_MUL,0x22cb525a,0xadd79efa,0x912b406d);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-5: Multiplier: Din1: 2.000000 Din2: -2.000000 Res: -4.000000
+    exit += fpu_check(CMD_FPU_SP_MUL,0x40000000,0xc0000000,0xc0800000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-6: Multiplier: Din1: -1.211871 Din2: -2.889479 Res: 3.501675
+    exit += fpu_check(CMD_FPU_SP_MUL,0xbf9b1e94,0xc038ed3a,0x40601b72);
+    reg_glbl_soft_reg_0  = exit;
+
+    //--------------------------------------
+    // Floating Point Division
+    //--------------------------------------
+    // TEST-1: Division: Din1: 0.500000 Din2: 1.500000 Res: 0.750000
+    exit += fpu_check(CMD_FPU_SP_DIV,0x3f000000,0x3fc00000,0x3eaaaaab);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-2: Division: Din1: 0.500000 Din2: 1.250000 Res: 0.400000
+    exit += fpu_check(CMD_FPU_SP_DIV,0x3f000000,0x3fa00000,0x3ecccccd);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-3: Division: Din1: 0.500000 Din2: 0.250000 Res: 2.000000
+    exit += fpu_check(CMD_FPU_SP_DIV,0x3f000000,0x3e800000,0x40000000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-4: Division: Din1: 0.000000 Din2: -0.000000 Res: 0.000000
+    exit += fpu_check(CMD_FPU_SP_DIV,0x22cb525a,0xadd79efa,0xb47165bd);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-5: Division: Din1: 2.000000 Din2: -2.000000 Res: -1.000000
+    exit += fpu_check(CMD_FPU_SP_DIV,0x40000000,0xc0000000,0xbf800000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-6: Division: Din1: -1.211871 Din2: -2.889479 Res: 0.419408
+    exit += fpu_check(CMD_FPU_SP_DIV,0xbf9b1e94,0xc038ed3a,0x3ed6bca5);
+    reg_glbl_soft_reg_0  = exit;
+
+    //--------------------------------------
+    // Intger To Floating Point 
+    //--------------------------------------
+    // TEST-1: I2F: Input: 1069547520 Result: 1069547520.000000
+    exit += fpu_check(CMD_FPU_SP_I2F,0x3fc00000,0x0,0x4e7f0000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-2: I2F: Input: 1067450368 Result: 1067450368.000000
+    exit += fpu_check(CMD_FPU_SP_I2F,0x3fa00000,0x0,0x4e7e8000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-3: I2F: Input: 1048576000 Result: 1048576000.000000
+    exit += fpu_check(CMD_FPU_SP_I2F,0x3e800000,0x0,0x4e7a0000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-4: I2F: Input: 1075838976 Result: 1075838976.000000
+    exit += fpu_check(CMD_FPU_SP_I2F,0x40200000,0x0,0x4e804000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-5: I2F: Input: 1084017869 Result: 1084017920.000000
+    exit += fpu_check(CMD_FPU_SP_I2F,0x409ccccd,0x0,0x4e81399a);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-6: I2F: Input: -1071644672 Result: -1071644672.000000
+    exit += fpu_check(CMD_FPU_SP_I2F,0xc0200000,0x0,0xce7f8000);
+    reg_glbl_soft_reg_0  = exit;
+
+    //--------------------------------------
+    // Floating To Integer Point 
+    //--------------------------------------
+    // TEST-1: F2I: Input: 1.500000  Result: 1
+    exit += fpu_check(CMD_FPU_SP_F2I,0x3fc00000,0x0,0x00000001);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-2: F2I: Input: 1.250000  Result: 1
+    exit += fpu_check(CMD_FPU_SP_F2I,0x3fa00000,0x0,0x00000001);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-3: F2I: Input: 0.250000  Result: 0
+    exit += fpu_check(CMD_FPU_SP_F2I,0x3e800000,0x0,0x00000000);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-4: F2I: Input: 2.500000  Result: 2
+    exit += fpu_check(CMD_FPU_SP_F2I,0x40200000,0x0,0x00000002);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-5: F2I: Input: -2.500000  Result: -2
+    exit += fpu_check(CMD_FPU_SP_F2I,0xc0200000,0x0,0xfffffffe);
+    reg_glbl_soft_reg_0  = exit;
+
+    // TEST-6: F2I: Input: -222.800003  Result: -222
+    exit += fpu_check(CMD_FPU_SP_F2I,0xc35ecccd,0x0,0xffffff22);
+    reg_glbl_soft_reg_0  = exit;
+
+    if(exit == 0) {
+        reg_gpio_odata  = 0x00001800; 
+    } else {
+        reg_gpio_odata  = 0x0000A800; 
+    }
+
+    return exit;
+}
+
+int fpu_check(uint8_t Cmd, uint32_t Din1, uint32_t Din2, uint32_t Result){
+
+
+   reg_fpu_din1 = Din1;
+   reg_fpu_din2 = Din2;
+   reg_fpu_ctrl = Cmd | 0x80000000;
+
+   while(reg_fpu_ctrl & 0x80000000); // Wait for FPU completion
+  
+    reg_glbl_soft_reg_1  = reg_fpu_res;
+    reg_glbl_soft_reg_2  = Result;
+   if(reg_fpu_res != Result) return 1;
+   else return 0;
+     
+}
+
+
+
+
+
diff --git a/verilog/dv/user_fpu_core/user_fpu_core_tb.v b/verilog/dv/user_fpu_core/user_fpu_core_tb.v
new file mode 100644
index 0000000..e79506e
--- /dev/null
+++ b/verilog/dv/user_fpu_core/user_fpu_core_tb.v
@@ -0,0 +1,297 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Standalone User validation Test bench                       ////
+////                                                              ////
+////  This file is part of the Riscduino cores project            ////
+////                                                              ////
+////  Description                                                 ////
+////      To validate FPU Core                                    ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 10th Nov 2022, Dinesh A                              ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+`include "uart_agent.v"
+
+`define TB_HEX "user_fpu_core.hex"
+`define TB_TOP  user_fpu_core_tb
+module `TB_TOP;
+
+parameter real CLK1_PERIOD  = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
+
+`include "user_tasks.sv"
+
+
+//----------------------------------
+// Uart Configuration
+// ---------------------------------
+reg [1:0]  uart_data_bit        ;
+reg	       uart_stop_bits       ; // 0: 1 stop bit; 1: 2 stop bit;
+reg	       uart_stick_parity    ; // 1: force even parity
+reg	       uart_parity_en       ; // parity enable
+reg	       uart_even_odd_parity ; // 0: odd parity; 1: even parity
+
+reg [7:0]      uart_data            ;
+reg [15:0]     uart_divisor         ;	// divided by n * 16
+reg [15:0]     uart_timeout         ;// wait time limit
+
+reg [15:0]     uart_rx_nu           ;
+reg [15:0]     uart_tx_nu           ;
+reg [7:0]      uart_write_data [0:39];
+reg 	       uart_fifo_enable     ;	// fifo mode disable
+
+
+
+     /************* Port-B Mapping **********************************
+     *   Pin-14       PB0/CLKO/ICP1             digital_io[16]
+     *   Pin-15       PB1/SS[1]OC1A(PWM3)       digital_io[17]
+     *   Pin-16       PB2/SS[0]/OC1B(PWM4)      digital_io[18]
+     *   Pin-17       PB3/MOSI/OC2A(PWM5)       digital_io[19]
+     *   Pin-18       PB4/MISO                  digital_io[20]
+     *   Pin-19       PB5/SCK                   digital_io[21]
+     *   Pin-9        PB6/XTAL1/TOSC1           digital_io[11]
+     *   Pin-10       PB7/XTAL2/TOSC2           digital_io[12]
+     *   ********************************************************/
+
+     wire [7:0]  port_b_in = {   io_out[12],
+		                         io_out[11],
+		                         io_out[21],
+		                         io_out[20],
+			                     io_out[19],
+			                     io_out[18],
+		                         io_out[17],
+		                         io_out[16]
+			     };
+	initial begin
+		test_fail = 0;
+                wbd_ext_cyc_i ='h0;  // strobe/request
+                wbd_ext_stb_i ='h0;  // strobe/request
+                wbd_ext_adr_i ='h0;  // address
+                wbd_ext_we_i  ='h0;  // write
+                wbd_ext_dat_i ='h0;  // data output
+                wbd_ext_sel_i ='h0;  // byte enable
+	end
+
+	`ifdef WFDUMP
+	   initial begin
+	   	$dumpfile("simx.vcd");
+	   	$dumpvars(2, `TB_TOP);
+	   	$dumpvars(0, `TB_TOP.u_top.u_fpu);
+	   	$dumpvars(0, `TB_TOP.u_top.u_riscv_top);
+	   	$dumpvars(0, `TB_TOP.u_top.u_pinmux);
+	   end
+       `endif
+
+	initial begin
+
+	       $value$plusargs("risc_core_id=%d", d_risc_id);
+           init();
+
+               uart_data_bit           = 2'b11;
+               uart_stop_bits          = 0; // 0: 1 stop bit; 1: 2 stop bit;
+               uart_stick_parity       = 0; // 1: force even parity
+               uart_parity_en          = 0; // parity enable
+               uart_even_odd_parity    = 1; // 0: odd parity; 1: even parity
+               uart_divisor            = 15;// divided by n * 16
+               uart_timeout            = 500;// wait time limit
+               uart_fifo_enable        = 0;	// fifo mode disable
+
+               #200; // Wait for reset removal
+               repeat (10) @(posedge clock);
+               $display("Monitor: Standalone User Uart Test Started");
+               
+               // Remove Wb Reset
+               //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+               // Enable UART Multi Functional Ports
+               wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h100);
+               
+                wait_riscv_boot();
+               repeat (2) @(posedge clock);
+               #1;
+		// Remove all the reset
+		if(d_risc_id == 0) begin
+		     $display("STATUS: Working with Risc core 0");
+                   //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+		end else if(d_risc_id == 1) begin
+		     $display("STATUS: Working with Risc core 1");
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+		end else if(d_risc_id == 2) begin
+		     $display("STATUS: Working with Risc core 2");
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+		end else if(d_risc_id == 3) begin
+		     $display("STATUS: Working with Risc core 3");
+                     wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+		end
+
+               repeat (100) @(posedge clock);  // wait for Processor Get Ready
+
+               tb_uart.uart_init;
+               wb_user_core_write(`ADDR_SPACE_UART0+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1});  
+               tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
+                                              uart_stick_parity, uart_timeout, uart_divisor);
+
+		// Set the PORT-B Direction as Output
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h0000FF00);
+		// Set the GPIO Output data: 0x00000000
+                wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h0000000);
+   
+              fork
+	          begin
+                     repeat (1400000) @(posedge clock); 
+	          end
+	          begin
+                     wait(port_b_in == 8'h18 || port_b_in == 8'hA8);
+	          end
+	          begin
+                     while(1) begin
+                        wb_user_core_read(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,read_data);
+                        repeat (1000) @(posedge clock); 
+                     end
+	          end
+               join_any
+	
+	       wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h00000000);
+
+               $display("###################################################");
+               if(test_fail == 0) begin
+                  `ifdef GL
+                      $display("Monitor: %m (GL) Passed");
+                  `else
+                      $display("Monitor: %m (RTL) Passed");
+                  `endif
+               end else begin
+                   `ifdef GL
+                       $display("Monitor: %m (GL) Failed");
+                   `else
+                       $display("Monitor: %m (RTL) Failed");
+                   `endif
+                end
+               $display("###################################################");
+               #100
+               $finish;
+
+	end
+
+
+
+// SSPI Slave I/F
+assign io_in[5]  = 1'b1; // RESET
+assign io_in[21] = 1'b0 ; // SPIS SCK 
+
+
+//------------------------------------------------------
+//  Integrate the Serial flash with qurd support to
+//  user core using the gpio pads
+//  ----------------------------------------------------
+
+   wire flash_clk = io_out[28];
+   wire flash_csb = io_out[29];
+   // Creating Pad Delay
+   wire #1 io_oeb_29 = io_oeb[33];
+   wire #1 io_oeb_30 = io_oeb[34];
+   wire #1 io_oeb_31 = io_oeb[35];
+   wire #1 io_oeb_32 = io_oeb[36];
+   tri  #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
+   tri  #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
+   tri  #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
+   tri  #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+
+   assign io_in[33] = flash_io0;
+   assign io_in[34] = flash_io1;
+   assign io_in[35] = flash_io2;
+   assign io_in[36] = flash_io3;
+
+   // Quard flash
+     s25fl256s #(.mem_file_name(`TB_HEX),
+	         .otp_file_name("none"),
+                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
+		 u_spi_flash_256mb (
+           // Data Inputs/Outputs
+       .SI      (flash_io0),
+       .SO      (flash_io1),
+       // Controls
+       .SCK     (flash_clk),
+       .CSNeg   (flash_csb),
+       .WPNeg   (flash_io2),
+       .HOLDNeg (flash_io3),
+       .RSTNeg  (!wb_rst_i)
+
+       );
+
+
+//---------------------------
+//  UART Agent integration
+// --------------------------
+wire uart_txd,uart_rxd;
+
+assign uart_txd   = io_out[7];
+assign io_in[6]  = uart_rxd ;
+ 
+uart_agent tb_uart(
+	.mclk                (clock              ),
+	.txd                 (uart_rxd           ),
+	.rxd                 (uart_txd           )
+	);
+
+
+
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 0901b82..5a594c2 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -72,7 +72,7 @@
 
 `default_nettype wire
 
-`timescale 1 ns / 1 ns
+`timescale 1 ns / 10 ps
 
 `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 
@@ -92,7 +92,10 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(3, `TB_TOP);
+	   	$dumpvars(1, `TB_TOP);
+	   	$dumpvars(1, `TB_TOP.u_top.u_wb_host);
+	   	$dumpvars(1, `TB_TOP.u_top.u_pinmux);
+	   	$dumpvars(1, `TB_TOP.u_top);
 	   end
        `endif
 
diff --git a/verilog/dv/user_rtc/Makefile b/verilog/dv/user_rtc/Makefile
new file mode 100755
index 0000000..f3485a3
--- /dev/null
+++ b/verilog/dv/user_rtc/Makefile
@@ -0,0 +1,85 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+ 
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = user_rtc
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+	iverilog-vpi pli_rtc.c
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+   endif
+else  
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
+endif
+
+%.vcd: %.vvp
+	vvp -M. -m pli_rtc $< 
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.vpi *.o
+
+.PHONY: clean hex all
diff --git a/verilog/dv/user_rtc/pli_rtc.c b/verilog/dv/user_rtc/pli_rtc.c
new file mode 100644
index 0000000..461e40d
--- /dev/null
+++ b/verilog/dv/user_rtc/pli_rtc.c
@@ -0,0 +1,295 @@
+#include <stdlib.h> /* ANSI C standard library */
+#include <stdio.h> /* ANSI C standard input/output library */
+#include <time.h>  
+#include <stdarg.h> /* ANSI C standard arguments library */
+#include  "vpi_user.h"  /*  IEEE 1364 PLI VPI routine library  */
+
+#define CMD_RTC_INIT        0
+#define CMD_RTC_NEXT_SECOND 1
+#define CMD_RTC_NEXT_DATE 2
+
+/* prototypes of PLI application routine names */
+PLI_INT32 PLIbook_RtcSizetf(PLI_BYTE8  *user_data);
+PLI_INT32 PLIbook_RtcCalltf(PLI_BYTE8  *user_data);
+PLI_INT32 PLIbook_RtcCompiletf(PLI_BYTE8  *user_data);
+PLI_INT32 PLIbook_RtcStartOfSim(s_cb_data  *callback_data);
+
+   /* tm structure */
+   /* struct tm {
+       int tm_sec;         // seconds,  range 0 to 59          
+       int tm_min;         // minutes, range 0 to 59           
+       int tm_hour;        // hours, range 0 to 23             
+       int tm_mday;        // day of the month, range 1 to 31  
+       int tm_mon;         // month, range 0 to 11             
+       int tm_year;        // The number of years since 1900   
+       int tm_wday;        // day of the week, range 0 to 6    
+       int tm_yday;        // day in the year, range 0 to 365  
+       int tm_isdst;       // daylight saving time             
+    }; */
+struct tm tm = {0};
+
+/*******************************************
+* Sizetf application
+* *****************************************/
+PLI_INT32  PLIbook_RtcSizetf(PLI_BYTE8  *user_data)
+{
+   return(32); /* $rtc returns 32-bit values */
+}
+
+/*********************************************
+* compiletf application to verify valid systf args.
+* *************************************************/
+PLI_INT32  PLIbook_RtcCompiletf(PLI_BYTE8  *user_data)
+{
+   s_vpi_value value_s;
+   vpiHandle systf_handle, arg_itr, arg_handle;
+   PLI_INT32 tfarg_type;
+   PLI_INT32 cmd;
+
+   int err_flag = 0;
+   do { /* group all tests, so can break out of group on error */
+       systf_handle = vpi_handle(vpiSysTfCall, NULL);
+       arg_itr = vpi_iterate(vpiArgument, systf_handle);
+       if (arg_itr == NULL) {
+           vpi_printf("ERROR: $c_rtc requires 7 arguments; has none\n");
+           err_flag = 1;
+           break;
+      }
+      arg_handle = vpi_scan(arg_itr);
+      tfarg_type = vpi_get(vpiType, arg_handle);
+      if ( (tfarg_type != vpiReg) &&
+          (tfarg_type != vpiIntegerVar) &&
+          (tfarg_type != vpiConstant) ) {
+          vpi_printf("ERROR: $c_rtc arg1 must be number, variable or net\n");
+          err_flag = 1;
+          break;
+      }
+      value_s.format = vpiIntVal;
+      vpi_get_value(arg_handle, &value_s);
+      cmd = value_s.value.integer;
+ 
+      // RTC Init has 7 Parameter 
+      if(cmd == CMD_RTC_INIT) { 
+          arg_handle = vpi_scan(arg_itr);
+          tfarg_type = vpi_get(vpiType, arg_handle);
+          if ( (tfarg_type != vpiReg) &&
+              (tfarg_type != vpiIntegerVar) &&
+              (tfarg_type != vpiConstant) ) {
+              vpi_printf("ERROR: $c_rtc arg2 must be number, variable or net\n");
+              err_flag = 1;
+              break;
+          }
+          arg_handle = vpi_scan(arg_itr);
+          tfarg_type = vpi_get(vpiType, arg_handle);
+          if ( (tfarg_type != vpiReg) &&
+              (tfarg_type != vpiIntegerVar) &&
+              (tfarg_type != vpiConstant) ) {
+              vpi_printf("ERROR: $c_rtc arg3 must be number, variable or net\n");
+              err_flag = 1;
+              break;
+          }
+          arg_handle = vpi_scan(arg_itr);
+          tfarg_type = vpi_get(vpiType, arg_handle);
+          if ( (tfarg_type != vpiReg) &&
+              (tfarg_type != vpiIntegerVar) &&
+              (tfarg_type != vpiConstant) ) {
+              vpi_printf("ERROR: $c_rtc arg4 must be number, variable or net\n");
+              err_flag = 1;
+              break;
+          }
+          arg_handle = vpi_scan(arg_itr);
+          tfarg_type = vpi_get(vpiType, arg_handle);
+          if ( (tfarg_type != vpiReg) &&
+              (tfarg_type != vpiIntegerVar) &&
+              (tfarg_type != vpiConstant) ) {
+              vpi_printf("ERROR: $c_rtc arg5 must be number, variable or net\n");
+              err_flag = 1;
+              break;
+          }
+          arg_handle = vpi_scan(arg_itr);
+          tfarg_type = vpi_get(vpiType, arg_handle);
+          if ( (tfarg_type != vpiReg) &&
+              (tfarg_type != vpiIntegerVar) &&
+              (tfarg_type != vpiConstant) ) {
+              vpi_printf("ERROR: $c_rtc arg6 must be number, variable or net\n");
+              err_flag = 1;
+              break;
+          }
+          arg_handle = vpi_scan(arg_itr);
+          tfarg_type = vpi_get(vpiType, arg_handle);
+          if ( (tfarg_type != vpiReg) &&
+              (tfarg_type != vpiIntegerVar) &&
+              (tfarg_type != vpiConstant) ) {
+              vpi_printf("ERROR: $c_rtc arg7 must be number, variable or net\n");
+              err_flag = 1;
+              break;
+          }
+
+          arg_handle = vpi_scan(arg_itr);
+          if (arg_handle != NULL) {
+              vpi_printf("ERROR: $c_rtc requires 7 arguments; has too many\n");
+              vpi_free_object(arg_itr);
+              err_flag = 1;
+              break;
+          }
+        } else { // CMD_RTC_NEXT_SECOND & CMD_RTC_NEXT_DATE has only 1 arguments
+
+          arg_handle = vpi_scan(arg_itr);
+          if (arg_handle != NULL) {
+              vpi_printf("ERROR: $c_rtc requires 1 arguments; has too many\n");
+              vpi_free_object(arg_itr);
+              err_flag = 1;
+              break;
+          }
+       }
+   } while (0 == 1); /* end of test group; only executed once */
+   if (err_flag) {
+      vpi_control(vpiFinish, 1);  /* abort simulation */
+   }
+   return(0);
+}
+
+/******************************************************************
+* calltf to calculate floating point addr
+* ******************************************************************/
+#include <stdio.h> 
+#include <time.h>  
+#include <stdlib.h>
+
+PLI_INT32  PLIbook_RtcCalltf(PLI_BYTE8  *user_data)
+{
+   s_vpi_value value_s;
+   vpiHandle systf_handle,  arg_itr,  arg_handle;
+   PLI_INT32 cmd,year, month, date, hour,minute,second;
+   float result;
+   systf_handle = vpi_handle(vpiSysTfCall, NULL);
+   arg_itr = vpi_iterate(vpiArgument, systf_handle);
+   if (arg_itr == NULL) {
+       vpi_printf("ERROR:  $c_rtc failed to obtain systf arg handles\n");
+       return(0);
+   }
+   /* read cmd from systf arg 1 (compiletf has already verified) */
+   arg_handle = vpi_scan(arg_itr);
+   value_s.format = vpiIntVal;
+   vpi_get_value(arg_handle, &value_s);
+   cmd = value_s.value.integer;
+
+
+   if(cmd == CMD_RTC_INIT) {
+      /* read input1 from systf arg 6 (compiletf has already verified) */
+      arg_handle = vpi_scan(arg_itr);
+      vpi_get_value(arg_handle,  &value_s);
+      year = value_s.value.integer;
+
+      /* read input2 from systf arg 6 (compiletf has already verified) */
+      arg_handle = vpi_scan(arg_itr);
+      vpi_get_value(arg_handle,  &value_s);
+      month = value_s.value.integer;
+
+      /* read input2 from systf arg 6 (compiletf has already verified) */
+      arg_handle = vpi_scan(arg_itr);
+      vpi_get_value(arg_handle,  &value_s);
+      date = value_s.value.integer;
+
+      /* read input3 from systf arg 6 (compiletf has already verified) */
+      arg_handle = vpi_scan(arg_itr);
+      vpi_get_value(arg_handle,  &value_s);
+      hour = value_s.value.integer;
+
+      /* read input4 from systf arg 6 (compiletf has already verified) */
+      arg_handle = vpi_scan(arg_itr);
+      vpi_get_value(arg_handle,  &value_s);
+      minute = value_s.value.integer;
+
+      /* read input5 from systf arg 6 (compiletf has already verified) */
+      arg_handle = vpi_scan(arg_itr);
+      vpi_get_value(arg_handle,  &value_s);
+      second = value_s.value.integer;
+
+      // initialize the Structure
+      tm.tm_year = year-1900;
+      tm.tm_mon  = month-1; /* C Month start from 0 to 11 and RTL 1 to 12 */
+      tm.tm_mday = date;
+      tm.tm_hour = hour;
+      tm.tm_min  = minute;
+      tm.tm_sec  = second;
+    }
+
+   // vpi_printf("c_func: year: %d; month: %d; day: %d;hour: %d; minute: %d; second: %d;week day: %d; year day: %d\n",
+   //          tm.tm_year + 1900, tm.tm_mon, tm.tm_mday,
+   //          tm.tm_hour, tm.tm_min, tm.tm_sec,
+   //          tm.tm_wday, tm.tm_yday);
+
+   if(cmd == CMD_RTC_NEXT_SECOND)
+      tm.tm_sec  = tm.tm_sec + 1;
+   else if(cmd == CMD_RTC_NEXT_DATE)
+      tm.tm_mday  = tm.tm_mday + 1;
+   mktime(&tm);
+
+   //vpi_printf("c_func: year: %d; month: %d; day: %d;hour: %d; minute: %d; second: %d;week day: %d; year day: %d\n",
+   //         tm.tm_year + 1900, tm.tm_mon, tm.tm_mday,
+   //         tm.tm_hour, tm.tm_min, tm.tm_sec,
+   //         tm.tm_wday, tm.tm_yday);
+
+   char str[80];
+   if(cmd == CMD_RTC_NEXT_SECOND)
+      sprintf(str,"%02d%02d%02d%02d",tm.tm_mday,tm.tm_hour,tm.tm_min,tm.tm_sec);
+   else if(cmd == CMD_RTC_NEXT_DATE)
+      sprintf(str,"%04d%02d%02d",tm.tm_year+1900,tm.tm_mon+1,tm.tm_mday);
+
+   vpi_printf("c_func: year: %d; month: %d; day: %d;hour: %d; minute: %d; second: %d;week day: %d; year day: %d\n",
+            tm.tm_year + 1900, tm.tm_mon+1, tm.tm_mday,
+            tm.tm_hour, tm.tm_min, tm.tm_sec,
+            tm.tm_wday, tm.tm_yday);
+
+   ///* write result to simulation as return value $fpu_add */
+   int c = (int)strtol(str, NULL, 16); 
+
+   value_s.value.integer =  (PLI_INT32)c;
+   vpi_put_value(systf_handle,  &value_s, NULL, vpiNoDelay);
+   return(0);
+}
+
+
+/**
+* Start-of-simulation application
+****/
+PLI_INT32  PLIbook_RtcStartOfSim(s_cb_data  *callback_data)
+{
+   vpi_printf("\n$c_rtc PLI application is being used.\n\n");
+   return(0);
+}
+
+/**********************************************************
+    $fpu_add Registration Data
+(add this function name to the vlog_startup_routines array)
+***********************************************************/
+void  PLIbook_fpu_add_register()
+{
+    s_vpi_systf_data tf_data;
+    s_cb_data cb_data_s;
+    vpiHandle callback_handle;
+    
+    tf_data.type = vpiSysFunc;
+    tf_data.sysfunctype = vpiSysFuncSized;
+    tf_data.tfname =  "$c_rtc";
+    tf_data.calltf = PLIbook_RtcCalltf;
+    tf_data.compiletf = PLIbook_RtcCompiletf;
+    tf_data.sizetf = PLIbook_RtcSizetf;
+    tf_data.user_data = NULL;
+    vpi_register_systf(&tf_data);
+    cb_data_s.reason = cbStartOfSimulation;
+    cb_data_s.cb_rtn = PLIbook_RtcStartOfSim;
+    cb_data_s.obj = NULL;
+    cb_data_s.time = NULL;
+    cb_data_s.value = NULL;
+    cb_data_s.user_data = NULL;
+    callback_handle = vpi_register_cb(&cb_data_s);
+    vpi_free_object(callback_handle); /* don’t need callback handle */
+}
+
+void (*vlog_startup_routines[])() = {
+    PLIbook_fpu_add_register,
+    0
+};
+
diff --git a/verilog/dv/user_rtc/user_rtc_tb.v b/verilog/dv/user_rtc/user_rtc_tb.v
new file mode 100644
index 0000000..d53aefe
--- /dev/null
+++ b/verilog/dv/user_rtc/user_rtc_tb.v
@@ -0,0 +1,317 @@
+/*********************************************************************************
+ SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+ 
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+      http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+ SPDX-License-Identifier: Apache-2.0
+ SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com>
+
+***********************************************************************************/
+/**********************************************************************************
+                                                              
+                   RTC Test Bench
+                                                              
+                                                              
+  Author(s):                                                  
+      - Dinesh Annayya, dinesh.annayya@gmail.com                 
+                                                              
+  Revision :                                                  
+     0.0  - Nov 16, 2022 
+            Initial Version 
+     0.1  - Nov 21, 2022 
+            A.Sys-clk and RTC clock domain are seperated.
+            B.Register are moved to seperate module
+            
+************************************************************************************/
+/************************************************************************************
+                      Copyright (C) 2000-2002 
+              Dinesh Annayya <dinesh.annayya@gmail.com>
+                                                             
+       This source file may be used and distributed without        
+       restriction provided that this copyright statement is not   
+       removed from the file and that any derivative work contains 
+       the original copyright notice and the associated disclaimer.
+                                                                   
+           THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     
+       EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   
+       TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   
+       FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      
+       OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         
+       INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    
+       (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   
+       GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        
+       BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  
+       LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  
+       (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  
+       OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         
+       POSSIBILITY OF SUCH DAMAGE.                                 
+                                                             
+************************************************************************************/
+
+`timescale 1 ns / 1 ps
+
+
+
+`define  CMD_C_INIT       4'h0 // Initialize the C PLI Timer
+`define  CMD_C_NEXT_TIME  4'h1 // Get Next Second Value
+`define  CMD_C_NEXT_DATE  4'h2 // Het Next Date value
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+
+`define TB_TOP user_rtc_tb
+
+module `TB_TOP;
+
+parameter real CLK1_PERIOD  = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
+
+parameter RTC_PERIOD = 30518; // 32768 Hz
+
+`include "user_tasks.sv"
+
+reg		    rtc_clk;
+reg		    rst_n;
+reg [15:0]  error_cnt;
+
+//---------------------
+// Register I/F
+wire        trig_s  = u_top.u_peri.inc_time_s;
+wire        trig_d  = u_top.u_peri.inc_date_d;
+
+
+// Wishbone Interface
+
+always #(RTC_PERIOD/2) rtc_clk = ~rtc_clk;
+
+assign io_in[11] = rtc_clk;
+
+	initial begin
+		test_fail = 0;
+        wbd_ext_cyc_i ='h0;  // strobe/request
+        wbd_ext_stb_i ='h0;  // strobe/request
+        wbd_ext_adr_i ='h0;  // address
+        wbd_ext_we_i  ='h0;  // write
+        wbd_ext_dat_i ='h0;  // data output
+        wbd_ext_sel_i ='h0;  // byte enable
+	    rtc_clk       = 0;
+	    error_cnt     = 0;
+	end
+
+initial
+   begin
+	$value$plusargs("risc_core_id=%d", d_risc_id);
+    init();
+
+	$display("\n\n");
+	$display("*****************************************************");
+	$display("* RTC Test bench ...");
+	$display("*****************************************************");
+	$display("\n");
+
+
+    normal_test;
+    fast_test1;
+    fast_test2;
+
+	repeat(1000)	@(posedge clock);
+
+    if(error_cnt > 0) test_fail = 1;
+
+    $display("###################################################");
+    if(test_fail == 0) begin
+       `ifdef GL
+           $display("Monitor: %m (GL) Passed");
+       `else
+           $display("Monitor: %m (RTL) Passed");
+       `endif
+    end else begin
+        `ifdef GL
+            $display("Monitor: %m (GL) Failed");
+        `else
+            $display("Monitor: %m (RTL) Failed");
+        `endif
+     end
+    $display("###################################################");
+	repeat(10)	@(posedge clock);
+	$finish;
+end
+
+`ifdef WFDUMP
+   initial begin
+   	  $dumpfile("simx.vcd");
+   	  $dumpvars(0, `TB_TOP);
+   end
+`endif
+
+
+
+wire [7:0] rtl_time   = {1'b0, u_top.u_peri.u_rtc.time_ts,u_top.u_peri.u_rtc.time_s};
+wire [7:0] rtl_minute = {1'b0, u_top.u_peri.u_rtc.time_tm,u_top.u_peri.u_rtc.time_m};
+wire [7:0] rtl_hour   = {1'b0, u_top.u_peri.u_rtc.time_th,u_top.u_peri.u_rtc.time_h};
+wire [7:0] rtl_dow    = {5'b0, u_top.u_peri.u_rtc.time_dow};
+
+wire [7:0] rtl_date   = {2'b0,u_top.u_peri.u_rtc.date_td,u_top.u_peri.u_rtc.date_d};
+wire [7:0] rtl_month  = {2'b0,u_top.u_peri.u_rtc.date_tm,u_top.u_peri.u_rtc.date_m};
+wire [15:0] rtl_year  = {u_top.u_peri.u_rtc.date_tc,u_top.u_peri.u_rtc.date_c,u_top.u_peri.u_rtc.date_ty,u_top.u_peri.u_rtc.date_y};
+wire [7:0] rtl_cent   = {u_top.u_peri.u_rtc.date_tc,u_top.u_peri.u_rtc.date_c};
+
+//---------------------------
+// Normal Test Without any Over-ride
+task normal_test;
+reg [31:0] exp_time;
+reg [31:0] cfg_time;
+reg [31:0] cfg_date;
+integer i;
+begin
+    //initialize the Timer Structure in C-PLI
+   $c_rtc(`CMD_C_INIT,2022,10,19,0,0,0);
+   init();
+
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_TIME,{8'h01,8'h0,8'h0,8'h0});
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_DATE,{16'h2022,8'h10,8'h19});
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CMD ,{30'h0,2'b01});
+
+   for(i=0; i < 10; i = i+1) begin
+     repeat(1)	@(negedge trig_s);
+     exp_time = $c_rtc(1);
+     wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CMD ,{30'h0,2'b10});
+     wb_user_core_read(`ADDR_SPACE_RTC+`RTC_TIME,cfg_time);
+     wb_user_core_read(`ADDR_SPACE_RTC+`RTC_DATE,cfg_date);
+
+     if(exp_time == {cfg_date[7:0],cfg_time[23:0]}) begin
+        $display("STATUS: Exp: [Day: %02x Hour: %02x Minute: %02x Second: %02x] RTL: [Day: %02x Hour: %02x Minute: %02x Second: %02x]",
+                      exp_time[31:24],exp_time[23:16],exp_time[15:8],exp_time[7:0],cfg_date[7:0],cfg_time[23:16],cfg_time[15:8],cfg_time[7:0]);
+     end else begin
+        error_cnt = error_cnt+1;
+        $display("ERROR: Exp: [Day: %02x Hour: %02x Minute: %02x Second: %02x] RTL: [Day: %02x Hour: %02x Minute: %02x Second: %02x]",
+                      exp_time[31:24],exp_time[23:16],exp_time[15:8],exp_time[7:0],cfg_date[7:0],cfg_time[23:16],cfg_time[15:8],cfg_time[7:0]);
+        repeat(10) @(posedge clock);
+        $finish;
+     end
+   end
+   if(error_cnt > 0)
+      $display("STATUS: Normal Test[Day, Hour,Minute,Second] without Over-ride Failed");
+   else
+      $display("STATUS: Normal Test[Day, Hour, Minute,Second] without Over-ride Passed");
+
+
+end
+endtask
+
+//------------------------------------------------------
+// Fast Time Test With Over-ride fast_sim_time=1
+//------------------------------------------------------
+task fast_test1;
+reg [31:0] exp_time;
+integer i;
+begin
+  //initialize the Timer Structure in C-PLI
+   $c_rtc(`CMD_C_INIT,2022,10,19,0,0,0);
+
+   init();
+
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_TIME,{8'h01,8'h0,8'h0,8'h0});
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_DATE,{16'h2022,8'h10,8'h19});
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CMD ,{30'h0,2'b01});
+
+   fork
+   begin
+      //fast_sim_time=1;
+      wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CTRL ,{16'h0,2'b01,14'h400});
+   end
+   begin
+      for(i=0; i < (65536*10); i = i+1) begin
+        repeat(1)	@(negedge trig_s);
+        exp_time = $c_rtc(`CMD_C_NEXT_TIME);
+        if(exp_time == {rtl_date,rtl_hour,rtl_minute,rtl_time}) begin
+           $display("STATUS: Exp: [Day: %02x Hour: %02x Minute: %02x Second: %02x] RTL: [Year:%04x Month: %02x Day: %02x Hour: %02x Minute: %02x Second: %02x]",
+                         exp_time[31:24],exp_time[23:16],exp_time[15:8],exp_time[7:0],rtl_year,rtl_month,rtl_date,rtl_hour,rtl_minute,rtl_time);
+        end else begin
+           error_cnt = error_cnt+1;
+           $display("ERROR: Exp: [Day: %02x Hour: %02x Minute: %02x Second: %02x] RTL: [Year:%04x Month: %02x Day: %02x Hour: %02x Minute: %02x Second: %02x]",
+                         exp_time[31:24],exp_time[23:16],exp_time[15:8],exp_time[7:0],rtl_year,rtl_month,rtl_date,rtl_hour,rtl_minute,rtl_time);
+           repeat(10) @(posedge clock);
+           $finish;
+        end
+      end
+    end
+    join
+
+   //fast_sim_time=0;
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CTRL ,{16'h0,2'b00,14'h400});
+
+   if(error_cnt > 0)
+      $display("STATUS: Fast Test1 with (Fast Time) Over-ride Failed");
+   else
+      $display("STATUS: Fast Test1 with (Fast Time) Over-ride Passed");
+end
+endtask
+
+//------------------------------------------------------
+// Fast Time Test With Over-ride fast_sim_date=1
+//------------------------------------------------------
+task fast_test2;
+reg [31:0] exp_date;
+integer i;
+begin
+  //initialize the Timer Structure in C-PLI
+   $c_rtc(`CMD_C_INIT,2022,10,19,0,0,0);
+
+   init();
+
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_TIME,{8'h01,8'h0,8'h0,8'h0});
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_DATE,{16'h2022,8'h10,8'h19});
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CMD ,{30'h0,2'b01});
+
+   fork
+   begin
+      wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CTRL ,{16'h0,2'b10,14'h400});
+      repeat(1) @(posedge clock);
+   end
+   begin
+      for(i=0; i < (65536*10); i = i+1) begin
+        repeat(1)	@(negedge trig_d);
+        exp_date = $c_rtc(`CMD_C_NEXT_DATE);
+        if(exp_date == {rtl_year,rtl_month,rtl_date}) begin
+           $display("STATUS: Exp: [Year: %04x Month: %02x Date: %02x] RTL: [Year:%04x Month: %02x Day: %02x]",
+                         exp_date[31:16],exp_date[15:8],exp_date[7:0],rtl_year,rtl_month,rtl_date);
+        end else begin
+           error_cnt = error_cnt+1;
+           $display("ERROR: Exp: [Year: %04x Month: %02x Date: %02x] RTL: [Year:%04x Month: %02x Day: %02x]",
+                         exp_date[31:16],exp_date[15:8],exp_date[7:0],rtl_year,rtl_month,rtl_date);
+           repeat(10) @(posedge clock);
+           $finish;
+        end
+      end
+   end
+   join
+
+   wb_user_core_write(`ADDR_SPACE_RTC+`RTC_CTRL ,{16'h0,2'b00,14'h0});
+
+   if(error_cnt > 0)
+      $display("STATUS: Fast Test2 with (Fast Date) Over-ride Failed");
+   else
+      $display("STATUS: Fast Test2 with (Fast Date) Over-ride Passed");
+end
+endtask
+
+
+
+
+
+
+
+endmodule
+
+
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index 35d26f5..7a843f5 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -228,6 +228,7 @@
 $(USER_PROJECT_VERILOG)/gl/bus_rep_north.v
 $(USER_PROJECT_VERILOG)/gl/bus_rep_east.v
 $(USER_PROJECT_VERILOG)/gl/bus_rep_west.v
+$(USER_PROJECT_VERILOG)/gl/peri_top.v
 
 -v $(USER_PROJECT_VERILOG)/rtl/dg_pll/src/dg_pll.v
 
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index e770eff..4c5f2f6 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -171,3 +171,10 @@
 -v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_north.sv
 -v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_east.sv
 -v $(USER_PROJECT_VERILOG)/rtl/bus_rep/bus_rep_west.sv
+
+-v $(USER_PROJECT_VERILOG)/rtl/peripheral/src/peri_top.sv
+
+$(USER_PROJECT_VERILOG)/rtl/rtc/verilog/rtl/core/rtc_top.sv
+$(USER_PROJECT_VERILOG)/rtl/rtc/verilog/rtl/core/rtc_core.sv
+$(USER_PROJECT_VERILOG)/rtl/rtc/verilog/rtl/core/rtc_reg.sv
+
diff --git a/verilog/rtl/bus_rep/bus_rep_north.sv b/verilog/rtl/bus_rep/bus_rep_north.sv
index bb13510..cbc3f24 100644
--- a/verilog/rtl/bus_rep/bus_rep_north.sv
+++ b/verilog/rtl/bus_rep/bus_rep_north.sv
@@ -19,7 +19,8 @@
 //               Bus Repater                                        //
 //////////////////////////////////////////////////////////////////////
 module bus_rep_north #(
-	parameter BUS_REP_WD = 7
+	parameter BUS_REP_WD = 7,
+	parameter BUS_BUF_WD = 42
         ) (
 `ifdef USE_POWER_PINS
          input logic            vccd1,    // User area 1 1.8V supply
@@ -27,7 +28,10 @@
 `endif
 	 // Bus repeaters
 	 input  [BUS_REP_WD-1:0]  ch_in,
-	 output [BUS_REP_WD-1:0] ch_out
+	 output [BUS_REP_WD-1:0]  ch_out,
+     // Bus Buffering 
+	 input  [BUS_BUF_WD-1:0]  buf_in,
+	 output [BUS_BUF_WD-1:0]  buf_out
       );
 
 // channel repeater
@@ -35,6 +39,7 @@
 `ifndef SYNTHESIS
 
 assign ch_out = ch_in;
+assign buf_out = buf_in;
 
 `else
 
@@ -45,6 +50,8 @@
     end
  endgenerate
 
+assign buf_out = buf_in;
+
 `endif
 
 
diff --git a/verilog/rtl/bus_repeater.sv b/verilog/rtl/bus_repeater.sv
index 8312ed8..41fc3f4 100644
--- a/verilog/rtl/bus_repeater.sv
+++ b/verilog/rtl/bus_repeater.sv
@@ -549,47 +549,47 @@
 **********************************************/
 
 wire [41:0] ch_in_west = {
-                          io_oeb_int[37],
-                          io_out_int[37],
+                          io_oeb_rp1[37],
+                          io_out_rp1[37],
                           io_in[37],
-                          io_oeb_int[36],
-                          io_out_int[36],
+                          io_oeb_rp1[36],
+                          io_out_rp1[36],
                           io_in[36],
-                          io_oeb_int[35],
-                          io_out_int[35],
+                          io_oeb_rp1[35],
+                          io_out_rp1[35],
                           io_in[35],
-                          io_oeb_int[34],
-                          io_out_int[34],
+                          io_oeb_rp1[34],
+                          io_out_rp1[34],
                           io_in[34],
-                          io_oeb_int[33],
-                          io_out_int[33],
+                          io_oeb_rp1[33],
+                          io_out_rp1[33],
                           io_in[33],
-                          io_oeb_int[32],
-                          io_out_int[32],
+                          io_oeb_rp1[32],
+                          io_out_rp1[32],
                           io_in[32],
-                          io_oeb_int[31],
-                          io_out_int[31],
+                          io_oeb_rp1[31],
+                          io_out_rp1[31],
                           io_in[31],
-                          io_oeb_int[30],
-                          io_out_int[30],
+                          io_oeb_rp1[30],
+                          io_out_rp1[30],
                           io_in[30],
-                          io_oeb_int[29],
-                          io_out_int[29],
+                          io_oeb_rp1[29],
+                          io_out_rp1[29],
                           io_in[29],
-                          io_oeb_int[28],
-                          io_out_int[28],
+                          io_oeb_rp1[28],
+                          io_out_rp1[28],
                           io_in[28],
-                          io_oeb_int[27],
-                          io_out_int[27],
+                          io_oeb_rp1[27],
+                          io_out_rp1[27],
                           io_in[27],
-                          io_oeb_int[26],
-                          io_out_int[26],
+                          io_oeb_rp1[26],
+                          io_out_rp1[26],
                           io_in[26],
-                          io_oeb_int[25],
-                          io_out_int[25],
+                          io_oeb_rp1[25],
+                          io_out_rp1[25],
                           io_in[25],
-                          io_oeb_int[24],
-                          io_out_int[24],
+                          io_oeb_rp1[24],
+                          io_out_rp1[24],
                           io_in[24]
                          };
 
@@ -597,46 +597,46 @@
 assign  {
                           io_oeb[37],
                           io_out[37],
-                          io_in_rp[37],
+                          io_in_rp1[37],
                           io_oeb[36],
                           io_out[36],
-                          io_in_rp[36],
+                          io_in_rp1[36],
                           io_oeb[35],
                           io_out[35],
-                          io_in_rp[35],
+                          io_in_rp1[35],
                           io_oeb[34],
                           io_out[34],
-                          io_in_rp[34],
+                          io_in_rp1[34],
                           io_oeb[33],
                           io_out[33],
-                          io_in_rp[33],
+                          io_in_rp1[33],
                           io_oeb[32],
                           io_out[32],
-                          io_in_rp[32],
+                          io_in_rp1[32],
                           io_oeb[31],
                           io_out[31],
-                          io_in_rp[31],
+                          io_in_rp1[31],
                           io_oeb[30],
                           io_out[30],
-                          io_in_rp[30],
+                          io_in_rp1[30],
                           io_oeb[29],
                           io_out[29],
-                          io_in_rp[29],
+                          io_in_rp1[29],
                           io_oeb[28],
                           io_out[28],
-                          io_in_rp[28],
+                          io_in_rp1[28],
                           io_oeb[27],
                           io_out[27],
-                          io_in_rp[27],
+                          io_in_rp1[27],
                           io_oeb[26],
                           io_out[26],
-                          io_in_rp[26],
+                          io_in_rp1[26],
                           io_oeb[25],
                           io_out[25],
-                          io_in_rp[25],
+                          io_in_rp1[25],
                           io_oeb[24],
                           io_out[24],
-                          io_in_rp[24]
+                          io_in_rp1[24]
 
          } = ch_out_west;
 
@@ -690,46 +690,147 @@
 
 wire [26:0] ch_out_north ;
 assign  {
-           io_in_rp[15],
+           io_in_rp1[15],
            io_out[15],
            io_oeb[15],
-           io_in_rp[16],
+           io_in_rp1[16],
            io_out[16],
            io_oeb[16],
-           io_in_rp[17],
+           io_in_rp1[17],
            io_out[17],
            io_oeb[17],
-           io_in_rp[18],
+           io_in_rp1[18],
            io_out[18],
            io_oeb[18],
-           io_in_rp[19],
+           io_in_rp1[19],
            io_out[19],
            io_oeb[19],
-           io_in_rp[20],
+           io_in_rp1[20],
            io_out[20],
            io_oeb[20],
-           io_in_rp[21],
+           io_in_rp1[21],
            io_out[21],
            io_oeb[21],
-           io_in_rp[22],
+           io_in_rp1[22],
            io_out[22],
            io_oeb[22],
-           io_in_rp[23],
+           io_in_rp1[23],
            io_out[23],
            io_oeb[23]
           } = ch_out_north;
 
+//--------------------------------------------------------------------------------
+// As West boundary is far from Pinmux module, there is feed through created
+// through the north repeater block
+// Buffering from Pinmux to PAD , feed through Pinmux <=> north <=> west
+//--------------------------------------------------------------------------------
+
+wire [41:0] buf_in_north = {
+                          io_oeb_int[37],
+                          io_out_int[37],
+                          io_in_rp1[37],
+                          io_oeb_int[36],
+                          io_out_int[36],
+                          io_in_rp1[36],
+                          io_oeb_int[35],
+                          io_out_int[35],
+                          io_in_rp1[35],
+                          io_oeb_int[34],
+                          io_out_int[34],
+                          io_in_rp1[34],
+                          io_oeb_int[33],
+                          io_out_int[33],
+                          io_in_rp1[33],
+                          io_oeb_int[32],
+                          io_out_int[32],
+                          io_in_rp1[32],
+                          io_oeb_int[31],
+                          io_out_int[31],
+                          io_in_rp1[31],
+                          io_oeb_int[30],
+                          io_out_int[30],
+                          io_in_rp1[30],
+                          io_oeb_int[29],
+                          io_out_int[29],
+                          io_in_rp1[29],
+                          io_oeb_int[28],
+                          io_out_int[28],
+                          io_in_rp1[28],
+                          io_oeb_int[27],
+                          io_out_int[27],
+                          io_in_rp1[27],
+                          io_oeb_int[26],
+                          io_out_int[26],
+                          io_in_rp1[26],
+                          io_oeb_int[25],
+                          io_out_int[25],
+                          io_in_rp1[25],
+                          io_oeb_int[24],
+                          io_out_int[24],
+                          io_in_rp1[24]
+                         };
+
+wire [41:0] buf_out_north ;
+assign  {
+                          io_oeb_rp1[37],
+                          io_out_rp1[37],
+                          io_in_rp2[37],
+                          io_oeb_rp1[36],
+                          io_out_rp1[36],
+                          io_in_rp2[36],
+                          io_oeb_rp1[35],
+                          io_out_rp1[35],
+                          io_in_rp2[35],
+                          io_oeb_rp1[34],
+                          io_out_rp1[34],
+                          io_in_rp2[34],
+                          io_oeb_rp1[33],
+                          io_out_rp1[33],
+                          io_in_rp2[33],
+                          io_oeb_rp1[32],
+                          io_out_rp1[32],
+                          io_in_rp2[32],
+                          io_oeb_rp1[31],
+                          io_out_rp1[31],
+                          io_in_rp2[31],
+                          io_oeb_rp1[30],
+                          io_out_rp1[30],
+                          io_in_rp2[30],
+                          io_oeb_rp1[29],
+                          io_out_rp1[29],
+                          io_in_rp2[29],
+                          io_oeb_rp1[28],
+                          io_out_rp1[28],
+                          io_in_rp2[28],
+                          io_oeb_rp1[27],
+                          io_out_rp1[27],
+                          io_in_rp2[27],
+                          io_oeb_rp1[26],
+                          io_out_rp1[26],
+                          io_in_rp2[26],
+                          io_oeb_rp1[25],
+                          io_out_rp1[25],
+                          io_in_rp2[25],
+                          io_oeb_rp1[24],
+                          io_out_rp1[24],
+                          io_in_rp2[24]
+
+         } = buf_out_north;
+
 bus_rep_north  #(
 `ifndef SYNTHESIS
-.BUS_REP_WD(27)
+.BUS_REP_WD(27),
+.BUS_BUF_WD(42)
 `endif
       ) u_rp_north(
 `ifdef USE_POWER_PINS
     .vccd1                 (vccd1                  ),
     .vssd1                 (vssd1                  ),
 `endif
-    .ch_in (ch_in_north),
-    .ch_out (ch_out_north)
+    .ch_in  (ch_in_north),
+    .ch_out (ch_out_north),
+    .buf_in  (buf_in_north),
+    .buf_out (buf_out_north)
    );
 
 /*********************************************
@@ -787,49 +888,49 @@
 
 wire [44:0] ch_out_east ;
 assign  {
-                            io_in_rp[0],
+                            io_in_rp1[0],
                             io_out[0],
                             io_oeb[0],
-                            io_in_rp[1],
+                            io_in_rp1[1],
                             io_out[1],
                             io_oeb[1],
-                            io_in_rp[2],
+                            io_in_rp1[2],
                             io_out[2],
                             io_oeb[2],
-                            io_in_rp[3],
+                            io_in_rp1[3],
                             io_out[3],
                             io_oeb[3],
-                            io_in_rp[4],
+                            io_in_rp1[4],
                             io_out[4],
                             io_oeb[4],
-                            io_in_rp[5],
+                            io_in_rp1[5],
                             io_out[5],
                             io_oeb[5],
-                            io_in_rp[6],
+                            io_in_rp1[6],
                             io_out[6],
                             io_oeb[6],
-                            io_in_rp[7],
+                            io_in_rp1[7],
                             io_out[7],
                             io_oeb[7],
-                            io_in_rp[8],
+                            io_in_rp1[8],
                             io_out[8],
                             io_oeb[8],
-                            io_in_rp[9],
+                            io_in_rp1[9],
                             io_out[9],
                             io_oeb[9],
-                            io_in_rp[10],
+                            io_in_rp1[10],
                             io_out[10],
                             io_oeb[10],
-                            io_in_rp[11],
+                            io_in_rp1[11],
                             io_out[11],
                             io_oeb[11],
-                            io_in_rp[12],
+                            io_in_rp1[12],
                             io_out[12],
                             io_oeb[12],
-                            io_in_rp[13],
+                            io_in_rp1[13],
                             io_out[13],
                             io_oeb[13],
-                            io_in_rp[14],
+                            io_in_rp1[14],
                             io_out[14],
                             io_oeb[14]
         } = ch_out_east;
@@ -852,8 +953,8 @@
 //---------------------------------------------------------
 //assign io_oeb[14:0]    = io_oeb_int[14:0];
 //assign io_out[14:0]    = io_out_int[14:0];
-//assign io_in_rp[14:0]  = io_in[14:0];
+assign io_in_rp[37:0]    = {io_in_rp2[37:24],io_in_rp1[23:0]};
 
 //assign io_oeb[37:24]    = io_oeb_int[37:24];
 //assign io_out[37:24]    = io_out_int[37:24];
-//assign io_in_rp[37:24]  = io_in[37:24];
+//assign io_in_rp1[37:24]  = io_in[37:24];
diff --git a/verilog/rtl/lib/async_reg_bus.sv b/verilog/rtl/lib/async_reg_bus.sv
index 3392cbf..02dca1d 100644
--- a/verilog/rtl/lib/async_reg_bus.sv
+++ b/verilog/rtl/lib/async_reg_bus.sv
@@ -58,9 +58,10 @@
           out_reg_rdata              ,
           out_reg_ack
    );
-parameter AW = 26 ; // Address width
-parameter DW = 32 ; // DATA WIDTH
-parameter BEW = 4 ; // Byte enable width
+parameter AW = 26         ; // Address width
+parameter DW = 32         ; // DATA WIDTH
+parameter BEW = 4         ; // Byte enable width
+parameter TIMEOUT_ENB = 1 ; // TIMEOUT Generation enabled
 
 //----------------------------------------
 // Reg Bus reg inout declration
@@ -191,17 +192,18 @@
 		in_reg_ack          <= 1'b1;
                 in_state           <= INI_WAIT_TAR_DONE;
              end
-             else begin
-                 if(in_timer == 9'h1FF) begin
-                    in_flag          <= 1'b0;
-                    in_reg_ack       <= 1'b1;
-                    in_reg_rdata     <= 32'h0;
-                    in_reg_timeout   <= 1'b1;
-                    in_state         <= INI_IDLE;
-                 end
-                 else begin
-                     in_timer       <= in_timer + 1;
-                 end
+             else begin if(TIMEOUT_ENB) begin
+                    if(in_timer == 9'h1FF ) begin
+                       in_flag          <= 1'b0;
+                       in_reg_ack       <= 1'b1;
+                       in_reg_rdata     <= 32'h0;
+                       in_reg_timeout   <= 1'b1;
+                       in_state         <= INI_IDLE;
+                    end
+                    else begin
+                        in_timer       <= in_timer + 1;
+                    end
+                end
              end
            end
       INI_WAIT_TAR_DONE :
diff --git a/verilog/rtl/peripheral/src/peri_top.sv b/verilog/rtl/peripheral/src/peri_top.sv
new file mode 100755
index 0000000..352d0b4
--- /dev/null
+++ b/verilog/rtl/peripheral/src/peri_top.sv
@@ -0,0 +1,186 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya                          
+// 
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org>
+//
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Peripheral Top                                              ////
+////                                                              ////
+////  This file is part of the riscduino cores project            ////
+////  https://github.com/dineshannayya/riscduino.git              ////
+////                                                              ////
+////  Description                                                 ////
+////      Hold the All the Misc IP Integration                    ////
+////        A. dig2ang                                            ////
+////        B. RTC                                                ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 07 Dec 2022, Dinesh A                               ////
+////          initial version                                     ////
+//////////////////////////////////////////////////////////////////////
+
+`include "user_params.svh"
+module peri_top (
+                    `ifdef USE_POWER_PINS
+                       input logic             vccd1,// User area 1 1.8V supply
+                       input logic             vssd1,// User area 1 digital ground
+                    `endif
+                        // clock skew adjust
+                       input logic [3:0]       cfg_cska_peri,
+                       input logic	           wbd_clk_int,
+                       output logic	           wbd_clk_peri,
+
+                       // System Signals
+                       // Inputs
+		               input logic             mclk,
+                       input logic             s_reset_n              ,  // soft reset
+
+		       // Reg Bus Interface Signal
+                       input logic             reg_cs,
+                       input logic             reg_wr,
+                       input logic [10:0]      reg_addr,
+                       input logic [31:0]      reg_wdata,
+                       input logic [3:0]       reg_be,
+
+                       // Outputs
+                       output logic [31:0]     reg_rdata,
+                       output logic            reg_ack,
+
+                       // RTC Clock Domain
+                       input  logic            rtc_clk,
+                       output logic            rtc_intr,
+
+                       output logic            inc_time_s,
+                       output logic            inc_date_d,
+               
+                      // DAC Config
+                       output logic [7:0]      cfg_dac0_mux_sel,
+                       output logic [7:0]      cfg_dac1_mux_sel,
+                       output logic [7:0]      cfg_dac2_mux_sel,
+                       output logic [7:0]      cfg_dac3_mux_sel     
+
+   ); 
+
+
+
+logic         s_reset_ssn;  // Sync Reset
+
+
+//----------------------------------------
+//  Register Response Path Mux
+//  --------------------------------------
+
+logic [31:0]  reg_d2a_rdata;
+logic         reg_d2a_ack;
+logic         reg_d2a_cs;
+
+logic [31:0]  reg_rtc_rdata;
+logic         reg_rtc_ack;
+logic         reg_rtc_cs;
+
+assign reg_rdata  = (reg_addr[10:7] == `SEL_D2A) ? reg_d2a_rdata :
+                    (reg_addr[10:7] == `SEL_RTC) ? reg_rtc_rdata :
+                     'h0;
+assign reg_ack    = (reg_addr[10:7] == `SEL_D2A) ? reg_d2a_ack   :
+                    (reg_addr[10:7] == `SEL_RTC) ? reg_rtc_ack   :
+                    1'b0;
+assign reg_d2a_cs = (reg_addr[10:7] == `SEL_D2A)  ? reg_cs : 1'b0;
+assign reg_rtc_cs = (reg_addr[10:7] == `SEL_RTC)  ? reg_cs : 1'b0;
+
+
+// peri clock skew control
+clk_skew_adjust u_skew_peri
+       (
+`ifdef USE_POWER_PINS
+               .vccd1      (vccd1                      ),// User area 1 1.8V supply
+               .vssd1      (vssd1                      ),// User area 1 digital ground
+`endif
+	           .clk_in     (wbd_clk_int                ), 
+	           .sel        (cfg_cska_peri              ), 
+	           .clk_out    (wbd_clk_peri               ) 
+       );
+
+reset_sync  u_rst_sync (
+	      .scan_mode  (1'b0           ),
+          .dclk       (mclk           ), // Destination clock domain
+	      .arst_n     (s_reset_n      ), // active low async reset
+          .srst_n     (s_reset_ssn    )
+          );
+
+
+//-----------------------------------------------------------------------
+// Digital To Analog Register
+//-----------------------------------------------------------------------
+dig2ana_reg  u_d2a(
+              // System Signals
+              // Inputs
+		      .mclk                     ( mclk                      ),
+              .h_reset_n                (s_reset_ssn                ),
+
+		      // Reg Bus Interface Signal
+              .reg_cs                   (reg_d2a_cs                 ),
+              .reg_wr                   (reg_wr                     ),
+              .reg_addr                 (reg_addr[5:2]              ),
+              .reg_wdata                (reg_wdata[31:0]            ),
+              .reg_be                   (reg_be[3:0]                ),
+
+              // Outputs
+              .reg_rdata                (reg_d2a_rdata              ),
+              .reg_ack                  (reg_d2a_ack                ),
+
+              .cfg_dac0_mux_sel         (cfg_dac0_mux_sel           ),
+              .cfg_dac1_mux_sel         (cfg_dac1_mux_sel           ),
+              .cfg_dac2_mux_sel         (cfg_dac2_mux_sel           ),
+              .cfg_dac3_mux_sel         (cfg_dac3_mux_sel           )
+         );
+
+//-----------------------------------------------------------------------
+// RTC
+//-----------------------------------------------------------------------
+rtc_top  u_rtc(
+              // System Signals
+              // Inputs
+		      .sys_clk                  ( mclk                      ),
+              .rst_n                    (s_reset_ssn                ),
+
+		      // Reg Bus Interface Signal
+              .reg_cs                   (reg_rtc_cs                 ),
+              .reg_wr                   (reg_wr                     ),
+              .reg_addr                 (reg_addr[4:0]              ),
+              .reg_wdata                (reg_wdata[31:0]            ),
+              .reg_be                   (reg_be[3:0]                ),
+
+              // Outputs
+              .reg_rdata                (reg_rtc_rdata              ),
+              .reg_ack                  (reg_rtc_ack                ),
+
+              .rtc_clk                  (rtc_clk                    ),
+              .rtc_intr                 (rtc_intr                   ),
+
+              .inc_date_d               (inc_date_d                 ),
+              .inc_time_s               (inc_time_s                 )
+
+         );
+
+endmodule 
+
+
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv
index a1cd27b..28c315c 100644
--- a/verilog/rtl/pinmux/src/glbl_reg.sv
+++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -94,6 +94,7 @@
 		               input  logic            usb_intr               ,
 		               input  logic            i2cm_intr              ,
 		               input  logic            pwm_intr              ,
+		               input  logic            rtc_intr              ,
 
 		               output logic [15:0]     cfg_riscv_ctrl         ,
                        output  logic [31:0]    cfg_multi_func_sel     ,// multifunction pins
@@ -370,6 +371,7 @@
 
 logic usb_intr_s,usb_intr_ss;   // Usb Interrupt Double Sync
 logic i2cm_intr_s,i2cm_intr_ss; // I2C Interrupt Double Sync
+logic rtc_intr_s,rtc_intr_ss;
 
 always @ (posedge mclk or negedge s_reset_n)
 begin  
@@ -378,15 +380,19 @@
      usb_intr_ss  <= 'h0;
      i2cm_intr_s  <= 'h0;
      i2cm_intr_ss <= 'h0;
+     rtc_intr_s  <= 'h0;
+     rtc_intr_ss <= 'h0;
    end else begin
      usb_intr_s   <= usb_intr;
      usb_intr_ss  <= usb_intr_s;
      i2cm_intr_s  <= i2cm_intr;
      i2cm_intr_ss <= i2cm_intr_s;
+     rtc_intr_s   <= rtc_intr;
+     rtc_intr_ss  <= rtc_intr_s;
    end
 end
 
-wire [31:0] hware_intr_req = {gpio_intr[31:8], 2'b0,pwm_intr,usb_intr_ss, i2cm_intr_ss,timer_intr[2:0]};
+wire [31:0] hware_intr_req = {gpio_intr[31:8], 1'b0,rtc_intr_ss,pwm_intr,usb_intr_ss, i2cm_intr_ss,timer_intr[2:0]};
 
 generic_intr_stat_reg #(.WD(32),
 	                .RESET_DEFAULT(0)) u_reg4 (
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index f8143ed..cfb0312 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -508,8 +508,7 @@
      else if(cfg_port_d_dir_sel[4])  digital_io_oen[10]   = 1'b0;
 
      //Pin-9        PB6/WS[1]/XTAL1/TOSC1     digital_io[11]
-     if   (cfg_uart_enb[1])          digital_io_oen[11]   = 1'b1;
-     else if(cfg_port_b_port_type[6]) digital_io_oen[11]   = 1'b1;
+     if(cfg_port_b_port_type[6])       digital_io_oen[11]   = 1'b1;
      else if(cfg_port_b_dir_sel[6])    digital_io_oen[11]   = 1'b0;
 
      // Pin-10       PB7/WS[1]/XTAL2/TOSC2     digital_io[12]
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv
index 58419e2..0fb87ca 100755
--- a/verilog/rtl/pinmux/src/pinmux_top.sv
+++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -119,7 +119,7 @@
 		       // Reg Bus Interface Signal
                        input logic             reg_cs,
                        input logic             reg_wr,
-                       input logic [9:0]       reg_addr,
+                       input logic [10:0]      reg_addr,
                        input logic [31:0]      reg_wdata,
                        input logic [3:0]       reg_be,
 
@@ -198,13 +198,19 @@
                output logic[25:0]      cfg_dc_trim        , // External trim for DCO mode
                output logic            pll_ref_clk        , // Input oscillator to match
 
-               
-               // DAC Config
-               output logic [7:0]    cfg_dac0_mux_sel     ,
-               output logic [7:0]    cfg_dac1_mux_sel     ,
-               output logic [7:0]    cfg_dac2_mux_sel     ,
-               output logic [7:0]    cfg_dac3_mux_sel     
+		       // Peripheral Reg Bus Interface Signal
+               output logic             reg_peri_cs,
+               output logic             reg_peri_wr,
+               output logic [10:0]      reg_peri_addr,
+               output logic [31:0]      reg_peri_wdata,
+               output logic [3:0]       reg_peri_be,
 
+               // Input
+               input logic [31:0]       reg_peri_rdata,
+               input logic              reg_peri_ack,
+
+               input logic              rtc_intr
+               
    ); 
 
 
@@ -258,17 +264,6 @@
 
 assign      pinmux_debug = '0; // Todo: Need to fix
 
-//------------------------------------------------------
-// Register Map Decoding
-
-`define SEL_GLBL    3'b000   // GLOBAL REGISTER
-`define SEL_GPIO    3'b001   // GPIO REGISTER
-`define SEL_PWM     3'b010   // PWM REGISTER
-`define SEL_TIMER   3'b011   // TIMER REGISTER
-`define SEL_SEMA    3'b100   // SEMAPHORE REGISTER
-`define SEL_WS      3'b101   // WS281x  REGISTER
-`define SEL_D2A     3'b110   // Digital2Analog  REGISTER
-
 
 //----------------------------------------
 //  Register Response Path Mux
@@ -296,6 +291,15 @@
 
 logic [7:0]   pwm_gpio_in;
 
+logic         reg_glbl_cs ;
+logic         reg_gpio_cs ;
+logic         reg_pwm_cs  ;
+logic         reg_timer_cs;
+logic         reg_sema_cs ;
+logic         reg_ws_cs   ;
+
+
+
 
 //---------------------------------------------------------------------
 
@@ -389,6 +393,7 @@
           .usb_intr                     (usb_intr                ),
           .i2cm_intr                    (i2cm_intr               ),
           .pwm_intr                     (pwm_intr                ),
+          .rtc_intr                     (rtc_intr                ),
 
 
 
@@ -611,38 +616,11 @@
 
    ); 
 
-//-----------------------------------------------------------------------
-// Digital To Analog Register
-//-----------------------------------------------------------------------
-dig2ana_reg  u_d2a(
-              // System Signals
-              // Inputs
-		      .mclk                     ( mclk                      ),
-              .h_reset_n                (s_reset_ssn                ),
-
-		      // Reg Bus Interface Signal
-              .reg_cs                   (reg_d2a_cs                 ),
-              .reg_wr                   (reg_wr                     ),
-              .reg_addr                 (reg_addr[5:2]              ),
-              .reg_wdata                (reg_wdata[31:0]            ),
-              .reg_be                   (reg_be[3:0]                ),
-
-              // Outputs
-              .reg_rdata                (reg_d2a_rdata              ),
-              .reg_ack                  (reg_d2a_ack                ),
-
-              .cfg_dac0_mux_sel         (cfg_dac0_mux_sel           ),
-              .cfg_dac1_mux_sel         (cfg_dac1_mux_sel           ),
-              .cfg_dac2_mux_sel         (cfg_dac2_mux_sel           ),
-              .cfg_dac3_mux_sel         (cfg_dac3_mux_sel           )
-
-
-         );
 
 //-------------------------------------------------
 // Register Block Selection Logic
 //-------------------------------------------------
-reg [2:0] reg_blk_sel;
+reg [3:0] reg_blk_sel;
 
 always @(posedge mclk or negedge s_reset_ssn)
 begin
@@ -650,33 +628,46 @@
      reg_blk_sel <= 'h0;
    end
    else begin
-      if(reg_cs) reg_blk_sel <= reg_addr[9:7];
+      if(reg_cs) reg_blk_sel <= reg_addr[10:7];
    end
 end
 
-assign reg_rdata = (reg_blk_sel == `SEL_GLBL)  ? {reg_glbl_rdata} : 
-	               (reg_blk_sel == `SEL_GPIO)  ? {reg_gpio_rdata} :
-	               (reg_blk_sel == `SEL_PWM)   ? {reg_pwm_rdata}  :
-	               (reg_blk_sel == `SEL_TIMER) ? reg_timer_rdata  : 
-	               (reg_blk_sel == `SEL_SEMA)  ? {16'h0,reg_sema_rdata} : 
-	               (reg_blk_sel == `SEL_WS)    ? reg_ws_rdata     : 
-	               (reg_blk_sel == `SEL_D2A)   ? reg_d2a_rdata    : 'h0;
+assign reg_rdata = (reg_blk_sel    == `SEL_GLBL)  ? {reg_glbl_rdata} : 
+	               (reg_blk_sel    == `SEL_GPIO)  ? {reg_gpio_rdata} :
+	               (reg_blk_sel    == `SEL_PWM)   ? {reg_pwm_rdata}  :
+	               (reg_blk_sel    == `SEL_TIMER) ? reg_timer_rdata  : 
+	               (reg_blk_sel    == `SEL_SEMA)  ? {16'h0,reg_sema_rdata} : 
+	               (reg_blk_sel    == `SEL_WS)    ? reg_ws_rdata     : 
+	               (reg_blk_sel[3] == `SEL_PERI)  ? reg_peri_rdata   : 'h0;
 
-assign reg_ack   = (reg_blk_sel == `SEL_GLBL)  ? reg_glbl_ack   : 
-	               (reg_blk_sel == `SEL_GPIO)  ? reg_gpio_ack   : 
-	               (reg_blk_sel == `SEL_PWM)   ? reg_pwm_ack    : 
-	               (reg_blk_sel == `SEL_TIMER) ? reg_timer_ack  : 
-	               (reg_blk_sel == `SEL_SEMA)  ? reg_sema_ack   : 
-	               (reg_blk_sel == `SEL_WS)    ? reg_ws_ack     : 
-	               (reg_blk_sel == `SEL_D2A)   ? reg_d2a_ack    : 1'b0;
+assign reg_ack   = (reg_blk_sel    == `SEL_GLBL)  ? reg_glbl_ack   : 
+	               (reg_blk_sel    == `SEL_GPIO)  ? reg_gpio_ack   : 
+	               (reg_blk_sel    == `SEL_PWM)   ? reg_pwm_ack    : 
+	               (reg_blk_sel    == `SEL_TIMER) ? reg_timer_ack  : 
+	               (reg_blk_sel    == `SEL_SEMA)  ? reg_sema_ack   : 
+	               (reg_blk_sel    == `SEL_WS)    ? reg_ws_ack     : 
+	               (reg_blk_sel[3] == `SEL_PERI)  ? reg_peri_ack   : 1'b0;
 
-wire reg_glbl_cs  = (reg_addr[9:7] == `SEL_GLBL) ? reg_cs : 1'b0;
-wire reg_gpio_cs  = (reg_addr[9:7] == `SEL_GPIO) ? reg_cs : 1'b0;
-wire reg_pwm_cs   = (reg_addr[9:7] == `SEL_PWM)  ? reg_cs : 1'b0;
-wire reg_timer_cs = (reg_addr[9:7] == `SEL_TIMER)? reg_cs : 1'b0;
-wire reg_sema_cs  = (reg_addr[9:7] == `SEL_SEMA) ? reg_cs : 1'b0;
-wire reg_ws_cs    = (reg_addr[9:7] == `SEL_WS)   ? reg_cs : 1'b0;
-wire reg_d2a_cs   = (reg_addr[9:7] == `SEL_D2A)  ? reg_cs : 1'b0;
+assign reg_glbl_cs  = (reg_addr[10:7] == `SEL_GLBL) ? reg_cs : 1'b0;
+assign reg_gpio_cs  = (reg_addr[10:7] == `SEL_GPIO) ? reg_cs : 1'b0;
+assign reg_pwm_cs   = (reg_addr[10:7] == `SEL_PWM)  ? reg_cs : 1'b0;
+assign reg_timer_cs = (reg_addr[10:7] == `SEL_TIMER)? reg_cs : 1'b0;
+assign reg_sema_cs  = (reg_addr[10:7] == `SEL_SEMA) ? reg_cs : 1'b0;
+assign reg_ws_cs    = (reg_addr[10:7] == `SEL_WS)   ? reg_cs : 1'b0;
+assign reg_peri_cs  = (reg_addr[10]   == `SEL_PERI) ? reg_cs : 1'b0;
+
+assign  reg_peri_wr    = reg_wr;
+assign  reg_peri_addr  = reg_addr;
+assign  reg_peri_wdata = reg_wdata;
+assign  reg_peri_be    = reg_be;
+
+
+
+
+
+
+
+
 endmodule 
 
 
diff --git a/verilog/rtl/rtc b/verilog/rtl/rtc
new file mode 160000
index 0000000..6e2ff09
--- /dev/null
+++ b/verilog/rtl/rtc
@@ -0,0 +1 @@
+Subproject commit 6e2ff09c3037ff83ea0ced2b87823361ca8daa78
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index 9aebae3..82c3685 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh
@@ -4,12 +4,12 @@
 // ASCI Representation of RISC = 32'h8273_8343
 parameter CHIP_SIGNATURE = 32'h8273_8343;
 // Software Reg-1, Release date: <DAY><MONTH><YEAR>
-parameter CHIP_RELEASE_DATE = 32'h0412_2022;
+parameter CHIP_RELEASE_DATE = 32'h0712_2022;
 // Software Reg-2: Poject Revison 5.1 = 0005200
-parameter CHIP_REVISION   = 32'h0006_2000;
+parameter CHIP_REVISION   = 32'h0006_3000;
 
-parameter CLK_SKEW1_RESET_VAL = 32'b0000_0000_0100_0111_1000_1110_1000_0100;
-parameter CLK_SKEW2_RESET_VAL = 32'b1000_1000_1000_1000_1000_1000_0111_1110;
+parameter CLK_SKEW1_RESET_VAL = 32'b0100_0000_0100_0111_1001_1110_1000_0011;
+parameter CLK_SKEW2_RESET_VAL = 32'b0111_1000_1000_1000_0100_0100_1000_1110;
 
 parameter PSTRAP_DEFAULT_VALUE = 15'b000_0011_1010_0000;
 
@@ -149,6 +149,17 @@
 `define STRAP_QSPI_INIT_BYPASS     30
 `define STRAP_SOFT_REBOOT_REQ      31
 
+//------------------------------------------------------
+// Pinumux/PeriPheral Register Map Decoding
 
+`define SEL_GLBL    4'b0000   // GLOBAL REGISTER
+`define SEL_GPIO    4'b0001   // GPIO REGISTER
+`define SEL_PWM     4'b0010   // PWM REGISTER
+`define SEL_TIMER   4'b0011   // TIMER REGISTER
+`define SEL_SEMA    4'b0100   // SEMAPHORE REGISTER
+`define SEL_WS      4'b0101   // WS281x  REGISTER
+`define SEL_PERI    1'b1      // Peripheral
+`define SEL_D2A     4'b1000   // Digital2Analog  REGISTER
+`define SEL_RTC     4'b1001   // RTC     REGISTER
 `endif // USER_PARMS
 
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 926f6f4..9c767a2 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -42,6 +42,7 @@
 ////      15. SPI Slave (As Arduino ISP)                          ////
 ////      16. AES 126 Encription/Decryption                       ////
 ////      17. FPU (Single Precision)                              ////
+////      18. RTC                                                 ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
@@ -296,6 +297,9 @@
 ////    6.2  Dec 4, 2022, Dinesh A                                ////
 ////         Bus repeater north/south/east/west added for better  ////
 ////         global buffering                                     ////
+////    6.3  Dec 7, 2022, Dinesh A                                ////
+////         A. peripheral block integration                      ////
+////         B. RTC Integration                                   ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -570,7 +574,7 @@
 //    Global Register Wishbone Interface
 //---------------------------------------------------------------------
 wire                           wbd_glbl_stb_o                         ; // strobe/request
-wire   [9:0]                   wbd_glbl_adr_o                         ; // address
+wire   [10:0]                  wbd_glbl_adr_o                         ; // address
 wire                           wbd_glbl_we_o                          ; // write
 wire   [WB_WIDTH-1:0]          wbd_glbl_dat_o                         ; // data output
 wire   [3:0]                   wbd_glbl_sel_o                         ; // byte enable
@@ -622,14 +626,15 @@
 wire [7:0]                     cfg_glb_ctrl                           ;
 wire [31:0]                    cfg_clk_skew_ctrl1                     ;
 wire [31:0]                    cfg_clk_skew_ctrl2                     ;
-wire [3:0]                     cfg_wcska_wi                            ; // clock skew adjust for wishbone interconnect
-wire [3:0]                     cfg_wcska_wh                            ; // clock skew adjust for web host
+wire [3:0]                     cfg_wcska_wi                           ; // clock skew adjust for wishbone interconnect
+wire [3:0]                     cfg_wcska_wh                           ; // clock skew adjust for web host
+wire [3:0]                     cfg_wcska_peri                         ; // clock skew adjust for peripheral
 
-wire [3:0]                     cfg_wcska_riscv                         ; // clock skew adjust for riscv
-wire [3:0]                     cfg_wcska_uart                          ; // clock skew adjust for uart
-wire [3:0]                     cfg_wcska_qspi                          ; // clock skew adjust for spi
-wire [3:0]                     cfg_wcska_pinmux                        ; // clock skew adjust for pinmux
-wire [3:0]                     cfg_wcska_qspi_co                       ; // clock skew adjust for global reg
+wire [3:0]                     cfg_wcska_riscv                        ; // clock skew adjust for riscv
+wire [3:0]                     cfg_wcska_uart                         ; // clock skew adjust for uart
+wire [3:0]                     cfg_wcska_qspi                         ; // clock skew adjust for spi
+wire [3:0]                     cfg_wcska_pinmux                       ; // clock skew adjust for pinmux
+wire [3:0]                     cfg_wcska_qspi_co                      ; // clock skew adjust for global reg
 
 // Bus Repeater Signals  output from Wishbone Interface
 wire [3:0]                     cfg_wcska_riscv_rp                      ; // clock skew adjust for riscv
@@ -637,6 +642,7 @@
 wire [3:0]                     cfg_wcska_qspi_rp                       ; // clock skew adjust for spi
 wire [3:0]                     cfg_wcska_pinmux_rp                     ; // clock skew adjust for pinmux
 wire [3:0]                     cfg_wcska_qspi_co_rp                    ; // clock skew adjust for global reg
+wire [3:0]                     cfg_wcska_peri_rp                       ; // clock skew adjust for peripheral 
 
 wire [31:0]                    irq_lines_rp                           ; // Repeater
 wire                           soft_irq_rp                            ; // Repeater
@@ -646,6 +652,8 @@
 wire                           wbd_clk_uart_rp                        ;
 wire                           wbd_clk_pinmux_rp                      ;
 wire                           wbd_clk_pinmux_skew                    ;
+wire                           wbd_clk_peri_rp                        ;
+wire                           wbd_clk_peri_skew                      ;
 
 // Progammable Clock Skew inserted signals
 wire                           wbd_clk_wi_skew                        ; // clock for wishbone interconnect with clock skew
@@ -759,6 +767,7 @@
 // AES Integration local decleration
 //------------------------------------------------------------
 wire                           cpu_clk_aes                            ;
+wire                           cpu_clk_aes_skew                       ;
 wire [3:0]                     cfg_ccska_aes                          ;
 wire [3:0]                     cfg_ccska_aes_rp                       ;
 wire                           aes_dmem_req                           ;
@@ -773,7 +782,8 @@
 //------------------------------------------------------------
 // FPU Integration local decleration
 //------------------------------------------------------------
-wire                           cpu_clk_fpu                            ;
+wire                           cpu_clk_fpu                           ;
+wire                           cpu_clk_fpu_skew                       ;
 wire [3:0]                     cfg_ccska_fpu                          ;
 wire [3:0]                     cfg_ccska_fpu_rp                       ;
 wire                           fpu_dmem_req                           ;
@@ -821,6 +831,19 @@
 wire [7:0]                     cfg_dac3_mux_sel                       ;
 
 //---------------------------------------------------------------------
+// Peripheral Reg I/F
+//---------------------------------------------------------------------
+wire                           reg_peri_cs                            ;
+wire                           reg_peri_wr                            ;
+wire [10:0]                    reg_peri_addr                          ;
+wire [31:0]                    reg_peri_wdata                         ;
+wire [3:0]                     reg_peri_be                            ;
+
+wire [31:0]                    reg_peri_rdata                         ;
+wire                           reg_peri_ack                           ;
+
+wire                           rtc_intr                               ; // RTC interrupt
+//---------------------------------------------------------------------
 // Strap
 //---------------------------------------------------------------------
 wire [31:0]                    system_strap                           ;
@@ -858,6 +881,7 @@
 assign cfg_wcska_uart        = cfg_clk_skew_ctrl1[19:16];
 assign cfg_wcska_pinmux      = cfg_clk_skew_ctrl1[23:20];
 assign cfg_wcska_qspi_co     = cfg_clk_skew_ctrl1[27:24];
+assign cfg_wcska_peri        = cfg_clk_skew_ctrl1[31:28];
 
 /////////////////////////////////////////////////////////
 // RISCV Clock skew control
@@ -885,19 +909,21 @@
 //-------------------------------------
 // cpu clock repeater mapping
 //-------------------------------------
-wire [9:0] cpu_clk_rp;
+wire [2:0] cpu_clk_rp;
 
-wire [5:0] cpu_clk_rp_risc   = cpu_clk_rp[5:0];
-wire       cpu_clk_rp_aes    = cpu_clk_rp[6];
-wire       cpu_clk_rp_fpu    = cpu_clk_rp[7];
-wire       cpu_clk_rp_pinmux = cpu_clk_rp[8];
+wire [1:0] cpu_clk_rp_risc   = cpu_clk_rp[1:0];
+wire       cpu_clk_rp_pinmux = cpu_clk_rp[2];
 
 //----------------------------------------------------------
 // Bus Repeater Initiatiation
 //----------------------------------------------------------
 wire  [37:0]                io_in_rp           ;
+wire  [37:0]                io_in_rp1          ;
+wire  [37:0]                io_in_rp2          ;
 wire  [37:0]                io_out_int         ;
 wire  [37:0]                io_oeb_int         ;
+wire  [37:0]                io_out_rp1         ;
+wire  [37:0]                io_oeb_rp1         ;
 wire                        user_clock2_rp     ;
 
 `include "bus_repeater.sv"
@@ -1144,6 +1170,7 @@
           .wbd_dmem_lack_i         (wbd_riscv_dmem_lack_o   ),
           .wbd_dmem_err_i          (wbd_riscv_dmem_err_o    ),
 
+          .cpu_clk_aes             (cpu_clk_aes             ),
           .aes_dmem_req            (aes_dmem_req            ),
           .aes_dmem_cmd            (aes_dmem_cmd            ),
           .aes_dmem_width          (aes_dmem_width          ),
@@ -1153,6 +1180,7 @@
           .aes_dmem_rdata          (aes_dmem_rdata          ),
           .aes_dmem_resp           (aes_dmem_resp           ),
 
+          .cpu_clk_fpu             (cpu_clk_fpu             ),
           .fpu_dmem_req            (fpu_dmem_req            ),
           .fpu_dmem_cmd            (fpu_dmem_cmd            ),
           .fpu_dmem_width          (fpu_dmem_width          ),
@@ -1163,6 +1191,10 @@
           .fpu_dmem_resp           (fpu_dmem_resp           )
 );
 
+//----------------------------------------------
+// TCM
+//----------------------------------------------
+
 `ifndef SCR1_TCM_MEM
 sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb(
 `ifdef USE_POWER_PINS
@@ -1207,6 +1239,9 @@
 ***/
 `endif
 
+//------------------------------------------------
+// icache
+//------------------------------------------------
 
 sky130_sram_2kbyte_1rw1r_32x512_8 u_icache_2kb(
 `ifdef USE_POWER_PINS
@@ -1228,6 +1263,10 @@
           .dout1              (icache_mem_dout1             )
   );
 
+//----------------------------------------------------------
+// dcache
+//----------------------------------------------------------
+
 sky130_sram_2kbyte_1rw1r_32x512_8 u_dcache_2kb(
 `ifdef USE_POWER_PINS
           .vccd1              (vccd1                        ),// User area 1 1.8V supply
@@ -1257,12 +1296,12 @@
     .vssd1                 (vssd1            ),
 `endif
 
-    .mclk                  (cpu_clk_aes      ),
+    .mclk                  (cpu_clk_aes_skew ),
     .rst_n                 (cpu_intf_rst_n   ),
 
     .cfg_cska              (cfg_ccska_aes_rp ),
-    .wbd_clk_int           (cpu_clk_rp_aes   ),
-    .wbd_clk_out           (cpu_clk_aes      ),
+    .wbd_clk_int           (cpu_clk_aes      ),
+    .wbd_clk_out           (cpu_clk_aes_skew ),
 
     .dmem_req              (aes_dmem_req     ),
     .dmem_cmd              (aes_dmem_cmd     ),
@@ -1283,21 +1322,21 @@
     .vssd1                 (vssd1            ),
 `endif
 
-    .mclk                  (cpu_clk_fpu      ),
-    .rst_n                 (cpu_intf_rst_n   ),
+          .mclk               (cpu_clk_fpu_skew             ),
+          .rst_n              (cpu_intf_rst_n               ),
 
-    .cfg_cska              (cfg_ccska_fpu_rp ),
-    .wbd_clk_int           (cpu_clk_rp_fpu   ),
-    .wbd_clk_out           (cpu_clk_fpu      ),
+          .cfg_cska           (cfg_ccska_fpu_rp             ),
+          .wbd_clk_int        (cpu_clk_fpu                  ),
+          .wbd_clk_out        (cpu_clk_fpu_skew             ),
 
-    .dmem_req              (fpu_dmem_req     ),
-    .dmem_cmd              (fpu_dmem_cmd     ),
-    .dmem_width            (fpu_dmem_width   ),
-    .dmem_addr             (fpu_dmem_addr    ),
-    .dmem_wdata            (fpu_dmem_wdata   ),
-    .dmem_req_ack          (fpu_dmem_req_ack ),
-    .dmem_rdata            (fpu_dmem_rdata   ),
-    .dmem_resp             (fpu_dmem_resp    )
+          .dmem_req           (fpu_dmem_req                 ),
+          .dmem_cmd           (fpu_dmem_cmd                 ),
+          .dmem_width         (fpu_dmem_width               ),
+          .dmem_addr          (fpu_dmem_addr                ),
+          .dmem_wdata         (fpu_dmem_wdata               ),
+          .dmem_req_ack       (fpu_dmem_req_ack             ),
+          .dmem_rdata         (fpu_dmem_rdata               ),
+          .dmem_resp          (fpu_dmem_resp                )
 );
 
 /*********************************************************
@@ -1356,39 +1395,38 @@
 );
 
 
+//---------------------------------------------------
+// wb_interconnect
+//---------------------------------------------------
 
 wb_interconnect  #(
 	`ifndef SYNTHESIS
-          .CH_CLK_WD           (14                      ),
-	      .CH_DATA_WD          (154                     )
+          .CH_CLK_WD          (8                            ),
+          .CH_DATA_WD         (158                          )
         `endif
 	) u_intercon (
 `ifdef USE_POWER_PINS
-          .vccd1                   (vccd1                   ),// User area 1 1.8V supply
-          .vssd1                   (vssd1                   ),// User area 1 digital ground
+       .vccd1              (vccd1                        ),// User area 1 1                                                     .8V supply
+       .vssd1              (vssd1                        ),// User area 1 digital ground
 `endif
-	  .ch_clk_in               ({
+	  .ch_clk_in              ({
                                      cpu_clk,
                                      cpu_clk,
                                      cpu_clk,
-                                     cpu_clk,
-                                     cpu_clk,
-                                     cpu_clk,
-                                     cpu_clk,
-                                     cpu_clk,
-                                     cpu_clk,
-                                     cpu_clk,
+                                     wbd_clk_int, 
                                      wbd_clk_int, 
                                      wbd_clk_int, 
                                      wbd_clk_int, 
                                      wbd_clk_int}                  ),
-	  .ch_clk_out              ({
+	  .ch_clk_out             ({
                                      cpu_clk_rp,
+                                     wbd_clk_peri_rp, 
                                      wbd_clk_pinmux_rp, 
                                      wbd_clk_uart_rp, 
                                      wbd_clk_qspi_rp, 
                                      wbd_clk_risc_rp}              ),
-	  .ch_data_in              ({
+	  .ch_data_in             ({
+			                      cfg_wcska_peri[3:0],
                                   cfg_ccska_fpu[3:0],
                                   cfg_ccska_aes[3:0],
                                   strap_sticky[31:0],
@@ -1414,7 +1452,8 @@
 		                          cfg_wcska_qspi[3:0],
                                   cfg_wcska_riscv[3:0]
 			             }                             ),
-	  .ch_data_out             ({
+	  .ch_data_out            ({
+		                          cfg_wcska_peri_rp[3:0],
 			                      cfg_ccska_fpu_rp[3:0],
 			                      cfg_ccska_aes_rp[3:0],
                                   strap_sticky_rp[31:0],
@@ -1441,309 +1480,372 @@
                                   cfg_wcska_riscv_rp[3:0]
                                } ),
      // Clock Skew adjust
-	  .wbd_clk_int                 (wbd_clk_int             ), 
-	  .cfg_cska_wi                 (cfg_wcska_wi            ), 
-	  .wbd_clk_wi                  (wbd_clk_wi_skew         ),
+          .wbd_clk_int        (wbd_clk_int                  ), 
+          .cfg_cska_wi        (cfg_wcska_wi                 ), 
+          .wbd_clk_wi         (wbd_clk_wi_skew              ),
 
-          .clk_i                   (wbd_clk_wi_skew         ), 
-          .rst_n                   (wbd_int_rst_n           ),
+          .clk_i              (wbd_clk_wi_skew              ), 
+          .rst_n              (wbd_int_rst_n                ),
 
          // Master 0 Interface
-          .m0_wbd_dat_i            (wbd_int_dat_i           ),
-          .m0_wbd_adr_i            (wbd_int_adr_i           ),
-          .m0_wbd_sel_i            (wbd_int_sel_i           ),
-          .m0_wbd_we_i             (wbd_int_we_i            ),
-          .m0_wbd_cyc_i            (wbd_int_cyc_i           ),
-          .m0_wbd_stb_i            (wbd_int_stb_i           ),
-          .m0_wbd_dat_o            (wbd_int_dat_o           ),
-          .m0_wbd_ack_o            (wbd_int_ack_o           ),
-          .m0_wbd_err_o            (wbd_int_err_o           ),
+          .m0_wbd_dat_i       (wbd_int_dat_i                ),
+          .m0_wbd_adr_i       (wbd_int_adr_i                ),
+          .m0_wbd_sel_i       (wbd_int_sel_i                ),
+          .m0_wbd_we_i        (wbd_int_we_i                 ),
+          .m0_wbd_cyc_i       (wbd_int_cyc_i                ),
+          .m0_wbd_stb_i       (wbd_int_stb_i                ),
+          .m0_wbd_dat_o       (wbd_int_dat_o                ),
+          .m0_wbd_ack_o       (wbd_int_ack_o                ),
+          .m0_wbd_err_o       (wbd_int_err_o                ),
          
          // Master 1 Interface
-          .m1_wbd_dat_i            (wbd_riscv_dmem_dat_i    ),
-          .m1_wbd_adr_i            (wbd_riscv_dmem_adr_i    ),
-          .m1_wbd_sel_i            (wbd_riscv_dmem_sel_i    ),
-          .m1_wbd_bl_i             (wbd_riscv_dmem_bl_i    ),
-          .m1_wbd_bry_i            (wbd_riscv_dmem_bry_i    ),
-          .m1_wbd_we_i             (wbd_riscv_dmem_we_i     ),
-          .m1_wbd_cyc_i            (wbd_riscv_dmem_stb_i    ),
-          .m1_wbd_stb_i            (wbd_riscv_dmem_stb_i    ),
-          .m1_wbd_dat_o            (wbd_riscv_dmem_dat_o    ),
-          .m1_wbd_ack_o            (wbd_riscv_dmem_ack_o    ),
-          .m1_wbd_lack_o           (wbd_riscv_dmem_lack_o   ),
-          .m1_wbd_err_o            (wbd_riscv_dmem_err_o    ),
+          .m1_wbd_dat_i       (wbd_riscv_dmem_dat_i         ),
+          .m1_wbd_adr_i       (wbd_riscv_dmem_adr_i         ),
+          .m1_wbd_sel_i       (wbd_riscv_dmem_sel_i         ),
+          .m1_wbd_bl_i        (wbd_riscv_dmem_bl_i          ),
+          .m1_wbd_bry_i       (wbd_riscv_dmem_bry_i         ),
+          .m1_wbd_we_i        (wbd_riscv_dmem_we_i          ),
+          .m1_wbd_cyc_i       (wbd_riscv_dmem_stb_i         ),
+          .m1_wbd_stb_i       (wbd_riscv_dmem_stb_i         ),
+          .m1_wbd_dat_o       (wbd_riscv_dmem_dat_o         ),
+          .m1_wbd_ack_o       (wbd_riscv_dmem_ack_o         ),
+          .m1_wbd_lack_o      (wbd_riscv_dmem_lack_o        ),
+          .m1_wbd_err_o       (wbd_riscv_dmem_err_o         ),
          
          // Master 2 Interface
-          .m2_wbd_dat_i            (wbd_riscv_dcache_dat_i  ),
-          .m2_wbd_adr_i            (wbd_riscv_dcache_adr_i  ),
-          .m2_wbd_sel_i            (wbd_riscv_dcache_sel_i  ),
-          .m2_wbd_bl_i             (wbd_riscv_dcache_bl_i   ),
-          .m2_wbd_bry_i            (wbd_riscv_dcache_bry_i  ),
-          .m2_wbd_we_i             (wbd_riscv_dcache_we_i   ),
-          .m2_wbd_cyc_i            (wbd_riscv_dcache_stb_i  ),
-          .m2_wbd_stb_i            (wbd_riscv_dcache_stb_i  ),
-          .m2_wbd_dat_o            (wbd_riscv_dcache_dat_o  ),
-          .m2_wbd_ack_o            (wbd_riscv_dcache_ack_o  ),
-          .m2_wbd_lack_o           (wbd_riscv_dcache_lack_o ),
-          .m2_wbd_err_o            (wbd_riscv_dcache_err_o  ),
+          .m2_wbd_dat_i       (wbd_riscv_dcache_dat_i       ),
+          .m2_wbd_adr_i       (wbd_riscv_dcache_adr_i       ),
+          .m2_wbd_sel_i       (wbd_riscv_dcache_sel_i       ),
+          .m2_wbd_bl_i        (wbd_riscv_dcache_bl_i        ),
+          .m2_wbd_bry_i       (wbd_riscv_dcache_bry_i       ),
+          .m2_wbd_we_i        (wbd_riscv_dcache_we_i        ),
+          .m2_wbd_cyc_i       (wbd_riscv_dcache_stb_i       ),
+          .m2_wbd_stb_i       (wbd_riscv_dcache_stb_i       ),
+          .m2_wbd_dat_o       (wbd_riscv_dcache_dat_o       ),
+          .m2_wbd_ack_o       (wbd_riscv_dcache_ack_o       ),
+          .m2_wbd_lack_o      (wbd_riscv_dcache_lack_o      ),
+          .m2_wbd_err_o       (wbd_riscv_dcache_err_o       ),
 
          // Master 3 Interface
-          .m3_wbd_adr_i            (wbd_riscv_icache_adr_i  ),
-          .m3_wbd_sel_i            (wbd_riscv_icache_sel_i  ),
-          .m3_wbd_bl_i             (wbd_riscv_icache_bl_i   ),
-          .m3_wbd_bry_i            (wbd_riscv_icache_bry_i  ),
-          .m3_wbd_we_i             (wbd_riscv_icache_we_i   ),
-          .m3_wbd_cyc_i            (wbd_riscv_icache_stb_i  ),
-          .m3_wbd_stb_i            (wbd_riscv_icache_stb_i  ),
-          .m3_wbd_dat_o            (wbd_riscv_icache_dat_o  ),
-          .m3_wbd_ack_o            (wbd_riscv_icache_ack_o  ),
-          .m3_wbd_lack_o           (wbd_riscv_icache_lack_o ),
-          .m3_wbd_err_o            (wbd_riscv_icache_err_o  ),
+          .m3_wbd_adr_i       (wbd_riscv_icache_adr_i       ),
+          .m3_wbd_sel_i       (wbd_riscv_icache_sel_i       ),
+          .m3_wbd_bl_i        (wbd_riscv_icache_bl_i        ),
+          .m3_wbd_bry_i       (wbd_riscv_icache_bry_i       ),
+          .m3_wbd_we_i        (wbd_riscv_icache_we_i        ),
+          .m3_wbd_cyc_i       (wbd_riscv_icache_stb_i       ),
+          .m3_wbd_stb_i       (wbd_riscv_icache_stb_i       ),
+          .m3_wbd_dat_o       (wbd_riscv_icache_dat_o       ),
+          .m3_wbd_ack_o       (wbd_riscv_icache_ack_o       ),
+          .m3_wbd_lack_o      (wbd_riscv_icache_lack_o      ),
+          .m3_wbd_err_o       (wbd_riscv_icache_err_o       ),
          
          
          // Slave 0 Interface
-       // .s0_wbd_err_i            (1'b0                    ), - Moved inside IP
-          .s0_wbd_dat_i            (wbd_spim_dat_i          ),
-          .s0_wbd_ack_i            (wbd_spim_ack_i          ),
-          .s0_wbd_lack_i           (wbd_spim_lack_i         ),
-          .s0_wbd_dat_o            (wbd_spim_dat_o          ),
-          .s0_wbd_adr_o            (wbd_spim_adr_o          ),
-          .s0_wbd_bry_o            (wbd_spim_bry_o          ),
-          .s0_wbd_bl_o             (wbd_spim_bl_o           ),
-          .s0_wbd_sel_o            (wbd_spim_sel_o          ),
-          .s0_wbd_we_o             (wbd_spim_we_o           ),  
-          .s0_wbd_cyc_o            (wbd_spim_cyc_o          ),
-          .s0_wbd_stb_o            (wbd_spim_stb_o          ),
+       // .s0_wbd_err_i       (1'b0                         ), - Moved inside IP
+          .s0_wbd_dat_i       (wbd_spim_dat_i               ),
+          .s0_wbd_ack_i       (wbd_spim_ack_i               ),
+          .s0_wbd_lack_i      (wbd_spim_lack_i              ),
+          .s0_wbd_dat_o       (wbd_spim_dat_o               ),
+          .s0_wbd_adr_o       (wbd_spim_adr_o               ),
+          .s0_wbd_bry_o       (wbd_spim_bry_o               ),
+          .s0_wbd_bl_o        (wbd_spim_bl_o                ),
+          .s0_wbd_sel_o       (wbd_spim_sel_o               ),
+          .s0_wbd_we_o        (wbd_spim_we_o                ),  
+          .s0_wbd_cyc_o       (wbd_spim_cyc_o               ),
+          .s0_wbd_stb_o       (wbd_spim_stb_o               ),
          
          // Slave 1 Interface
-       // .s1_wbd_err_i            (1'b0                    ), - Moved inside IP
-          .s1_wbd_dat_i            (wbd_uart_dat_i          ),
-          .s1_wbd_ack_i            (wbd_uart_ack_i          ),
-          .s1_wbd_dat_o            (wbd_uart_dat_o          ),
-          .s1_wbd_adr_o            (wbd_uart_adr_o          ),
-          .s1_wbd_sel_o            (wbd_uart_sel_o          ),
-          .s1_wbd_we_o             (wbd_uart_we_o           ),  
-          .s1_wbd_cyc_o            (wbd_uart_cyc_o          ),
-          .s1_wbd_stb_o            (wbd_uart_stb_o          ),
+       // .s1_wbd_err_i       (1'b0                         ), - Moved inside IP
+          .s1_wbd_dat_i       (wbd_uart_dat_i               ),
+          .s1_wbd_ack_i       (wbd_uart_ack_i               ),
+          .s1_wbd_dat_o       (wbd_uart_dat_o               ),
+          .s1_wbd_adr_o       (wbd_uart_adr_o               ),
+          .s1_wbd_sel_o       (wbd_uart_sel_o               ),
+          .s1_wbd_we_o        (wbd_uart_we_o                ),  
+          .s1_wbd_cyc_o       (wbd_uart_cyc_o               ),
+          .s1_wbd_stb_o       (wbd_uart_stb_o               ),
          
          // Slave 2 Interface
-       // .s2_wbd_err_i            (1'b0                    ), - Moved inside IP
-          .s2_wbd_dat_i            (wbd_glbl_dat_i          ),
-          .s2_wbd_ack_i            (wbd_glbl_ack_i          ),
-          .s2_wbd_dat_o            (wbd_glbl_dat_o          ),
-          .s2_wbd_adr_o            (wbd_glbl_adr_o          ),
-          .s2_wbd_sel_o            (wbd_glbl_sel_o          ),
-          .s2_wbd_we_o             (wbd_glbl_we_o           ),  
-          .s2_wbd_cyc_o            (wbd_glbl_cyc_o          ),
-          .s2_wbd_stb_o            (wbd_glbl_stb_o          )
+       // .s2_wbd_err_i       (1'b0                         ), - Moved inside IP
+          .s2_wbd_dat_i       (wbd_glbl_dat_i               ),
+          .s2_wbd_ack_i       (wbd_glbl_ack_i               ),
+          .s2_wbd_dat_o       (wbd_glbl_dat_o               ),
+          .s2_wbd_adr_o       (wbd_glbl_adr_o               ),
+          .s2_wbd_sel_o       (wbd_glbl_sel_o               ),
+          .s2_wbd_we_o        (wbd_glbl_we_o                ),  
+          .s2_wbd_cyc_o       (wbd_glbl_cyc_o               ),
+          .s2_wbd_stb_o       (wbd_glbl_stb_o               )
 
 
 	);
 
+//-----------------------------------------------
+// uart+i2c+usb+spi
+//-----------------------------------------------
 
 uart_i2c_usb_spi_top   u_uart_i2c_usb_spi (
 `ifdef USE_POWER_PINS
-          .vccd1                   (vccd1                   ),// User area 1 1.8V supply
-          .vssd1                   (vssd1                   ),// User area 1 digital ground
+          .vccd1              (vccd1                        ),// User area 1 1.8V supply
+          .vssd1              (vssd1                        ),// User area 1 digital ground
 `endif
-          .wbd_clk_int             (wbd_clk_uart_rp         ), 
-          .cfg_cska_uart           (cfg_wcska_uart_rp        ), 
-          .wbd_clk_uart            (wbd_clk_uart_skew       ),
+          .wbd_clk_int        (wbd_clk_uart_rp              ), 
+          .cfg_cska_uart      (cfg_wcska_uart_rp            ), 
+          .wbd_clk_uart       (wbd_clk_uart_skew            ),
 
-          .uart_rstn               (uart_rst_n              ), // uart reset
-          .i2c_rstn                (i2c_rst_n               ), // i2c reset
-          .usb_rstn                (usb_rst_n               ), // USB reset
-          .spi_rstn                (sspim_rst_n             ), // SPI reset
-          .app_clk                 (wbd_clk_uart_skew       ),
-	      .usb_clk                 (usb_clk                 ),
+          .uart_rstn          (uart_rst_n                   ), // uart reset
+          .i2c_rstn           (i2c_rst_n                    ), // i2c reset
+          .usb_rstn           (usb_rst_n                    ), // USB reset
+          .spi_rstn           (sspim_rst_n                  ), // SPI reset
+          .app_clk            (wbd_clk_uart_skew            ),
+          .usb_clk            (usb_clk                      ),
 
         // Reg Bus Interface Signal
-          .reg_cs                  (wbd_uart_stb_o          ),
-          .reg_wr                  (wbd_uart_we_o           ),
-          .reg_addr                (wbd_uart_adr_o[8:0]     ),
-          .reg_wdata               (wbd_uart_dat_o          ),
-          .reg_be                  (wbd_uart_sel_o          ),
+          .reg_cs             (wbd_uart_stb_o               ),
+          .reg_wr             (wbd_uart_we_o                ),
+          .reg_addr           (wbd_uart_adr_o[8:0]          ),
+          .reg_wdata          (wbd_uart_dat_o               ),
+          .reg_be             (wbd_uart_sel_o               ),
 
        // Outputs
-          .reg_rdata               (wbd_uart_dat_i          ),
-          .reg_ack                 (wbd_uart_ack_i          ),
+          .reg_rdata          (wbd_uart_dat_i               ),
+          .reg_ack            (wbd_uart_ack_i               ),
 
        // Pad interface
-          .scl_pad_i               (i2cm_clk_i              ),
-          .scl_pad_o               (i2cm_clk_o              ),
-          .scl_pad_oen_o           (i2cm_clk_oen            ),
+          .scl_pad_i          (i2cm_clk_i                   ),
+          .scl_pad_o          (i2cm_clk_o                   ),
+          .scl_pad_oen_o      (i2cm_clk_oen                 ),
 
-          .sda_pad_i               (i2cm_data_i             ),
-          .sda_pad_o               (i2cm_data_o             ),
-          .sda_padoen_o            (i2cm_data_oen           ),
+          .sda_pad_i          (i2cm_data_i                  ),
+          .sda_pad_o          (i2cm_data_o                  ),
+          .sda_padoen_o       (i2cm_data_oen                ),
      
-          .i2cm_intr_o             (i2cm_intr_o             ),
+          .i2cm_intr_o        (i2cm_intr_o                  ),
 
-          .uart_rxd                (uart_rxd                ),
-          .uart_txd                (uart_txd                ),
+          .uart_rxd           (uart_rxd                     ),
+          .uart_txd           (uart_txd                     ),
 
-          .usb_in_dp               (usb_dp_i                ),
-          .usb_in_dn               (usb_dn_i                ),
+          .usb_in_dp          (usb_dp_i                     ),
+          .usb_in_dn          (usb_dn_i                     ),
 
-          .usb_out_dp              (usb_dp_o                ),
-          .usb_out_dn              (usb_dn_o                ),
-          .usb_out_tx_oen          (usb_oen                 ),
+          .usb_out_dp         (usb_dp_o                     ),
+          .usb_out_dn         (usb_dn_o                     ),
+          .usb_out_tx_oen     (usb_oen                      ),
        
-          .usb_intr_o              (usb_intr_o              ),
+          .usb_intr_o         (usb_intr_o                   ),
 
       // SPIM Master
-          .sspim_sck               (sspim_sck               ), 
-          .sspim_so                (sspim_so                ),  
-          .sspim_si                (sspim_si                ),  
-          .sspim_ssn               (sspim_ssn               )  
+          .sspim_sck          (sspim_sck                    ), 
+          .sspim_so           (sspim_so                     ),  
+          .sspim_si           (sspim_si                     ),  
+          .sspim_ssn          (sspim_ssn                    )  
 
      );
 
+//---------------------------------------
+// Pinmux
+//---------------------------------------
+
 pinmux_top u_pinmux(
 `ifdef USE_POWER_PINS
-          .vccd1                   (vccd1                   ),// User area 1 1.8V supply
-          .vssd1                   (vssd1                   ),// User area 1 digital ground
+          .vccd1              (vccd1                        ),// User area 1 1.8V supply
+          .vssd1              (vssd1                        ),// User area 1 digital ground
 `endif
         //clk skew adjust
-          .cfg_cska_pinmux         (cfg_wcska_pinmux_rp      ),
-          .wbd_clk_int             (wbd_clk_pinmux_rp       ),
-          .wbd_clk_pinmux          (wbd_clk_pinmux_skew     ),
+          .cfg_cska_pinmux    (cfg_wcska_pinmux_rp          ),
+          .wbd_clk_int        (wbd_clk_pinmux_rp            ),
+          .wbd_clk_pinmux     (wbd_clk_pinmux_skew          ),
 
         // System Signals
         // Inputs
-          .mclk                    (wbd_clk_pinmux_skew     ),
-          .e_reset_n               (e_reset_n_rp            ),
-          .p_reset_n               (p_reset_n_rp            ),
-          .s_reset_n               (wbd_int_rst_n           ),
+          .mclk               (wbd_clk_pinmux_skew          ),
+          .e_reset_n          (e_reset_n_rp                 ),
+          .p_reset_n          (p_reset_n_rp                 ),
+          .s_reset_n          (wbd_int_rst_n                ),
 
-          .cfg_strap_pad_ctrl      (cfg_strap_pad_ctrl_rp   ),
-          .system_strap            (system_strap_rp         ),
-          .strap_sticky            (strap_sticky            ),
-	      .strap_uartm             (strap_uartm             ),
+          .cfg_strap_pad_ctrl (cfg_strap_pad_ctrl_rp        ),
+          .system_strap       (system_strap_rp              ),
+          .strap_sticky       (strap_sticky                 ),
+          .strap_uartm        (strap_uartm                  ),
 
-          .user_clock1             (wb_clk_i_rp             ),
-          .user_clock2             (user_clock2_rp          ),
-          .int_pll_clock           (int_pll_clock           ),
-          .xtal_clk                (xtal_clk                ),
-          .cpu_clk                 (cpu_clk_rp_pinmux       ),
+          .user_clock1        (wb_clk_i_rp                  ),
+          .user_clock2        (user_clock2_rp               ),
+          .int_pll_clock      (int_pll_clock                ),
+          .xtal_clk           (xtal_clk                     ),
+          .cpu_clk            (cpu_clk_rp_pinmux            ),
 
 
-          .rtc_clk                 (rtc_clk                 ),
-          .usb_clk                 (usb_clk                 ),
+          .rtc_clk            (rtc_clk                      ),
+          .usb_clk            (usb_clk                      ),
 	// Reset Control
-          .cpu_core_rst_n          (cpu_core_rst_n          ),
-          .cpu_intf_rst_n          (cpu_intf_rst_n          ),
-          .qspim_rst_n             (qspim_rst_n             ),
-          .sspim_rst_n             (sspim_rst_n             ),
-          .uart_rst_n              (uart_rst_n              ),
-          .i2cm_rst_n              (i2c_rst_n               ),
-          .usb_rst_n               (usb_rst_n               ),
+          .cpu_core_rst_n     (cpu_core_rst_n               ),
+          .cpu_intf_rst_n     (cpu_intf_rst_n               ),
+          .qspim_rst_n        (qspim_rst_n                  ),
+          .sspim_rst_n        (sspim_rst_n                  ),
+          .uart_rst_n         (uart_rst_n                   ),
+          .i2cm_rst_n         (i2c_rst_n                    ),
+          .usb_rst_n          (usb_rst_n                    ),
 
-	      .cfg_riscv_ctrl          (cfg_riscv_ctrl          ),
+          .cfg_riscv_ctrl     (cfg_riscv_ctrl               ),
 
         // Reg Bus Interface Signal
-          .reg_cs                  (wbd_glbl_stb_o          ),
-          .reg_wr                  (wbd_glbl_we_o           ),
-          .reg_addr                (wbd_glbl_adr_o          ),
-          .reg_wdata               (wbd_glbl_dat_o          ),
-          .reg_be                  (wbd_glbl_sel_o          ),
+          .reg_cs             (wbd_glbl_stb_o               ),
+          .reg_wr             (wbd_glbl_we_o                ),
+          .reg_addr           (wbd_glbl_adr_o               ),
+          .reg_wdata          (wbd_glbl_dat_o               ),
+          .reg_be             (wbd_glbl_sel_o               ),
 
        // Outputs
-          .reg_rdata               (wbd_glbl_dat_i          ),
-          .reg_ack                 (wbd_glbl_ack_i          ),
+          .reg_rdata          (wbd_glbl_dat_i               ),
+          .reg_ack            (wbd_glbl_ack_i               ),
 
 
        // Risc configuration
-          .irq_lines               (irq_lines               ),
-          .soft_irq                (soft_irq                ),
-          .user_irq                (user_irq                ),
-          .usb_intr                (usb_intr_o              ),
-          .i2cm_intr               (i2cm_intr_o             ),
+          .irq_lines          (irq_lines                    ),
+          .soft_irq           (soft_irq                     ),
+          .user_irq           (user_irq                     ),
+          .usb_intr           (usb_intr_o                   ),
+          .i2cm_intr          (i2cm_intr_o                  ),
 
        // Digital IO
-          .digital_io_out          (io_out_int              ),
-          .digital_io_oen          (io_oeb_int              ),
-          .digital_io_in           (io_in_rp                ),
+          .digital_io_out     (io_out_int                   ),
+          .digital_io_oen     (io_oeb_int                   ),
+          .digital_io_in      (io_in_rp                     ),
 
        // SFLASH I/F
-          .sflash_sck              (sflash_sck              ),
-          .sflash_ss               (spi_csn                 ),
-          .sflash_oen              (sflash_oen              ),
-          .sflash_do               (sflash_do               ),
-          .sflash_di               (sflash_di               ),
+          .sflash_sck         (sflash_sck                   ),
+          .sflash_ss          (spi_csn                      ),
+          .sflash_oen         (sflash_oen                   ),
+          .sflash_do          (sflash_do                    ),
+          .sflash_di          (sflash_di                    ),
 
 
        // USB I/F
-          .usb_dp_o                (usb_dp_o                ),
-          .usb_dn_o                (usb_dn_o                ),
-          .usb_oen                 (usb_oen                 ),
-          .usb_dp_i                (usb_dp_i                ),
-          .usb_dn_i                (usb_dn_i                ),
+          .usb_dp_o           (usb_dp_o                     ),
+          .usb_dn_o           (usb_dn_o                     ),
+          .usb_oen            (usb_oen                      ),
+          .usb_dp_i           (usb_dp_i                     ),
+          .usb_dn_i           (usb_dn_i                     ),
 
        // UART I/F
-          .uart_txd                (uart_txd                ),
-          .uart_rxd                (uart_rxd                ),
+          .uart_txd           (uart_txd                     ),
+          .uart_rxd           (uart_rxd                     ),
 
        // I2CM I/F
-          .i2cm_clk_o              (i2cm_clk_o              ),
-          .i2cm_clk_i              (i2cm_clk_i              ),
-          .i2cm_clk_oen            (i2cm_clk_oen            ),
-          .i2cm_data_oen           (i2cm_data_oen           ),
-          .i2cm_data_o             (i2cm_data_o             ),
-          .i2cm_data_i             (i2cm_data_i             ),
+          .i2cm_clk_o         (i2cm_clk_o                   ),
+          .i2cm_clk_i         (i2cm_clk_i                   ),
+          .i2cm_clk_oen       (i2cm_clk_oen                 ),
+          .i2cm_data_oen      (i2cm_data_oen                ),
+          .i2cm_data_o        (i2cm_data_o                  ),
+          .i2cm_data_i        (i2cm_data_i                  ),
 
        // SPI MASTER
-          .spim_sck                (sspim_sck               ),
-          .spim_ssn                (sspim_ssn               ),
-          .spim_miso               (sspim_so                ),
-          .spim_mosi               (sspim_si                ),
+          .spim_sck           (sspim_sck                    ),
+          .spim_ssn           (sspim_ssn                    ),
+          .spim_miso          (sspim_so                     ),
+          .spim_mosi          (sspim_si                     ),
        
        // SPI SLAVE
-          .spis_sck                (sspis_sck               ),
-          .spis_ssn                (sspis_ssn               ),
-          .spis_miso               (sspis_so                ),
-          .spis_mosi               (sspis_si                ),
+          .spis_sck           (sspis_sck                    ),
+          .spis_ssn           (sspis_ssn                    ),
+          .spis_miso          (sspis_so                     ),
+          .spis_mosi          (sspis_si                     ),
 
       // UART MASTER I/F
-          .uartm_rxd               (uartm_rxd               ),
-          .uartm_txd               (uartm_txd               ),
+          .uartm_rxd          (uartm_rxd                    ),
+          .uartm_txd          (uartm_txd                    ),
 
 
-	  .pulse1m_mclk            (pulse1m_mclk            ),
+          .pulse1m_mclk       (pulse1m_mclk                 ),
+     
+          .pinmux_debug       (pinmux_debug                 ),
+     
+     
+          .cfg_pll_enb        (cfg_pll_enb                  ), 
+          .cfg_pll_fed_div    (cfg_pll_fed_div              ), 
+          .cfg_dco_mode       (cfg_dco_mode                 ), 
+          .cfg_dc_trim        (cfg_dc_trim                  ),
+          .pll_ref_clk        (pll_ref_clk                  ),
+     
+        // Peripheral Reg Bus Interface Signal
+          .reg_peri_cs        (reg_peri_cs                  ),
+          .reg_peri_wr        (reg_peri_wr                  ),
+          .reg_peri_addr      (reg_peri_addr                ),
+          .reg_peri_wdata     (reg_peri_wdata               ),
+          .reg_peri_be        (reg_peri_be                  ),
 
-	  .pinmux_debug            (pinmux_debug            ),
+       // Outputs
+          .reg_peri_rdata     (reg_peri_rdata               ),
+          .reg_peri_ack       (reg_peri_ack                 ),
 
+          .rtc_intr           (rtc_intr                     )
 
-       .cfg_pll_enb            (cfg_pll_enb             ), 
-       .cfg_pll_fed_div        (cfg_pll_fed_div         ), 
-       .cfg_dco_mode           (cfg_dco_mode            ), 
-       .cfg_dc_trim            (cfg_dc_trim             ),
-       .pll_ref_clk            (pll_ref_clk             ),
+   ); 
 
-       .cfg_dac0_mux_sel       (cfg_dac0_mux_sel        ),
-       .cfg_dac1_mux_sel       (cfg_dac1_mux_sel        ),
-       .cfg_dac2_mux_sel       (cfg_dac2_mux_sel        ),
-       .cfg_dac3_mux_sel       (cfg_dac3_mux_sel        )
+//---------------------------------------------------------
+// Peripheral block
+//----------------------------------------------------------
+
+peri_top u_peri(
+`ifdef USE_POWER_PINS
+          .vccd1              (vccd1                        ),// User area 1 1.8V supply
+          .vssd1              (vssd1                        ),// User area 1 digital ground
+`endif
+        //clk skew adjust
+          .cfg_cska_peri      (cfg_wcska_peri_rp            ),
+          .wbd_clk_int        (wbd_clk_peri_rp              ),
+          .wbd_clk_peri       (wbd_clk_peri_skew            ),
+
+        // System Signals
+        // Inputs
+          .mclk                    (wbd_clk_peri_skew       ),
+          .s_reset_n               (wbd_int_rst_n           ),
+
+        // Peripheral Reg Bus Interface Signal
+          .reg_cs                  (reg_peri_cs             ),
+          .reg_wr                  (reg_peri_wr             ),
+          .reg_addr                (reg_peri_addr           ),
+          .reg_wdata               (reg_peri_wdata          ),
+          .reg_be                  (reg_peri_be             ),
+
+       // Outputs
+          .reg_rdata               (reg_peri_rdata          ),
+          .reg_ack                 (reg_peri_ack            ),
+
+          // RTC clock domain
+          .rtc_clk                 (rtc_clk                 ),
+          .rtc_intr                (rtc_intr                ),
+
+          .inc_time_s              (                        ),
+          .inc_date_d              (                        ),
+
+          .cfg_dac0_mux_sel        (cfg_dac0_mux_sel        ),
+          .cfg_dac1_mux_sel        (cfg_dac1_mux_sel        ),
+          .cfg_dac2_mux_sel        (cfg_dac2_mux_sel        ),
+          .cfg_dac3_mux_sel        (cfg_dac3_mux_sel        )
 
    ); 
 
 
 
+//------------------------------------------
+// 4 x 8 bit DAC
+//------------------------------------------
+
 
 dac_top  u_4x8bit_dac(
 `ifdef USE_POWER_PINS
-    .vccd1                 (vdda1                  ),
-    .vssd1                 (vssa1                  ),
+          .vccd1              (vdda1                        ),
+          .vssd1              (vssa1                        ),
 `endif
-    .Vref (analog_io[23]),
-    .DIn0 (cfg_dac0_mux_sel),
-    .DIn1 (cfg_dac1_mux_sel),
-    .DIn2 (cfg_dac2_mux_sel),
-    .DIn3 (cfg_dac3_mux_sel),
-    .Vout0(analog_io[15]   ),
-    .Vout1(analog_io[16]   ),
-    .Vout2(analog_io[17]   ),
-    .Vout3(analog_io[18]   )
+          .Vref               (analog_io[23]                ),
+          .DIn0               (cfg_dac0_mux_sel             ),
+          .DIn1               (cfg_dac1_mux_sel             ),
+          .DIn2               (cfg_dac2_mux_sel             ),
+          .DIn3               (cfg_dac3_mux_sel             ),
+          .Vout0              (analog_io[15]                ),
+          .Vout1              (analog_io[16]                ),
+          .Vout2              (analog_io[17]                ),
+          .Vout3              (analog_io[18]                )
    );
 
 
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v
index 3c904f9..f2b704a 100644
--- a/verilog/rtl/user_reg_map.v
+++ b/verilog/rtl/user_reg_map.v
@@ -15,7 +15,8 @@
 `define ADDR_SPACE_TIMER   32'h3002_0180
 `define ADDR_SPACE_SEMA    32'h3002_0200
 `define ADDR_SPACE_WS281X  32'h3002_0280
-`define ADDR_SPACE_ANALOG  32'h3002_0300
+`define ADDR_SPACE_ANALOG  32'h3002_0400
+`define ADDR_SPACE_RTC     32'h3002_0480
 `define ADDR_SPACE_WBHOST  32'h3008_0000
 
 //--------------------------------------------------
@@ -166,3 +167,13 @@
 `define UART_RDATA        8'h18  // Reg-6
 `define UART_TFIFO_STAT   8'h1C  // Reg-7
 `define UART_RFIFO_STAT   8'h20  // Reg-8
+
+//--------------------------------------------------------
+// RTC Register Map
+//--------------------------------------------------------
+`define  RTC_CMD          8'h0
+`define  RTC_TIME         8'h4
+`define  RTC_DATE         8'h8
+`define  RTC_ALRM1        8'hC
+`define  RTC_ALRM2        8'h10
+`define  RTC_CTRL         8'h14
diff --git a/verilog/rtl/wb_host/src/wbh_reg.sv b/verilog/rtl/wb_host/src/wbh_reg.sv
index ab3ad2b..4c6a5ca 100644
--- a/verilog/rtl/wb_host/src/wbh_reg.sv
+++ b/verilog/rtl/wb_host/src/wbh_reg.sv
@@ -228,7 +228,7 @@
                               (strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b01) ?  CLK_SKEW1_RESET_VAL[27:24] + 2 :
                               (strap_sticky[`STRAP_SCLK_SKEW_QSPI_CO] == 2'b10) ?  CLK_SKEW1_RESET_VAL[27:24] + 4 : CLK_SKEW1_RESET_VAL[27:24]-4;
 
-assign rst_clk_ctrl1[31:28] = 4'b0;
+assign rst_clk_ctrl1[31:28] = CLK_SKEW1_RESET_VAL[31:28];
 
 
 always @ (posedge mclk ) begin 
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
index e595919..ea798b9 100644
--- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -203,7 +203,7 @@
          input	logic 	        s2_wbd_ack_i,
          // input	logic 	s2_wbd_err_i, - unused
          output	logic [31:0]	s2_wbd_dat_o,
-         output	logic [9:0]	    s2_wbd_adr_o, // glbl reg need only 9 bits
+         output	logic [10:0]	s2_wbd_adr_o, // glbl reg need only 9 bits
          output	logic [3:0]	    s2_wbd_sel_o,
          output	logic 	        s2_wbd_we_o,
          output	logic 	        s2_wbd_cyc_o,
@@ -677,7 +677,7 @@
  assign  s1_wbd_stb_o =  s1_wb_wr.wbd_stb ;
                       
  assign  s2_wbd_dat_o =  s2_wb_wr.wbd_dat ;
- assign  s2_wbd_adr_o =  s2_wb_wr.wbd_adr[9:0] ; // Global Reg Need 8 bit
+ assign  s2_wbd_adr_o =  s2_wb_wr.wbd_adr[10:0] ; // Global Reg Need 8 bit
  assign  s2_wbd_sel_o =  s2_wb_wr.wbd_sel ;
  assign  s2_wbd_we_o  =  s2_wb_wr.wbd_we  ;
  assign  s2_wbd_cyc_o =  s2_wb_wr.wbd_cyc ;