| ############################################################################### |
| # Created by write_sdc |
| # Sun Aug 14 14:58:56 2022 |
| ############################################################################### |
| current_design pinmux |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name mclk -period 10.0000 [get_ports {mclk}] |
| set_clock_transition 0.1500 [get_clocks {mclk}] |
| set_clock_uncertainty -setup 0.5000 mclk |
| set_clock_uncertainty -hold 0.2500 mclk |
| set_propagated_clock [get_clocks {mclk}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {h_reset_n}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_addr[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_addr[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_be[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_be[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_cs}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_cs}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wdata[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wdata[9]}] |
| set_input_delay 2.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_wr}] |
| set_input_delay 4.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_wr}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {qspim_rst_n}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {qspim_rst_n}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_ack}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_ack}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[0]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[0]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[10]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[10]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[11]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[11]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[12]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[12]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[13]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[13]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[14]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[14]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[15]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[15]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[16]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[16]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[17]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[17]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[18]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[18]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[19]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[19]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[1]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[1]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[20]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[20]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[21]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[21]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[22]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[22]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[23]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[23]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[24]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[24]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[25]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[25]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[26]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[26]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[27]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[27]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[28]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[28]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[29]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[29]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[2]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[2]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[30]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[30]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[31]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[31]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[3]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[3]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[4]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[4]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[5]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[5]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[6]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[6]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[7]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[7]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[8]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[8]}] |
| set_output_delay -3.0000 -clock [get_clocks {mclk}] -min -add_delay [get_ports {reg_rdata[9]}] |
| set_output_delay 1.0000 -clock [get_clocks {mclk}] -max -add_delay [get_ports {reg_rdata[9]}] |
| set_max_delay\ |
| -from [get_ports {wbd_clk_int}] 3.5000 |
| set_max_delay\ |
| -from [get_ports {wbd_clk_int}]\ |
| -to [get_ports {wbd_clk_pinmux}] 3.5000 |
| set_max_delay\ |
| -to [get_ports {wbd_clk_pinmux}] 2.0000 |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {cpu_intf_rst_n}] |
| set_load -pin_load 0.0334 [get_ports {i2cm_clk_i}] |
| set_load -pin_load 0.0334 [get_ports {i2cm_data_i}] |
| set_load -pin_load 0.0334 [get_ports {i2cm_rst_n}] |
| set_load -pin_load 0.0334 [get_ports {pulse1m_mclk}] |
| set_load -pin_load 0.0334 [get_ports {qspim_rst_n}] |
| set_load -pin_load 0.0334 [get_ports {reg_ack}] |
| set_load -pin_load 0.0334 [get_ports {soft_irq}] |
| set_load -pin_load 0.0334 [get_ports {spim_mosi}] |
| set_load -pin_load 0.0334 [get_ports {spis_mosi}] |
| set_load -pin_load 0.0334 [get_ports {spis_sck}] |
| set_load -pin_load 0.0334 [get_ports {spis_ssn}] |
| set_load -pin_load 0.0334 [get_ports {sspim_rst_n}] |
| set_load -pin_load 0.0334 [get_ports {uartm_rxd}] |
| set_load -pin_load 0.0334 [get_ports {usb_dn_i}] |
| set_load -pin_load 0.0334 [get_ports {usb_dp_i}] |
| set_load -pin_load 0.0334 [get_ports {usb_rst_n}] |
| set_load -pin_load 0.0334 [get_ports {wbd_clk_pinmux}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[15]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[14]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[13]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[12]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[11]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[10]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[9]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[8]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[7]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[6]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[5]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[4]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[3]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[2]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[1]}] |
| set_load -pin_load 0.0334 [get_ports {cfg_riscv_ctrl[0]}] |
| set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[1]}] |
| set_load -pin_load 0.0334 [get_ports {cpu_core_rst_n[0]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[37]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[36]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[35]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[34]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[33]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[32]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[31]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[30]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[29]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[28]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[27]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[26]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[25]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[24]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[23]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[22]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[21]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[20]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[19]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[18]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[17]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[16]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[15]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[14]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[13]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[12]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[11]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[10]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[9]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[8]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[7]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[6]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[5]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[4]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[3]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[2]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[1]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_oen[0]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[37]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[36]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[35]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[34]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[33]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[32]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[31]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[30]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[29]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[28]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[27]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[26]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[25]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[24]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[23]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[22]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[21]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[20]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[19]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[18]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[17]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[16]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[15]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[14]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[13]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[12]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[11]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[10]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[9]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[8]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[7]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[6]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[5]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[4]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[3]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[2]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[1]}] |
| set_load -pin_load 0.0334 [get_ports {digital_io_out[0]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[15]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[14]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[13]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[12]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[11]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[10]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[9]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[8]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[7]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[6]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[5]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[4]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[3]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[2]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[1]}] |
| set_load -pin_load 0.0334 [get_ports {irq_lines[0]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[31]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[30]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[29]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[28]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[27]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[26]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[25]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[24]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[23]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[22]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[21]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[20]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[19]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[18]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[17]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[16]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[15]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[14]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[13]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[12]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[11]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[10]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[9]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[8]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[7]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[6]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[5]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[4]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[3]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[2]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[1]}] |
| set_load -pin_load 0.0334 [get_ports {pinmux_debug[0]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}] |
| set_load -pin_load 0.0334 [get_ports {sflash_di[3]}] |
| set_load -pin_load 0.0334 [get_ports {sflash_di[2]}] |
| set_load -pin_load 0.0334 [get_ports {sflash_di[1]}] |
| set_load -pin_load 0.0334 [get_ports {sflash_di[0]}] |
| set_load -pin_load 0.0334 [get_ports {uart_rst_n[1]}] |
| set_load -pin_load 0.0334 [get_ports {uart_rst_n[0]}] |
| set_load -pin_load 0.0334 [get_ports {uart_rxd[1]}] |
| set_load -pin_load 0.0334 [get_ports {uart_rxd[0]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq[2]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq[1]}] |
| set_load -pin_load 0.0334 [get_ports {user_irq[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dbg_clk_mon}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {h_reset_n}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_clk_o}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_clk_oen}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_o}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_data_oen}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2cm_intr}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_sck}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_miso}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_sck}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spis_miso}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uartm_txd}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_dn_o}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_dp_o}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_intr}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_oen}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_pinmux[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[37]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[36]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[35]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[34]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[33]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[32]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {digital_io_in[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_do[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_oen[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sflash_ss[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {spim_ssn[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_txd[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_txd[0]}] |
| set_case_analysis 0 [get_ports {cfg_cska_pinmux[0]}] |
| set_case_analysis 0 [get_ports {cfg_cska_pinmux[1]}] |
| set_case_analysis 0 [get_ports {cfg_cska_pinmux[2]}] |
| set_case_analysis 0 [get_ports {cfg_cska_pinmux[3]}] |
| set_timing_derate -early 0.9500 |
| set_timing_derate -late 1.0500 |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |