| ############################################################################### |
| # Created by write_sdc |
| # Sat Dec 10 05:54:02 2022 |
| ############################################################################### |
| current_design ycr_intf |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name core_clk -period 10.0000 [get_ports {core_clk}] |
| set_clock_transition 0.1500 [get_clocks {core_clk}] |
| set_clock_uncertainty -setup 0.5000 core_clk |
| set_clock_uncertainty -hold 0.2500 core_clk |
| set_propagated_clock [get_clocks {core_clk}] |
| create_clock -name rtc_clk -period 40.0000 |
| set_clock_uncertainty -setup 0.5000 rtc_clk |
| set_clock_uncertainty -hold 0.2500 rtc_clk |
| create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}] |
| set_clock_transition 0.1500 [get_clocks {wb_clk}] |
| set_clock_uncertainty -setup 0.5000 wb_clk |
| set_clock_uncertainty -hold 0.2500 wb_clk |
| set_propagated_clock [get_clocks {wb_clk}] |
| create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {dcache mem clock0} [get_ports {dcache_mem_clk0}] |
| set_clock_transition 0.1500 [get_clocks {dcache_mem_clk0}] |
| set_clock_uncertainty -setup 0.5000 dcache_mem_clk0 |
| set_clock_uncertainty -hold 0.2500 dcache_mem_clk0 |
| set_propagated_clock [get_clocks {dcache_mem_clk0}] |
| create_generated_clock -name dcache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {dcache mem clock1} [get_ports {dcache_mem_clk1}] |
| set_clock_transition 0.1500 [get_clocks {dcache_mem_clk1}] |
| set_clock_uncertainty -setup 0.5000 dcache_mem_clk1 |
| set_clock_uncertainty -hold 0.2500 dcache_mem_clk1 |
| set_propagated_clock [get_clocks {dcache_mem_clk1}] |
| create_generated_clock -name icache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {icache mem clock0} [get_ports {icache_mem_clk0}] |
| set_clock_transition 0.1500 [get_clocks {icache_mem_clk0}] |
| set_clock_uncertainty -setup 0.5000 icache_mem_clk0 |
| set_clock_uncertainty -hold 0.2500 icache_mem_clk0 |
| set_propagated_clock [get_clocks {icache_mem_clk0}] |
| create_generated_clock -name icache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks {core_clk}] -divide_by 1 -comment {icache mem clock1} [get_ports {icache_mem_clk1}] |
| set_clock_transition 0.1500 [get_clocks {icache_mem_clk1}] |
| set_clock_uncertainty -setup 0.5000 icache_mem_clk1 |
| set_clock_uncertainty -hold 0.2500 icache_mem_clk1 |
| set_propagated_clock [get_clocks {icache_mem_clk1}] |
| set_clock_groups -name async_clock -asynchronous \ |
| -group [get_clocks {rtc_clk}]\ |
| -group [get_clocks {wb_clk}]\ |
| -group [list [get_clocks {core_clk}]\ |
| [get_clocks {dcache_mem_clk0}]\ |
| [get_clocks {dcache_mem_clk1}]\ |
| [get_clocks {icache_mem_clk0}]\ |
| [get_clocks {icache_mem_clk1}]] -comment {Async Clock group} |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[0]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[10]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[11]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[12]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[13]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[14]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[15]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[16]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[17]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[18]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[19]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[1]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[20]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[21]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[22]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[23]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[24]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[25]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[26]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[27]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[28]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[29]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[2]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[30]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[31]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[3]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[4]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[5]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[6]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[7]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[8]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_addr[9]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_addr[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_cmd}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_cmd}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_req}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_req}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[0]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[10]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[11]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[12]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[13]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[14]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[15]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[16]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[17]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[18]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[19]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[1]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[20]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[21]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[22]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[23]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[24]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[25]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[26]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[27]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[28]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[29]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[2]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[30]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[31]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[3]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[4]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[5]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[6]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[7]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[8]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_wdata[9]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_wdata[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_width[0]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_width[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_width[1]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_width[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[10]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[11]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[12]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[13]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[14]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[15]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[16]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[17]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[18]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[19]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[20]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[21]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[22]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[23]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[24]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[25]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[26]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[27]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[28]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[29]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[30]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[31]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[4]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[5]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[6]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[7]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[8]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_addr[9]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_addr[9]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_cmd}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_cmd}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_req}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_req}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[10]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[11]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[12]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[13]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[14]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[15]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[16]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[17]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[18]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[19]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[20]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[21]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[22]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[23]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[24]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[25]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[26]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[27]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[28]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[29]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[30]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[31]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[4]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[5]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[6]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[7]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[8]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_wdata[9]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_wdata[9]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_width[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_width[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_width[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_width[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[0]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[10]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[11]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[12]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[13]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[14]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[15]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[16]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[17]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[18]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[19]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[1]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[20]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[21]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[22]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[23]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[24]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[25]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[26]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[27]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[28]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[29]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[2]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[30]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[31]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[3]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[4]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[5]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[6]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[7]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[8]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_addr[9]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_addr[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_bl[0]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_bl[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_bl[1]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_bl[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_bl[2]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_bl[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_cmd}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_cmd}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_req}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_req}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_width[0]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_width[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_width[1]}] |
| set_input_delay 8.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_width[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[10]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[11]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[12]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[13]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[14]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[15]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[16]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[17]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[18]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[19]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[20]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[21]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[22]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[23]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[24]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[25]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[26]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[27]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[28]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[29]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[30]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[31]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[4]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[5]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[6]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[7]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[8]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_dout0[9]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_dout0[9]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[10]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[11]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[12]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[13]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[14]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[15]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[16]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[17]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[18]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[19]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[20]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[21]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[22]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[23]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[24]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[25]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[26]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[27]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[28]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[29]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[30]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[31]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[4]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[5]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[6]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[7]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[8]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_dout1[9]}] |
| set_input_delay 6.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_dout1[9]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[10]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[11]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[12]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[13]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[14]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[15]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[16]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[17]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[18]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[19]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[20]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[21]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[22]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[23]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[24]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[25]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[26]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[27]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[28]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[29]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[30]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[31]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[4]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[5]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[6]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[7]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[8]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_dout1[9]}] |
| set_input_delay 6.0000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_dout1[9]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_ack_i}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_ack_i}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[10]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[11]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[12]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[13]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[14]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[15]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[16]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[17]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[18]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[19]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[20]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[21]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[22]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[23]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[24]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[25]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[26]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[27]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[28]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[29]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[30]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[31]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[4]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[5]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[6]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[7]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[8]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_dat_i[9]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_dat_i[9]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_err_i}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_err_i}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_lack_i}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_lack_i}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_ack_i}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_ack_i}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[10]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[11]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[12]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[13]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[14]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[15]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[16]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[17]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[18]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[19]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[20]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[21]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[22]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[23]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[24]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[25]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[26]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[27]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[28]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[29]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[30]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[31]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[4]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[5]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[6]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[7]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[8]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_dat_i[9]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_dat_i[9]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_err_i}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_err_i}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_icache_lack_i}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_icache_lack_i}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_ack_i}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_ack_i}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[0]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[0]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[10]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[10]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[11]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[11]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[12]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[12]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[13]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[13]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[14]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[14]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[15]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[15]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[16]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[16]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[17]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[17]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[18]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[18]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[19]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[19]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[1]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[1]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[20]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[20]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[21]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[21]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[22]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[22]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[23]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[23]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[24]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[24]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[25]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[25]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[26]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[26]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[27]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[27]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[28]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[28]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[29]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[29]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[2]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[2]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[30]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[30]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[31]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[31]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[3]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[3]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[4]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[4]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[5]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[5]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[6]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[6]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[7]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[7]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[8]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[8]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_dat_i[9]}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_dat_i[9]}] |
| set_input_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wbd_dmem_err_i}] |
| set_input_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wbd_dmem_err_i}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[0]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[0]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[10]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[10]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[11]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[11]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[12]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[12]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[13]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[13]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[14]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[14]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[15]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[15]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[16]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[16]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[17]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[17]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[18]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[18]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[19]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[19]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[1]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[1]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[20]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[20]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[21]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[21]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[22]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[22]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[23]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[23]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[24]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[24]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[25]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[25]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[26]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[26]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[27]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[27]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[28]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[28]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[29]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[29]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[2]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[2]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[30]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[30]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[31]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[31]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[3]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[3]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[4]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[4]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[5]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[5]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[6]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[6]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[7]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[7]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[8]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[8]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_rdata[9]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_rdata[9]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_req_ack}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_req_ack}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_resp[0]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_resp[0]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dcache_resp[1]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dcache_resp[1]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[0]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[0]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[10]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[10]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[11]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[11]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[12]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[12]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[13]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[13]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[14]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[14]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[15]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[15]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[16]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[16]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[17]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[17]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[18]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[18]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[19]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[19]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[1]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[1]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[20]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[20]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[21]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[21]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[22]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[22]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[23]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[23]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[24]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[24]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[25]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[25]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[26]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[26]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[27]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[27]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[28]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[28]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[29]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[29]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[2]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[2]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[30]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[30]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[31]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[31]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[3]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[3]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[4]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[4]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[5]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[5]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[6]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[6]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[7]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[7]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[8]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[8]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_rdata[9]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_rdata[9]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_req_ack}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_req_ack}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_resp[0]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_resp[0]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_dmem_resp[1]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_dmem_resp[1]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[0]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[0]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[10]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[10]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[11]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[11]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[12]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[12]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[13]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[13]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[14]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[14]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[15]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[15]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[16]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[16]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[17]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[17]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[18]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[18]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[19]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[19]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[1]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[1]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[20]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[20]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[21]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[21]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[22]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[22]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[23]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[23]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[24]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[24]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[25]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[25]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[26]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[26]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[27]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[27]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[28]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[28]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[29]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[29]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[2]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[2]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[30]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[30]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[31]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[31]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[3]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[3]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[4]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[4]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[5]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[5]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[6]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[6]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[7]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[7]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[8]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[8]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_rdata[9]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_rdata[9]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_req_ack}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_req_ack}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_resp[0]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_resp[0]}] |
| set_output_delay 2.0000 -clock [get_clocks {core_clk}] -min -add_delay [get_ports {core_icache_resp[1]}] |
| set_output_delay 6.0000 -clock [get_clocks {core_clk}] -max -add_delay [get_ports {core_icache_resp[1]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[0]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[0]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[1]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[1]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[2]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[2]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[3]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[3]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[4]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[4]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[5]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[5]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[6]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[6]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[7]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[7]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_addr0[8]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_addr0[8]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[0]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[0]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[1]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[1]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[2]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[2]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[3]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[3]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[4]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[4]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[5]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[5]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[6]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[6]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[7]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[7]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_addr1[8]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_addr1[8]}] |
| set_output_delay -1.2500 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_csb0}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_csb0}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk1}] -min -add_delay [get_ports {dcache_mem_csb1}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk1}] -max -add_delay [get_ports {dcache_mem_csb1}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[0]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[0]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[10]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[10]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[11]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[11]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[12]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[12]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[13]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[13]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[14]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[14]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[15]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[15]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[16]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[16]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[17]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[17]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[18]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[18]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[19]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[19]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[1]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[1]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[20]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[20]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[21]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[21]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[22]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[22]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[23]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[23]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[24]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[24]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[25]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[25]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[26]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[26]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[27]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[27]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[28]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[28]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[29]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[29]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[2]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[2]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[30]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[30]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[31]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[31]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[3]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[3]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[4]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[4]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[5]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[5]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[6]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[6]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[7]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[7]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[8]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[8]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_din0[9]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_din0[9]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_web0}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_web0}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_wmask0[0]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_wmask0[0]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_wmask0[1]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_wmask0[1]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_wmask0[2]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_wmask0[2]}] |
| set_output_delay -1.0000 -clock [get_clocks {dcache_mem_clk0}] -min -add_delay [get_ports {dcache_mem_wmask0[3]}] |
| set_output_delay 1.0000 -clock [get_clocks {dcache_mem_clk0}] -max -add_delay [get_ports {dcache_mem_wmask0[3]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[0]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[0]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[1]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[1]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[2]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[2]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[3]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[3]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[4]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[4]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[5]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[5]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[6]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[6]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[7]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[7]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_addr0[8]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_addr0[8]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[0]}] |
| set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[0]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[1]}] |
| set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[1]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[2]}] |
| set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[2]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[3]}] |
| set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[3]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[4]}] |
| set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[4]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[5]}] |
| set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[5]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[6]}] |
| set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[6]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[7]}] |
| set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[7]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_addr1[8]}] |
| set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_addr1[8]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_csb0}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_csb0}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk1}] -min -add_delay [get_ports {icache_mem_csb1}] |
| set_output_delay 3.5000 -clock [get_clocks {icache_mem_clk1}] -max -add_delay [get_ports {icache_mem_csb1}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[0]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[0]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[10]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[10]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[11]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[11]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[12]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[12]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[13]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[13]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[14]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[14]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[15]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[15]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[16]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[16]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[17]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[17]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[18]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[18]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[19]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[19]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[1]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[1]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[20]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[20]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[21]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[21]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[22]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[22]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[23]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[23]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[24]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[24]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[25]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[25]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[26]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[26]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[27]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[27]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[28]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[28]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[29]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[29]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[2]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[2]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[30]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[30]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[31]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[31]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[3]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[3]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[4]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[4]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[5]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[5]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[6]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[6]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[7]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[7]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[8]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[8]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_din0[9]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_din0[9]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_web0}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_web0}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_wmask0[0]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_wmask0[0]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_wmask0[1]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_wmask0[1]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_wmask0[2]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_wmask0[2]}] |
| set_output_delay -1.0000 -clock [get_clocks {icache_mem_clk0}] -min -add_delay [get_ports {icache_mem_wmask0[3]}] |
| set_output_delay 1.0000 -clock [get_clocks {icache_mem_clk0}] -max -add_delay [get_ports {icache_mem_wmask0[3]}] |
| set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[0]}] |
| set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[0]}] |
| set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[10]}] |
| set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[10]}] |
| set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[11]}] |
| set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[11]}] |
| set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[12]}] |
| set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[12]}] |
| set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[13]}] |
| set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[13]}] |
| set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[14]}] |
| set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[14]}] |
| set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[15]}] |
| set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[15]}] |
| set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[16]}] |
| set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[16]}] |
| set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[17]}] |
| set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[17]}] |
| set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[18]}] |
| set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[18]}] |
| set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[19]}] |
| set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[19]}] |
| set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[1]}] |
| set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_adr_o[1]}] |
| set_output_delay 2.0000 -clock [get_clocks {wb_clk}] -min -add_delay [get_ports {wb_dcache_adr_o[20]}] |
| set_output_delay 6.0000 -clock [get_clocks {wb_clk}] -max -add_delay [get_ports {wb_dcache_a
|