commit: faacfa367a934d4f7b861411725b20a330b34ad8
[log] [tgz]
author: hikaysici <hikaysici@gmail.com>
Mon May 16 10:22:38 2022 +0300
committer: hikaysici <hikaysici@gmail.com>
Mon May 16 10:22:38 2022 +0300
tree: 8ea55a83e7a803d925ea7930840ad6ede49aad2f
parent: fcd5e820dae9890c381bff522d76a40d1879ab8f [diff]

initial commit

LICENSE[Added - diff]
Makefile[Added - diff]
checks/erase_box_user_project_wrapper.gds.log[Added - diff]
checks/erase_box_user_project_wrapper_empty.gds.log[Added - diff]
checks/full_log.log[Added - diff]
checks/magic_drc.log[Added - diff]
checks/manifest_check.log[Added - diff]
checks/spdx_compliance_report.log[Added - diff]
checks/user_project_wrapper.magic.drc[Added - diff]
checks/user_project_wrapper.xor.gds.png[Added - diff]
checks/user_project_wrapper.xor.xml[Added - diff]
checks/xor.log[Added - diff]
checks/xor_total.txt[Added - diff]
def/user_project_wrapper.def.gz[Added - diff]
docs/source/_static/6-Channel-SAR-ADC.png[Added - diff]
docs/source/_static/RiscDunio-PinMapping.png[Added - diff]
docs/source/_static/Riscduino-derivatives.png[Added - diff]
docs/source/_static/Riscduino_Soc.png[Added - diff]
docs/source/_static/riscvcore_blockdiagram.png[Added - diff]
docs/source/_static/user_project_wrapper.gds.png[Added - diff]
gds/.magicrc[Added - diff]
gds/DFFRAM.gds.gz[Added - diff]
gds/pinmux.gds.gz[Added - diff]
gds/qspim_top.gds.gz[Added - diff]
gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds.gz[Added - diff]
gds/uart_i2c_usb_spi_top.gds.gz[Added - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
gds/wb_host.gds.gz[Added - diff]
gds/wb_interconnect.gds.gz[Added - diff]
gds/yifive.gds.gz[Added - diff]
hacks/patch/pdngen.patch[Added - diff]
hacks/patch/resizer.patch[Added - diff]
hacks/patch/scan_swap.patch[Added - diff]
hacks/src/OpenROAD/PdnGen.tcl[Added - diff]
hacks/src/OpenROAD/Resizer.cc[Added - diff]
hacks/src/OpenSTA/network/ConcreteNetwork.cc[Added - diff]
hacks/src/OpenSTA/tcl/NetworkEdit.tcl[Added - diff]
hacks/src/OpenSTA/tcl/Sta.tcl[Added - diff]
hacks/src/openlane/io_place.py[Added - diff]
hacks/src/openlane/synth.tcl[Added - diff]
hacks/src/openlane/synth_top.tcl[Added - diff]
lef/DFFRAM.lef.gz[Added - diff]
lef/pinmux.lef.gz[Added - diff]
lef/qspim_top.lef.gz[Added - diff]
lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef.gz[Added - diff]
lef/uart_i2c_usb_spi_top.lef.gz[Added - diff]
lef/user_project_wrapper.lef.gz[Added - diff]
lef/wb_host.lef.gz[Added - diff]
lef/wb_interconnect.lef.gz[Added - diff]
lef/yifive.lef.gz[Added - diff]
lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib[Added - diff]
openlane/Makefile[Added - diff]
openlane/Read.me[Added - diff]
openlane/clk_skew_adjust/config.tcl[Added - diff]
openlane/clk_skew_adjust/pin_order.cfg[Added - diff]
openlane/mbist/base.sdc[Added - diff]
openlane/mbist/config.tcl[Added - diff]
openlane/mbist/interactive.tcl[Added - diff]
openlane/mbist/pin_order.cfg[Added - diff]
openlane/mbist/sta.tcl[Added - diff]
openlane/mbist1/base.sdc[Added - diff]
openlane/mbist1/config.tcl[Added - diff]
openlane/mbist1/interactive.tcl[Added - diff]
openlane/mbist1/pin_order.cfg[Added - diff]
openlane/mbist1/sta.tcl[Added - diff]
openlane/pinmux/base.sdc[Added - diff]
openlane/pinmux/config.tcl[Added - diff]
openlane/pinmux/pin_order.cfg[Added - diff]
openlane/qspim_top/base.sdc[Added - diff]
openlane/qspim_top/config.tcl[Added - diff]
openlane/qspim_top/pdn.tcl[Added - diff]
openlane/qspim_top/pin_order.cfg[Added - diff]
openlane/qspim_top/sta.tcl[Added - diff]
openlane/sar_adc/config.tcl[Added - diff]
openlane/sar_adc/interactive.tcl[Added - diff]
openlane/sar_adc/pdn.tcl[Added - diff]
openlane/sar_adc/pin_order.cfg[Added - diff]
openlane/uart_i2cm_usb_spi_top/base.sdc[Added - diff]
openlane/uart_i2cm_usb_spi_top/config.tcl[Added - diff]
openlane/uart_i2cm_usb_spi_top/pdn.tcl[Added - diff]
openlane/uart_i2cm_usb_spi_top/pin_order.cfg[Added - diff]
openlane/uart_i2cm_usb_spi_top/sta.tcl[Added - diff]
openlane/user_project_wrapper/base.sdc[Added - diff]
openlane/user_project_wrapper/config.tcl[Added - diff]
openlane/user_project_wrapper/gen_pdn.tcl[Added - diff]
openlane/user_project_wrapper/interactive.mpw4.tcl[Added - diff]
openlane/user_project_wrapper/interactive.tcl[Added - diff]
openlane/user_project_wrapper/macro.cfg[Added - diff]
openlane/user_project_wrapper/mod.tcl[Added - diff]
openlane/user_project_wrapper/pdn_cfg.tcl[Added - diff]
openlane/user_project_wrapper/pin_order.cfg[Added - diff]
openlane/user_project_wrapper/sta.tcl[Added - diff]
openlane/wb_host/base.sdc[Added - diff]
openlane/wb_host/config.tcl[Added - diff]
openlane/wb_host/pin_order.cfg[Added - diff]
openlane/wb_interconnect/base.sdc[Added - diff]
openlane/wb_interconnect/config.tcl[Added - diff]
openlane/wb_interconnect/pdn.tcl[Added - diff]
openlane/wb_interconnect/pin_order.cfg[Added - diff]
openlane/wb_interconnect/sta.tcl[Added - diff]
openlane/yifive/base.sdc[Added - diff]
openlane/yifive/config.tcl[Added - diff]
openlane/yifive/pdn.tcl[Added - diff]
openlane/yifive/pin_order.cfg[Added - diff]
openlane/yifive/sta.tcl[Added - diff]
run_regress[Added - diff]
signoff/clk_buf/OPENLANE_VERSION[Added - diff]
signoff/clk_buf/PDK_SOURCES[Added - diff]
signoff/clk_buf/final_summary_report.csv[Added - diff]
signoff/clk_skew_adjust/OPENLANE_VERSION[Added - diff]
signoff/clk_skew_adjust/PDK_SOURCES[Added - diff]
signoff/clk_skew_adjust/final_summary_report.csv[Added - diff]
signoff/glbl_cfg/OPENLANE_VERSION[Added - diff]
signoff/glbl_cfg/PDK_SOURCES[Added - diff]
signoff/glbl_cfg/final_summary_report.csv[Added - diff]
signoff/mbist/OPENLANE_VERSION[Added - diff]
signoff/mbist/PDK_SOURCES[Added - diff]
signoff/mbist/final_summary_report.csv[Added - diff]
signoff/mbist_wrapper/OPENLANE_VERSION[Added - diff]
signoff/mbist_wrapper/PDK_SOURCES[Added - diff]
signoff/mbist_wrapper/final_summary_report.csv[Added - diff]
signoff/pinmux/OPENLANE_VERSION[Added - diff]
signoff/pinmux/PDK_SOURCES[Added - diff]
signoff/pinmux/final_summary_report.csv[Added - diff]
signoff/qspim/OPENLANE_VERSION[Added - diff]
signoff/qspim/PDK_SOURCES[Added - diff]
signoff/qspim/final_summary_report.csv[Added - diff]
signoff/qspim_top/OPENLANE_VERSION[Added - diff]
signoff/qspim_top/PDK_SOURCES[Added - diff]
signoff/qspim_top/final_summary_report.csv[Added - diff]
signoff/sar_adc/OPENLANE_VERSION[Added - diff]
signoff/sar_adc/PDK_SOURCES[Added - diff]
signoff/sar_adc/final_summary_report.csv[Added - diff]
signoff/sdram/OPENLANE_VERSION[Added - diff]
signoff/sdram/PDK_SOURCES[Added - diff]
signoff/sdram/final_summary_report.csv[Added - diff]
signoff/spi_master/OPENLANE_VERSION[Added - diff]
signoff/spi_master/PDK_SOURCES[Added - diff]
signoff/spi_master/final_summary_report.csv[Added - diff]
signoff/syntacore/OPENLANE_VERSION[Added - diff]
signoff/syntacore/PDK_SOURCES[Added - diff]
signoff/syntacore/final_summary_report.csv[Added - diff]
signoff/uart/OPENLANE_VERSION[Added - diff]
signoff/uart/PDK_SOURCES[Added - diff]
signoff/uart/final_summary_report.csv[Added - diff]
signoff/uart_i2cm/OPENLANE_VERSION[Added - diff]
signoff/uart_i2cm/PDK_SOURCES[Added - diff]
signoff/uart_i2cm/final_summary_report.csv[Added - diff]
signoff/uart_i2cm_usb/OPENLANE_VERSION[Added - diff]
signoff/uart_i2cm_usb/PDK_SOURCES[Added - diff]
signoff/uart_i2cm_usb/final_summary_report.csv[Added - diff]
signoff/uart_i2cm_usb_spi/OPENLANE_VERSION[Added - diff]
signoff/uart_i2cm_usb_spi/PDK_SOURCES[Added - diff]
signoff/uart_i2cm_usb_spi/final_summary_report.csv[Added - diff]
signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION[Added - diff]
signoff/uart_i2cm_usb_spi_top/PDK_SOURCES[Added - diff]
signoff/uart_i2cm_usb_spi_top/final_summary_report.csv[Added - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[Added - diff]
signoff/user_project_wrapper/PDK_SOURCES[Added - diff]
signoff/user_project_wrapper/final_summary_report.csv[Added - diff]
signoff/wb_host/OPENLANE_VERSION[Added - diff]
signoff/wb_host/PDK_SOURCES[Added - diff]
signoff/wb_host/final_summary_report.csv[Added - diff]
signoff/wb_interconnect/OPENLANE_VERSION[Added - diff]
signoff/wb_interconnect/PDK_SOURCES[Added - diff]
signoff/wb_interconnect/final_summary_report.csv[Added - diff]
signoff/yifive/OPENLANE_VERSION[Added - diff]
signoff/yifive/PDK_SOURCES[Added - diff]
signoff/yifive/final_summary_report.csv[Added - diff]
spef/DFFRAM.spef.gz[Added - diff]
spef/pinmux.spef.gz[Added - diff]
spef/qspim_top.spef.gz[Added - diff]
spef/uart_i2c_usb_spi_top.spef.gz[Added - diff]
spef/user_project_wrapper.spef.gz[Added - diff]
spef/wb_host.spef.gz[Added - diff]
spef/wb_interconnect.spef.gz[Added - diff]
spef/ycr1_top_wb.spef.gz[Added - diff]
spi/lvs/DFFRAM.spice.gz[Added - diff]
spi/lvs/pinmux.spice.gz[Added - diff]
spi/lvs/qspim_top.spice.gz[Added - diff]
spi/lvs/uart_i2c_usb_spi_top.spice.gz[Added - diff]
spi/lvs/user_project_wrapper.spice.gz[Added - diff]
spi/lvs/wb_host.spice.gz[Added - diff]
spi/lvs/wb_interconnect.spice.gz[Added - diff]
spi/lvs/yifive.spice.gz[Added - diff]
sta/Makefile[Added - diff]
sta/base.sdc[Added - diff]
sta/run_sta[Added - diff]
sta/scripts/caravel_timing.tcl[Added - diff]
sta/scripts/or_write_verilog.tcl[Added - diff]
sta/scripts/pinmux_timing.tcl[Added - diff]
sta/scripts/qspim.tcl[Added - diff]
sta/scripts/riscdunio.tcl[Added - diff]
sta/scripts/sta.tcl[Added - diff]
sta/scripts/uart_i2c_usb_spi_timing.tcl[Added - diff]
sta/scripts/wb_host.tcl[Added - diff]
sta/scripts/yifive_timing.tcl[Added - diff]
sta/sdc/caravel.sdc[Added - diff]
sta/sdc/pinmux.sdc[Added - diff]
sta/sdc/qspim.sdc[Added - diff]
sta/sdc/uart_i2c_usb_spi.sdc[Added - diff]
sta/sdc/wb_host.sdc[Added - diff]
sta/sdc/yifive.sdc[Added - diff]
verilog/dv/Makefile[Added - diff]
verilog/dv/README.md[Added - diff]
verilog/dv/agents/test_control.v[Added - diff]
verilog/dv/agents/uart_agent.v[Added - diff]
verilog/dv/agents/uart_master_tasks.sv[Added - diff]
verilog/dv/agents/usb_agents.v[Added - diff]
verilog/dv/bfm/usb1d_defines.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_core.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_crc16.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_crc5.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_ctrl.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_fifo2.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_generic_dpram.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_generic_fifo.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_idma.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_pa.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_pd.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_pe.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_pl.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_rom1.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_sync_fifo.v[Added - diff]
verilog/dv/bfm/usb_device/core/usb1d_utmi_if.v[Added - diff]
verilog/dv/bfm/usb_device/phy/usb1d_phy.v[Added - diff]
verilog/dv/bfm/usb_device/phy/usb1d_rx_phy.v[Added - diff]
verilog/dv/bfm/usb_device/phy/usb1d_tx_phy.v[Added - diff]
verilog/dv/bfm/usb_device/top/usb1d_top.v[Added - diff]
verilog/dv/bfm/usbd_files.v[Added - diff]
verilog/dv/c_func/inc/pwm.h[Added - diff]
verilog/dv/c_func/inc/user_reg_map.h[Added - diff]
verilog/dv/firmware/LICENSE[Added - diff]
verilog/dv/firmware/common.mk[Added - diff]
verilog/dv/firmware/crt.S[Added - diff]
verilog/dv/firmware/crt_tcm.S[Added - diff]
verilog/dv/firmware/csr.h[Added - diff]
verilog/dv/firmware/link.ld[Added - diff]
verilog/dv/firmware/link_tcm.ld[Added - diff]
verilog/dv/firmware/reloc.h[Added - diff]
verilog/dv/firmware/riscv_csr_encoding.h[Added - diff]
verilog/dv/firmware/riscv_macros.h[Added - diff]
verilog/dv/firmware/sc_print.c[Added - diff]
verilog/dv/firmware/sc_print.h[Added - diff]
verilog/dv/firmware/sc_test.h[Added - diff]
verilog/dv/firmware/ycr1_specific.h[Added - diff]
verilog/dv/model/i2c_slave_model.v[Added - diff]
verilog/dv/model/is62wvs1288.v[Added - diff]
verilog/dv/model/mt48lc8m8a2.v[Added - diff]
verilog/dv/model/s25fl256s.sv[Added - diff]
verilog/dv/model/spiram.v[Added - diff]
verilog/dv/risc_boot/Makefile[Added - diff]
verilog/dv/risc_boot/risc_boot.c[Added - diff]
verilog/dv/risc_boot/risc_boot_tb.v[Added - diff]
verilog/dv/risc_boot/run_iverilog[Added - diff]
verilog/dv/risc_boot/user_uart.c[Added - diff]
verilog/dv/riscv_regress/Makefile[Added - diff]
verilog/dv/riscv_regress/riscv_runtests.sv[Added - diff]
verilog/dv/riscv_regress/run_iverilog[Added - diff]
verilog/dv/riscv_regress/tests/benchmarks/coremark/Makefile[Added - diff]
verilog/dv/riscv_regress/tests/benchmarks/coremark/core_portme.c[Added - diff]
verilog/dv/riscv_regress/tests/benchmarks/coremark/core_portme.h[Added - diff]
verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/Makefile[Added - diff]
verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry.h[Added - diff]
verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry_1.c[Added - diff]
verilog/dv/riscv_regress/tests/benchmarks/dhrystone21/dhry_2.c[Added - diff]
verilog/dv/riscv_regress/tests/hello/Makefile[Added - diff]
verilog/dv/riscv_regress/tests/hello/hello.c[Added - diff]
verilog/dv/riscv_regress/tests/isr_sample/Makefile[Added - diff]
verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S[Added - diff]
verilog/dv/riscv_regress/tests/isr_sample/timer.h[Added - diff]
verilog/dv/riscv_regress/tests/riscv_compliance/Makefile[Added - diff]
verilog/dv/riscv_regress/tests/riscv_compliance/aw_test_macros.h[Added - diff]
verilog/dv/riscv_regress/tests/riscv_compliance/compliance_io.h[Added - diff]
verilog/dv/riscv_regress/tests/riscv_compliance/compliance_test.h[Added - diff]
verilog/dv/riscv_regress/tests/riscv_compliance/riscv_test.h[Added - diff]
verilog/dv/riscv_regress/tests/riscv_compliance/riscv_test_macros.h[Added - diff]
verilog/dv/riscv_regress/tests/riscv_compliance/test_macros.h[Added - diff]
verilog/dv/riscv_regress/tests/riscv_isa/Makefile[Added - diff]
verilog/dv/riscv_regress/tests/riscv_isa/riscv_test.h[Added - diff]
verilog/dv/riscv_regress/tests/riscv_isa/rv32_tests.inc[Added - diff]
verilog/dv/riscv_regress/tests/riscv_isa/test_macros.h[Added - diff]
verilog/dv/riscv_regress/user_risc_regress_tb.v[Added - diff]
verilog/dv/uart_master/Makefile[Added - diff]
verilog/dv/uart_master/run_verilog[Added - diff]
verilog/dv/uart_master/uart_master.c[Added - diff]
verilog/dv/uart_master/uart_master_tb.v[Added - diff]
verilog/dv/user_basic/Makefile[Added - diff]
verilog/dv/user_basic/user_basic_tb.v[Added - diff]
verilog/dv/user_i2cm/Makefile[Added - diff]
verilog/dv/user_i2cm/run_iverilog[Added - diff]
verilog/dv/user_i2cm/user_i2cm_tb.v[Added - diff]
verilog/dv/user_i2cm/user_uart.c[Added - diff]
verilog/dv/user_pwm/Makefile[Added - diff]
verilog/dv/user_pwm/user_pwm_tb.v[Added - diff]
verilog/dv/user_qspi/Makefile[Added - diff]
verilog/dv/user_qspi/flash0.hex[Added - diff]
verilog/dv/user_qspi/flash1.hex[Added - diff]
verilog/dv/user_qspi/run_iverilog[Added - diff]
verilog/dv/user_qspi/user_qspi_tb.v[Added - diff]
verilog/dv/user_qspi/user_risc_boot.c[Added - diff]
verilog/dv/user_risc_boot/Makefile[Added - diff]
verilog/dv/user_risc_boot/run_iverilog[Added - diff]
verilog/dv/user_risc_boot/user_risc_boot.c[Added - diff]
verilog/dv/user_risc_boot/user_risc_boot_tb.v[Added - diff]
verilog/dv/user_risc_boot/user_uart.c[Added - diff]
verilog/dv/user_sspi/Makefile[Added - diff]
verilog/dv/user_sspi/flash0.hex[Added - diff]
verilog/dv/user_sspi/flash1.hex[Added - diff]
verilog/dv/user_sspi/flash2.hex[Added - diff]
verilog/dv/user_sspi/flash3.hex[Added - diff]
verilog/dv/user_sspi/sspi_task.v[Added - diff]
verilog/dv/user_sspi/user_sspi_tb.v[Added - diff]
verilog/dv/user_timer/Makefile[Added - diff]
verilog/dv/user_timer/user_timer_tb.v[Added - diff]
verilog/dv/user_uart/.user_uart.c.un~[Added - diff]
verilog/dv/user_uart/Makefile[Added - diff]
verilog/dv/user_uart/run_iverilog[Added - diff]
verilog/dv/user_uart/user_uart.c[Added - diff]
verilog/dv/user_uart/user_uart_tb.v[Added - diff]
verilog/dv/user_uart1/.user_uart.c.un~[Added - diff]
verilog/dv/user_uart1/Makefile[Added - diff]
verilog/dv/user_uart1/run_iverilog[Added - diff]
verilog/dv/user_uart1/user_uart.c[Added - diff]
verilog/dv/user_uart1/user_uart1_tb.v[Added - diff]
verilog/dv/user_uart_master/Makefile[Added - diff]
verilog/dv/user_uart_master/run_iverilog[Added - diff]
verilog/dv/user_uart_master/user_uart.c[Added - diff]
verilog/dv/user_uart_master/user_uart_master_tb.v[Added - diff]
verilog/dv/user_usb/Makefile[Added - diff]
verilog/dv/user_usb/tests/usb_test1.v[Added - diff]
verilog/dv/user_usb/tests/usb_test2.v[Added - diff]
verilog/dv/user_usb/tests/usb_test3.v[Added - diff]
verilog/dv/user_usb/user_usb_tb.v[Added - diff]
verilog/dv/vpi/system/system.c[Added - diff]
verilog/dv/wb_port/Makefile[Added - diff]
verilog/dv/wb_port/run_verilog[Added - diff]
verilog/dv/wb_port/wb_port.c[Added - diff]
verilog/dv/wb_port/wb_port_tb.v[Added - diff]
verilog/gl/DFFRAM.v[Added - diff]
verilog/gl/clk_skew_adjust.v[Added - diff]
verilog/gl/pinmux.v[Added - diff]
verilog/gl/qspim_top.v[Added - diff]
verilog/gl/sar_adc.v[Added - diff]
verilog/gl/sky130_sram_2kbyte_1rw1r_32x512_8.v[Added - diff]
verilog/gl/uart_i2c_usb_spi_top.v[Added - diff]
verilog/gl/user_project_wrapper.v[Added - diff]
verilog/gl/wb_host.v[Added - diff]
verilog/gl/wb_interconnect.v[Added - diff]
verilog/gl/yifive.v[Added - diff]
verilog/includes/includes.rtl.caravel_user_project[Added - diff]
verilog/rtl/DFFRAM/DFFRAM.v[Added - diff]
verilog/rtl/DFFRAM/DFFRAMBB.v[Added - diff]
verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv[Added - diff]
verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v[Added - diff]
verilog/rtl/clk_skew_adjust/synth/Makefile[Added - diff]
verilog/rtl/clk_skew_adjust/synth/synth.tcl[Added - diff]
verilog/rtl/digital_core/filelist_rtl.f[Added - diff]
verilog/rtl/digital_core/run_modelsim[Added - diff]
verilog/rtl/digital_core/src/digital_core.sv[Added - diff]
verilog/rtl/digital_core/src/glbl_cfg.sv[Added - diff]
verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v[Added - diff]
verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v[Added - diff]
verilog/rtl/i2cm/src/core/i2cm_top.v[Added - diff]
verilog/rtl/i2cm/src/includes/i2cm_defines.v[Added - diff]
verilog/rtl/lib/async_fifo.sv[Added - diff]
verilog/rtl/lib/async_fifo_th.sv[Added - diff]
verilog/rtl/lib/async_reg_bus.sv[Added - diff]
verilog/rtl/lib/async_wb.sv[Added - diff]
verilog/rtl/lib/clk_buf.v[Added - diff]
verilog/rtl/lib/clk_ctl.v[Added - diff]
verilog/rtl/lib/clk_skew_adjust.gv[Added - diff]
verilog/rtl/lib/ctech_cells.sv[Added - diff]
verilog/rtl/lib/double_sync_high.v[Added - diff]
verilog/rtl/lib/double_sync_low.v[Added - diff]
verilog/rtl/lib/pulse_gen_type1.sv[Added - diff]
verilog/rtl/lib/pulse_gen_type2.sv[Added - diff]
verilog/rtl/lib/registers.v[Added - diff]
verilog/rtl/lib/reset_sync.sv[Added - diff]
verilog/rtl/lib/ser_inf_32b.sv[Added - diff]
verilog/rtl/lib/ser_shift.sv[Added - diff]
verilog/rtl/lib/sync_fifo.sv[Added - diff]
verilog/rtl/lib/sync_fifo2.sv[Added - diff]
verilog/rtl/lib/sync_wbb.sv[Added - diff]
verilog/rtl/lib/wb_interface.v[Added - diff]
verilog/rtl/lib/wb_stagging.sv[Added - diff]
verilog/rtl/mbist/include/mbist_def.svh[Added - diff]
verilog/rtl/mbist/run_iverilog[Added - diff]
verilog/rtl/mbist/run_verilator[Added - diff]
verilog/rtl/mbist/src/core/mbist_addr_gen.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_data_cmp.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_fsm.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_mux.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_op_sel.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_pat_sel.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_repair_addr.sv[Added - diff]
verilog/rtl/mbist/src/core/mbist_sti_sel.sv[Added - diff]
verilog/rtl/mbist/src/top/mbist_top.sv[Added - diff]
verilog/rtl/mbist/src/top/mbist_top1.sv[Added - diff]
verilog/rtl/mbist/src/top/mbist_top2.sv[Added - diff]
verilog/rtl/mbist_wrapper/src/mbist_wb.sv[Added - diff]
verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv[Added - diff]
verilog/rtl/pinmux/src/gpio_control.sv[Added - diff]
verilog/rtl/pinmux/src/gpio_intr.sv[Added - diff]
verilog/rtl/pinmux/src/pinmux.sv[Added - diff]
verilog/rtl/pinmux/src/pinmux_reg.sv[Added - diff]
verilog/rtl/pinmux/src/pwm.sv[Added - diff]
verilog/rtl/pinmux/src/timer.sv[Added - diff]
verilog/rtl/sar_adc/ACMP.sv[Added - diff]
verilog/rtl/sar_adc/ACMP_HVL.v[Added - diff]
verilog/rtl/sar_adc/DAC_8BIT.v[Added - diff]
verilog/rtl/sar_adc/SAR.sv[Added - diff]
verilog/rtl/sar_adc/adc_reg.sv[Added - diff]
verilog/rtl/sar_adc/sar_adc.sv[Added - diff]
verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v[Added - diff]
verilog/rtl/sspim/src/filelist_spi.f[Added - diff]
verilog/rtl/sspim/src/sspim_cfg.sv[Added - diff]
verilog/rtl/sspim/src/sspim_ctl.sv[Added - diff]
verilog/rtl/sspim/src/sspim_if.sv[Added - diff]
verilog/rtl/sspim/src/sspim_top.sv[Added - diff]
verilog/rtl/uart/src/uart_cfg.sv[Added - diff]
verilog/rtl/uart/src/uart_core.sv[Added - diff]
verilog/rtl/uart/src/uart_rxfsm.sv[Added - diff]
verilog/rtl/uart/src/uart_txfsm.sv[Added - diff]
verilog/rtl/uart2wb/src/run_verilog[Added - diff]
verilog/rtl/uart2wb/src/uart2_core.sv[Added - diff]
verilog/rtl/uart2wb/src/uart2wb.sv[Added - diff]
verilog/rtl/uart2wb/src/uart_msg_handler.v[Added - diff]
verilog/rtl/uart_i2c/src/uart_i2c_top.sv[Added - diff]
verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv[Added - diff]
verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv[Added - diff]
verilog/rtl/uprj_netlists.v[Added - diff]
verilog/rtl/usb1_host/src/core/usbh_core.sv[Added - diff]
verilog/rtl/usb1_host/src/core/usbh_crc16.sv[Added - diff]
verilog/rtl/usb1_host/src/core/usbh_crc5.sv[Added - diff]
verilog/rtl/usb1_host/src/core/usbh_fifo.sv[Added - diff]
verilog/rtl/usb1_host/src/core/usbh_sie.sv[Added - diff]
verilog/rtl/usb1_host/src/filelist.f[Added - diff]
verilog/rtl/usb1_host/src/includes/usbh_host_defs.v[Added - diff]
verilog/rtl/usb1_host/src/phy/usb_fs_phy.v[Added - diff]
verilog/rtl/usb1_host/src/phy/usb_transceiver.v[Added - diff]
verilog/rtl/usb1_host/src/top/usb1_host.sv[Added - diff]
verilog/rtl/user_project_wrapper.v[Added - diff]
verilog/rtl/user_reg_map.v[Added - diff]
verilog/rtl/wb_host/src/wb_host.sv[Added - diff]
verilog/rtl/wb_interconnect/src/wb_arb.sv[Added - diff]
verilog/rtl/wb_interconnect/src/wb_interconnect.sv[Added - diff]
verilog/rtl/wb_interconnect/src/wb_slave_port.sv[Added - diff]

449 files changed

tree: 8ea55a83e7a803d925ea7930840ad6ede49aad2f

README.md

Efabless_MPW6_riscduino

This project is cloned from dineshannayya / riscduino Public