| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,1h23m37s,-1,54940.642179905975,1.2551,27470.321089952988,30.97,1607.58,34478,0,0,0,0,0,0,0,33,0,-1,-1,2753267,389772,-15.47,-48.52,-1,-1.05,-1,-34117.75,-19828.04,-1,-6.64,-1,2065115550.0,17.89,40.67,58.45,4.63,5.31,-1,28633,48324,1779,21063,0,0,0,34183,0,0,0,0,0,0,0,4,8286,8734,54,1116,17360,0,18476,90.9090909090909,11,10,AREA 0,4,50,1,153.6,153.18,0.32,0.0,sky130_fd_sc_hd,4,4 |
