final gds oasis
90 files changed
tree: f63a339661e1128a664c483ab0776fc8c032766c
  1. docs/
  2. gds/
  3. mag/
  4. mpw_precheck/
  5. netgen/
  6. openlane/
  7. signoff/
  8. tapeout/
  9. verilog/
  10. xschem/
  11. .gitignore
  12. LICENSE
  13. Makefile
  14. README.md
README.md

10 bit SAR-ADC + Analog Circuits

This submission features:

  • 10b SAR-ADC on powered from external supply.
  • 10b SAR-ADC powered from internal regulators.
  • Bandgap reference.
  • Testbuffer with multiplexer input.
  • Clock generator
  • 2 linear regulators, 1.2V and 1.5V.
  • Bias current/voltage generator.

Included are:

  • Hierachical GDS of the whole layout with all individual blocks.
  • Schematics for all parts of the layout.
  • Testbenches for all the individual blocks.
  • Simulation corners setups for process corner simulations.

Schematics

Simply source cadrc in the xschem folder and execute xschem afterwards to get an full overview.

Top Schematic

Layout

Top-level layout