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foss-eda-tools / third_party / shuttle / sky130 / mpw-006 / slot-013 / e324def62fd63d270cdb9f92385839885d9706ae
commite324def62fd63d270cdb9f92385839885d9706ae[log] [tgz]
authorchrische <christoph-weiser@gmx.de>Tue May 17 22:15:29 2022 +0200
committerchrische <christoph-weiser@gmx.de>Tue May 17 22:15:29 2022 +0200
tree02dd0f40f5cd16c9203ab7fa8b234cec01832833
parent526213fac2289e0b9d15785097d90679550b8f69 [diff]
added project license
1 file changed
tree: 02dd0f40f5cd16c9203ab7fa8b234cec01832833
  1. docs/
  2. gds/
  3. mag/
  4. netgen/
  5. openlane/
  6. verilog/
  7. xschem/
  8. caravel
  9. .gitignore
  10. LICENSE
  11. Makefile
  12. README.md
README.md

10 bit SAR-ADC + Analog Circuits

This submission features:

  • 10b SAR-ADC on powered from external supply.
  • 10b SAR-ADC powered from internal regulators.
  • Bandgap reference.
  • Testbuffer with multiplexer input.
  • Clock generator
  • 2 linear regulators, 1.2V and 1.5V.
  • Bias current/voltage generator.

Included are:

  • Hierachical GDS of the whole layout with all individual blocks.
  • Schematics for all parts of the layout.
  • Testbenches for all the individual blocks.
  • Simulation corners setups for process corner simulations.

Schematics

Simply source cadrc in the xschem folder and execute xschem afterwards to get an full overview.

Top Schematic

Layout

Top-level layout