pll movement near to pinmux
diff --git a/gds/pinmux_top.gds.gz b/gds/pinmux_top.gds.gz
index 3aa8d8f..ad11414 100644
--- a/gds/pinmux_top.gds.gz
+++ b/gds/pinmux_top.gds.gz
Binary files differ
diff --git a/gds/uart_i2c_usb_spi_top.gds.gz b/gds/uart_i2c_usb_spi_top.gds.gz
index 910d1dd..f74cb0a 100644
--- a/gds/uart_i2c_usb_spi_top.gds.gz
+++ b/gds/uart_i2c_usb_spi_top.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 257748c..c2bf5d8 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/gds/wb_host.gds.gz b/gds/wb_host.gds.gz
index 8cd28a7..d2d2fbc 100644
--- a/gds/wb_host.gds.gz
+++ b/gds/wb_host.gds.gz
Binary files differ
diff --git a/lef/pinmux_top.lef.gz b/lef/pinmux_top.lef.gz
index add8628..26303aa 100644
--- a/lef/pinmux_top.lef.gz
+++ b/lef/pinmux_top.lef.gz
Binary files differ
diff --git a/lef/uart_i2c_usb_spi_top.lef.gz b/lef/uart_i2c_usb_spi_top.lef.gz
index e29e070..b356799 100644
--- a/lef/uart_i2c_usb_spi_top.lef.gz
+++ b/lef/uart_i2c_usb_spi_top.lef.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index 9872c44..d9a659d 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ
diff --git a/lef/wb_host.lef.gz b/lef/wb_host.lef.gz
index b07139a..7b96a81 100644
--- a/lef/wb_host.lef.gz
+++ b/lef/wb_host.lef.gz
Binary files differ
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl
index b1bce35..243f5e5 100755
--- a/openlane/pinmux_top/config.tcl
+++ b/openlane/pinmux_top/config.tcl
@@ -98,8 +98,8 @@
set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.38"
-set ::env(CELL_PAD) "4"
+set ::env(PL_TARGET_DENSITY) "0.36"
+set ::env(CELL_PAD) "8"
#set ::env(GRT_ADJUSTMENT) {0.2}
@@ -131,13 +131,11 @@
set ::env(DIODE_INSERTION_STRATEGY) 4
+
#LVS Issue - DEF Base looks to having issue
set ::env(MAGIC_EXT_USE_GDS) {1}
-set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
-set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1"
-set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1"
-set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) "1"
+
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
set ::env(QUIT_ON_MAGIC_DRC) "1"
set ::env(QUIT_ON_LVS_ERROR) "1"
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg
index d0074cf..e99154e 100644
--- a/openlane/pinmux_top/pin_order.cfg
+++ b/openlane/pinmux_top/pin_order.cfg
@@ -73,6 +73,8 @@
p_reset_n
s_reset_n
usb_clk
+strap_uartm\[1\]
+strap_uartm\[0\]
strap_sticky\[31\]
strap_sticky\[30\]
strap_sticky\[29\]
@@ -170,7 +172,7 @@
pinmux_debug\[29\]
pinmux_debug\[30\]
pinmux_debug\[31\]
-dbg_clk_mon
+cpu_clk
#W
@@ -302,7 +304,7 @@
#N
-rtc_clk 000 0 2
+rtc_clk 000 0 4
digital_io_oen\[37\]
digital_io_out\[37\]
digital_io_in\[37\]
@@ -334,6 +336,40 @@
digital_io_out\[28\]
+cfg_dco_mode 0200 0 2
+cfg_pll_enb
+pll_ref_clk
+cfg_pll_fed_div\[4\]
+cfg_pll_fed_div\[3\]
+cfg_pll_fed_div\[2\]
+cfg_pll_fed_div\[1\]
+cfg_pll_fed_div\[0\]
+cfg_dc_trim\[25\]
+cfg_dc_trim\[24\]
+cfg_dc_trim\[23\]
+cfg_dc_trim\[22\]
+cfg_dc_trim\[21\]
+cfg_dc_trim\[20\]
+cfg_dc_trim\[19\]
+cfg_dc_trim\[18\]
+cfg_dc_trim\[17\]
+cfg_dc_trim\[16\]
+cfg_dc_trim\[15\]
+cfg_dc_trim\[14\]
+cfg_dc_trim\[13\]
+cfg_dc_trim\[12\]
+cfg_dc_trim\[11\]
+cfg_dc_trim\[10\]
+cfg_dc_trim\[9\]
+cfg_dc_trim\[8\]
+cfg_dc_trim\[7\]
+cfg_dc_trim\[6\]
+cfg_dc_trim\[5\]
+cfg_dc_trim\[4\]
+cfg_dc_trim\[3\]
+cfg_dc_trim\[2\]
+cfg_dc_trim\[1\]
+cfg_dc_trim\[0\]
digital_io_in\[28\] 0300 0 2
digital_io_oen\[27\]
diff --git a/openlane/qspim_top/config.tcl b/openlane/qspim_top/config.tcl
index 06d3dd2..4cdf315 100755
--- a/openlane/qspim_top/config.tcl
+++ b/openlane/qspim_top/config.tcl
@@ -85,9 +85,6 @@
# helps in anteena fix
set ::env(USE_ARC_ANTENNA_CHECK) "0"
-#LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
-
#set ::env(FP_IO_VEXTEND) 4
#set ::env(FP_IO_HEXTEND) 4
@@ -102,6 +99,10 @@
set ::env(DIODE_INSERTION_STRATEGY) 4
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
+
+
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
set ::env(QUIT_ON_MAGIC_DRC) "1"
set ::env(QUIT_ON_LVS_ERROR) "1"
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl
index 0415b67..86a397e 100644
--- a/openlane/uart_i2cm_usb_spi_top/config.tcl
+++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -105,9 +105,6 @@
set ::env(PL_TIME_DRIVEN) 1
set ::env(PL_TARGET_DENSITY) "0.42"
-#LVS Issue - DEF Base looks to having issue
-set ::env(MAGIC_EXT_USE_GDS) {1}
-
# helps in anteena fix
set ::env(USE_ARC_ANTENNA_CHECK) "0"
@@ -127,9 +124,9 @@
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
-#set ::env(GLB_RT_ADJUSTMENT) {0.25}
-#set ::env(GRT_LAYER_ADJUSTMENTS) {0.25,0,0,0,0,0}
set ::env(CELL_PAD) {8}
+#LVS Issue - DEF Base looks to having issue
+set ::env(MAGIC_EXT_USE_GDS) {1}
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
set ::env(QUIT_ON_MAGIC_DRC) "1"
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index ce84731..7e004cb 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -136,6 +136,7 @@
set ::env(VDD_PIN) {vccd1}
set ::env(GND_PIN) {vssd1}
+set ::env(DRT_OPT_ITERS) {32}
set ::env(GRT_OBS) " \
li1 150 130 833.1 546.54,\
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 0bbe026..8c696b9 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,6 +1,7 @@
u_qspi_master 2250 650 N
u_uart_i2c_usb_spi 2250 1350 N
u_pinmux 2250 2250 N
+u_pll 2500 3148 N
u_riscv_top.i_core_top_0 75 1400 N
u_riscv_top.i_core_top_1 1200 1400 FN
@@ -15,4 +16,4 @@
u_intercon 1850 650 N
u_wb_host 1750 100 N
-u_pll 2300 68 N
+
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 2f1eeb6..08d18dd 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -42,7 +42,8 @@
set ::env(VERILOG_FILES) "\
$::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
$::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wb_host.sv \
- $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wb_reset_fsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wbh_reset_fsm.sv \
+ $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wbh_reg.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/lib/async_fifo.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/lib/async_wb.sv \
$::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_ctl.v \
@@ -85,7 +86,7 @@
# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0
+set ::env(RUN_CVC) 1
#set ::env(PDN_CFG) $script_dir/pdn.tcl
@@ -95,8 +96,8 @@
-#set ::env(FP_IO_VEXTEND) 4
-#set ::env(FP_IO_HEXTEND) 4
+set ::env(FP_IO_VEXTEND) 4
+set ::env(FP_IO_HEXTEND) 4
set ::env(FP_PDN_VPITCH) 100
set ::env(FP_PDN_HPITCH) 100
@@ -109,6 +110,7 @@
set ::env(DIODE_INSERTION_STRATEGY) 4
+
#LVS Issue - DEF Base looks to having issue
set ::env(MAGIC_EXT_USE_GDS) {1}
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 2c6a14d..26c9f8e 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg
@@ -141,46 +141,8 @@
la_data_in\[17\]
#E
-cfg_dc_trim\[7\] 000 0 2
-cfg_dc_trim\[8\]
-cfg_dc_trim\[9\]
-cfg_dc_trim\[10\]
-cfg_dc_trim\[11\]
-cfg_dc_trim\[12\]
-cfg_dc_trim\[13\]
-cfg_dc_trim\[14\]
-cfg_dc_trim\[15\]
-cfg_dc_trim\[16\]
-cfg_dc_trim\[17\]
-cfg_dc_trim\[18\]
-cfg_dc_trim\[19\]
-cfg_dc_trim\[25\]
-cfg_dc_trim\[24\]
-cfg_dc_trim\[23\]
-cfg_dc_trim\[22\]
-cfg_dc_trim\[21\]
-cfg_dc_trim\[20\]
-
-pll_clk_out\[0\]
-pll_clk_out\[1\]
-cfg_pll_fed_div\[0\]
-cfg_pll_fed_div\[1\]
-cfg_pll_fed_div\[2\]
-cfg_pll_fed_div\[3\]
-cfg_pll_fed_div\[4\]
-cfg_pll_enb
-cfg_dco_mode
-cfg_dc_trim\[0\]
-cfg_dc_trim\[1\]
-cfg_dc_trim\[2\]
-cfg_dc_trim\[3\]
-cfg_dc_trim\[4\]
-cfg_dc_trim\[5\]
-cfg_dc_trim\[6\]
-
-wbd_pll_rst_n
-pll_ref_clk
+wbd_pll_rst_n 000 0 2
@@ -193,7 +155,6 @@
sdout_oen
-dbg_clk_mon
#N
@@ -354,6 +315,8 @@
p_reset_n
s_reset_n
xtal_clk
+strap_uartm\[1\]
+strap_uartm\[0\]
strap_sticky\[31\]
strap_sticky\[30\]
strap_sticky\[29\]
diff --git a/spef/pinmux_top.spef.gz b/spef/pinmux_top.spef.gz
index 7925e43..18380a6 100644
--- a/spef/pinmux_top.spef.gz
+++ b/spef/pinmux_top.spef.gz
Binary files differ
diff --git a/spef/uart_i2c_usb_spi_top.spef.gz b/spef/uart_i2c_usb_spi_top.spef.gz
index 38da2cd..a1d7884 100644
--- a/spef/uart_i2c_usb_spi_top.spef.gz
+++ b/spef/uart_i2c_usb_spi_top.spef.gz
Binary files differ
diff --git a/spef/user_project_wrapper.spef.gz b/spef/user_project_wrapper.spef.gz
index 5cf16ca..41018c3 100644
--- a/spef/user_project_wrapper.spef.gz
+++ b/spef/user_project_wrapper.spef.gz
Binary files differ
diff --git a/spef/wb_host.spef.gz b/spef/wb_host.spef.gz
index 21c69ee..c3af1ee 100644
--- a/spef/wb_host.spef.gz
+++ b/spef/wb_host.spef.gz
Binary files differ
diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz
index 81abd3e..0ac7bb9 100644
--- a/spi/lvs/user_project_wrapper.spice.gz
+++ b/spi/lvs/user_project_wrapper.spice.gz
Binary files differ
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index f1f0d68..238d50c 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -19,12 +19,15 @@
.SUFFIXES:
.SILENT: clean all
-PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec user_cache_bypass user_gpio user_spi_isp arduino_risc_boot arduino_hello_world arduino_ascii_table arduino_multi_serial arduino_arrays arduino_switchCase2 arduino_character_analysis arduino_string arduino_digital_port_control user_sspi user_aes user_sema arduino_timer_intr user_mcore_test1 user_mcore_test2 arduino_gpio_intr arduino_i2c_scaner
+PATTERNS = user_basic user_uart user_uart1 user_risc_boot user_qspi user_sspi user_i2cm user_usb user_gpio user_aes user_spi_isp user_timer user_uart_master user_sram_exec user_cache_bypass user_pwm user_sema risc_boot uart_master wb_port arduino_arrays arduino_digital_port_control arduino_i2c_scaner arduino_risc_boot arduino_timer_intr arduino_ascii_table arduino_gpio_intr arduino_i2c_wr_rd arduino_string arduino_ws281x arduino_character_analysis arduino_hello_world arduino_multi_serial arduino_switchCase2 user_mcore_test1 user_mcore_test2 riscv_regress
all: ${PATTERNS}
+ echo "################# Test case Summary #####################" > regression.rpt
+ xterm -e /usr/bin/watch -n 25 /bin/cat regression.rpt &
for i in ${PATTERNS}; do \
- ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ ( cd $$i && make | tee run.log && grep Monitor run.log | grep $$i >> ../regression.rpt) ; \
done
+ echo "################# End of Test case Summary #####################" >> regression.rpt
DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
$(DV_PATTERNS): verify-% :
diff --git a/verilog/dv/agents/user_tasks.sv b/verilog/dv/agents/user_tasks.sv
deleted file mode 100644
index a6dedb0..0000000
--- a/verilog/dv/agents/user_tasks.sv
+++ /dev/null
@@ -1,201 +0,0 @@
-
-/********************
-parameter bit [15:0] PAD_STRAP = (2'b00 << `PSTRAP_CLK_SRC ) |
- (2'b00 << `PSTRAP_CLK_DIV ) |
- (1'b1 << `PSTRAP_UARTM_CFG ) |
- (1'b1 << `PSTRAP_QSPI_SRAM ) |
- (2'b10 << `PSTRAP_QSPI_FLASH ) |
- (1'b1 << `PSTRAP_RISCV_RESET_MODE ) |
- (1'b1 << `PSTRAP_RISCV_CACHE_BYPASS ) |
- (1'b1 << `PSTRAP_RISCV_SRAM_CLK_EDGE ) |
- (2'b00 << `PSTRAP_CLK_SKEW ) |
- (1'b0 << `PSTRAP_DEFAULT_VALUE ) ;
-****/
-
-`ifdef RISC_BOOT // RISCV Based Test case
-parameter bit [15:0] PAD_STRAP = 16'b0000_0001_1011_0000;
-`else
-parameter bit [15:0] PAD_STRAP = 16'b0000_0000_1011_0000;
-`endif
-
-/***********************************************
-
-wire [15:0] strap_in;
-assign strap_in[`PSTRAP_CLK_SRC] = 2'b00; // System Clock Source wbs/riscv: User clock1
-assign strap_in[`PSTRAP_CLK_DIV] = 2'b00; // Clock Division for wbs/riscv : 0 Div
-assign strap_in[`PSTRAP_UARTM_CFG] = 1'b0; // uart master config control - constant value based on system clock selection
-assign strap_in[`PSTRAP_QSPI_SRAM] = 1'b1; // QSPI SRAM Mode Selection - Quad
-assign strap_in[`PSTRAP_QSPI_FLASH] = 2'b10; // QSPI Fash Mode Selection - Quad
-assign strap_in[`PSTRAP_RISCV_RESET_MODE] = 1'b1; // Riscv Reset control - Removed Riscv on Power On Reset
-assign strap_in[`PSTRAP_RISCV_CACHE_BYPASS] = 1'b0; // Riscv Cache Bypass: 0 - Cache Enable
-assign strap_in[`PSTRAP_RISCV_SRAM_CLK_EDGE] = 1'b0; // Riscv SRAM clock edge selection: 0 - Normal
-assign strap_in[`PSTRAP_CLK_SKEW] = 2'b00; // Skew selection 2'b00 - Default value
-
-assign strap_in[`PSTRAP_DEFAULT_VALUE] = 1'b0; // 0 - Normal
-***/
-
-initial
-begin
- // Run in Fast Sim Mode
- `ifdef GL
- force u_top.u_wb_host._8654_.Q= 1'b1;
- `else
- force u_top.u_wb_host.u_fastsim_buf.X = 1'b1;
- `endif
-
-end
-task init;
-begin
- //#1 - Apply Reset
- #1000 wb_rst_i = 0;
- repeat (10) @(posedge clock);
- #1000 wb_rst_i = 1;
-
- //#3 - Remove Reset
- #1000 wb_rst_i = 0;
- repeat (10) @(posedge clock);
- //#4 - Wait for Power on reset removal
- wait(u_top.p_reset_n == 1);
-
- // #5 - Wait for system reset removal
- wait(u_top.s_reset_n == 1); // Wait for system reset removal
- repeat (10) @(posedge clock);
-
-/****
- //#2 - Apply Strap
- strap_in[`PSTRAP_CLK_SRC] = 2'b00; // System Clock Source wbs/riscv: User clock1
- strap_in[`PSTRAP_CLK_DIV] = 2'b00; // Clock Division for wbs/riscv : 0 Div
- strap_in[`PSTRAP_UARTM_CFG] = 1'b0; // uart master config control - constant value based on system clock selection
- strap_in[`PSTRAP_QSPI_SRAM] = 1'b1; // QSPI SRAM Mode Selection - Quad
- strap_in[`PSTRAP_QSPI_FLASH] = 2'b10; // QSPI Fash Mode Selection - Quad
- strap_in[`PSTRAP_RISCV_RESET_MODE] = 1'b1; // Riscv Reset control - Removed Riscv on Power On Reset
- strap_in[`PSTRAP_RISCV_CACHE_BYPASS] = 1'b0; // Riscv Cache Bypass: 0 - Cache Enable
- strap_in[`PSTRAP_RISCV_SRAM_CLK_EDGE] = 1'b0; // Riscv SRAM clock edge selection: 0 - Normal
- strap_in[`PSTRAP_CLK_SKEW] = 2'b00; // Skew selection 2'b00 - Default value
-
- strap_in[`PSTRAP_DEFAULT_VALUE] = 1'b0; // 0 - Normal
-
- force u_top.io_in[36:29] = strap_in[15:8];
- force u_top.io_in[20:13] = strap_in[7:0];
- repeat (10) @(posedge clock);
-
- //#3 - Remove Reset
- wb_rst_i = 0; // Remove Reset
- repeat (10) @(posedge clock);
- //#4 - Wait for Power on reset removal
- wait(u_top.p_reset_n == 1);
-
- // #5 - Release the Strap
- release u_top.io_in[36:29];
- release u_top.io_in[20:13];
-
- // #6 - Wait for system reset removal
- wait(u_top.s_reset_n == 1); // Wait for system reset removal
- repeat (10) @(posedge clock);
-
-***/
- end
-endtask
-
-//-----------------------------------------------
-// Apply user defined strap at power-on
-//-----------------------------------------------
-
-task apply_strap;
-input [15:0] strap;
-begin
-
- repeat (10) @(posedge clock);
- //#1 - Apply Reset
- wb_rst_i = 1;
- //#2 - Apply Strap
- force u_top.io_in[36:29] = strap[15:8];
- force u_top.io_in[20:13] = strap[7:0];
- repeat (10) @(posedge clock);
-
- //#3 - Remove Reset
- wb_rst_i = 0; // Remove Reset
-
- //#4 - Wait for Power on reset removal
- wait(u_top.p_reset_n == 1);
-
- // #5 - Release the Strap
- release u_top.io_in[36:29];
- release u_top.io_in[20:13];
-
- // #6 - Wait for system reset removal
- wait(u_top.s_reset_n == 1); // Wait for system reset removal
- repeat (10) @(posedge clock);
-
-end
-endtask
-
-//---------------------------------------------------------
-// Create Pull Up/Down Based on Reset Strap Parameter
-//---------------------------------------------------------
-genvar gCnt;
-generate
- for(gCnt=0; gCnt<16; gCnt++) begin : g_strap
- if(gCnt < 8) begin
- if(PAD_STRAP[gCnt]) begin
- pullup(io_in[13+gCnt]);
- end else begin
- pulldown(io_in[13+gCnt]);
- end
- end else begin
- if(PAD_STRAP[gCnt]) begin
- pullup(io_in[29+gCnt-8]);
- end else begin
- pulldown(io_in[29+gCnt-8]);
- end
- end
- end
-
-`ifdef RISC_BOOT // RISCV Based Test case
-//-------------------------------------------
-task wait_riscv_boot;
-input [7:0] id;
-begin
- // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
- // bit[7:0] - core-0
- // bit[15:8] - core-1
- // bit[23:16] - core-2
- // bit[31:24] - core-3
- $display("Status: Waiting for RISCV Core Boot ... ");
- read_data = 0;
- while((read_data >> (id*8)) != 8'h1) begin
- repeat (200) @(posedge clock);
- wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_CFG_MAIL_BOX,read_data);
- end
-
- $display("Status: RISCV Core is Booted ");
-
-end
-endtask
-
-
-task wait_riscv_exit;
-input [7:0] id;
-begin
- // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
- // bit[7:0] - core-0
- // bit[15:8] - core-1
- // bit[23:16] - core-2
- // bit[31:24] - core-3
- $display("Status: Waiting for RISCV Core Boot ... ");
- read_data = 0;
- while((read_data >> (id*8)) != 8'hFF) begin
- repeat (200) @(posedge clock);
- wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_CFG_MAIL_BOX,read_data);
- end
-
- $display("Status: RISCV Core is Exited ");
-
-end
-endtask
-
-`endif
-
-
-endgenerate
-
diff --git a/verilog/dv/arduino_arrays/Makefile b/verilog/dv/arduino_arrays/Makefile
index 0e61c01..e6eb75d 100644
--- a/verilog/dv/arduino_arrays/Makefile
+++ b/verilog/dv/arduino_arrays/Makefile
@@ -29,7 +29,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/arduino_arrays/arduino_arrays_tb.v b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
index cd671e2..f7f4808 100644
--- a/verilog/dv/arduino_arrays/arduino_arrays_tb.v
+++ b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
@@ -74,32 +74,14 @@
`define TB_HEX "arduino_arrays.hex"
`define TB_TOP arduino_arrays_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+parameter real CLK1_PERIOD = 20; // 50 Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
+`include "user_tasks.sv"
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
reg flag ;
parameter P_FSM_C = 4'b0000; // Command Phase Only
@@ -129,25 +111,15 @@
parameter P_QDDR = 2'b11;
- integer d_risc_id;
integer i,j;
- // 50Mhz CLock
- always #10 clock <= (clock === 1'b0);
initial begin
- clock = 0;
flag = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
@@ -192,7 +164,7 @@
$display("Monitor: Standalone User Risc Boot Test Started");
init();
- wait_riscv_boot(d_risc_id);
+ wait_riscv_boot();
// Remove Wb Reset
//wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
@@ -266,58 +238,21 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Ardunio arrays (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Ardunio arrays (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Ardunio arrays (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Ardunio arrays (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
assign io_in[5] = 1'b1; // RESET
@@ -338,14 +273,14 @@
wire flash_clk = io_out[28];
wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
assign io_in[33] = flash_io0;
assign io_in[34] = flash_io1;
@@ -397,136 +332,6 @@
endtask
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-`include "user_tasks.sv"
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/arduino_ascii_table/Makefile b/verilog/dv/arduino_ascii_table/Makefile
index 38987f6..8370ca4 100644
--- a/verilog/dv/arduino_ascii_table/Makefile
+++ b/verilog/dv/arduino_ascii_table/Makefile
@@ -29,7 +29,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
@@ -104,24 +104,24 @@
rm *.o *.a
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
index 0927816..5152893 100644
--- a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
+++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
@@ -74,32 +74,14 @@
`define TB_HEX "arduino_ascii_table.hex"
`define TB_TOP arduino_ascii_table_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+`include "user_tasks.sv"
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
//----------------------------------
// Uart Configuration
// ---------------------------------
@@ -121,25 +103,11 @@
reg [31:0] check_sum ;
- integer d_risc_id;
integer i,j;
-
-
-
- // 50Mhz CLock
- always #10 clock <= (clock === 1'b0);
-
initial begin
- clock = 0;
flag = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
@@ -195,19 +163,22 @@
$value$plusargs("risc_core_id=%d", d_risc_id);
+ init();
+
+
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
// Remove Wb Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+ //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
repeat (2) @(posedge clock);
#1;
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
@@ -219,13 +190,15 @@
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
end
+ wait_riscv_boot();
+
repeat (100) @(posedge clock); // wait for Processor Get Ready
tb_uart.debug_mode = 0; // disable debug display
tb_uart.uart_init;
tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor);
- repeat (45000) @(posedge clock); // wait for Processor Get Ready
+ repeat (1000) @(posedge clock); // wait for Processor Get Ready
flag = 0;
check_sum = 0;
@@ -262,63 +235,21 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone Hello World (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone Hello World (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone Hello World (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone Hello World (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
assign io_in[0] = 1'b1; // RESET
assign io_in[16] = 1'b0 ; // SPIS SCK
@@ -338,14 +269,14 @@
wire flash_clk = io_out[28];
wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
assign io_in[33] = flash_io0;
assign io_in[34] = flash_io1;
@@ -398,135 +329,6 @@
);
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/arduino_character_analysis/Makefile b/verilog/dv/arduino_character_analysis/Makefile
index b50000c..9c24fbb 100644
--- a/verilog/dv/arduino_character_analysis/Makefile
+++ b/verilog/dv/arduino_character_analysis/Makefile
@@ -29,7 +29,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
index b93e319..275b18b 100644
--- a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
+++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
@@ -75,32 +75,13 @@
`define TB_HEX "arduino_character_analysis.hex"
`define TB_TOP arduino_character_analysis_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+`include "user_tasks.sv"
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
//----------------------------------
// Uart Configuration
// ---------------------------------
@@ -123,7 +104,6 @@
reg [31:0] check_sum ;
- integer d_risc_id;
integer i,j;
@@ -155,18 +135,8 @@
- // 50Mhz CLock
- always #10 clock <= (clock === 1'b0);
-
initial begin
- clock = 0;
flag = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
@@ -227,7 +197,7 @@
$display("Monitor: Standalone User Risc Boot Test Started");
init();
- wait_riscv_boot(d_risc_id);
+ wait_riscv_boot();
// Remove Wb Reset
//wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
@@ -313,63 +283,21 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: character_analysis (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: character_analysis (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: character_analysis (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: character_analysis (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
assign io_in[5] = 1'b1; // RESET
assign io_in[21] = 1'b0; // CLOCK
@@ -449,136 +377,6 @@
);
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-`include "user_tasks.sv"
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/arduino_digital_port_control/Makefile b/verilog/dv/arduino_digital_port_control/Makefile
index 7d035ec..fbdcf71 100644
--- a/verilog/dv/arduino_digital_port_control/Makefile
+++ b/verilog/dv/arduino_digital_port_control/Makefile
@@ -29,7 +29,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
index edd4444..eaf97d5 100644
--- a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
+++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
@@ -74,33 +74,15 @@
`define TB_HEX "arduino_digital_port_control.hex"
`define TB_TOP arduino_digital_port_control_tb
module arduino_digital_port_control_tb;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
+`include "user_tasks.sv"
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
- reg flag ;
+reg flag ;
parameter P_FSM_C = 4'b0000; // Command Phase Only
parameter P_FSM_CW = 4'b0001; // Command + Write DATA Phase Only
@@ -129,7 +111,6 @@
parameter P_QDDR = 2'b11;
- integer d_risc_id;
integer channel,level;
integer i,j;
@@ -137,18 +118,8 @@
- // 50Mhz CLock
- always #10 clock <= (clock === 1'b0);
-
initial begin
- clock = 0;
- flag = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
+ flag = 0;
end
`ifdef WFDUMP
@@ -173,7 +144,7 @@
$display("Monitor: Standalone User Risc Boot Test Started");
init();
- wait_riscv_boot(d_risc_id);
+ wait_riscv_boot();
// Remove Wb Reset
//wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
@@ -238,15 +209,15 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Ardunio Digital Port Control (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Ardunio Digital Port Control (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Ardunio Digital Port Control (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Ardunio Digital Port Control (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
@@ -254,43 +225,6 @@
$finish;
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
assign io_in[5] = 1'b1; // RESET
@@ -378,136 +312,6 @@
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-`include "user_tasks.sv"
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/arduino_gpio_intr/Makefile b/verilog/dv/arduino_gpio_intr/Makefile
index 0912a65..ec277ae 100644
--- a/verilog/dv/arduino_gpio_intr/Makefile
+++ b/verilog/dv/arduino_gpio_intr/Makefile
@@ -29,7 +29,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
index 035faac..23e360e 100644
--- a/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
+++ b/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v
@@ -75,32 +75,14 @@
`define TB_TOP arduino_gpio_intr_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+parameter real CLK1_PERIOD = 20; // 50MHz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
+`include "user_tasks.sv"
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
//----------------------------------
// Uart Configuration
// ---------------------------------
@@ -123,26 +105,15 @@
reg [31:0] check_sum ;
- integer d_risc_id;
integer i,j;
- // 50Mhz CLock
- always #10 clock <= (clock === 1'b0);
-
initial begin
- clock = 0;
flag = 0;
compare_start = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
@@ -286,7 +257,7 @@
$value$plusargs("risc_core_id=%d", d_risc_id);
init();
- wait_riscv_boot(d_risc_id);
+ wait_riscv_boot();
#200; // Wait for reset removal
repeat (10) @(posedge clock);
@@ -387,58 +358,21 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone String (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone String (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone String (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone String (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
assign io_in[5] = 1'b1; // RESET
//assign io_in[21] = 1'b0; // CLOCK
@@ -458,14 +392,14 @@
wire flash_clk = io_out[28];
wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
assign io_in[33] = flash_io0;
assign io_in[34] = flash_io1;
@@ -518,142 +452,6 @@
);
-//----------------------------
-// All the task are defined here
-//----------------------------
-
-
-
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-`include "user_tasks.sv"
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/arduino_hello_world/Makefile b/verilog/dv/arduino_hello_world/Makefile
index 06f0645..ef9a591 100644
--- a/verilog/dv/arduino_hello_world/Makefile
+++ b/verilog/dv/arduino_hello_world/Makefile
@@ -29,7 +29,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
index 8fac63c..44b41db 100644
--- a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
+++ b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
@@ -75,32 +75,13 @@
`define TB_HEX "arduino_hello_world.hex"
`define TB_TOP arduino_hello_world_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+`include "user_tasks.sv"
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
//----------------------------------
// Uart Configuration
// ---------------------------------
@@ -120,25 +101,14 @@
reg uart_fifo_enable ; // fifo mode disable
reg flag ;
- integer d_risc_id;
integer i,j;
- // 50Mhz CLock
- always #10 clock <= (clock === 1'b0);
-
initial begin
- clock = 0;
flag = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
@@ -189,7 +159,7 @@
uart_parity_en = 0; // parity enable
uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
tb_set_uart_baud(50000000,230400,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
- uart_timeout = 2000;// wait time limit
+ uart_timeout = 500;// wait time limit
uart_fifo_enable = 0; // fifo mode disable
$value$plusargs("risc_core_id=%d", d_risc_id);
@@ -199,7 +169,7 @@
$display("Monitor: Standalone User Risc Boot Test Started");
init();
- wait_riscv_boot(d_risc_id);
+ wait_riscv_boot();
// Remove Wb Reset
//wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
@@ -220,12 +190,12 @@
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
end
- repeat (100) @(posedge clock); // wait for Processor Get Ready
tb_uart.uart_init;
tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
uart_stick_parity, uart_timeout, uart_divisor);
+ repeat (1000) @(posedge clock); // wait for Processor Get Ready
flag = 1;
@@ -267,63 +237,21 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone Hello World (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone Hello World (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone Hello World (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone Hello World (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
assign io_in[5] = 1'b1; // RESET
assign io_in[21] = 1'b0; // CLOCK
@@ -343,14 +271,14 @@
wire flash_clk = io_out[28];
wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
assign io_in[33] = flash_io0;
assign io_in[34] = flash_io1;
@@ -403,136 +331,6 @@
);
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-`include "user_tasks.sv"
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/arduino_i2c_scaner/Makefile b/verilog/dv/arduino_i2c_scaner/Makefile
index 06dc4bd..0c8a874 100644
--- a/verilog/dv/arduino_i2c_scaner/Makefile
+++ b/verilog/dv/arduino_i2c_scaner/Makefile
@@ -29,7 +29,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
@@ -105,24 +105,24 @@
rm *.o *.a
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
index 6cb6a4d..ace2a5b 100644
--- a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
+++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
@@ -75,32 +75,13 @@
`define TB_HEX "arduino_i2c_scaner.hex"
`define TB_TOP arduino_i2c_scaner_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+`include "user_tasks.sv"
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
//----------------------------------
// Uart Configuration
// ---------------------------------
@@ -123,26 +104,14 @@
reg [31:0] check_sum ;
- integer d_risc_id;
integer i,j;
-
- // 50Mhz CLock
- always #10 clock <= (clock === 1'b0);
-
initial begin
- clock = 0;
flag = 0;
compare_start = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
@@ -200,19 +169,20 @@
$value$plusargs("risc_core_id=%d", d_risc_id);
+ init();
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
// Remove Wb Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+ //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
repeat (2) @(posedge clock);
#1;
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
@@ -224,6 +194,7 @@
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
end
+ wait_riscv_boot();
repeat (100) @(posedge clock); // wait for Processor Get Ready
tb_uart.debug_mode = 0; // disable debug display
@@ -237,7 +208,7 @@
u_i2c_slave_3.debug = 0; // disable i2c bfm debug message
u_i2c_slave_4.debug = 0; // disable i2c bfm debug message
- repeat (45000) @(posedge clock); // wait for Processor Get Ready
+ repeat (1000) @(posedge clock); // wait for Processor Get Ready
flag = 0;
check_sum = 0;
compare_start = 1;
@@ -274,66 +245,23 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone i2c scanner (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone i2c scanner (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone i2c scanner (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone i2c scanner (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
-assign io_in[0] = 1'b1; // RESET
-assign io_in[16] = 1'b0 ; // SPIS SCK
+assign io_in[5] = 1'b1; // RESET
//---------------------------
// I2C
@@ -389,14 +317,14 @@
wire flash_clk = io_out[28];
wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
assign io_in[33] = flash_io0;
assign io_in[34] = flash_io1;
@@ -448,136 +376,6 @@
.rxd (uart_txd )
);
-
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/arduino_i2c_wr_rd/Makefile b/verilog/dv/arduino_i2c_wr_rd/Makefile
index b868513..2dc17d6 100644
--- a/verilog/dv/arduino_i2c_wr_rd/Makefile
+++ b/verilog/dv/arduino_i2c_wr_rd/Makefile
@@ -29,7 +29,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
@@ -105,24 +105,24 @@
rm *.o *.a
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
diff --git a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
index ee7124a..3c94c7d 100644
--- a/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
+++ b/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v
@@ -75,32 +75,13 @@
`define TB_HEX "arduino_i2c_wr_rd.hex"
`define TB_TOP arduino_i2c_wr_rd_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+`include "user_tasks.sv"
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
//----------------------------------
// Uart Configuration
// ---------------------------------
@@ -123,26 +104,14 @@
reg [31:0] check_sum ;
- integer d_risc_id;
integer i,j;
-
- // 50Mhz CLock
- always #10 clock <= (clock === 1'b0);
-
initial begin
- clock = 0;
flag = 0;
compare_start = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
@@ -200,19 +169,20 @@
$value$plusargs("risc_core_id=%d", d_risc_id);
+ init();
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
// Remove Wb Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+ //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
repeat (2) @(posedge clock);
#1;
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
@@ -224,6 +194,7 @@
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
end
+ wait_riscv_boot();
repeat (100) @(posedge clock); // wait for Processor Get Ready
tb_uart.debug_mode = 0; // disable debug display
@@ -234,7 +205,7 @@
u_i2c_slave_0.debug = 1; // disable i2c bfm debug message
u_i2c_slave_1.debug = 1; // disable i2c bfm debug message
- repeat (45000) @(posedge clock); // wait for Processor Get Ready
+ repeat (1000) @(posedge clock); // wait for Processor Get Ready
flag = 0;
check_sum = 0;
compare_start = 1;
@@ -271,63 +242,21 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone i2c scanner (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone i2c scanner (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone i2c scanner (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone i2c scanner (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
assign io_in[5] = 1'b1; // RESET
@@ -370,14 +299,14 @@
wire flash_clk = io_out[28];
wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
assign io_in[33] = flash_io0;
assign io_in[34] = flash_io1;
@@ -415,7 +344,6 @@
.io3 (flash_io3)
);
-//-------------------------------------
//---------------------------
// UART Agent integration
// --------------------------
@@ -430,136 +358,6 @@
.rxd (uart_txd )
);
-
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/arduino_multi_serial/Makefile b/verilog/dv/arduino_multi_serial/Makefile
index 2c7cd0d..42a61f3 100644
--- a/verilog/dv/arduino_multi_serial/Makefile
+++ b/verilog/dv/arduino_multi_serial/Makefile
@@ -29,7 +29,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
index 8a969ad..fc55f4c 100644
--- a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
+++ b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
@@ -71,37 +71,17 @@
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
`include "is62wvs1288.v"
`include "uart_agent.v"
-`include "user_params.svh"
`define TB_HEX "arduino_multi_serial.hex"
`define TB_TOP arduino_multi_serial_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+`include "user_tasks.sv"
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
//----------------------------------
// Uart Configuration
// ---------------------------------
@@ -124,27 +104,11 @@
reg [31:0] check_sum ;
- integer d_risc_id;
integer i,j,k,l;
-
- // 50Mhz CLock
- always #10 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- flag = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
-
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
@@ -188,19 +152,18 @@
initial begin
- uart_data_bit = 2'b11;
- uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
- uart_stick_parity = 0; // 1: force even parity
- uart_parity_en = 0; // parity enable
- uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
- tb_set_uart_baud(50000000,288000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
- uart_timeout = 2000;// wait time limit
- uart_fifo_enable = 0; // fifo mode disable
+ uart_data_bit = 2'b11;
+ uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
+ uart_stick_parity = 0; // 1: force even parity
+ uart_parity_en = 0; // parity enable
+ uart_even_odd_parity = 1; // 0: odd parity; 1: even parity
+ tb_set_uart_baud(50000000,288000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400
+ uart_timeout = 2000;// wait time limit
+ uart_fifo_enable = 0; // fifo mode disable
$value$plusargs("risc_core_id=%d", d_risc_id);
+ init();
- init();
- wait_riscv_boot(d_risc_id);
#200; // Wait for reset removal
repeat (10) @(posedge clock);
@@ -211,155 +174,114 @@
repeat (2) @(posedge clock);
#1;
- // Remove all the reset
- if(d_risc_id == 0) begin
- $display("STATUS: Working with Risc core 0");
- //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
- end else if(d_risc_id == 1) begin
- $display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
- end else if(d_risc_id == 2) begin
- $display("STATUS: Working with Risc core 2");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
- end else if(d_risc_id == 3) begin
- $display("STATUS: Working with Risc core 3");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
- end
+ // Remove all the reset
+ if(d_risc_id == 0) begin
+ $display("STATUS: Working with Risc core 0");
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ end else if(d_risc_id == 1) begin
+ $display("STATUS: Working with Risc core 1");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+ end else if(d_risc_id == 2) begin
+ $display("STATUS: Working with Risc core 2");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F);
+ end else if(d_risc_id == 3) begin
+ $display("STATUS: Working with Risc core 3");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
+ end
- repeat (100) @(posedge clock); // wait for Processor Get Ready
+ wait_riscv_boot();
- tb_uart0.debug_mode = 1; // enable debug display
- tb_uart0.uart_init;
- tb_uart0.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
+ repeat (100) @(posedge clock); // wait for Processor Get Ready
+
+ tb_uart0.debug_mode = 1; // enable debug display
+ tb_uart0.uart_init;
+ tb_uart0.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
uart_stick_parity, uart_timeout, uart_divisor);
- tb_uart1.debug_mode = 1; // enable debug display
- tb_uart1.uart_init;
- tb_uart1.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
+ tb_uart1.debug_mode = 1; // enable debug display
+ tb_uart1.uart_init;
+ tb_uart1.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
uart_stick_parity, uart_timeout, uart_divisor);
- repeat (5000) @(posedge clock); // wait for Processor Get Ready
- flag = 0;
- check_sum = 0;
+ repeat (10000) @(posedge clock); // wait for Processor Get Ready
+ flag = 0;
+ check_sum = 0;
- for (i=0; i<40; i=i+1)
- uart0_write_data[i] = $random;
+ for (i=0; i<40; i=i+1)
+ uart0_write_data[i] = $random;
- for (i=0; i<40; i=i+1)
- uart1_write_data[i] = $random;
+ for (i=0; i<40; i=i+1)
+ uart1_write_data[i] = $random;
- fork
- //Drive UART-0
- begin
- for (i=0; i<40; i=i+1)
- begin
- $display ("\n... UART-0 Agent Writing char %x ...", uart0_write_data[i]);
- tb_uart0.write_char (uart0_write_data[i]);
- end
- end
+ fork
+ //Drive UART-0
+ begin
+ for (i=0; i<40; i=i+1)
+ begin
+ $display ("\n... UART-0 Agent Writing char %x ...", uart0_write_data[i]);
+ tb_uart0.write_char (uart0_write_data[i]);
+ end
+ end
- //Drive UART-1
- begin
- for (j=0; j<40; j=j+1)
- begin
- $display ("\n... UART-1 Agent Writing char %x ...", uart1_write_data[j]);
- tb_uart1.write_char (uart1_write_data[j]);
- end
- end
+ //Drive UART-1
+ begin
+ for (j=0; j<40; j=j+1)
+ begin
+ $display ("\n... UART-1 Agent Writing char %x ...", uart1_write_data[j]);
+ tb_uart1.write_char (uart1_write_data[j]);
+ end
+ end
- //Receive UART-0
- begin
- for (k=0; k<40; k=k+1)
- begin
- tb_uart0.read_char_chk(uart1_write_data[k]);
- end
- end
+ //Receive UART-0
+ begin
+ for (k=0; k<40; k=k+1)
+ begin
+ tb_uart0.read_char_chk(uart1_write_data[k]);
+ end
+ end
- //Receive UART-1
- begin
- for (l=0; l<40; l=l+1)
- begin
- tb_uart1.read_char_chk(uart0_write_data[l]);
- end
- end
- join
+ //Receive UART-1
+ begin
+ for (l=0; l<40; l=l+1)
+ begin
+ tb_uart1.read_char_chk(uart0_write_data[l]);
+ end
+ end
+ join
- test_fail = 0;
- #100
- tb_uart0.report_status(uart_rx_nu, uart_tx_nu);
- if(uart_tx_nu != 40) test_fail = 1;
- if(uart_rx_nu != 40) test_fail = 1;
+ test_fail = 0;
+ #100
+ tb_uart0.report_status(uart_rx_nu, uart_tx_nu);
+ if(uart_tx_nu != 40) test_fail = 1;
+ if(uart_rx_nu != 40) test_fail = 1;
- tb_uart1.report_status(uart_rx_nu, uart_tx_nu);
- if(uart_tx_nu != 40) test_fail = 1;
- if(uart_rx_nu != 40) test_fail = 1;
+ tb_uart1.report_status(uart_rx_nu, uart_tx_nu);
+ if(uart_tx_nu != 40) test_fail = 1;
+ if(uart_rx_nu != 40) test_fail = 1;
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone Multi Serial (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone Multi Serial (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone Multi Serial (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone Multi Serial (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
assign io_in[5] = 1'b1; // RESET
assign io_in[21] = 1'b0 ; // SPIS SCK
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
- end
-`endif
//------------------------------------------------------
// Integrate the Serial flash with qurd support to
@@ -369,14 +291,14 @@
wire flash_clk = io_out[28];
wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
assign io_in[33] = flash_io0;
assign io_in[34] = flash_io1;
@@ -441,136 +363,6 @@
.rxd (uart1_txd )
);
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-`include "user_tasks.sv"
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/arduino_risc_boot/Makefile b/verilog/dv/arduino_risc_boot/Makefile
index 68dd9fc..7437a10 100644
--- a/verilog/dv/arduino_risc_boot/Makefile
+++ b/verilog/dv/arduino_risc_boot/Makefile
@@ -29,7 +29,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
@@ -104,24 +104,24 @@
rm *.o *.a
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
diff --git a/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp b/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp
index c663a26..9ee2dfb 100644
--- a/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp
+++ b/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp
@@ -1,31 +1,16 @@
#include <Arduino.h>
#define uint32_t long
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel
-#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0
-#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1
-#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2
-#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3
-#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
-#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
-
-
-
void setup();
void loop();
void setup() {
// put your setup code here, to run once:
- reg_mprj_globl_soft0 = 0x11223344;
- reg_mprj_globl_soft1 = 0x22334455;
- reg_mprj_globl_soft2 = 0x33445566;
- reg_mprj_globl_soft3 = 0x44556677;
- reg_mprj_globl_soft4 = 0x55667788;
- reg_mprj_globl_soft5 = 0x66778899;
+ GLBL_REG(GLBL_SOFT_REG0) = 0x11223344;
+ GLBL_REG(GLBL_SOFT_REG1) = 0x22334455;
+ GLBL_REG(GLBL_SOFT_REG2) = 0x33445566;
+ GLBL_REG(GLBL_SOFT_REG3) = 0x44556677;
+ GLBL_REG(GLBL_SOFT_REG4) = 0x55667788;
+ GLBL_REG(GLBL_SOFT_REG5) = 0x66778899;
}
diff --git a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
index eb4d0d0..c4b21ff 100644
--- a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
+++ b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
@@ -73,52 +73,15 @@
`define TB_TOP arduino_risc_boot_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20;
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
-
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
- integer d_risc_id;
+`include "user_tasks.sv"
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
-
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
@@ -130,43 +93,42 @@
$value$plusargs("risc_core_id=%d", d_risc_id);
+ init();
+
#200; // Wait for reset removal
- repeat (10) @(posedge clock);
+ repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
// Remove Wb Reset
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
- repeat (2) @(posedge clock);
+ repeat (2) @(posedge clock);
#1;
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
end
+ wait_riscv_boot();
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (40) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
+ repeat (10000) @(posedge clock); // wait for Processor Get Ready
$display("Monitor: Reading Back the expected value");
// User RISC core expect to write these value in global
// register, read back and decide on pass fail
// 0x30000018 = 0x11223344;
- // 0x3000001C = 0x22334455;
- // 0x30000020 = 0x33445566;
- // 0x30000024 = 0x44556677;
- // 0x30000028 = 0x55667788;
- // 0x3000002C = 0x66778899;
+ // 0x3000001C = 0x22334455;
+ // 0x30000020 = 0x33445566;
+ // 0x30000024 = 0x44556677;
+ // 0x30000028 = 0x55667788;
+ // 0x3000002C = 0x66778899;
- test_fail = 0;
+ test_fail = 0;
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
@@ -179,63 +141,21 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
assign io_in[0] = 1'b1; // RESET
assign io_in[16] = 1'b0 ; // SPIS SCK
@@ -303,137 +223,6 @@
//-------------------------------------
-
-
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/arduino_string/Makefile b/verilog/dv/arduino_string/Makefile
index bf750df..a0279dd 100644
--- a/verilog/dv/arduino_string/Makefile
+++ b/verilog/dv/arduino_string/Makefile
@@ -29,7 +29,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
@@ -104,24 +104,24 @@
rm *.o *.a
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
diff --git a/verilog/dv/arduino_string/arduino_string_tb.v b/verilog/dv/arduino_string/arduino_string_tb.v
index f57b93f..a02727a 100644
--- a/verilog/dv/arduino_string/arduino_string_tb.v
+++ b/verilog/dv/arduino_string/arduino_string_tb.v
@@ -74,32 +74,13 @@
`define TB_HEX "arduino_string.hex"
`define TB_TOP arduino_string_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+`include "user_tasks.sv"
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
//----------------------------------
// Uart Configuration
// ---------------------------------
@@ -122,26 +103,15 @@
reg [31:0] check_sum ;
- integer d_risc_id;
integer i,j;
- // 50Mhz CLock
- always #10 clock <= (clock === 1'b0);
-
initial begin
- clock = 0;
flag = 0;
compare_start = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
@@ -196,20 +166,21 @@
uart_fifo_enable = 0; // fifo mode disable
$value$plusargs("risc_core_id=%d", d_risc_id);
+ init();
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
// Remove Wb Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+ //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
repeat (2) @(posedge clock);
#1;
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
@@ -221,6 +192,7 @@
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
end
+ wait_riscv_boot();
repeat (100) @(posedge clock); // wait for Processor Get Ready
tb_uart.debug_mode = 0; // disable debug display
@@ -228,7 +200,7 @@
tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
uart_stick_parity, uart_timeout, uart_divisor);
- repeat (60000) @(posedge clock); // wait for Processor Get Ready
+ repeat (20000) @(posedge clock); // wait for Processor Get Ready
flag = 0;
check_sum = 0;
compare_start = 1;
@@ -266,73 +238,23 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone String (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone String (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone String (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone String (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
-
// SSPI Slave I/F
-assign io_in[0] = 1'b1; // RESET
-
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
- end
-`endif
+assign io_in[5] = 1'b1; // RESET
//------------------------------------------------------
// Integrate the Serial flash with qurd support to
@@ -342,14 +264,14 @@
wire flash_clk = io_out[28];
wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
assign io_in[33] = flash_io0;
assign io_in[34] = flash_io1;
@@ -402,135 +324,6 @@
);
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/arduino_switchCase2/Makefile b/verilog/dv/arduino_switchCase2/Makefile
index 6470aef..0263e17 100644
--- a/verilog/dv/arduino_switchCase2/Makefile
+++ b/verilog/dv/arduino_switchCase2/Makefile
@@ -29,7 +29,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
@@ -104,24 +104,24 @@
rm *.o *.a
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
diff --git a/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
index 8a3a7d8..3432fca 100644
--- a/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
+++ b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
@@ -73,32 +73,15 @@
`define TB_HEX "arduino_switchCase2.hex"
`define TB_TOP arduino_switchCase2_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+`include "user_tasks.sv"
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
//----------------------------------
// Uart Configuration
// ---------------------------------
@@ -120,7 +103,6 @@
reg [31:0] check_sum ;
- integer d_risc_id;
integer i,j;
@@ -152,18 +134,9 @@
- // 50Mhz CLock
- always #10 clock <= (clock === 1'b0);
initial begin
- clock = 0;
flag = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
@@ -239,29 +212,30 @@
uart_fifo_enable = 0; // fifo mode disable
$value$plusargs("risc_core_id=%d", d_risc_id);
+ init();
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
// Remove Wb Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+ //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
repeat (2) @(posedge clock);
#1;
// Remove WB and SPI Reset, Keep SDARM and CORE under Reset
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
- // QSPI SRAM:CS#2 Switch to QSPI Mode
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
- wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
- wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
- wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
+ //// QSPI SRAM:CS#2 Switch to QSPI Mode
+ ////wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000
+ //wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100});
+ //wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38});
+ //wb_user_core_write(`ADDR_SPACE_QSPI+`QSPIM_IMEM_WDATA,32'h0);
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
@@ -273,6 +247,8 @@
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
end
+ wait_riscv_boot();
+
repeat (100) @(posedge clock); // wait for Processor Get Ready
tb_uart.debug_mode = 0; // disable debug display
@@ -280,7 +256,7 @@
tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
uart_stick_parity, uart_timeout, uart_divisor);
- repeat (45000) @(posedge clock); // wait for Processor Get Ready
+ repeat (10000) @(posedge clock); // wait for Processor Get Ready
flag = 1;
check_sum = 0;
fork
@@ -322,73 +298,26 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: arduino_switchCase2 (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: arduino_switchCase2 (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: arduino_switchCase2 (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: arduino_switchCase2 (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
-assign io_in[0] = 1'b1; // RESET
-assign io_in[16] = 1'b0 ; // SPIS SCK
+assign io_in[5] = 1'b1; // RESET
+assign io_in[21] = 1'b0 ; // SPIS SCK
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
- end
-`endif
//------------------------------------------------------
// Integrate the Serial flash with qurd support to
@@ -398,14 +327,14 @@
wire flash_clk = io_out[28];
wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
assign io_in[33] = flash_io0;
assign io_in[34] = flash_io1;
@@ -456,136 +385,6 @@
.rxd (uart_txd )
);
-
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/arduino_timer_intr/Makefile b/verilog/dv/arduino_timer_intr/Makefile
index 4a23ffa..aec2931 100644
--- a/verilog/dv/arduino_timer_intr/Makefile
+++ b/verilog/dv/arduino_timer_intr/Makefile
@@ -29,7 +29,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
@@ -108,24 +108,24 @@
rm *.o *.a
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
diff --git a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
index 4107a97..ace0ce7 100644
--- a/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
+++ b/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v
@@ -74,32 +74,13 @@
`define TB_TOP arduino_timer_intr_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20;
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+`include "user_tasks.sv"
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
//----------------------------------
// Uart Configuration
// ---------------------------------
@@ -122,26 +103,14 @@
reg [31:0] check_sum ;
- integer d_risc_id;
integer i,j;
-
- // 50Mhz CLock
- always #10 clock <= (clock === 1'b0);
-
initial begin
- clock = 0;
flag = 0;
compare_start = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
@@ -204,19 +173,22 @@
$value$plusargs("risc_core_id=%d", d_risc_id);
+ init();
+
+
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
// Remove Wb Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+ //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
repeat (2) @(posedge clock);
#1;
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
@@ -228,6 +200,7 @@
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
end
+ wait_riscv_boot();
repeat (100) @(posedge clock); // wait for Processor Get Ready
tb_uart.debug_mode = 0; // disable debug display
@@ -235,7 +208,7 @@
tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity,
uart_stick_parity, uart_timeout, uart_divisor);
- repeat (55000) @(posedge clock); // wait for Processor Get Ready
+ repeat (1000) @(posedge clock); // wait for Processor Get Ready
flag = 0;
check_sum = 0;
compare_start = 1;
@@ -253,7 +226,7 @@
end
end
begin
- repeat (510000) @(posedge clock); // wait for Processor Get Ready
+ repeat (600000) @(posedge clock); // wait for Processor Get Ready
end
join_any
@@ -274,63 +247,21 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone String (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone String (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone String (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone String (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
assign io_in[5] = 1'b1; // RESET
//assign io_in[16] = 1'b0 ; // SPIS SCK
@@ -350,14 +281,14 @@
wire flash_clk = io_out[28];
wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
assign io_in[33] = flash_io0;
assign io_in[34] = flash_io1;
@@ -409,141 +340,7 @@
);
-//----------------------------
-// All the task are defined here
-//----------------------------
-
-
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/arduino_ws281x/Makefile b/verilog/dv/arduino_ws281x/Makefile
index 0a22bf8..7d2330e 100644
--- a/verilog/dv/arduino_ws281x/Makefile
+++ b/verilog/dv/arduino_ws281x/Makefile
@@ -29,7 +29,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
export RISCDUINO_BOARD ?= $(USER_PROJECT_VERILOG)/dv/common/riscduino_board/custom_board/riscduino
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
@@ -108,24 +108,24 @@
rm *.o *.a
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
diff --git a/verilog/dv/arduino_ws281x/arduino_ws281x.ino.cpp b/verilog/dv/arduino_ws281x/arduino_ws281x.ino.cpp
index db5dc4a..a2e3dbf 100644
--- a/verilog/dv/arduino_ws281x/arduino_ws281x.ino.cpp
+++ b/verilog/dv/arduino_ws281x/arduino_ws281x.ino.cpp
@@ -36,7 +36,11 @@
#include"WS281X.h"
// These constants won't change. They're used to give names to the pins used:
-
+//-------------------
+// We have only 2 WS281X port
+// Port 2 will using port-0 data
+// Port 3 will using port-1 data
+//------------------------
int port0 = 2;
int port1 = 3;
int port2 = 5;
@@ -51,6 +55,7 @@
// Enable WS_281X PORT-0
ws281x.enable(port0);
+ ws281x.enable(port2);
ws281x.write(port0, 0x112233);
ws281x.write(port0, 0x223344);
ws281x.write(port0, 0x334455);
@@ -70,6 +75,7 @@
// Enable WS_281X PORT-1
ws281x.enable(port1);
+ ws281x.enable(port3);
ws281x.write(port1, 0x010203);
ws281x.write(port1, 0x020304);
ws281x.write(port1, 0x030405);
@@ -87,43 +93,6 @@
ws281x.write(port1, 0x0F0001);
ws281x.write(port1, 0x000102);
-// Enable WS_281X PORT-2
- ws281x.enable(port2);
- ws281x.write(port2, 0x102030);
- ws281x.write(port2, 0x203040);
- ws281x.write(port2, 0x304050);
- ws281x.write(port2, 0x405060);
- ws281x.write(port2, 0x506070);
- ws281x.write(port2, 0x607080);
- ws281x.write(port2, 0x708090);
- ws281x.write(port2, 0x8090A0);
- ws281x.write(port2, 0x90A0B0);
- ws281x.write(port2, 0xA0B0C0);
- ws281x.write(port2, 0xB0C0D0);
- ws281x.write(port2, 0xC0D0E0);
- ws281x.write(port2, 0xD0E0F0);
- ws281x.write(port2, 0xE0F000);
- ws281x.write(port2, 0xF00010);
- ws281x.write(port2, 0x001020);
-
-// Enable WS_281X PORT-3
- ws281x.enable(port3);
- ws281x.write(port3, 0x012345);
- ws281x.write(port3, 0x123456);
- ws281x.write(port3, 0x234567);
- ws281x.write(port3, 0x345678);
- ws281x.write(port3, 0x456789);
- ws281x.write(port3, 0x56789A);
- ws281x.write(port3, 0x6789AB);
- ws281x.write(port3, 0x789ABC);
- ws281x.write(port3, 0x89ABCD);
- ws281x.write(port3, 0x9ABCDE);
- ws281x.write(port3, 0xABCDEF);
- ws281x.write(port3, 0xBCDEF0);
- ws281x.write(port3, 0xCDEF01);
- ws281x.write(port3, 0xDEF012);
- ws281x.write(port3, 0xEF0123);
- ws281x.write(port3, 0xF01234);
}
void loop() {
diff --git a/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v b/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v
index a6cc886..43929a1 100644
--- a/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v
+++ b/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v
@@ -75,39 +75,19 @@
`define TB_TOP arduino_ws281x_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+`include "user_tasks.sv"
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
reg flag ;
reg compare_start ; // User Need to make sure that compare start match with RiscV core completing initial booting
reg [31:0] rx_wcnt ;
reg [31:0] check_sum ;
- integer d_risc_id;
integer i,j;
@@ -167,14 +147,14 @@
* Pin-8 GND -
* Pin-9 20 PB6/WS[1]/XTAL1/TOSC1 digital_io[11]
* Pin-10 21 PB7/WS[1]/XTAL2/TOSC2 digital_io[12]
-* Pin-11 5 PD5/WS[2]/SS[3]/OC0B(PWM1)/T1 digital_io[13]
-* Pin-12 6 PD6/WS[2]/SS[2]/OC0A(PWM2)/AIN0 digital_io[14]/analog_io[2]
-* Pin-13 7 PD7/WS[2]/A1N1 digital_io[15]/analog_io[3]
-* Pin-14 8 PB0/WS[2]/CLKO/ICP1 digital_io[16]
-* Pin-15 9 PB1/WS[3]/SS[1]OC1A(PWM3) digital_io[17]
-* Pin-16 10 PB2/WS[3]/SS[0]/OC1B(PWM4) digital_io[18]
-* Pin-17 11 PB3/WS[3]/MOSI/OC2A(PWM5) digital_io[19]
-* Pin-18 12 PB4/WS[3]/MISO digital_io[20]
+* Pin-11 5 PD5/WS[0]/SS[3]/OC0B(PWM1)/T1 digital_io[13]
+* Pin-12 6 PD6/WS[0]/SS[2]/OC0A(PWM2)/AIN0 digital_io[14]/analog_io[2]
+* Pin-13 7 PD7/WS[0]/A1N1 digital_io[15]/analog_io[3]
+* Pin-14 8 PB0/WS[0]/CLKO/ICP1 digital_io[16]
+* Pin-15 9 PB1/WS[1]/SS[1]OC1A(PWM3) digital_io[17]
+* Pin-16 10 PB2/WS[1]/SS[0]/OC1B(PWM4) digital_io[18]
+* Pin-17 11 PB3/WS[1]/MOSI/OC2A(PWM5) digital_io[19]
+* Pin-18 12 PB4/WS[1]/MISO digital_io[20]
* Pin-19 13 PB5/SCK digital_io[21]
* Pin-20 AVCC -
* Pin-21 AREF analog_io[10]
@@ -193,20 +173,22 @@
ws281x_enb = 0;
$value$plusargs("risc_core_id=%d", d_risc_id);
+ init();
+
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
// Remove Wb Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+ //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
repeat (2) @(posedge clock);
#1;
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
@@ -218,10 +200,11 @@
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F);
end
+ wait_riscv_boot();
repeat (100) @(posedge clock); // wait for Processor Get Ready
- repeat (40000) @(posedge clock); // wait for Processor Get Ready
+ repeat (1000) @(posedge clock); // wait for Processor Get Ready
ws281x_enb = 1;
flag = 0;
check_sum = 0;
@@ -250,71 +233,29 @@
// if all the 102 byte received
// if no error
if(rx_wcnt != 64) test_fail = 1;
- if(check_sum != 32'h2ffe8) test_fail = 1;
+ if(check_sum != 32'h2f0e0) test_fail = 1;
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone String (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone String (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone String (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone String (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
-assign io_in[0] = 1'b1; // RESET
+assign io_in[5] = 1'b1; // RESET
//assign io_in[16] = 1'b0 ; // SPIS SCK
`ifndef GL // Drive Power for Hold Fix Buf
@@ -332,14 +273,14 @@
wire flash_clk = io_out[28];
wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
assign io_in[33] = flash_io0;
assign io_in[34] = flash_io1;
@@ -432,141 +373,6 @@
.enb (ws281x_enb ),
.rxd (ws281x_port[3])
);
-//----------------------------
-// All the task are defined here
-//----------------------------
-
-
-
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/c_func/inc/pwm.h b/verilog/dv/c_func/inc/pwm.h
deleted file mode 100644
index 580a9a8..0000000
--- a/verilog/dv/c_func/inc/pwm.h
+++ /dev/null
@@ -1,8 +0,0 @@
-
-void InitTimers ();
-void InitTimersSafe (); //doesn't init timers responsible for time keeping functions
-void pwmWrite (uint8_t pin, uint8_t val);
-void pwmWriteHR (uint8_t pin, uint16_t val); //accepts a 16 bit value and maps it down to the timer for maximum resolution
-bool SetPinFrequency (int8_t pin, uint32_t frequency);
-bool SetPinFrequencySafe(int8_t pin, uint32_t frequency); //does not set timers responsible for time keeping functions
-float GetPinResolution(uint8_t pin); //gets the PWM resolution of a pin in base 2, 0 is returned if the pin is not connected to a timer
diff --git a/verilog/dv/agents/caravel_task.sv b/verilog/dv/common/agents/caravel_task.sv
similarity index 97%
rename from verilog/dv/agents/caravel_task.sv
rename to verilog/dv/common/agents/caravel_task.sv
index 8ce81ef..83a9c70 100644
--- a/verilog/dv/agents/caravel_task.sv
+++ b/verilog/dv/common/agents/caravel_task.sv
@@ -38,9 +38,9 @@
begin
// Run in Fast Sim Mode
`ifdef GL
- force u_top.mprj.u_wb_host._8654_.Q= 1'b1;
+ force u_top.mprj.u_wb_host.u_reg._8654_.Q= 1'b1;
`else
- force u_top.mprj.u_wb_host.u_fastsim_buf.X = 1'b1;
+ force u_top.mprj.u_wb_host.u_reg.u_fastsim_buf.X = 1'b1;
`endif
end
diff --git a/verilog/dv/agents/test_control.v b/verilog/dv/common/agents/test_control.v
similarity index 100%
rename from verilog/dv/agents/test_control.v
rename to verilog/dv/common/agents/test_control.v
diff --git a/verilog/dv/agents/uart_agent.v b/verilog/dv/common/agents/uart_agent.v
similarity index 100%
rename from verilog/dv/agents/uart_agent.v
rename to verilog/dv/common/agents/uart_agent.v
diff --git a/verilog/dv/agents/uart_master_tasks.sv b/verilog/dv/common/agents/uart_master_tasks.sv
similarity index 100%
rename from verilog/dv/agents/uart_master_tasks.sv
rename to verilog/dv/common/agents/uart_master_tasks.sv
diff --git a/verilog/dv/agents/usb_agents.v b/verilog/dv/common/agents/usb_agents.v
similarity index 100%
rename from verilog/dv/agents/usb_agents.v
rename to verilog/dv/common/agents/usb_agents.v
diff --git a/verilog/dv/common/agents/user_tasks.sv b/verilog/dv/common/agents/user_tasks.sv
new file mode 100644
index 0000000..8365b6b
--- /dev/null
+++ b/verilog/dv/common/agents/user_tasks.sv
@@ -0,0 +1,444 @@
+
+/***********************************************
+
+wire [15:0] strap_in;
+assign strap_in[`PSTRAP_CLK_SRC] = 2'b00; // System Clock Source wbs/riscv: User clock1
+assign strap_in[`PSTRAP_CLK_DIV] = 2'b00; // Clock Division for wbs/riscv : 0 Div
+assign strap_in[`PSTRAP_UARTM_CFG] = 2'b0; // uart master config control - constant value based on system clock selection
+assign strap_in[`PSTRAP_QSPI_SRAM] = 1'b1; // QSPI SRAM Mode Selection - Quad
+assign strap_in[`PSTRAP_QSPI_FLASH] = 2'b10; // QSPI Fash Mode Selection - Quad
+assign strap_in[`PSTRAP_RISCV_RESET_MODE] = 1'b1; // Riscv Reset control - Removed Riscv on Power On Reset
+assign strap_in[`PSTRAP_RISCV_CACHE_BYPASS] = 1'b0; // Riscv Cache Bypass: 0 - Cache Enable
+assign strap_in[`PSTRAP_RISCV_SRAM_CLK_EDGE] = 1'b0; // Riscv SRAM clock edge selection: 0 - Normal
+assign strap_in[`PSTRAP_CLK_SKEW] = 2'b00; // Skew selection 2'b00 - Default value
+
+assign strap_in[`PSTRAP_DEFAULT_VALUE] = 1'b0; // 0 - Normal
+parameter bit [15:0] PAD_STRAP = (2'b00 << `PSTRAP_CLK_SRC ) |
+ (2'b00 << `PSTRAP_CLK_DIV ) |
+ (1'b1 << `PSTRAP_UARTM_CFG ) |
+ (1'b1 << `PSTRAP_QSPI_SRAM ) |
+ (2'b10 << `PSTRAP_QSPI_FLASH ) |
+ (1'b1 << `PSTRAP_RISCV_RESET_MODE ) |
+ (1'b1 << `PSTRAP_RISCV_CACHE_BYPASS ) |
+ (1'b1 << `PSTRAP_RISCV_SRAM_CLK_EDGE ) |
+ (2'b00 << `PSTRAP_CLK_SKEW ) |
+ (1'b0 << `PSTRAP_DEFAULT_VALUE ) ;
+****/
+
+//--------------------------------------------------------
+// Pad Pull-up/down initialization based on Boot Mode
+//---------------------------------------------------------
+
+`ifdef RISC_BOOT // RISCV Based Test case
+parameter bit [15:0] PAD_STRAP = 16'b0000_0001_1010_0000;
+`else
+parameter bit [15:0] PAD_STRAP = 16'b0000_0000_1010_0000;
+`endif
+
+//-------------------------------------------------------------
+// Variable Decleration
+//-------------------------------------------------------------
+
+reg clock ;
+reg clock2 ;
+reg xtal_clk ;
+reg wb_rst_i ;
+
+reg power1, power2;
+reg power3, power4;
+
+// Wishbone Interface
+reg wbd_ext_cyc_i ; // strobe/request
+reg wbd_ext_stb_i ; // strobe/request
+reg [31:0] wbd_ext_adr_i ; // address
+reg wbd_ext_we_i ; // write
+reg [31:0] wbd_ext_dat_i ; // data output
+reg [3:0] wbd_ext_sel_i ; // byte enable
+
+wire [31:0] wbd_ext_dat_o ; // data input
+wire wbd_ext_ack_o ; // acknowlegement
+wire wbd_ext_err_o ; // error
+
+// User I/O
+wire [37:0] io_oeb ;
+wire [37:0] io_out ;
+wire [37:0] io_in ;
+reg [127:0] la_data_in;
+
+reg test_fail ;
+reg [31:0] write_data ;
+reg [31:0] read_data ;
+integer d_risc_id;
+
+
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+//-----------------------------------------
+// Clock Decleration
+//-----------------------------------------
+
+always #(CLK1_PERIOD/2) clock <= (clock === 1'b0);
+always #(CLK2_PERIOD/2) clock2 <= (clock2 === 1'b0);
+always #(XTAL_PERIOD/2) xtal_clk <= (xtal_clk === 1'b0);
+
+
+//-----------------------------------------
+// Variable Initiatlization
+//-----------------------------------------
+initial
+begin
+ // Run in Fast Sim Mode
+ `ifdef GL
+ force u_top.u_wb_host.u_reg._8654_.Q= 1'b1;
+ `else
+ force u_top.u_wb_host.u_reg.u_fastsim_buf.X = 1'b1;
+ `endif
+
+ clock = 0;
+ clock2 = 0;
+ xtal_clk = 0;
+ test_fail = 0;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ la_data_in = 1;
+end
+//-----------------------------------------
+// DUT Instatiation
+//-----------------------------------------
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+ .vccd1(USER_VDD1V8), // User area 1 1.8V supply
+ .vssd1(VSS), // User area 1 digital ground
+`endif
+ .wb_clk_i (clock), // System clock
+ .user_clock2 (clock2), // Real-time clock
+ .wb_rst_i (wb_rst_i), // Regular Reset signal
+
+ .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
+ .wbs_stb_i (wbd_ext_stb_i), // strobe/request
+ .wbs_adr_i (wbd_ext_adr_i), // address
+ .wbs_we_i (wbd_ext_we_i), // write
+ .wbs_dat_i (wbd_ext_dat_i), // data output
+ .wbs_sel_i (wbd_ext_sel_i), // byte enable
+
+ .wbs_dat_o (wbd_ext_dat_o), // data input
+ .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
+
+
+ // Logic Analyzer Signals
+ .la_data_in (la_data_in) ,
+ .la_data_out (),
+ .la_oenb ('0),
+
+
+ // IOs
+ .io_in (io_in ) ,
+ .io_out (io_out) ,
+ .io_oeb (io_oeb) ,
+
+ .user_irq ()
+
+);
+
+//--------------------------------------------------------
+// Apply Reset Sequence and wait for reset completion
+//-------------------------------------------------------
+
+task init;
+begin
+ //#1 - Apply Reset
+ #1000 wb_rst_i = 0;
+ repeat (10) @(posedge clock);
+ #1000 wb_rst_i = 1;
+
+ //#3 - Remove Reset
+ #1000 wb_rst_i = 0;
+ repeat (10) @(posedge clock);
+ //#4 - Wait for Power on reset removal
+ wait(u_top.p_reset_n == 1);
+
+ // #5 - Wait for system reset removal
+ wait(u_top.s_reset_n == 1); // Wait for system reset removal
+ repeat (10) @(posedge clock);
+
+ end
+endtask
+
+//-----------------------------------------------
+// Apply user defined strap at power-on
+//-----------------------------------------------
+
+task apply_strap;
+input [15:0] strap;
+begin
+
+ repeat (10) @(posedge clock);
+ //#1 - Apply Reset
+ wb_rst_i = 1;
+ //#2 - Apply Strap
+ force u_top.io_in[36:29] = strap[15:8];
+ force u_top.io_in[20:13] = strap[7:0];
+ repeat (10) @(posedge clock);
+
+ //#3 - Remove Reset
+ wb_rst_i = 0; // Remove Reset
+
+ //#4 - Wait for Power on reset removal
+ wait(u_top.p_reset_n == 1);
+
+ // #5 - Release the Strap
+ release u_top.io_in[36:29];
+ release u_top.io_in[20:13];
+
+ // #6 - Wait for system reset removal
+ wait(u_top.s_reset_n == 1); // Wait for system reset removal
+ repeat (10) @(posedge clock);
+
+end
+endtask
+
+//---------------------------------------------------------
+// Create Pull Up/Down Based on Reset Strap Parameter
+//---------------------------------------------------------
+genvar gCnt;
+generate
+ for(gCnt=0; gCnt<16; gCnt++) begin : g_strap
+ if(gCnt < 8) begin
+ if(PAD_STRAP[gCnt]) begin
+ pullup(io_in[13+gCnt]);
+ end else begin
+ pulldown(io_in[13+gCnt]);
+ end
+ end else begin
+ if(PAD_STRAP[gCnt]) begin
+ pullup(io_in[29+gCnt-8]);
+ end else begin
+ pulldown(io_in[29+gCnt-8]);
+ end
+ end
+ end
+endgenerate
+
+`ifdef RISC_BOOT // RISCV Based Test case
+//-------------------------------------------
+task wait_riscv_boot;
+begin
+ // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
+ // bit[7:0] - core-0
+ // bit[15:8] - core-1
+ // bit[23:16] - core-2
+ // bit[31:24] - core-3
+ $display("Status: Waiting for RISCV Core Boot ... ");
+ read_data = 0;
+ //while((read_data >> (d_risc_id*8)) != 8'h1) begin
+ while(read_data != 8'h1) begin // Temp fix - Hardcoded to risc_id = 0
+ wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_CFG_MAIL_BOX,read_data);
+ repeat (100) @(posedge clock);
+ end
+
+ $display("Status: RISCV Core is Booted ");
+
+end
+endtask
+
+task wait_riscv_exit;
+begin
+ // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
+ // bit[7:0] - core-0
+ // bit[15:8] - core-1
+ // bit[23:16] - core-2
+ // bit[31:24] - core-3
+ $display("Status: Waiting for RISCV Core Boot ... ");
+ read_data = 0;
+ //while((read_data >> (d_risc_id*8)) != 8'hFF) begin
+ while(read_data != 8'hFF) begin
+ wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_CFG_MAIL_BOX,read_data);
+ repeat (1000) @(posedge clock);
+ end
+
+ $display("Status: RISCV Core is Booted ");
+
+end
+endtask
+
+//-----------------------
+// Set TB ready indication
+//-----------------------
+task set_tb_ready;
+begin
+ // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
+ // bit[7:0] - core-0
+ // bit[15:8] - core-1
+ // bit[23:16] - core-2
+ // bit[31:24] - core-3
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MAIL_BOX,32'h81818181);
+
+ $display("Status: Set TB Ready Indication");
+
+end
+endtask
+
+`endif
+
+//-------------------------------
+// Wishbone Write
+//-------------------------------
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h1; // write
+ wbd_ext_dat_i =data; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+
+//--------------------------------------
+// Wishbone Read
+//--------------------------------------
+task wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+ repeat (2) @(posedge clock);
+end
+endtask
+
+
+//--------------------------------------
+// Wishbone Read and compare
+//--------------------------------------
+task wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ if(data !== cmp_data) begin
+ $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+ test_fail = 1;
+ end else begin
+ $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
+ end
+ repeat (2) @(posedge clock);
+end
+endtask
+
+
+task wb_user_core_read_cmp;
+input [31:0] address;
+input [31:0] cmp_data;
+reg [31:0] data;
+begin
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_adr_i =address; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='0; // data output
+ wbd_ext_sel_i ='hF; // byte enable
+ wbd_ext_cyc_i ='h1; // strobe/request
+ wbd_ext_stb_i ='h1; // strobe/request
+ wait(wbd_ext_ack_o == 1);
+ repeat (1) @(negedge clock);
+ data = wbd_ext_dat_o;
+ repeat (1) @(posedge clock);
+ #1;
+ wbd_ext_cyc_i ='h0; // strobe/request
+ wbd_ext_stb_i ='h0; // strobe/request
+ wbd_ext_adr_i ='h0; // address
+ wbd_ext_we_i ='h0; // write
+ wbd_ext_dat_i ='h0; // data output
+ wbd_ext_sel_i ='h0; // byte enable
+ if(data !== cmp_data) begin
+ $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+ test_fail = 1;
+ end else begin
+ $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
+ end
+ repeat (2) @(posedge clock);
+end
+endtask
+
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+ if(`RISC_CORE.wbd_imem_ack_i)
+ $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+ if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+ if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+
diff --git a/verilog/dv/bfm/bfm_ad5205.sv b/verilog/dv/common/bfm/bfm_ad5205.sv
similarity index 100%
rename from verilog/dv/bfm/bfm_ad5205.sv
rename to verilog/dv/common/bfm/bfm_ad5205.sv
diff --git a/verilog/dv/bfm/bfm_spim.v b/verilog/dv/common/bfm/bfm_spim.v
similarity index 100%
rename from verilog/dv/bfm/bfm_spim.v
rename to verilog/dv/common/bfm/bfm_spim.v
diff --git a/verilog/dv/bfm/bfm_ws281x.sv b/verilog/dv/common/bfm/bfm_ws281x.sv
similarity index 100%
rename from verilog/dv/bfm/bfm_ws281x.sv
rename to verilog/dv/common/bfm/bfm_ws281x.sv
diff --git a/verilog/dv/bfm/usb1d_defines.v b/verilog/dv/common/bfm/usb1d_defines.v
similarity index 100%
rename from verilog/dv/bfm/usb1d_defines.v
rename to verilog/dv/common/bfm/usb1d_defines.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_core.v b/verilog/dv/common/bfm/usb_device/core/usb1d_core.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_core.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_core.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_crc16.v b/verilog/dv/common/bfm/usb_device/core/usb1d_crc16.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_crc16.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_crc16.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_crc5.v b/verilog/dv/common/bfm/usb_device/core/usb1d_crc5.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_crc5.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_crc5.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_ctrl.v b/verilog/dv/common/bfm/usb_device/core/usb1d_ctrl.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_ctrl.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_ctrl.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_fifo2.v b/verilog/dv/common/bfm/usb_device/core/usb1d_fifo2.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_fifo2.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_fifo2.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_generic_dpram.v b/verilog/dv/common/bfm/usb_device/core/usb1d_generic_dpram.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_generic_dpram.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_generic_dpram.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_generic_fifo.v b/verilog/dv/common/bfm/usb_device/core/usb1d_generic_fifo.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_generic_fifo.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_generic_fifo.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_idma.v b/verilog/dv/common/bfm/usb_device/core/usb1d_idma.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_idma.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_idma.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_pa.v b/verilog/dv/common/bfm/usb_device/core/usb1d_pa.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_pa.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_pa.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_pd.v b/verilog/dv/common/bfm/usb_device/core/usb1d_pd.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_pd.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_pd.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_pe.v b/verilog/dv/common/bfm/usb_device/core/usb1d_pe.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_pe.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_pe.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_pl.v b/verilog/dv/common/bfm/usb_device/core/usb1d_pl.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_pl.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_pl.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_rom1.v b/verilog/dv/common/bfm/usb_device/core/usb1d_rom1.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_rom1.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_rom1.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_sync_fifo.v b/verilog/dv/common/bfm/usb_device/core/usb1d_sync_fifo.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_sync_fifo.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_sync_fifo.v
diff --git a/verilog/dv/bfm/usb_device/core/usb1d_utmi_if.v b/verilog/dv/common/bfm/usb_device/core/usb1d_utmi_if.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/core/usb1d_utmi_if.v
rename to verilog/dv/common/bfm/usb_device/core/usb1d_utmi_if.v
diff --git a/verilog/dv/bfm/usb_device/phy/usb1d_phy.v b/verilog/dv/common/bfm/usb_device/phy/usb1d_phy.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/phy/usb1d_phy.v
rename to verilog/dv/common/bfm/usb_device/phy/usb1d_phy.v
diff --git a/verilog/dv/bfm/usb_device/phy/usb1d_rx_phy.v b/verilog/dv/common/bfm/usb_device/phy/usb1d_rx_phy.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/phy/usb1d_rx_phy.v
rename to verilog/dv/common/bfm/usb_device/phy/usb1d_rx_phy.v
diff --git a/verilog/dv/bfm/usb_device/phy/usb1d_tx_phy.v b/verilog/dv/common/bfm/usb_device/phy/usb1d_tx_phy.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/phy/usb1d_tx_phy.v
rename to verilog/dv/common/bfm/usb_device/phy/usb1d_tx_phy.v
diff --git a/verilog/dv/bfm/usb_device/top/usb1d_top.v b/verilog/dv/common/bfm/usb_device/top/usb1d_top.v
similarity index 100%
rename from verilog/dv/bfm/usb_device/top/usb1d_top.v
rename to verilog/dv/common/bfm/usb_device/top/usb1d_top.v
diff --git a/verilog/dv/bfm/usbd_files.v b/verilog/dv/common/bfm/usbd_files.v
similarity index 100%
rename from verilog/dv/bfm/usbd_files.v
rename to verilog/dv/common/bfm/usbd_files.v
diff --git a/verilog/dv/firmware/LICENSE b/verilog/dv/common/firmware/LICENSE
similarity index 100%
rename from verilog/dv/firmware/LICENSE
rename to verilog/dv/common/firmware/LICENSE
diff --git a/verilog/dv/firmware/common.mk b/verilog/dv/common/firmware/common.mk
similarity index 100%
rename from verilog/dv/firmware/common.mk
rename to verilog/dv/common/firmware/common.mk
diff --git a/verilog/dv/firmware/common_bthread.c b/verilog/dv/common/firmware/common_bthread.c
similarity index 100%
rename from verilog/dv/firmware/common_bthread.c
rename to verilog/dv/common/firmware/common_bthread.c
diff --git a/verilog/dv/firmware/common_bthread.h b/verilog/dv/common/firmware/common_bthread.h
similarity index 100%
rename from verilog/dv/firmware/common_bthread.h
rename to verilog/dv/common/firmware/common_bthread.h
diff --git a/verilog/dv/firmware/common_misc.h b/verilog/dv/common/firmware/common_misc.h
similarity index 100%
rename from verilog/dv/firmware/common_misc.h
rename to verilog/dv/common/firmware/common_misc.h
diff --git a/verilog/dv/firmware/crt.S b/verilog/dv/common/firmware/crt.S
similarity index 100%
rename from verilog/dv/firmware/crt.S
rename to verilog/dv/common/firmware/crt.S
diff --git a/verilog/dv/firmware/crt_tcm.S b/verilog/dv/common/firmware/crt_tcm.S
similarity index 100%
rename from verilog/dv/firmware/crt_tcm.S
rename to verilog/dv/common/firmware/crt_tcm.S
diff --git a/verilog/dv/firmware/csr.h b/verilog/dv/common/firmware/csr.h
similarity index 100%
rename from verilog/dv/firmware/csr.h
rename to verilog/dv/common/firmware/csr.h
diff --git a/verilog/dv/c_func/inc/ext_reg_map.h b/verilog/dv/common/firmware/ext_reg_map.h
similarity index 89%
rename from verilog/dv/c_func/inc/ext_reg_map.h
rename to verilog/dv/common/firmware/ext_reg_map.h
index c5a46c0..7be283e 100644
--- a/verilog/dv/c_func/inc/ext_reg_map.h
+++ b/verilog/dv/common/firmware/ext_reg_map.h
@@ -16,6 +16,14 @@
#define reg_glbl_strap_sticky (*(volatile uint32_t*)0x30020034) // reg_6 - RTC/USB Clock control
#define reg_glbl_system_strap (*(volatile uint32_t*)0x30020038) // reg_6 - RTC/USB Clock control
#define reg_glbl_mail_box (*(volatile uint32_t*)0x3002003C) // reg_15 - Mail Box
+#define reg_glbl_soft_reg_0 (*(volatile uint32_t*)0x30020040) // reg_16 - Soft Register-0
+#define reg_glbl_soft_reg_1 (*(volatile uint32_t*)0x30020044) // reg_17 - Soft Register-1
+#define reg_glbl_soft_reg_2 (*(volatile uint32_t*)0x30020048) // reg_18 - Soft Register-2
+#define reg_glbl_soft_reg_3 (*(volatile uint32_t*)0x3002004C) // reg_19 - Soft Register-3
+#define reg_glbl_soft_reg_4 (*(volatile uint32_t*)0x30020050) // reg_20 - Soft Register-4
+#define reg_glbl_soft_reg_5 (*(volatile uint32_t*)0x30020054) // reg_21 - Soft Register-5
+#define reg_glbl_soft_reg_6 (*(volatile uint32_t*)0x30020058) // reg_22 - Soft Register-6
+#define reg_glbl_soft_reg_7 (*(volatile uint32_t*)0x3002005C) // reg_23 - Soft Register-7
#define reg_gpio_dsel (*(volatile uint32_t*)0x30020080) // reg_0 - GPIO Direction Select
#define reg_gpio_type (*(volatile uint32_t*)0x30020084) // reg_1 - GPIO TYPE - Static/Waveform
diff --git a/verilog/dv/c_func/inc/int_reg_map.h b/verilog/dv/common/firmware/int_reg_map.h
similarity index 95%
rename from verilog/dv/c_func/inc/int_reg_map.h
rename to verilog/dv/common/firmware/int_reg_map.h
index 3e38aed..fa79ec1 100644
--- a/verilog/dv/c_func/inc/int_reg_map.h
+++ b/verilog/dv/common/firmware/int_reg_map.h
@@ -12,9 +12,11 @@
#define reg_glbl_intr (*(volatile uint32_t*)0x10020010) // reg_4 - Global Interrupt
#define reg_glbl_multi_func (*(volatile uint32_t*)0x10020014) // reg_5 - GPIO Multi Function
#define reg_glbl_clk_ctrl (*(volatile uint32_t*)0x10020018) // reg_6 - RTC/USB Clock control
-#define reg_glbl_pad_strap (*(volatile uint32_t*)0x10020030) // reg_6 - RTC/USB Clock control
-#define reg_glbl_strap_sticky (*(volatile uint32_t*)0x10020034) // reg_6 - RTC/USB Clock control
-#define reg_glbl_system_strap (*(volatile uint32_t*)0x10020038) // reg_6 - RTC/USB Clock control
+#define reg_glbl_pll_ctrl1 (*(volatile uint32_t*)0x1002001C) // reg_7 - PLL Control-1
+#define reg_glbl_pll_ctrl2 (*(volatile uint32_t*)0x10020020) // reg_8 - PLL Control-2
+#define reg_glbl_pad_strap (*(volatile uint32_t*)0x10020030) // reg_12 - Pad Strap
+#define reg_glbl_strap_sticky (*(volatile uint32_t*)0x10020034) // reg_13 - Strap Sticky
+#define reg_glbl_system_strap (*(volatile uint32_t*)0x10020038) // reg_14 - System Strap
#define reg_glbl_mail_box (*(volatile uint32_t*)0x1002003C) // reg_15 - Mail Box
#define reg_glbl_soft_reg_0 (*(volatile uint32_t*)0x10020040) // reg_16 - Soft Register-0
#define reg_glbl_soft_reg_1 (*(volatile uint32_t*)0x10020044) // reg_17 - Soft Register-1
diff --git a/verilog/dv/firmware/link.ld b/verilog/dv/common/firmware/link.ld
similarity index 100%
rename from verilog/dv/firmware/link.ld
rename to verilog/dv/common/firmware/link.ld
diff --git a/verilog/dv/firmware/link_tcm.ld b/verilog/dv/common/firmware/link_tcm.ld
similarity index 100%
rename from verilog/dv/firmware/link_tcm.ld
rename to verilog/dv/common/firmware/link_tcm.ld
diff --git a/verilog/dv/firmware/reloc.h b/verilog/dv/common/firmware/reloc.h
similarity index 100%
rename from verilog/dv/firmware/reloc.h
rename to verilog/dv/common/firmware/reloc.h
diff --git a/verilog/dv/firmware/riscv_csr_encoding.h b/verilog/dv/common/firmware/riscv_csr_encoding.h
similarity index 100%
rename from verilog/dv/firmware/riscv_csr_encoding.h
rename to verilog/dv/common/firmware/riscv_csr_encoding.h
diff --git a/verilog/dv/firmware/riscv_macros.h b/verilog/dv/common/firmware/riscv_macros.h
similarity index 100%
rename from verilog/dv/firmware/riscv_macros.h
rename to verilog/dv/common/firmware/riscv_macros.h
diff --git a/verilog/dv/firmware/sc_print.c b/verilog/dv/common/firmware/sc_print.c
similarity index 100%
rename from verilog/dv/firmware/sc_print.c
rename to verilog/dv/common/firmware/sc_print.c
diff --git a/verilog/dv/firmware/sc_print.h b/verilog/dv/common/firmware/sc_print.h
similarity index 100%
rename from verilog/dv/firmware/sc_print.h
rename to verilog/dv/common/firmware/sc_print.h
diff --git a/verilog/dv/firmware/sc_test.h b/verilog/dv/common/firmware/sc_test.h
similarity index 100%
rename from verilog/dv/firmware/sc_test.h
rename to verilog/dv/common/firmware/sc_test.h
diff --git a/verilog/dv/firmware/ycr_specific.h b/verilog/dv/common/firmware/ycr_specific.h
similarity index 100%
rename from verilog/dv/firmware/ycr_specific.h
rename to verilog/dv/common/firmware/ycr_specific.h
diff --git a/verilog/dv/model/i2c_slave_model.v b/verilog/dv/common/model/i2c_slave_model.v
similarity index 100%
rename from verilog/dv/model/i2c_slave_model.v
rename to verilog/dv/common/model/i2c_slave_model.v
diff --git a/verilog/dv/model/is62wvs1288.v b/verilog/dv/common/model/is62wvs1288.v
similarity index 100%
rename from verilog/dv/model/is62wvs1288.v
rename to verilog/dv/common/model/is62wvs1288.v
diff --git a/verilog/dv/model/mt48lc8m8a2.v b/verilog/dv/common/model/mt48lc8m8a2.v
similarity index 100%
rename from verilog/dv/model/mt48lc8m8a2.v
rename to verilog/dv/common/model/mt48lc8m8a2.v
diff --git a/verilog/dv/model/s25fl256s.sv b/verilog/dv/common/model/s25fl256s.sv
similarity index 100%
rename from verilog/dv/model/s25fl256s.sv
rename to verilog/dv/common/model/s25fl256s.sv
diff --git a/verilog/dv/model/spiram.v b/verilog/dv/common/model/spiram.v
similarity index 100%
rename from verilog/dv/model/spiram.v
rename to verilog/dv/common/model/spiram.v
diff --git a/verilog/dv/common/riscduino_board b/verilog/dv/common/riscduino_board
index ec9ef12..f0e1866 160000
--- a/verilog/dv/common/riscduino_board
+++ b/verilog/dv/common/riscduino_board
@@ -1 +1 @@
-Subproject commit ec9ef12933c2435d28bb91d4f653bfc99377f151
+Subproject commit f0e1866cea67544ef6a71839ddb50a806979d1a4
diff --git a/verilog/dv/vpi/system/system.c b/verilog/dv/common/vpi/system/system.c
similarity index 100%
rename from verilog/dv/vpi/system/system.c
rename to verilog/dv/common/vpi/system/system.c
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index f9bb9f4..db9d549 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile
@@ -58,7 +58,7 @@
############## USER SPECIFIC DEFINE ##################
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
######################################################
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index ee52d59..51bde45 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -132,7 +132,7 @@
$dumpfile("simx.vcd");
$dumpvars(1,risc_boot_tb);
//$dumpvars(1,risc_boot_tb.u_spi_flash_256mb);
- //$dumpvars(2,risc_boot_tb.u_top);
+ $dumpvars(2,risc_boot_tb.u_top);
$dumpvars(1,risc_boot_tb.u_top.mprj);
$dumpvars(0,risc_boot_tb.u_top.mprj.u_wb_host);
//$dumpvars(0,risc_boot_tb.tb_uart);
@@ -151,9 +151,9 @@
$display("%c[1;31m",27);
$display ("##########################################################");
`ifdef GL
- $display ("Monitor: Timeout, Test Risc Boot (GL) Failed");
+ $display ("Monitor: Timeout, %m (GL) Failed");
`else
- $display ("Monitor: Timeout, Test Risc Boot (RTL) Failed");
+ $display ("Monitor: Timeout, %m (RTL) Failed");
`endif
$display ("##########################################################");
$display("%c[0m",27);
@@ -186,7 +186,7 @@
uart_stick_parity, uart_timeout, uart_divisor);
- wait_riscv_boot(d_risc_id);
+ wait_riscv_boot();
repeat (50000) @(posedge clock);
for (i=0; i<40; i=i+1)
@@ -228,15 +228,15 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot Test (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone User Risc Boot Test (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot Test (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone User Risc Boot Test (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
diff --git a/verilog/dv/risc_boot/user_uart.c b/verilog/dv/risc_boot/user_uart.c
index b19a157..c9f5dd3 100644
--- a/verilog/dv/risc_boot/user_uart.c
+++ b/verilog/dv/risc_boot/user_uart.c
@@ -16,7 +16,7 @@
// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
// //////////////////////////////////////////////////////////////////////////
#define SC_SIM_OUTPORT (0xf0000000)
-#include "../c_func/inc/int_reg_map.h"
+#include "int_reg_map.h"
#include "common_misc.h"
#include "common_bthread.h"
diff --git a/verilog/dv/uart_master/uart_master.c b/verilog/dv/uart_master/uart_master.c
index e1a4bf0..991bdc5 100644
--- a/verilog/dv/uart_master/uart_master.c
+++ b/verilog/dv/uart_master/uart_master.c
@@ -18,7 +18,6 @@
// This include is relative to $CARAVEL_PATH (see Makefile)
#include <defs.h>
#include <stub.c>
-#include "../c_func/inc/ext_reg_map.h"
// User Project Slaves (0x3000_0000)
diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master/uart_master_tb.v
index ea30b91..2a99ff7 100644
--- a/verilog/dv/uart_master/uart_master_tb.v
+++ b/verilog/dv/uart_master/uart_master_tb.v
@@ -53,6 +53,7 @@
reg [31:0] read_data ;
reg flag;
reg test_fail ;
+reg [15:0] strap_in;
assign checkbits = mprj_io[31:16];
@@ -74,9 +75,9 @@
$dumpfile("simx.vcd");
$dumpvars(2, `TB_TOP);
$dumpvars(0, `TB_TOP.tb_master_uart);
- $dumpvars(0, `TB_TOP.uut.mprj.u_wb_host.u_uart2wb);
+ $dumpvars(0, `TB_TOP.u_top.mprj.u_wb_host.u_uart2wb);
$dumpvars(1, `TB_TOP.tb_master_uart);
- $dumpvars(0, `TB_TOP.uut.mprj.u_pinmux);
+ $dumpvars(0, `TB_TOP.u_top.mprj.u_pinmux);
end
`endif
@@ -90,9 +91,9 @@
$display("%c[1;31m",27);
$display ("##########################################################");
`ifdef GL
- $display ("Monitor: Timeout, Test UART Master (GL) Failed");
+ $display ("Monitor: Timeout, %m (GL) Failed");
`else
- $display ("Monitor: Timeout, Test UART Master (RTL) Failed");
+ $display ("Monitor: Timeout, %m (RTL) Failed");
`endif
$display ("##########################################################");
$display("%c[0m",27);
@@ -100,6 +101,11 @@
end
initial begin
+
+ strap_in = 0;
+ strap_in[`PSTRAP_UARTM_CFG] = 0; // uart master config control - load from LA
+ apply_strap(strap_in);
+
uart_data_bit = 2'b11;
uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
uart_stick_parity = 0; // 1: force even parity
@@ -156,15 +162,15 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User UART Master (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone User Uart Master (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User Uart Master (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone User Uart Master (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
@@ -212,7 +218,7 @@
wire USER_VDD1V8 = power4;
wire VSS = 1'b0;
- caravel uut (
+ caravel u_top (
.vddio (VDD3V3),
.vssio (VSS),
.vdda (VDD3V3),
@@ -263,8 +269,8 @@
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = mprj_io[23];
-assign mprj_io[22] = uart_rxd ;
+assign uart_txd = mprj_io[7];
+assign mprj_io[6] = uart_rxd ;
uart_agent tb_master_uart(
.mclk (clock ),
@@ -273,6 +279,7 @@
);
+`include "caravel_task.sv"
`include "uart_master_tasks.sv"
endmodule
diff --git a/verilog/dv/user_aes/Makefile b/verilog/dv/user_aes/Makefile
index 1ba7631..c68a4d1 100644
--- a/verilog/dv/user_aes/Makefile
+++ b/verilog/dv/user_aes/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
@@ -61,24 +61,24 @@
rm crt.o user_aes.o
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
diff --git a/verilog/dv/user_aes/user_aes.c b/verilog/dv/user_aes/user_aes.c
index cd1bfec..2830ebe 100644
--- a/verilog/dv/user_aes/user_aes.c
+++ b/verilog/dv/user_aes/user_aes.c
@@ -29,6 +29,9 @@
#define ECB 1
#include "aes.h"
+#include "int_reg_map.h"
+#include "common_misc.h"
+#include "common_bthread.h"
static void phex(uint8_t* str);
@@ -40,21 +43,6 @@
static int test_decrypt_ecb(void);
static void test_encrypt_ecb_verbose(void);
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel
-#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0
-#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1
-#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2
-#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3
-#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
-#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
-
-#define reg_mprg_gpio_odata (*(volatile uint32_t*)0x1002004C)
-
int main(void)
{
int exit;
@@ -69,35 +57,46 @@
//printf("You need to specify a symbol between AES128, AES192 or AES256. Exiting");
return 0;
#endif
+ reg_glbl_cfg0 |= 0x1F; // Remove Reset for UART
+ reg_glbl_multi_func &=0x7FFFFFFF; // Disable UART Master Bit[31] = 0
+ reg_glbl_multi_func |=0x100; // Enable UART Multi func
+ reg_uart0_ctrl = 0x07; // Enable Uart Access {3'h0,2'b00,1'b1,1'b1,1'b1}
+ // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
+ // bit[7:0] - core-0
+ // bit[15:8] - core-1
+ // bit[23:16] - core-2
+ // bit[31:24] - core-3
- reg_mprg_gpio_odata = 0x00000100;
- reg_mprj_globl_soft0 = 0x00000000;
+ reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main
+
+ reg_gpio_odata = 0x00000100;
+ reg_glbl_soft_reg_0 = 0x00000000;
exit = test_encrypt_cbc();
- reg_mprg_gpio_odata = 0x00000200;
- reg_mprj_globl_soft0 = exit;
+ reg_gpio_odata = 0x00000200;
+ reg_glbl_soft_reg_0 = exit;
exit += test_decrypt_cbc();
- reg_mprg_gpio_odata = 0x00000300;
- reg_mprj_globl_soft0 = exit;
+ reg_gpio_odata = 0x00000300;
+ reg_glbl_soft_reg_0 = exit;
exit += test_encrypt_ctr();
- reg_mprg_gpio_odata = 0x00000400;
- reg_mprj_globl_soft0 = exit;
+ reg_gpio_odata = 0x00000400;
+ reg_glbl_soft_reg_0 = exit;
exit += test_decrypt_ctr();
- reg_mprg_gpio_odata = 0x00000500;
- reg_mprj_globl_soft0 = exit;
+ reg_gpio_odata = 0x00000500;
+ reg_glbl_soft_reg_0 = exit;
exit += test_decrypt_ecb();
- reg_mprg_gpio_odata = 0x00000600;
- reg_mprj_globl_soft0 = exit;
+ reg_gpio_odata = 0x00000600;
+ reg_glbl_soft_reg_0 = exit;
exit += test_encrypt_ecb();
- reg_mprg_gpio_odata = 0x00000700;
- reg_mprj_globl_soft0 = exit;
+ reg_gpio_odata = 0x00000700;
+ reg_glbl_soft_reg_0 = exit;
test_encrypt_ecb_verbose();
- reg_mprg_gpio_odata = 0x00000800;
- reg_mprj_globl_soft0 = exit;
+ reg_gpio_odata = 0x00000800;
+ reg_glbl_soft_reg_0 = exit;
if(exit == 0) {
- reg_mprg_gpio_odata = 0x00001800;
+ reg_gpio_odata = 0x00001800;
} else {
- reg_mprg_gpio_odata = 0x0000A800;
+ reg_gpio_odata = 0x0000A800;
}
return exit;
diff --git a/verilog/dv/user_aes/user_aes_tb.v b/verilog/dv/user_aes/user_aes_tb.v
index 769596e..3d47bd3 100644
--- a/verilog/dv/user_aes/user_aes_tb.v
+++ b/verilog/dv/user_aes/user_aes_tb.v
@@ -69,33 +69,13 @@
`include "uart_agent.v"
module user_aes_tb;
-reg clock;
-reg wb_rst_i;
-reg power1, power2;
-reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
-reg wbd_ext_cyc_i; // strobe/request
-reg wbd_ext_stb_i; // strobe/request
-reg [31:0] wbd_ext_adr_i; // address
-reg wbd_ext_we_i; // write
-reg [31:0] wbd_ext_dat_i; // data output
-reg [3:0] wbd_ext_sel_i; // byte enable
+`include "user_tasks.sv"
-wire [31:0] wbd_ext_dat_o; // data input
-wire wbd_ext_ack_o; // acknowlegement
-wire wbd_ext_err_o; // error
-
-// User I/O
-wire [37:0] io_oeb;
-wire [37:0] io_out;
-wire [37:0] io_in;
-
-wire gpio;
-wire [37:0] mprj_io;
-wire [7:0] mprj_io_0;
-reg test_fail;
-reg [31:0] read_data;
-integer d_risc_id;
//----------------------------------
// Uart Configuration
@@ -116,11 +96,6 @@
reg uart_fifo_enable ; // fifo mode disable
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
/************* Port-B Mapping **********************************
* Pin-14 PB0/CLKO/ICP1 digital_io[11]
@@ -144,7 +119,6 @@
};
initial begin
test_fail = 0;
- clock = 0;
wbd_ext_cyc_i ='h0; // strobe/request
wbd_ext_stb_i ='h0; // strobe/request
wbd_ext_adr_i ='h0; // address
@@ -165,6 +139,7 @@
initial begin
$value$plusargs("risc_core_id=%d", d_risc_id);
+ init();
uart_data_bit = 2'b11;
uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit;
@@ -180,17 +155,18 @@
$display("Monitor: Standalone User Uart Test Started");
// Remove Wb Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+ //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
// Enable UART Multi Functional Ports
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h100);
+ wait_riscv_boot();
repeat (2) @(posedge clock);
#1;
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
@@ -214,13 +190,19 @@
// Set the GPIO Output data: 0x00000000
wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h0000000);
- fork
+ fork
begin
repeat (1400000) @(posedge clock);
end
begin
wait(port_b_in == 8'h18);
end
+ begin
+ while(1) begin
+ wb_user_core_read(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,read_data);
+ repeat (1000) @(posedge clock);
+ end
+ end
join_any
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h00000000);
@@ -228,15 +210,15 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User AES Test (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone User AES Test (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User AES Test (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone User AES Test (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
@@ -245,80 +227,34 @@
end
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
-assign io_in[0] = 1'b1; // RESET
-assign io_in[16] = 1'b0 ; // SPIS SCK
+assign io_in[5] = 1'b1; // RESET
+assign io_in[21] = 1'b0 ; // SPIS SCK
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
- end
-`endif
//------------------------------------------------------
// Integrate the Serial flash with qurd support to
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[24];
- wire flash_csb = io_out[25];
+ wire flash_clk = io_out[28];
+ wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[29];
- wire #1 io_oeb_30 = io_oeb[30];
- wire #1 io_oeb_31 = io_oeb[31];
- wire #1 io_oeb_32 = io_oeb[32];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+ wire #1 io_oeb_29 = io_oeb[33];
+ wire #1 io_oeb_30 = io_oeb[34];
+ wire #1 io_oeb_31 = io_oeb[35];
+ wire #1 io_oeb_32 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[29] = flash_io0;
- assign io_in[30] = flash_io1;
- assign io_in[31] = flash_io2;
- assign io_in[32] = flash_io3;
+ assign io_in[33] = flash_io0;
+ assign io_in[34] = flash_io1;
+ assign io_in[35] = flash_io2;
+ assign io_in[36] = flash_io3;
// Quard flash
s25fl256s #(.mem_file_name("user_aes.hex"),
@@ -343,8 +279,8 @@
// --------------------------
wire uart_txd,uart_rxd;
-assign uart_txd = io_out[2];
-assign io_in[1] = uart_rxd ;
+assign uart_txd = io_out[7];
+assign io_in[6] = uart_rxd ;
uart_agent tb_uart(
.mclk (clock ),
@@ -353,135 +289,7 @@
);
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile
index c1ad8ae..1067943 100644
--- a/verilog/dv/user_basic/Makefile
+++ b/verilog/dv/user_basic/Makefile
@@ -73,7 +73,7 @@
endif
%.vcd: %.vvp
- vvp $<
+ vvp $<
# ---- Clean ----
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 3317eab..2a1858d 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -76,48 +76,23 @@
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
`include "user_params.svh"
-module user_basic_tb;
-parameter CLK1_PERIOD = 10;
-parameter CLK2_PERIOD = 2.5;
-parameter IPLL_PERIOD = 5.008;
-parameter XTAL_PERIOD = 6;
+`define TB_TOP user_basic_tb
-reg clock ;
-reg clock2 ;
-reg xtal_clk ;
-reg wb_rst_i ;
-reg power1, power2;
-reg power3, power4;
+module `TB_TOP;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
-reg wbd_ext_cyc_i; // strobe/request
-reg wbd_ext_stb_i; // strobe/request
-reg [31:0] wbd_ext_adr_i; // address
-reg wbd_ext_we_i; // write
-reg [31:0] wbd_ext_dat_i; // data output
-reg [3:0] wbd_ext_sel_i; // byte enable
-
-wire [31:0] wbd_ext_dat_o; // data input
-wire wbd_ext_ack_o; // acknowlegement
-wire wbd_ext_err_o; // error
-
-// User I/O
-wire [37:0] io_oeb ;
-wire [37:0] io_out ;
-wire [37:0] io_in ;
-
-wire [37:0] mprj_io ;
-wire [7:0] mprj_io_0 ;
-reg test_fail ;
-reg [31:0] write_data ;
-reg [31:0] read_data ;
+`include "user_tasks.sv"
//----------------------------------
// Uart Configuration
// ---------------------------------
reg [1:0] uart_data_bit ;
-reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
-reg uart_stick_parity ; // 1: force even parity
-reg uart_parity_en ; // parity enable
-reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
+reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
+reg uart_stick_parity ; // 1: force even parity
+reg uart_parity_en ; // parity enable
+reg uart_even_odd_parity ; // 0: odd parity; 1: even parity
reg [7:0] uart_data ;
reg [15:0] uart_divisor ; // divided by n * 16
@@ -133,6 +108,7 @@
reg [15:0] strap_in;
wire [31:0] strap_sticky;
reg [7:0] test_id;
+reg [25:0] bcount;
assign io_in = {26'h0,xtal_clk,11'h0};
@@ -208,51 +184,29 @@
integer i,j;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
- always #(CLK1_PERIOD/2) clock <= (clock === 1'b0);
- always #(CLK2_PERIOD/2) clock2 <= (clock2 === 1'b0);
- always #(XTAL_PERIOD/2) xtal_clk <= (xtal_clk === 1'b0);
-
- initial begin
- test_step = 0;
- clock = 0;
- clock2 = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
+initial begin
+ test_step = 0;
+end
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(1, user_basic_tb);
- $dumpvars(1, user_basic_tb.u_top);
- //$dumpvars(0, user_basic_tb.u_top.u_pll);
- $dumpvars(0, user_basic_tb.u_top.u_wb_host);
- //$dumpvars(0, user_basic_tb.u_top.u_intercon);
- //$dumpvars(1, user_basic_tb.u_top.u_intercon);
- $dumpvars(0, user_basic_tb.u_top.u_pinmux);
+ $dumpvars(0, `TB_TOP);
+ $dumpvars(1, `TB_TOP.u_top);
+ $dumpvars(0, `TB_TOP.u_top.u_pll);
+ $dumpvars(0, `TB_TOP.u_top.u_wb_host);
+ //$dumpvars(0, `TB_TOP.u_top.u_intercon);
+ //$dumpvars(1, `TB_TOP.u_top.u_intercon);
+ $dumpvars(0, `TB_TOP.u_top.u_pinmux);
end
`endif
- initial begin
- wb_rst_i <= 1'b0;
- #1000;
- wb_rst_i <= 1'b1;
- #1000;
- wb_rst_i <= 1'b0; // Release reset
- end
-
-
initial
begin
+ init();
+
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Basic Test Started");
@@ -260,7 +214,6 @@
repeat (2) @(posedge clock);
test_fail=0;
-
fork
begin
$display("##########################################################");
@@ -359,14 +312,15 @@
end else begin
$display("STATUS: Step-4, Checking the soft reboot sequence - PASSED");
end
+
$display("##########################################################");
- /****
$display("Step-5, Checking the uart Master baud-16x clock is 9600* 16");
test_id = 5;
apply_strap(16'h10); // [4] - // uart master config control - constant value based on system clock selection
- uartm_clock_monitor(6510); // 1/(9600*16) = 6510 ns
+ repeat (10) @(posedge clock);
+ uartm_clock_monitor(6510); // 1/(9600*16) = 6510 ns, Assumption is user_clock1 = 40Mhz
if(test_fail == 1) begin
$display("ERROR: Step-5, Checking the uart Master baud-16x clock - FAILED");
@@ -374,53 +328,68 @@
$display("STATUS: Step-5, Checking the uart Master baud-16x clock - PASSED");
end
$display("##########################################################");
- ***/
- /***
+
+
+
`ifndef GL
$display("###################################################");
$display("Step-5,Monitor: Checking the PLL:");
$display("###################################################");
test_id = 5;
// Set PLL enable, no DCO mode ; Set PLL output divider to 0x03
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2});
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'h3,26'h00000});
- repeat (100) @(posedge clock);
- pll_clock_monitor(5.101);
-
+ // Checking the expression
+ // Internal PLL delay = 1.168 + 0.012 * $itor(bcount)
+ // Actual PLL Clock Period = delay * 4
+
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_PLL_CTRL1,{24'h0,1'b1,3'b000});
+ bcount =0;
+ for(i = 0; i < 26; i = i+1) begin
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_PLL_CTRL2,{1'b1,5'h0,bcount[25:0]});
+ repeat (10) @(posedge clock);
+ pll_clock_monitor((1.168 + (0.012 *i)) * 4);
+ //$display("i: %d bcount: %x Clk Period : %f",i,bcount,(1.168 + (0.012 *i)) * 4);
+ bcount = bcount | (1 << i );
+ end
+ /***
test_step = 12;
- // Set PLL enable, DCO mode ; Set PLL output divider to 0x01
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
- repeat (100) @(posedge clock);
- pll_clock_monitor(4.080);
-
+ // Set PLL enable, DCO mode ; Set PLL output divider to 0x05
+ // Input Ref Clock Divider - 0 , Means Div-2, So Osc clock = 40Mhz/2 = 20Mhz = 50ns
+ // Since PLL has divider by 4, Efectivly PLL Output Fequency = 20Mhz * 5 = 100Mhz
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b010,4'b0000,8'h3});
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'd10,26'h0000});
+ repeat (10000) @(posedge clock);
+ pll_clock_monitor(5);
+ */
if(test_fail == 1) begin
$display("ERROR: Step-5, Checking the PLL - FAILED");
end else begin
$display("STATUS: Step-5, Checking the PLL - PASSED");
end
$display("##########################################################");
-
+
+
$display("###################################################");
$display("Step-6,Monitor: PLL Monitor Clock output:");
$display("###################################################");
$display("Monitor: CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)");
test_id = 6;
test_step = 13;
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});
+ init();
+ repeat (10) @(posedge clock);
+ // Configured the PLL to highest frequency, 5.008ns
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_PLL_CTRL1,{24'h0,1'b1,3'b000});
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_PLL_CTRL2,{1'b1,5'h0,26'h0});
- // Set PLL enable, DCO mode ; Set PLL output divider to 0x01
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
- dbg_clk_monitor(79,60,5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD);
- `endif
+ // Monitor user_clock1 at debug Mon
+ dbg_clk_monitor();
if(test_fail == 1) begin
$display("ERROR: Step-6, PLL Monitor Clock output - FAILED");
end else begin
$display("STATUS: Step-6, PLL Monitor Clock output - PASSED");
end
- ****/
+
+ `endif
$display("##########################################################");
$display("Step-7,Monitor: Checking the chip signature :");
$display("###################################################");
@@ -430,8 +399,8 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h8273_8343);
- wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h0309_2022);
- wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h0005_3000);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h0709_2022);
+ wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h0005_4000);
if(test_fail == 1) begin
$display("ERROR: Step-7,Monitor: Checking the chip signature - FAILED");
end else begin
@@ -453,15 +422,15 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User UART Test (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone User UART Test (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User UART Test (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone User UART Test (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
@@ -470,53 +439,6 @@
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (clock2), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in ) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
-
-
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
-
- end
-`endif
task clock_monitor2;
input [3:0] cpu_cfg;
@@ -601,7 +523,8 @@
`ifdef GL
force clock_mon = u_top.u_wb_host.pll_clk_out[0];
`else
- force clock_mon = u_top.u_wb_host.u_clkbuf_pll.X;
+ force clock_mon = u_top.u_wb_host.int_pll_clock;
+
`endif
check_clock_period("PLL CLock",exp_period);
release clock_mon;
@@ -618,35 +541,38 @@
endtask
-wire dbg_clk_mon = io_out[33];
+wire dbg_clk_mon = io_out[37];
+
+//assign dbg_clk_ref = (cfg_mon_sel == 4'b000) ? user_clock1 :
+// (cfg_mon_sel == 4'b001) ? user_clock2 :
+// (cfg_mon_sel == 4'b010) ? xtal_clk :
+// (cfg_mon_sel == 4'b011) ? int_pll_clock:
+// (cfg_mon_sel == 4'b100) ? mclk :
+// (cfg_mon_sel == 4'b101) ? cpu_clk :
+// (cfg_mon_sel == 4'b110) ? usb_clk :
+// (cfg_mon_sel == 4'b111) ? rtc_clk : 1'b0;
task dbg_clk_monitor;
-input [15:0] exp_pll_div16_period;
-input [15:0] exp_pll_ref_period;
-input [15:0] exp_cpu_period;
-input [15:0] exp_usb_period;
-input [15:0] exp_rtc_period;
-input [15:0] exp_wbs_period;
begin
force clock_mon = dbg_clk_mon;
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2});
- check_clock_period("PLL CLock",exp_pll_div16_period);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG1,{16'h0,4'b0000,4'b0000});
+ check_clock_period("USER CLOCK1",CLK1_PERIOD*16);
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0001,8'h2});
- check_clock_period("PLL REF Clock",exp_pll_ref_period);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG1,{16'h0,4'b0001,4'b0000});
+ check_clock_period("USER CLOCK2",CLK2_PERIOD*16);
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0010,8'h2});
- check_clock_period("WBS Clock",exp_wbs_period);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG1,{16'h0,4'b0010,4'b0000});
+ check_clock_period("XTAL CLOCK2",XTAL_PERIOD*16);
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0011,8'h2});
- check_clock_period("CPU CLock",exp_cpu_period);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG1,{16'h0,4'b0011,4'b0000});
+ check_clock_period("INTERNAL PLL",IPLL_PERIOD*16);
+
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG1,{16'h0,4'b0100,4'b0000});
+ check_clock_period("WBS CLOCK",CLK1_PERIOD*16);
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0100,8'h2});
- check_clock_period("RTC Clock",exp_rtc_period);
-
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0101,8'h2});
- check_clock_period("USB Clock",exp_usb_period);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG1,{16'h0,4'b0101,4'b0000});
+ check_clock_period("CPU CLOCK",CLK1_PERIOD*16);
release clock_mon;
end
endtask
@@ -670,15 +596,15 @@
repeat(1) @(posedge clock_mon);
repeat(1) @(posedge clock_mon);
edge1 = $realtime;
- repeat(100) @(posedge clock_mon);
+ repeat(10) @(posedge clock_mon);
edge2 = $realtime;
- clock_period = (edge2-edge1)/100;
+ clock_period = (edge2-edge1)/10;
if ( clock_period > max_period ) begin
- $display("STATUS: FAIL => %s clock is too fast => Exp: %.3fns Rxd: %.3fns",clk_name,clock_period,max_period);
+ $display("STATUS: FAIL => %s clock is too fast => Rxp: %.3fns Exd: %.3fns",clk_name,clock_period,max_period);
test_fail = 1;
end else if ( clock_period < min_period ) begin
- $display("STATUS: FAIL => %s clock is too slow => Exp: %.3fns Rxd: %.3fns",clk_name,clock_period,min_period);
+ $display("STATUS: FAIL => %s clock is too slow => Rxp: %.3fns Exd: %.3fns",clk_name,clock_period,min_period);
test_fail = 1;
end else begin
$display("STATUS: PASS => %s Period: %.3fns ",clk_name,period);
@@ -689,137 +615,5 @@
-
-
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-`include "user_tasks.sv"
endmodule
`default_nettype wire
diff --git a/verilog/dv/user_cache_bypass/Makefile b/verilog/dv/user_cache_bypass/Makefile
index 7ecacbf..ec06c1f 100644
--- a/verilog/dv/user_cache_bypass/Makefile
+++ b/verilog/dv/user_cache_bypass/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
@@ -51,32 +51,32 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_cache_bypass.c -o user_cache_bypass.o
+ ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) ${PATTERN}.c -o ${PATTERN}.o
${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
- ${GCC_PREFIX}-gcc -o user_cache_bypass.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_cache_bypass.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
- ${GCC_PREFIX}-objcopy -O verilog user_cache_bypass.elf user_cache_bypass.hex
- ${GCC_PREFIX}-objdump -D user_cache_bypass.elf > user_cache_bypass.dump
- rm crt.o user_cache_bypass.o
+ ${GCC_PREFIX}-gcc -o ${PATTERN}.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld ${PATTERN}.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC_PREFIX}-objcopy -O verilog ${PATTERN}.elf ${PATTERN}.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump
+ rm crt.o ${PATTERN}.o
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
diff --git a/verilog/dv/user_cache_bypass/user_cache_bypass.c b/verilog/dv/user_cache_bypass/user_cache_bypass.c
index a3e9b0d..bd8ee6a 100644
--- a/verilog/dv/user_cache_bypass/user_cache_bypass.c
+++ b/verilog/dv/user_cache_bypass/user_cache_bypass.c
@@ -16,21 +16,9 @@
// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
// //////////////////////////////////////////////////////////////////////////
#define SC_SIM_OUTPORT (0xf0000000)
-#define uint32_t long
-#define uint16_t int
-
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel
-#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0
-#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1
-#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2
-#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3
-#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
-#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
+#include "int_reg_map.h"
+#include "common_misc.h"
+#include "common_bthread.h"
// -------------------------------------------------------------------------
@@ -39,8 +27,8 @@
void test_function()
{
- reg_mprj_globl_soft2 = 0x33445566; // Sig-2
- reg_mprj_globl_soft3 = 0x44556677; // Sig-3
+ reg_glbl_soft_reg_2 = 0x33445566; // Sig-2
+ reg_glbl_soft_reg_3 = 0x44556677; // Sig-3
return;
}
@@ -51,23 +39,37 @@
uint16_t *src_ptr;
uint16_t *dst_ptr;
+ // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
+ // bit[7:0] - core-0
+ // bit[15:8] - core-1
+ // bit[23:16] - core-2
+ // bit[31:24] - core-3
+
+ reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main
src_ptr = &test_function;
dst_ptr = func;
- reg_mprj_globl_soft0 = 0x11223344; // Sig-0
+ reg_glbl_soft_reg_0 = 0x11223344; // Sig-0
while (src_ptr < &main) {
*(dst_ptr++) = *(src_ptr++);
}
// Call the routine in SRAM
- reg_mprj_globl_soft1 = 0x22334455; // Sig-1
+ reg_glbl_soft_reg_1 = 0x22334455; // Sig-1
((void(*)())func)();
- reg_mprj_globl_soft4 = 0x55667788;
- reg_mprj_globl_soft5 = 0x66778899;
+ reg_glbl_soft_reg_4 = 0x55667788;
+ reg_glbl_soft_reg_5 = 0x66778899;
// Signal end of test
+ // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
+ // bit[7:0] - core-0
+ // bit[15:8] - core-1
+ // bit[23:16] - core-2
+ // bit[31:24] - core-3
+
+ reg_glbl_mail_box = 0xff << (bthread_get_core_id() * 8); // Start of Main
}
diff --git a/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
index 28c8f2c..b8909fa 100644
--- a/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
+++ b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
@@ -67,51 +67,15 @@
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
module user_cache_bypass_tb;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 25;
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
-
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
- integer d_risc_id;
+`include "user_tasks.sv"
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
+reg [15:0] strap_in;
`ifdef WFDUMP
initial begin
@@ -125,46 +89,35 @@
$value$plusargs("risc_core_id=%d", d_risc_id);
- #200; // Wait for reset removal
- repeat (10) @(posedge clock);
+ strap_in = PAD_STRAP;
+ strap_in[`PSTRAP_RISCV_CACHE_BYPASS] = 1'b1;
+ // Aplly the Strap
+ apply_strap(strap_in);
+
+ // Cross-check if the icache/dcache bypass flag is set
+ wait(u_top.u_riscv_top.cfg_bypass_icache == 1'b1);
+ wait(u_top.u_riscv_top.cfg_bypass_dcache == 1'b1);
+
+ repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
- // Remove Wb Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+ // wait for risc execution started
+ wait_riscv_boot();
+ $display("Monitor: RISCV execution started");
- repeat (2) @(posedge clock);
- #1;
- // Set the icahce and dcache bypass
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG1,{4'b0,2'b11,2'b00,8'b0,16'b0});
-
- // Remove all the reset
- if(d_risc_id == 0) begin
- $display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
- end else begin
- $display("STATUS: Working with Risc core 1");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
- end
-
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (30) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
-
-
- $display("Monitor: Reading Back the expected value");
+ // wait for risc execution Completed
+ wait_riscv_exit();
+ $display("Monitor: RISCV execution completed");
// User RISC core expect to write these value in global
// register, read back and decide on pass fail
// 0x30000018 = 0x11223344;
- // 0x3000001C = 0x22334455;
- // 0x30000020 = 0x33445566;
- // 0x30000024 = 0x44556677;
- // 0x30000028 = 0x55667788;
- // 0x3000002C = 0x66778899;
+ // 0x3000001C = 0x22334455;
+ // 0x30000020 = 0x33445566;
+ // 0x30000024 = 0x44556677;
+ // 0x30000028 = 0x55667788;
+ // 0x3000002C = 0x66778899;
- test_fail = 0;
+ test_fail = 0;
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
@@ -177,95 +130,47 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
-assign io_in[0] = 1'b1; // RESET
-assign io_in[16] = 1'b0 ; // SPIS SCK
+assign io_in[5] = 1'b1; // RESET
+assign io_in[21] = 1'b0 ; // SPIS SCK
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
- end
-`endif
//------------------------------------------------------
// Integrate the Serial flash with qurd support to
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[24];
- wire flash_csb = io_out[25];
+ wire flash_clk = io_out[28];
+ wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[29];
- wire #1 io_oeb_30 = io_oeb[30];
- wire #1 io_oeb_31 = io_oeb[31];
- wire #1 io_oeb_32 = io_oeb[32];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+ wire #1 io_oeb_29 = io_oeb[33];
+ wire #1 io_oeb_30 = io_oeb[34];
+ wire #1 io_oeb_31 = io_oeb[35];
+ wire #1 io_oeb_32 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[29] = flash_io0;
- assign io_in[30] = flash_io1;
- assign io_in[31] = flash_io2;
- assign io_in[32] = flash_io3;
+ assign io_in[33] = flash_io0;
+ assign io_in[34] = flash_io1;
+ assign io_in[35] = flash_io2;
+ assign io_in[36] = flash_io3;
// Quard flash
s25fl256s #(.mem_file_name("user_cache_bypass.hex"),
@@ -286,136 +191,6 @@
-
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/user_gpio/Makefile b/verilog/dv/user_gpio/Makefile
index 28bcc52..d53c0a4 100644
--- a/verilog/dv/user_gpio/Makefile
+++ b/verilog/dv/user_gpio/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/user_gpio/user_gpio_tb.v b/verilog/dv/user_gpio/user_gpio_tb.v
index a0ab607..0efe8fe 100644
--- a/verilog/dv/user_gpio/user_gpio_tb.v
+++ b/verilog/dv/user_gpio/user_gpio_tb.v
@@ -74,46 +74,19 @@
`define TB_GLBL user_gpio_tb
module user_gpio_tb;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
-
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
+`include "user_tasks.sv"
- reg [1:0] spi_chip_no;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
reg test_start;
integer test_step;
wire clock_mon;
- integer d_risc_id;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
/************* Port-A Mapping **********************************
@@ -241,15 +214,6 @@
wire [31:0] irq_lines = u_top.u_pinmux.u_glbl_reg.irq_lines;
- initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
`ifdef WFDUMP
initial begin
@@ -368,67 +332,21 @@
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: GPIO Mode (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: GPIO Mode (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: GPIO Mode (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: GPIO Mode (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
-
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
- end
-`endif
-
//----------------------------------------------------
// Task
@@ -625,137 +543,6 @@
end
endtask
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- //$display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- `TB_GLBL.test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-
-`include "user_tasks.sv"
endmodule
`default_nettype wire
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index b2bfe32..57d15a4 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index a343366..0547990 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -69,53 +69,20 @@
`include "i2c_slave_model.v"
module tb_top;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
-reg clock ;
-reg wb_rst_i ;
-reg power1, power2;
-reg power3, power4;
+`include "user_tasks.sv"
-reg wbd_ext_cyc_i; // strobe/request
-reg wbd_ext_stb_i; // strobe/request
-reg [31:0] wbd_ext_adr_i; // address
-reg wbd_ext_we_i; // write
-reg [31:0] wbd_ext_dat_i; // data output
-reg [3:0] wbd_ext_sel_i; // byte enable
-wire [31:0] wbd_ext_dat_o; // data input
-wire wbd_ext_ack_o; // acknowlegement
-wire wbd_ext_err_o; // error
-
-// User I/O
-wire [37:0] io_oeb ;
-wire [37:0] io_out ;
-wire [37:0] io_in ;
-
-wire [37:0] mprj_io ;
-wire [7:0] mprj_io_0 ;
-reg test_fail ;
-reg [31:0] read_data ;
//----------------------------------
// Uart Configuration
// ---------------------------------
integer i,j;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
`ifdef WFDUMP
initial begin
@@ -127,7 +94,7 @@
initial
begin
test_fail = 0;
- init();
+ init();
#200; // Wait for reset removal
repeat (10) @(posedge clock);
@@ -278,15 +245,15 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User I2M Test (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone User I2M Test (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User I2M Test (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone User I2M Test (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
@@ -294,54 +261,9 @@
$finish;
end
-
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
-assign io_in[0] = 1'b1; // RESET
+assign io_in[5] = 1'b1; // RESET
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
- end
-`endif
//---------------------------
// I2C
@@ -363,134 +285,6 @@
);
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- //$display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_cmp;
-input [31:0] address;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-`include "user_tasks.sv"
endmodule
`default_nettype wire
diff --git a/verilog/dv/user_mcore_test1/Makefile b/verilog/dv/user_mcore_test1/Makefile
index 376195f..f995178 100644
--- a/verilog/dv/user_mcore_test1/Makefile
+++ b/verilog/dv/user_mcore_test1/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/user_mcore_test1/user_mcore_test1.c b/verilog/dv/user_mcore_test1/user_mcore_test1.c
index a74159f..45136a5 100644
--- a/verilog/dv/user_mcore_test1/user_mcore_test1.c
+++ b/verilog/dv/user_mcore_test1/user_mcore_test1.c
@@ -16,7 +16,7 @@
*/
-#include "../c_func/inc/int_reg_map.h"
+#include "int_reg_map.h"
#include "common_misc.h"
#include "common_bthread.h"
@@ -29,23 +29,23 @@
// Multi-core test, Two Array is filled with below data, destination hold sum
// source result remark
// src0 src1 dest
-// 0x0000 0x00000000 0x00000000 updated by core-0
-// 0x1111 0x11110000 0x11111111 updated by core-0
-// 0x2222 0x22220000 0x22222222 updated by core-0
-// 0x3333 0x33330000 0x33333333 updated by core-0
-// 0x4444 0x44440000 0x44444444 updated by core-1
-// 0x5555 0x55550000 0x55555555 updated by core-1
-// 0x6666 0x66660000 0x66666666 updated by core-1
-// 0x7777 0x77770000 0x77777777 updated by core-1
-//
-// 0x8888 0x88880000 0x88888888 updated by core-2
-// 0x9999 0x99990000 0x99999999 updated by core-2
-// 0xAAAA 0xAAAA0000 0xAAAAAAAA updated by core-2
-// 0xBBBB 0xBBBB0000 0xBBBBBBBB updated by core-2
-// 0xCCCC 0xCCCC0000 0xCCCCCCCC updated by core-3
-// 0xDDDD 0xDDDD0000 0xDDDDDDDD updated by core-3
-// 0xEEEE 0xEEEE0000 0xEEEEEEEE updated by core-3
-// 0xFFFF 0xFFFF0000 0xFFFFFFFF updated by core-3
+// 0x00 0x0000 0x0000 updated by core-0
+// 0x11 0x1100 0x1111 updated by core-0
+// 0x22 0x2200 0x2222 updated by core-0
+// 0x33 0x3300 0x3333 updated by core-0
+// 0x44 0x4400 0x4444 updated by core-0
+// 0x55 0x5500 0x5555 updated by core-0
+// 0x66 0x6600 0x6666 updated by core-0
+// 0x77 0x7700 0x7777 updated by core-0
+//
+// 0x88 0x8800 0x8888 updated by core-1
+// 0x99 0x9900 0x9999 updated by core-1
+// 0xAA 0xAA00 0xAAAA updated by core-1
+// 0xBB 0xBB00 0xBBBB updated by core-1
+// 0xCC 0xCC00 0xCCCC updated by core-1
+// 0xDD 0xDD00 0xDDDD updated by core-1
+// 0xEE 0xEE00 0xEEEE updated by core-1
+// 0xFF 0xFF00 0xFFFF updated by core-1
//
// -------------------------------------------------------------------------
@@ -103,10 +103,8 @@
// Create two argument structures that include the array pointers and
// what elements each core should process.
- arg_t arg0 = { dest, src0, src1, 0, buf_size/4 };
- arg_t arg1 = { dest, src0, src1, buf_size/4, buf_size/2 };
- arg_t arg2 = { dest, src0, src1, buf_size/2, (3*buf_size)/4 };
- arg_t arg3 = { dest, src0, src1, (3*buf_size)/4, buf_size };
+ arg_t arg0 = { dest, src0, src1, 0, buf_size/2 };
+ arg_t arg1 = { dest, src0, src1, buf_size/2, buf_size };
reg_glbl_soft_reg_0 = 0x11223344; // Sig-0
// Initialize bare threads (bthread).
@@ -120,8 +118,6 @@
// Spawn work onto core 1
bthread_spawn( 1, &vvadd_mt, &arg1 );
- bthread_spawn( 2, &vvadd_mt, &arg2 );
- bthread_spawn( 3, &vvadd_mt, &arg3 );
reg_glbl_soft_reg_2 = 0x33445566; // Sig-2
// Have core 0 also do some work.
@@ -130,8 +126,6 @@
reg_glbl_soft_reg_3 = 0x44556677; // Sig-3
// Wait for core 1 to finish.
bthread_join(1);
- bthread_join(2);
- bthread_join(3);
// Stop counting stats
diff --git a/verilog/dv/user_mcore_test1/user_mcore_test1_tb.v b/verilog/dv/user_mcore_test1/user_mcore_test1_tb.v
index 1c6b6a2..d272b22 100644
--- a/verilog/dv/user_mcore_test1/user_mcore_test1_tb.v
+++ b/verilog/dv/user_mcore_test1/user_mcore_test1_tb.v
@@ -70,51 +70,12 @@
`define TB_TOP user_mcore_test1_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
-
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
- integer d_risc_id;
-
-
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
+`include "user_tasks.sv"
`ifdef WFDUMP
initial begin
@@ -140,25 +101,25 @@
repeat (2) @(posedge clock);
#1;
// Remove all the reset
- $display("STATUS: Working with Both core Risc core 0/1/2/3 ");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'hF1F);
+ $display("STATUS: Working with Both core Risc core 0 & 1 ");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h31F);
- wait_riscv_boot(0);
+ wait_riscv_boot();
- wait_riscv_exit(0);
+ wait_riscv_exit();
$display("Monitor: Reading Back the expected value");
// User RISC core expect to write these value in global
// register, read back and decide on pass fail
// 0x30000018 = 0x11223344;
- // 0x3000001C = 0x22334455;
- // 0x30000020 = 0x33445566;
- // 0x30000024 = 0x44556677;
- // 0x30000028 = 0x55667788;
- // 0x3000002C = 0x66778899;
+ // 0x3000001C = 0x22334455;
+ // 0x30000020 = 0x33445566;
+ // 0x30000024 = 0x44556677;
+ // 0x30000028 = 0x55667788;
+ // 0x3000002C = 0x66778899;
- test_fail = 0;
+ test_fail = 0;
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
@@ -168,72 +129,29 @@
- $display("###################################################");
- if(test_fail == 0) begin
- `ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Passed");
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Passed");
+ `else
+ $display("Monitor: %m (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+ $display("Monitor: %m (RTL) Failed");
`endif
- end else begin
- `ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Failed");
- `else
- $display("Monitor: Standalone User Risc Boot (RTL) Failed");
- `endif
- end
- $display("###################################################");
+ end
+ $display("###################################################");
$finish;
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
assign io_in[5] = 1'b1; // RESET
assign io_in[21] = 1'b0 ; // SPIS SCK
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
- end
-`endif
//------------------------------------------------------
// Integrate the Serial flash with qurd support to
@@ -243,14 +161,14 @@
wire flash_clk = io_out[28];
wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
assign io_in[33] = flash_io0;
assign io_in[34] = flash_io1;
@@ -277,136 +195,6 @@
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-`include "user_tasks.sv"
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/user_mcore_test2/Makefile b/verilog/dv/user_mcore_test2/Makefile
index 8054ca6..2975493 100644
--- a/verilog/dv/user_mcore_test2/Makefile
+++ b/verilog/dv/user_mcore_test2/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/user_mcore_test2/user_mcore_test2.c b/verilog/dv/user_mcore_test2/user_mcore_test2.c
index b2a53c8..5628795 100644
--- a/verilog/dv/user_mcore_test2/user_mcore_test2.c
+++ b/verilog/dv/user_mcore_test2/user_mcore_test2.c
@@ -18,7 +18,7 @@
#include "common_misc.h"
#include "common_bthread.h"
-#include "../c_func/inc/int_reg_map.h"
+#include "int_reg_map.h"
#define SC_SIM_OUTPORT (0xf0000000)
#define uint32_t long
@@ -74,6 +74,7 @@
}
// Core 0 thread
if ( bthread_get_core_id() == 0 ) {
+ while((reg_glbl_mail_box >> (bthread_get_core_id() *8) & 0xFF) != 0x81); // wait for test start
print_message("UART command-0 from core-0\n");
print_message("UART command-1 from core-0\n");
print_message("UART command-2 from core-0\n");
@@ -83,7 +84,7 @@
// Core 1 thread
if ( bthread_get_core_id() == 1 ) {
- while((reg_glbl_mail_box & 0x1) == 0x0); // wait for test start
+ while((reg_glbl_mail_box >> (bthread_get_core_id() *8) & 0xFF) != 0x81); // wait for test start
print_message("UART command-0 from core-1\n");
print_message("UART command-1 from core-1\n");
print_message("UART command-2 from core-1\n");
@@ -92,7 +93,7 @@
}
// Core 2 thread
if ( bthread_get_core_id() == 2 ) {
- while((reg_glbl_mail_box & 0x1) == 0x0); // wait for test start
+ while((reg_glbl_mail_box >> (bthread_get_core_id() *8) & 0xFF) != 0x81); // wait for test start
print_message("UART command-0 from core-2\n");
print_message("UART command-1 from core-2\n");
print_message("UART command-2 from core-2\n");
@@ -101,7 +102,7 @@
}
// Core 3 thread
if ( bthread_get_core_id() == 3 ) {
- while((reg_glbl_mail_box & 0x1) == 0x0); // wait for test start
+ while((reg_glbl_mail_box >> (bthread_get_core_id() *8) & 0xFF) != 0x81); // wait for test start
print_message("UART command-0 from core-3\n");
print_message("UART command-1 from core-3\n");
print_message("UART command-2 from core-3\n");
diff --git a/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v b/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v
index 6082305..c6f6181 100644
--- a/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v
+++ b/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v
@@ -71,34 +71,13 @@
`define TB_TOP user_mcore_test2_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+`include "user_tasks.sv"
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg test_start;
- reg [31:0] read_data;
- //----------------------------------
// Uart Configuration
// ---------------------------------
reg [1:0] uart_data_bit ;
@@ -118,30 +97,12 @@
reg flag ;
reg [31:0] check_sum ;
-
- integer d_risc_id;
+ reg [7:0] test_start ;
integer i,j;
-
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
-
- // 50Mhz CLock
- always #10 clock <= (clock === 1'b0);
-
initial begin
- clock = 0;
test_start = 0;
flag = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
@@ -212,15 +173,16 @@
repeat (2) @(posedge clock);
#1;
// Remove all the reset
- $display("STATUS: Working with Both core Risc core 0,1,2,3 ");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'hF1F);
+ $display("STATUS: Working with Both core Risc core 0 & 1 ");
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h31F);
tb_uart.debug_mode = 0; // disable debug display
tb_uart.uart_init;
tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor);
- wait_riscv_boot(0);
+ wait_riscv_boot();
+ set_tb_ready();
flag = 0;
@@ -252,76 +214,34 @@
// Check
// if all the 4224 byte received
// if no error
- if(uart_rx_nu != 432) test_fail = 1;
- if(check_sum != 32'h89f0) test_fail = 1;
+ if(uart_rx_nu != 216) test_fail = 1;
+ if(check_sum != 32'h44f0) test_fail = 1;
if(tb_uart.err_cnt != 0) test_fail = 1;
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: multi core test (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: multi core test (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: multi core test (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: multi core test (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
assign io_in[5] = 1'b1; // RESET
assign io_in[21] = 1'b0 ; // SPIS SCK
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
- end
-`endif
//------------------------------------------------------
// Integrate the Serial flash with qurd support to
@@ -331,14 +251,14 @@
wire flash_clk = io_out[28];
wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[33];
- wire #1 io_oeb_30 = io_oeb[34];
- wire #1 io_oeb_31 = io_oeb[35];
- wire #1 io_oeb_32 = io_oeb[36];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
+ wire #1 io_oeb_33 = io_oeb[33];
+ wire #1 io_oeb_34 = io_oeb[34];
+ wire #1 io_oeb_35 = io_oeb[35];
+ wire #1 io_oeb_36 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_33== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_34== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_35== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_36== 1'b0) ? io_out[36] : 1'bz;
assign io_in[33] = flash_io0;
assign io_in[34] = flash_io1;
@@ -377,137 +297,6 @@
.rxd (uart_txd )
);
-
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-`include "user_tasks.sv"
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/user_pwm/Makefile b/verilog/dv/user_pwm/Makefile
index b15037f..0d09337 100644
--- a/verilog/dv/user_pwm/Makefile
+++ b/verilog/dv/user_pwm/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v
index 32b5b69..8d7a20a 100644
--- a/verilog/dv/user_pwm/user_pwm_tb.v
+++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -72,55 +72,22 @@
module user_pwm_tb;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 25;
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
-
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
+`include "user_tasks.sv"
- reg [1:0] spi_chip_no;
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
reg [31:0] OneMsPeriod;
- integer test_step;
- wire clock_mon;
+ integer test_step;
+ wire clock_mon;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
initial begin
OneMsPeriod = 1000;
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
@@ -176,23 +143,21 @@
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: PWM Mode (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: PWM Mode (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: PWM Mode (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: PWM Mode (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
wire pwm0 = io_out[9];
wire pwm1 = io_out[13];
@@ -262,49 +227,9 @@
end
endtask
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
-assign io_in[0] = 1'b1; // RESET
+assign io_in[5] = 1'b1; // RESET
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
- end
-`endif
@@ -317,137 +242,5 @@
end
endtask
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- //$display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- `TB_GLBL.test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-
-`include "user_tasks.sv"
endmodule
`default_nettype wire
diff --git a/verilog/dv/user_qspi/Makefile b/verilog/dv/user_qspi/Makefile
index edf4cf1..6d60a89 100644
--- a/verilog/dv/user_qspi/Makefile
+++ b/verilog/dv/user_qspi/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v
index e4785b1..9801bdd 100644
--- a/verilog/dv/user_qspi/user_qspi_tb.v
+++ b/verilog/dv/user_qspi/user_qspi_tb.v
@@ -83,32 +83,12 @@
`include "is62wvs1288.v"
module user_qspi_tb;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
-
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
+`include "user_tasks.sv"
/*************************************************************
* SPI FSM State Control
@@ -167,21 +147,6 @@
parameter P_QUAD = 2'b10;
parameter P_QDDR = 2'b11;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
`ifdef WFDUMP
initial begin
@@ -1146,59 +1111,21 @@
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: SPI Master Mode (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: SPI Master Mode (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: SPI Master Mode (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: SPI Master Mode (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
-
// SSPI Slave I/F
assign io_in[0] = 1'b1; // RESET
@@ -1264,137 +1191,6 @@
);
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- user_qspi_tb.test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-`include "user_tasks.sv"
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index d83adcc..c070ca5 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/user_risc_boot/user_risc_boot.c b/verilog/dv/user_risc_boot/user_risc_boot.c
index 923dba7..0fb79f9 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot.c
+++ b/verilog/dv/user_risc_boot/user_risc_boot.c
@@ -16,7 +16,7 @@
// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
// //////////////////////////////////////////////////////////////////////////
#define SC_SIM_OUTPORT (0xf0000000)
-#include "../c_func/inc/int_reg_map.h"
+#include "int_reg_map.h"
#include "common_misc.h"
#include "common_bthread.h"
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 62a6c21..0901b82 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -79,52 +79,16 @@
`define TB_HEX "user_risc_boot.hex"
`define TB_TOP user_risc_boot_tb
module `TB_TOP;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+parameter real CLK1_PERIOD = 20; // %0Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
- integer d_risc_id;
+`include "user_tasks.sv"
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
-
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
@@ -155,19 +119,19 @@
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
end
- wait_riscv_boot(d_risc_id);
+ wait_riscv_boot();
$display("Monitor: Reading Back the expected value");
// User RISC core expect to write these value in global
// register, read back and decide on pass fail
// 0x30000018 = 0x11223344;
- // 0x3000001C = 0x22334455;
- // 0x30000020 = 0x33445566;
- // 0x30000024 = 0x44556677;
- // 0x30000028 = 0x55667788;
- // 0x3000002C = 0x66778899;
+ // 0x3000001C = 0x22334455;
+ // 0x30000020 = 0x33445566;
+ // 0x30000024 = 0x44556677;
+ // 0x30000028 = 0x55667788;
+ // 0x3000002C = 0x66778899;
- test_fail = 0;
+ test_fail = 0;
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
@@ -180,70 +144,26 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
-
// SSPI Slave I/F
assign io_in[5] = 1'b1; // RESET
assign io_in[21] = 1'b0; // CLOCK
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
- end
-`endif
//------------------------------------------------------
// Integrate the Serial flash with qurd support to
@@ -288,137 +208,6 @@
-
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-`include "user_tasks.sv"
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/user_sema/user_sema_tb.v b/verilog/dv/user_sema/user_sema_tb.v
index a4e08a2..fa2b8a8 100644
--- a/verilog/dv/user_sema/user_sema_tb.v
+++ b/verilog/dv/user_sema/user_sema_tb.v
@@ -70,35 +70,14 @@
`define TOP user_sema_tb
module `TOP;
-parameter CLK1_PERIOD = 10;
-parameter CLK2_PERIOD = 2;
+parameter real CLK1_PERIOD = 25;
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
-reg clock ;
-reg clock2 ;
-reg wb_rst_i ;
-reg power1, power2;
-reg power3, power4;
+`include "user_tasks.sv"
-reg wbd_ext_cyc_i; // strobe/request
-reg wbd_ext_stb_i; // strobe/request
-reg [31:0] wbd_ext_adr_i; // address
-reg wbd_ext_we_i; // write
-reg [31:0] wbd_ext_dat_i; // data output
-reg [3:0] wbd_ext_sel_i; // byte enable
-wire [31:0] wbd_ext_dat_o; // data input
-wire wbd_ext_ack_o; // acknowlegement
-wire wbd_ext_err_o; // error
-
-// User I/O
-wire [37:0] io_oeb ;
-wire [37:0] io_out ;
-wire [37:0] io_in ;
-
-wire [37:0] mprj_io ;
-wire [7:0] mprj_io_0 ;
-reg test_fail ;
-reg [31:0] read_data ;
reg [31:0] exp_data ;
//----------------------------------
// Uart Configuration
@@ -107,23 +86,9 @@
integer i,j;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #(CLK1_PERIOD/2) clock <= (clock === 1'b0);
- always #(CLK2_PERIOD/2) clock2 <= (clock2 === 1'b0);
initial begin
test_step = 0;
- clock = 0;
- clock2 = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
@@ -139,16 +104,11 @@
end
`endif
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
-
initial
begin
+ init();
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Basic Test Started");
@@ -158,8 +118,6 @@
test_fail=0;
fork
begin
- // Remove Wb/PinMux Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
// Setting Lock Bit Individually and clearing it imediatly
for(i=0; i < 15; i = i+1) begin
@@ -214,15 +172,15 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Semaphore Test (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Semaphore Test (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Semaphore Test (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Semaphore Test (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
@@ -231,189 +189,9 @@
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (clock2), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
-assign io_in[0] = 1'b1; // RESET
-assign io_in[16] = 1'b0 ; // SPIS SCK
+assign io_in[5] = 1'b1; // RESET
+assign io_in[21] = 1'b0 ; // SPIS SCK
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
-
- end
-`endif
-
-
-
-
-
-
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
endmodule
`default_nettype wire
diff --git a/verilog/dv/user_spi_isp/Makefile b/verilog/dv/user_spi_isp/Makefile
index f655404..b4b9118 100644
--- a/verilog/dv/user_spi_isp/Makefile
+++ b/verilog/dv/user_spi_isp/Makefile
@@ -27,7 +27,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/user_spi_isp/user_spi_isp_tb.v b/verilog/dv/user_spi_isp/user_spi_isp_tb.v
index 7d78ef2..bc6a80c 100644
--- a/verilog/dv/user_spi_isp/user_spi_isp_tb.v
+++ b/verilog/dv/user_spi_isp/user_spi_isp_tb.v
@@ -70,33 +70,15 @@
module user_spi_isp_tb;
-reg clock ;
-reg wb_rst_i ;
-reg power1, power2;
-reg power3, power4;
+parameter real CLK1_PERIOD = 25;
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
-reg wbd_ext_cyc_i; // strobe/request
-reg wbd_ext_stb_i; // strobe/request
-reg [31:0] wbd_ext_adr_i; // address
-reg wbd_ext_we_i; // write
-reg [31:0] wbd_ext_dat_i; // data output
-reg [3:0] wbd_ext_sel_i; // byte enable
+`include "user_tasks.sv"
-wire [31:0] wbd_ext_dat_o; // data input
-wire wbd_ext_ack_o; // acknowlegement
-wire wbd_ext_err_o; // error
-// User I/O
-wire [37:0] io_oeb ;
-wire [37:0] io_out ;
-wire [37:0] io_in ;
-wire [37:0] mprj_io ;
-wire [7:0] mprj_io_0 ;
-reg test_fail ;
-reg [31:0] read_data ;
-
-reg [127:0] la_data_in;
reg flag;
// SCLK
@@ -108,16 +90,6 @@
integer i,j;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- la_data_in = 1;
- end
`ifdef WFDUMP
initial begin
@@ -126,15 +98,6 @@
end
`endif
- initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
initial
begin
@@ -171,15 +134,15 @@
$display("###################################################");
if(u_spim.err_cnt == 0) begin
`ifdef GL
- $display("Monitor: Standalone User SPI ISP (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone User SPI ISP (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User SPI ISP (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone User SPI ISP (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
@@ -188,52 +151,6 @@
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in (la_data_in) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
-
-// SSPI Slave I/F
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
- end
-`endif
-
assign io_in[5] = 1'b0;
assign io_in[21] = sclk;
assign io_in[20] = sdi;
@@ -249,6 +166,5 @@
);
-`include "user_tasks.sv"
endmodule
`default_nettype wire
diff --git a/verilog/dv/user_sram_exec/Makefile b/verilog/dv/user_sram_exec/Makefile
index 6e2a6cd..a43d3d7 100644
--- a/verilog/dv/user_sram_exec/Makefile
+++ b/verilog/dv/user_sram_exec/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
@@ -51,32 +51,32 @@
vvp: ${PATTERN:=.vvp}
%.vvp: %_tb.v
- ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_sram_exec.c -o user_sram_exec.o
+ ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) ${PATTERN}.c -o ${PATTERN}.o
${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
- ${GCC_PREFIX}-gcc -o user_sram_exec.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_sram_exec.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
- ${GCC_PREFIX}-objcopy -O verilog user_sram_exec.elf user_sram_exec.hex
- ${GCC_PREFIX}-objdump -D user_sram_exec.elf > user_sram_exec.dump
- rm crt.o user_sram_exec.o
+ ${GCC_PREFIX}-gcc -o ${PATTERN}.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld ${PATTERN}.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+ ${GCC_PREFIX}-objcopy -O verilog ${PATTERN}.elf ${PATTERN}.hex
+ ${GCC_PREFIX}-objdump -D ${PATTERN}.elf > ${PATTERN}.dump
+ rm crt.o ${PATTERN}.o
ifeq ($(SIM),RTL)
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DSIM -DRISC_BOOT -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DRISC_BOOT -DSIM -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \
$< -o $@
endif
else
ifeq ($(DUMP),OFF)
- iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
else
- iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+ iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DRISC_BOOT -DGL -I $(PDK_PATH) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
$< -o $@
diff --git a/verilog/dv/user_sram_exec/user_sram_exec.c b/verilog/dv/user_sram_exec/user_sram_exec.c
index 3f36137..0f0fa12 100644
--- a/verilog/dv/user_sram_exec/user_sram_exec.c
+++ b/verilog/dv/user_sram_exec/user_sram_exec.c
@@ -17,29 +17,18 @@
#define SC_SIM_OUTPORT (0xf0000000)
-#define uint32_t long
-#define uint16_t int
+#include "int_reg_map.h"
+#include "common_misc.h"
+#include "common_bthread.h"
-#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID
-#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0
-#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1
-#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask
-#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt
-#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel
-#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0
-#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1
-#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2
-#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3
-#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4
-#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5
// -------------------------------------------------------------------------
// Test copying code into SRAM and running it from there.
// -------------------------------------------------------------------------
void test_function()
{
- reg_mprj_globl_soft2 = 0x33445566; // Sig-2
- reg_mprj_globl_soft3 = 0x44556677; // Sig-3
+ reg_glbl_soft_reg_2 = 0x33445566; // Sig-2
+ reg_glbl_soft_reg_3 = 0x44556677; // Sig-3
return;
}
@@ -50,23 +39,31 @@
uint16_t *src_ptr;
uint16_t *dst_ptr;
+ // GLBL_CFG_MAIL_BOX used as mail box, each core update boot up handshake at 8 bit
+ // bit[7:0] - core-0
+ // bit[15:8] - core-1
+ // bit[23:16] - core-2
+ // bit[31:24] - core-3
+
+ reg_glbl_mail_box = 0x1 << (bthread_get_core_id() * 8); // Start of Main
src_ptr = &test_function;
dst_ptr = func;
- reg_mprj_globl_soft0 = 0x11223344; // Sig-0
+ reg_glbl_soft_reg_0 = 0x11223344; // Sig-0
while (src_ptr < &main) {
*(dst_ptr++) = *(src_ptr++);
}
// Call the routine in SRAM
- reg_mprj_globl_soft1 = 0x22334455; // Sig-1
+ reg_glbl_soft_reg_1 = 0x22334455; // Sig-1
((void(*)())func)();
- reg_mprj_globl_soft4 = 0x55667788; // Sig-4
- reg_mprj_globl_soft5 = 0x66778899; // Sig-5
+ reg_glbl_soft_reg_4 = 0x55667788; // Sig-4
+ reg_glbl_soft_reg_5 = 0x66778899; // Sig-5
// Signal end of test
+ reg_glbl_mail_box = 0xff << (bthread_get_core_id() * 8); // Start of Main
}
diff --git a/verilog/dv/user_sram_exec/user_sram_exec_tb.v b/verilog/dv/user_sram_exec/user_sram_exec_tb.v
index 555fc4b..6e2bcf4 100644
--- a/verilog/dv/user_sram_exec/user_sram_exec_tb.v
+++ b/verilog/dv/user_sram_exec/user_sram_exec_tb.v
@@ -65,79 +65,45 @@
`timescale 1 ns / 1 ns
`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
-module user_sram_exec_tb;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
+`define TB_HEX "user_sram_exec.hex"
+`define TB_TOP user_sram_exec_tb
+module `TB_TOP;
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
+parameter real CLK1_PERIOD = 25;
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
- integer d_risc_id;
-
-
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
+`include "user_tasks.sv"
`ifdef WFDUMP
initial begin
$dumpfile("simx.vcd");
- $dumpvars(1, user_sram_exec_tb);
- $dumpvars(1, user_sram_exec_tb.u_top);
- $dumpvars(0, user_sram_exec_tb.u_top.u_riscv_top);
+ $dumpvars(1, `TB_TOP);
+ $dumpvars(1, `TB_TOP.u_top);
+ $dumpvars(0, `TB_TOP.u_top.u_riscv_top);
end
`endif
initial begin
$value$plusargs("risc_core_id=%d", d_risc_id);
+ init();
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
// Remove Wb Reset
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+ //wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
repeat (2) @(posedge clock);
#1;
// Remove all the reset
if(d_risc_id == 0) begin
$display("STATUS: Working with Risc core 0");
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F);
end else if(d_risc_id == 1) begin
$display("STATUS: Working with Risc core 1");
wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F);
@@ -150,24 +116,21 @@
end
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (30) begin
- repeat (1000) @(posedge clock);
- // $display("+1000 cycles");
- end
+ wait_riscv_boot();
+ wait_riscv_exit();
$display("Monitor: Reading Back the expected value");
// User RISC core expect to write these value in global
// register, read back and decide on pass fail
// 0x30000018 = 0x11223344;
- // 0x3000001C = 0x22334455;
- // 0x30000020 = 0x33445566;
- // 0x30000024 = 0x44556677;
- // 0x30000028 = 0x55667788;
- // 0x3000002C = 0x66778899;
+ // 0x3000001C = 0x22334455;
+ // 0x30000020 = 0x33445566;
+ // 0x30000024 = 0x44556677;
+ // 0x30000028 = 0x55667788;
+ // 0x3000002C = 0x66778899;
- test_fail = 0;
+ test_fail = 0;
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455);
wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566);
@@ -177,101 +140,53 @@
- $display("###################################################");
- if(test_fail == 0) begin
- `ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Passed");
- `else
- $display("Monitor: Standalone User Risc Boot (RTL) Passed");
- `endif
- end else begin
- `ifdef GL
- $display("Monitor: Standalone User Risc Boot (GL) Failed");
- `else
- $display("Monitor: Standalone User Risc Boot (RTL) Failed");
- `endif
+ $display("###################################################");
+ if(test_fail == 0) begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Passed");
+ `else
+ $display("Monitor: %m (RTL) Passed");
+ `endif
+ end else begin
+ `ifdef GL
+ $display("Monitor: %m (GL) Failed");
+ `else
+ $display("Monitor: %m (RTL) Failed");
+ `endif
end
- $display("###################################################");
+ $display("###################################################");
$finish;
end
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
-assign io_in[0] = 1'b1; // RESET
-assign io_in[16] = 1'b0 ; // SPIS SCK
+assign io_in[5] = 1'b1; // RESET
+assign io_in[21] = 1'b0 ; // SPIS SCK
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
- end
-`endif
//------------------------------------------------------
// Integrate the Serial flash with qurd support to
// user core using the gpio pads
// ----------------------------------------------------
- wire flash_clk = io_out[24];
- wire flash_csb = io_out[25];
+ wire flash_clk = io_out[28];
+ wire flash_csb = io_out[29];
// Creating Pad Delay
- wire #1 io_oeb_29 = io_oeb[29];
- wire #1 io_oeb_30 = io_oeb[30];
- wire #1 io_oeb_31 = io_oeb[31];
- wire #1 io_oeb_32 = io_oeb[32];
- tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
- tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
- tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
- tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+ wire #1 io_oeb_29 = io_oeb[33];
+ wire #1 io_oeb_30 = io_oeb[34];
+ wire #1 io_oeb_31 = io_oeb[35];
+ wire #1 io_oeb_32 = io_oeb[36];
+ tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[33] : 1'bz;
+ tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[34] : 1'bz;
+ tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[35] : 1'bz;
+ tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[36] : 1'bz;
- assign io_in[29] = flash_io0;
- assign io_in[30] = flash_io1;
- assign io_in[31] = flash_io2;
- assign io_in[32] = flash_io3;
+ assign io_in[33] = flash_io0;
+ assign io_in[34] = flash_io1;
+ assign io_in[35] = flash_io2;
+ assign io_in[36] = flash_io3;
// Quard flash
- s25fl256s #(.mem_file_name("user_sram_exec.hex"),
+ s25fl256s #(.mem_file_name(`TB_HEX),
.otp_file_name("none"),
.TimingModel("S25FL512SAGMFI010_F_30pF"))
u_spi_flash_256mb (
@@ -288,137 +203,6 @@
);
-
-
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/user_sspi/Makefile b/verilog/dv/user_sspi/Makefile
index ddc2549..9aa2e3c 100644
--- a/verilog/dv/user_sspi/Makefile
+++ b/verilog/dv/user_sspi/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v
index 11f2901..1650d50 100644
--- a/verilog/dv/user_sspi/user_sspi_tb.v
+++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -71,56 +71,17 @@
`define TB_GLBL user_sspi_tb
-
-
-
module user_sspi_tb;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
-
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
+`include "user_tasks.sv"
reg [1:0] spi_chip_no;
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
-
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
`ifdef WFDUMP
initial begin
@@ -391,61 +352,23 @@
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: SPI Master Mode (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: SPI Master Mode (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: SPI Master Mode (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: SPI Master Mode (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
-
// SSPI Slave I/F
-assign io_in[0] = 1'b1; // RESET
+assign io_in[5] = 1'b1; // RESET
`ifndef GL // Drive Power for Hold Fix Buf
@@ -529,137 +452,6 @@
end
endtask
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- //$display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- user_sspi_tb.test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
`include "sspi_task.v"
-`include "user_tasks.sv"
endmodule
`default_nettype wire
diff --git a/verilog/dv/user_timer/Makefile b/verilog/dv/user_timer/Makefile
index 6479120..0bf3da4 100644
--- a/verilog/dv/user_timer/Makefile
+++ b/verilog/dv/user_timer/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v
index d39122d..62aa667 100644
--- a/verilog/dv/user_timer/user_timer_tb.v
+++ b/verilog/dv/user_timer/user_timer_tb.v
@@ -72,55 +72,22 @@
module user_timer_tb;
- reg clock;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+parameter real CLK1_PERIOD = 25;
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
-
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
+`include "user_tasks.sv"
- reg [1:0] spi_chip_no;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
reg [31:0] OneUsPeriod;
- integer test_step;
- wire clock_mon;
+ integer test_step;
+ wire clock_mon;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
initial begin
OneUsPeriod = 1;
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
end
`ifdef WFDUMP
@@ -145,36 +112,36 @@
repeat (2) @(posedge clock);
#1;
- // Remove the reset
+ // Remove the reset
// Remove WB and SPI/UART Reset, Keep CORE under Reset
- //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
+ //wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F);
// config 1us based on system clock - 1000/25ns = 40
- wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_GLBL,39);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_GLBL,39);
// Enable Timer Interrupt
- wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'h007);
+ wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'h007);
test_fail = 0;
- repeat (200) @(posedge clock);
- wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 10
+ repeat (200) @(posedge clock);
+ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 10
- $display("Step-1, Timer-0: 1us * 100 = 100us; Timer-1: 200us; Timer-2: 300us");
- test_step = 1;
- wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0001_0063);
- wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0001_00C7);
- wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0001_012B);
- timer_monitor(OneUsPeriod*100,OneUsPeriod*200,OneUsPeriod*300);
+ $display("Step-1, Timer-0: 1us * 100 = 100us; Timer-1: 200us; Timer-2: 300us");
+ test_step = 1;
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0001_0063);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0001_00C7);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0001_012B);
+ timer_monitor(OneUsPeriod*100,OneUsPeriod*200,OneUsPeriod*300);
$display("Checking the Timer Interrupt generation and clearing");
// Disable the Timer - To avoid multiple interrupt generation
// during status check and interrupt clearing
- wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0000_0063);
- wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0000_00C7);
- wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0000_012B);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0000_0063);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0000_00C7);
+ wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0000_012B);
- wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data);
+ wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data);
if((u_top.u_pinmux.irq_lines[2:0] == 3'b111) && (read_data[2:0] == 3'b111)) begin
$display("STATUS: Timer Interrupt detected ");
// Clearing the Timer Interrupt
@@ -228,23 +195,21 @@
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Timer Mode (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Timer Mode (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Timer Mode (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Timer Mode (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
wire timer_intr0 = u_top.u_pinmux.timer_intr[0];
wire timer_intr1 = u_top.u_pinmux.timer_intr[1];
@@ -297,49 +262,8 @@
end
endtask
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
-assign io_in[0] = 1'b1; // RESET
-
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
- end
-`endif
+assign io_in[5] = 1'b1; // RESET
@@ -352,137 +276,5 @@
end
endtask
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- //$display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- `TB_GLBL.test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-
-`include "user_tasks.sv"
endmodule
`default_nettype wire
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index fc9b113..70af457 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
@@ -90,6 +90,6 @@
# ---- Clean ----
clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.o *.dump
.PHONY: clean hex all
diff --git a/verilog/dv/user_uart/user_uart.c b/verilog/dv/user_uart/user_uart.c
index b19a157..c9f5dd3 100644
--- a/verilog/dv/user_uart/user_uart.c
+++ b/verilog/dv/user_uart/user_uart.c
@@ -16,7 +16,7 @@
// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
// //////////////////////////////////////////////////////////////////////////
#define SC_SIM_OUTPORT (0xf0000000)
-#include "../c_func/inc/int_reg_map.h"
+#include "int_reg_map.h"
#include "common_misc.h"
#include "common_bthread.h"
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index e1db54f..8029645 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -82,33 +82,13 @@
`define TB_HEX "user_uart.hex"
`define TB_TOP user_uart_tb
module `TB_TOP;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
+`include "user_tasks.sv"
-reg clock ;
-reg wb_rst_i ;
-reg power1, power2;
-reg power3, power4;
-
-reg wbd_ext_cyc_i; // strobe/request
-reg wbd_ext_stb_i; // strobe/request
-reg [31:0] wbd_ext_adr_i; // address
-reg wbd_ext_we_i; // write
-reg [31:0] wbd_ext_dat_i; // data output
-reg [3:0] wbd_ext_sel_i; // byte enable
-
-wire [31:0] wbd_ext_dat_o; // data input
-wire wbd_ext_ack_o; // acknowlegement
-wire wbd_ext_err_o; // error
-
-// User I/O
-wire [37:0] io_oeb ;
-wire [37:0] io_out ;
-wire [37:0] io_in ;
-
-wire [37:0] mprj_io ;
-wire [7:0] mprj_io_0 ;
-reg test_fail ;
-reg [31:0] read_data ;
//----------------------------------
// Uart Configuration
// ---------------------------------
@@ -127,25 +107,10 @@
reg [7:0] uart_write_data [0:39];
reg uart_fifo_enable ; // fifo mode disable
- integer d_risc_id;
integer i,j;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
`ifdef WFDUMP
initial begin
@@ -211,7 +176,7 @@
uart_stick_parity, uart_timeout, uart_divisor);
- wait_riscv_boot(d_risc_id);
+ wait_riscv_boot();
for (i=0; i<40; i=i+1)
@@ -252,15 +217,15 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User UART Test (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone User UART Test (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User UART Test (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone User UART Test (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
@@ -269,57 +234,12 @@
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
assign io_in[5] = 1'b1; // RESET
assign io_in[21] = 1'b0; // CLOCK
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
- end
-`endif
-
-
//------------------------------------------------------
// Integrate the Serial flash with qurd support to
// user core using the gpio pads
@@ -377,135 +297,6 @@
);
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- `TB_TOP.test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-`include "user_tasks.sv"
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/user_uart1/Makefile b/verilog/dv/user_uart1/Makefile
index 280fed2..0b2add5 100644
--- a/verilog/dv/user_uart1/Makefile
+++ b/verilog/dv/user_uart1/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/user_uart1/user_uart1.c b/verilog/dv/user_uart1/user_uart1.c
index e680062..c06b431 100644
--- a/verilog/dv/user_uart1/user_uart1.c
+++ b/verilog/dv/user_uart1/user_uart1.c
@@ -16,7 +16,7 @@
// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org>
// //////////////////////////////////////////////////////////////////////////
#define SC_SIM_OUTPORT (0xf0000000)
-#include "../c_func/inc/int_reg_map.h"
+#include "int_reg_map.h"
#include "common_misc.h"
#include "common_bthread.h"
diff --git a/verilog/dv/user_uart1/user_uart1_tb.v b/verilog/dv/user_uart1/user_uart1_tb.v
index cab2731..2d1c2b2 100644
--- a/verilog/dv/user_uart1/user_uart1_tb.v
+++ b/verilog/dv/user_uart1/user_uart1_tb.v
@@ -81,36 +81,17 @@
`define TB_HEX "user_uart1.hex"
`define TB_TOP user_uart1_tb
module `TB_TOP;
+parameter real CLK1_PERIOD = 20; // 50Mhz
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
-reg clock ;
-reg wb_rst_i ;
-reg power1, power2;
-reg power3, power4;
+`include "user_tasks.sv"
-reg wbd_ext_cyc_i; // strobe/request
-reg wbd_ext_stb_i; // strobe/request
-reg [31:0] wbd_ext_adr_i; // address
-reg wbd_ext_we_i; // write
-reg [31:0] wbd_ext_dat_i; // data output
-reg [3:0] wbd_ext_sel_i; // byte enable
-
-wire [31:0] wbd_ext_dat_o; // data input
-wire wbd_ext_ack_o; // acknowlegement
-wire wbd_ext_err_o; // error
-
-// User I/O
-wire [37:0] io_oeb ;
-wire [37:0] io_out ;
-wire [37:0] io_in ;
-
-wire [37:0] mprj_io ;
-wire [7:0] mprj_io_0 ;
-reg test_fail ;
-reg [31:0] read_data ;
//----------------------------------
// Uart Configuration
// ---------------------------------
-reg [1:0] uart_data_bit ;
+reg [1:0] uart_data_bit ;
reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit;
reg uart_stick_parity ; // 1: force even parity
reg uart_parity_en ; // parity enable
@@ -125,25 +106,9 @@
reg [7:0] uart_write_data [0:39];
reg uart_fifo_enable ; // fifo mode disable
- integer d_risc_id;
integer i,j;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
`ifdef WFDUMP
initial begin
@@ -207,7 +172,7 @@
uart_stick_parity, uart_timeout, uart_divisor);
- wait_riscv_boot(d_risc_id);
+ wait_riscv_boot();
for (i=0; i<40; i=i+1)
@@ -248,15 +213,15 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User UART Test (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone User UART Test (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User UART Test (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone User UART Test (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
@@ -265,45 +230,6 @@
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
-
// SSPI Slave I/F
assign io_in[5] = 1'b1; // RESET
assign io_in[21] = 1'b0; // CLOCK
@@ -373,135 +299,6 @@
);
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- `TB_TOP.test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
-`include "user_tasks.sv"
endmodule
`include "s25fl256s.sv"
`default_nettype wire
diff --git a/verilog/dv/user_uart_master/Makefile b/verilog/dv/user_uart_master/Makefile
index b54f457..f325cea 100644
--- a/verilog/dv/user_uart_master/Makefile
+++ b/verilog/dv/user_uart_master/Makefile
@@ -27,7 +27,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v
index 2d909f4..33277cb 100644
--- a/verilog/dv/user_uart_master/user_uart_master_tb.v
+++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -70,33 +70,17 @@
`include "uart_agent.v"
`include "user_params.svh"
-module user_uart_master_tb;
+`define TB_TOP user_uart_master_tb
-reg clock ;
-reg wb_rst_i ;
-reg power1, power2;
-reg power3, power4;
+module `TB_TOP;
-reg wbd_ext_cyc_i; // strobe/request
-reg wbd_ext_stb_i; // strobe/request
-reg [31:0] wbd_ext_adr_i; // address
-reg wbd_ext_we_i; // write
-reg [31:0] wbd_ext_dat_i; // data output
-reg [3:0] wbd_ext_sel_i; // byte enable
+parameter real CLK1_PERIOD = 25;
+parameter real CLK2_PERIOD = 2.5;
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
-wire [31:0] wbd_ext_dat_o; // data input
-wire wbd_ext_ack_o; // acknowlegement
-wire wbd_ext_err_o; // error
+`include "user_tasks.sv"
-// User I/O
-wire [37:0] io_oeb ;
-wire [37:0] io_out ;
-wire [37:0] io_in ;
-
-wire [37:0] mprj_io ;
-wire [7:0] mprj_io_0 ;
-reg test_fail ;
-reg [31:0] read_data ;
//----------------------------------
// Uart Configuration
// ---------------------------------
@@ -115,44 +99,24 @@
reg [7:0] uart_write_data [0:39];
reg uart_fifo_enable ; // fifo mode disable
-reg [127:0] la_data_in;
reg flag;
reg [15:0] strap_in;
integer i,j;
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
- always #12.5 clock <= (clock === 1'b0);
+`ifdef WFDUMP
+initial begin
+ $dumpfile("risc_boot.vcd");
+ $dumpvars(0, `TB_TOP);
+end
+`endif
- initial begin
- clock = 0;
- la_data_in = 1;
- end
-
- `ifdef WFDUMP
- initial begin
- $dumpfile("risc_boot.vcd");
- $dumpvars(0, user_uart_master_tb);
- end
- `endif
-
- initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
initial
begin
strap_in = 0;
- strap_in[`PSTRAP_UARTM_CFG] = 0; // uart master config control - load from LA
+ strap_in[`PSTRAP_UARTM_CFG] = 2'b11; // uart master config control - load from LA
apply_strap(strap_in);
uart_data_bit = 2'b11;
@@ -189,9 +153,8 @@
end
-
// Remove Wb Reset
- uartm_reg_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+ //uartm_reg_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
repeat (2) @(posedge clock);
#1;
@@ -218,15 +181,15 @@
$display("###################################################");
if(test_fail == 0) begin
`ifdef GL
- $display("Monitor: Standalone User UART Master (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Standalone User Uart Master (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: Standalone User Uart Master (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: Standalone User Uart Master (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
@@ -235,54 +198,10 @@
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock), // System clock
- .user_clock2 (1'b1), // Real-time clock
- .wb_rst_i (wb_rst_i), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in (la_data_in) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
assign io_in[5] = 1'b1; // RESET
assign io_in[21] = 1'b0; // CLOCK
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
- end
-`endif
-
//---------------------------
// UART Agent integration
@@ -301,6 +220,5 @@
`include "uart_master_tasks.sv"
-`include "user_tasks.sv"
endmodule
`default_nettype wire
diff --git a/verilog/dv/user_usb/Makefile b/verilog/dv/user_usb/Makefile
index 4422ccd..8ed7903 100644
--- a/verilog/dv/user_usb/Makefile
+++ b/verilog/dv/user_usb/Makefile
@@ -28,7 +28,7 @@
export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog
## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/common/firmware
GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v
index b63b948..7c0dac5 100644
--- a/verilog/dv/user_usb/user_usb_tb.v
+++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -52,40 +52,14 @@
module user_usb_tb;
-parameter USB_HPER = 10.4167; // 48Mhz Half cycle
-parameter USER2_HPER = 2.7777; // 180Mhz Half cycle
+parameter CLK1_PERIOD = 10.4167; // 48Mhz Half cycle
+parameter CLK2_PERIOD = 2.7777; // 180Mhz Half cycle
+parameter real IPLL_PERIOD = 5.008;
+parameter real XTAL_PERIOD = 6;
- reg clock;
- reg user_clock2;
- reg usb_48mhz_clk;
- reg wb_rst_i;
- reg power1, power2;
- reg power3, power4;
+`include "user_tasks.sv"
- reg wbd_ext_cyc_i; // strobe/request
- reg wbd_ext_stb_i; // strobe/request
- reg [31:0] wbd_ext_adr_i; // address
- reg wbd_ext_we_i; // write
- reg [31:0] wbd_ext_dat_i; // data output
- reg [3:0] wbd_ext_sel_i; // byte enable
-
- wire [31:0] wbd_ext_dat_o; // data input
- wire wbd_ext_ack_o; // acknowlegement
- wire wbd_ext_err_o; // error
-
- // User I/O
- wire [37:0] io_oeb;
- wire [37:0] io_out;
- wire [37:0] io_in;
-
-
- reg [1:0] spi_chip_no;
-
- wire gpio;
- wire [37:0] mprj_io;
- wire [7:0] mprj_io_0;
- reg test_fail;
- reg [31:0] read_data;
+ wire usb_48mhz_clk;
//-----------------------------------
// Register Interface
@@ -99,38 +73,8 @@
reg [31:0] RegBank [0:15];
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
- always #12.5 clock <= (clock === 1'b0);
-
- // 48Mhz clock generation
- always begin
- #USB_HPER usb_48mhz_clk = 1'b0;
- #USB_HPER usb_48mhz_clk = 1'b1;
- end
-
- // USER Clock generation
- always begin
- #USER2_HPER user_clock2 = 1'b0;
- #USER2_HPER user_clock2 = 1'b1;
- end
-
- initial begin
- clock = 0;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- end
- initial begin
- wb_rst_i <= 1'b1;
- #100;
- wb_rst_i <= 1'b0; // Release reset
- end
+ assign usb_48mhz_clk = clock;
`ifdef WFDUMP
initial begin
@@ -144,7 +88,7 @@
end
`endif
- always@(posedge wb_rst_i or posedge usb_48mhz_clk)
+ always@(posedge wb_rst_i or posedge clock)
begin
if(wb_rst_i == 1'b1) begin
usbd_reg_rdata = 'h0;
@@ -166,7 +110,7 @@
initial begin
$dumpon;
- init();
+ init();
#200; // Wait for reset removal
repeat (10) @(posedge clock);
$display("Monitor: Standalone User Risc Boot Test Started");
@@ -201,73 +145,29 @@
if(test_control.error_count == 0) begin
`ifdef GL
- $display("Monitor: USB Mode (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: USB Mode (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
end else begin
`ifdef GL
- $display("Monitor: USB Mode (GL) Failed");
+ $display("Monitor: %m (GL) Failed");
`else
- $display("Monitor: USB Mode (RTL) Failed");
+ $display("Monitor: %m (RTL) Failed");
`endif
end
$display("###################################################");
$finish;
end
-wire USER_VDD1V8 = 1'b1;
-wire VSS = 1'b0;
-
-user_project_wrapper u_top(
-`ifdef USE_POWER_PINS
- .vccd1(USER_VDD1V8), // User area 1 1.8V supply
- .vssd1(VSS), // User area 1 digital ground
-`endif
- .wb_clk_i (clock ), // System clock
- .user_clock2 (user_clock2 ), // Real-time clock
- .wb_rst_i (wb_rst_i ), // Regular Reset signal
-
- .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request
- .wbs_stb_i (wbd_ext_stb_i), // strobe/request
- .wbs_adr_i (wbd_ext_adr_i), // address
- .wbs_we_i (wbd_ext_we_i), // write
- .wbs_dat_i (wbd_ext_dat_i), // data output
- .wbs_sel_i (wbd_ext_sel_i), // byte enable
-
- .wbs_dat_o (wbd_ext_dat_o), // data input
- .wbs_ack_o (wbd_ext_ack_o), // acknowlegement
-
-
- // Logic Analyzer Signals
- .la_data_in ('1) ,
- .la_data_out (),
- .la_oenb ('0),
-
-
- // IOs
- .io_in (io_in) ,
- .io_out (io_out) ,
- .io_oeb (io_oeb) ,
-
- .user_irq ()
-
-);
// SSPI Slave I/F
-assign io_in[0] = 1'b1; // RESET
+assign io_in[5] = 1'b1; // RESET
usb_agent u_usb_agent();
test_control test_control();
-`ifndef GL // Drive Power for Hold Fix Buf
- // All standard cell need power hook-up for functionality work
- initial begin
-
- end
-`endif
-
// Drive USB Pads
//
tri usbd_txdp = (io_oeb[24] == 1'b0) ? io_out[24] : 1'bz;
@@ -283,7 +183,7 @@
usb1d_top u_usb_top(
- .clk_i (usb_48mhz_clk),
+ .clk_i (clock),
.rstn_i (!wb_rst_i),
// USB PHY Interface
@@ -421,137 +321,7 @@
end
endtask
-task wb_user_core_write;
-input [31:0] address;
-input [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h1; // write
- wbd_ext_dat_i =data; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read;
-input [31:0] address;
-output [31:0] data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- repeat (1) @(negedge clock);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- //$display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- repeat (2) @(posedge clock);
-end
-endtask
-
-task wb_user_core_read_check;
-input [31:0] address;
-output [31:0] data;
-input [31:0] cmp_data;
-reg [31:0] data;
-begin
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_adr_i =address; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='0; // data output
- wbd_ext_sel_i ='hF; // byte enable
- wbd_ext_cyc_i ='h1; // strobe/request
- wbd_ext_stb_i ='h1; // strobe/request
- wait(wbd_ext_ack_o == 1);
- data = wbd_ext_dat_o;
- repeat (1) @(posedge clock);
- #1;
- wbd_ext_cyc_i ='h0; // strobe/request
- wbd_ext_stb_i ='h0; // strobe/request
- wbd_ext_adr_i ='h0; // address
- wbd_ext_we_i ='h0; // write
- wbd_ext_dat_i ='h0; // data output
- wbd_ext_sel_i ='h0; // byte enable
- if(data !== cmp_data) begin
- $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
- user_usb_tb.test_fail = 1;
- end else begin
- $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data);
- end
- repeat (2) @(posedge clock);
-end
-endtask
-
-
-`ifdef GL
-
-wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i;
-wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o;
-wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o;
-wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i;
-
-wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs;
-wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack;
-wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr;
-wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr;
-wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata;
-wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata;
-wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be;
-
-`endif
-
-/**
-`ifdef GL
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-
-`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top
-
-always@(posedge `RISC_CORE.wb_clk) begin
- if(`RISC_CORE.wbd_imem_ack_i)
- $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
- if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
- if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
- $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
-end
-
-`endif
-**/
`include "tests/usb_test1.v"
`include "tests/usb_test2.v"
-`include "user_tasks.sv"
endmodule
`default_nettype wire
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index 3ec839e..c617d00 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile
@@ -25,6 +25,7 @@
CONFIG = caravel_user_project
TOOLS?=/opt/riscv32i/
+export USER_FIRMWARE_PATH = $(DESIGNS)/verilog/dv/common/firmware
########################################################
#include $(MCW_ROOT)/verilog/dv/make/env.makefile
########################################################
@@ -129,6 +130,7 @@
-I$(VERILOG_PATH)/dv/generated \
-I$(VERILOG_PATH)/dv/ \
-I$(VERILOG_PATH)/common \
+ -I$(USER_FIRMWARE_PATH) \
$(CPUFLAGS) \
-Wl,-Bstatic,-T,$(LINKER_SCRIPT),--strip-debug \
-ffreestanding -nostdlib -o $@ $(SOURCE_FILES) $<
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index 303eb20..4c7a868 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c
@@ -18,7 +18,7 @@
// This include is relative to $CARAVEL_PATH (see Makefile)
#include <defs.h>
#include <stub.c>
-#include "../c_func/inc/ext_reg_map.h"
+#include "ext_reg_map.h"
@@ -97,7 +97,7 @@
// Remove Reset
reg_glbl_cfg0 = 0x01f;
- if (reg_glbl_chip_id != 0x82681501) bFail = 1;
+ if (reg_glbl_chip_id != 0x82684501) bFail = 1;
if (bFail == 1) reg_mprj_datal = 0xAB610000;
// write software write & read Register
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index ba2cae8..271e092 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -49,15 +49,15 @@
initial begin
$dumpfile("simx.vcd");
$dumpvars(1, wb_port_tb);
- $dumpvars(1, wb_port_tb.uut);
- $dumpvars(1, wb_port_tb.uut.mgmt_buffers);
- $dumpvars(1, wb_port_tb.uut.housekeeping);
- $dumpvars(1, wb_port_tb.uut.pll);
- $dumpvars(1, wb_port_tb.uut.soc);
- $dumpvars(1, wb_port_tb.uut.soc.core);
- $dumpvars(1, wb_port_tb.uut.mprj);
- $dumpvars(1, wb_port_tb.uut.mprj.u_wb_host);
- //$dumpvars(2, wb_port_tb.uut.mprj.u_pinmux);
+ $dumpvars(1, wb_port_tb.u_top);
+ $dumpvars(1, wb_port_tb.u_top.mgmt_buffers);
+ $dumpvars(1, wb_port_tb.u_top.housekeeping);
+ $dumpvars(1, wb_port_tb.u_top.pll);
+ $dumpvars(1, wb_port_tb.u_top.soc);
+ $dumpvars(1, wb_port_tb.u_top.soc.core);
+ $dumpvars(1, wb_port_tb.u_top.mprj);
+ $dumpvars(1, wb_port_tb.u_top.mprj.u_wb_host);
+ //$dumpvars(2, wb_port_tb.u_top.mprj.u_pinmux);
end
`endif
@@ -71,9 +71,9 @@
$display("%c[1;31m",27);
$display ("##########################################################");
`ifdef GL
- $display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
+ $display ("Monitor: Timeout, %m (GL) Failed");
`else
- $display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");
+ $display ("Monitor: Timeout, %m (RTL) Failed");
`endif
$display ("##########################################################");
$display("%c[0m",27);
@@ -81,24 +81,23 @@
end
initial begin
+ init();
wait(checkbits == 16'h AB60);
$display("Monitor: MPRJ-Logic WB Started");
wait(checkbits == 16'h AB6A);
$display ("##########################################################");
`ifdef GL
- $display("Monitor: Mega-Project WB (GL) Passed");
+ $display("Monitor: %m (GL) Passed");
`else
- $display("Monitor: Mega-Project WB (RTL) Passed");
+ $display("Monitor: %m (RTL) Passed");
`endif
$display ("##########################################################");
$finish;
end
initial begin
- RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
#2000;
- RSTB <= 1'b1; // Release reset
#170000;
CSB = 1'b0; // CSB can be released
end
@@ -133,7 +132,7 @@
wire USER_VDD1V8 = power4;
wire VSS = 1'b0;
- caravel uut (
+ caravel u_top (
.vddio (VDD3V3),
.vssio (VSS),
.vdda (VDD3V3),
@@ -174,5 +173,7 @@
initial begin
end
`endif
+
+`include "caravel_task.sv"
endmodule
`default_nettype wire
diff --git a/verilog/gl/pinmux_top.v.gz b/verilog/gl/pinmux_top.v.gz
index 72c7b5e..bcb11f4 100644
--- a/verilog/gl/pinmux_top.v.gz
+++ b/verilog/gl/pinmux_top.v.gz
Binary files differ
diff --git a/verilog/gl/uart_i2c_usb_spi_top.v.gz b/verilog/gl/uart_i2c_usb_spi_top.v.gz
index 592081c..f7ca1de 100644
--- a/verilog/gl/uart_i2c_usb_spi_top.v.gz
+++ b/verilog/gl/uart_i2c_usb_spi_top.v.gz
Binary files differ
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index 3bc912f..b39bb63 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ
diff --git a/verilog/gl/wb_host.v.gz b/verilog/gl/wb_host.v.gz
index e7d0074..782aa97 100644
--- a/verilog/gl/wb_host.v.gz
+++ b/verilog/gl/wb_host.v.gz
Binary files differ
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 90cefb2..1779d63 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -3,9 +3,9 @@
+incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes
+incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes
+incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/includes
-+incdir+$(USER_PROJECT_VERILOG)/dv/bfm
-+incdir+$(USER_PROJECT_VERILOG)/dv/model
-+incdir+$(USER_PROJECT_VERILOG)/dv/agents
++incdir+$(USER_PROJECT_VERILOG)/dv/common/bfm
++incdir+$(USER_PROJECT_VERILOG)/dv/common/model
++incdir+$(USER_PROJECT_VERILOG)/dv/common/agents
$(USER_PROJECT_VERILOG)/rtl/user_reg_map.v
-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_top.sv
-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv
@@ -68,7 +68,8 @@
-v $(USER_PROJECT_VERILOG)/rtl/lib/ser_shift.sv
-v $(USER_PROJECT_VERILOG)/rtl/digital_core/src/glbl_cfg.sv
-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_host.sv
--v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_reset_fsm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wbh_reset_fsm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wbh_reg.sv
-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/sspis_top.sv
-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/sspis_if.sv
-v $(USER_PROJECT_VERILOG)/rtl/sspis/src/spi2wb.sv
@@ -78,7 +79,6 @@
-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_arb.sv
-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_slave_port.sv
-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_interconnect.sv
-
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_hdu.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_tdu.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/core/pipeline/ycr_ipic.sv
diff --git a/verilog/rtl/digital_pll/src/digital_pll.v b/verilog/rtl/digital_pll/src/digital_pll.v
index a4f189b..79cb52e 100644
--- a/verilog/rtl/digital_pll/src/digital_pll.v
+++ b/verilog/rtl/digital_pll/src/digital_pll.v
@@ -15,8 +15,12 @@
/*****************************************************************
+Formula clock period: 1.168 + (bcount * 0.012)
-Offset bcount 4x clock period clock period (ns) clock (Mhz)
+Example for bcount: 10
+ clock period = 1.168 + (10 *0.012) = 1.288
+
+Offset bcount clock period 4xclock period (ns) clock (Mhz)
1.168 0 1.168 4.672 214.041095890411
1.168 1 1.18 4.72 211.864406779661
1.168 2 1.192 4.768 209.731543624161
diff --git a/verilog/rtl/digital_pll/src/digital_pll_controller.v b/verilog/rtl/digital_pll/src/digital_pll_controller.v
index ae13d9d..73b5d05 100644
--- a/verilog/rtl/digital_pll/src/digital_pll_controller.v
+++ b/verilog/rtl/digital_pll/src/digital_pll_controller.v
@@ -97,40 +97,43 @@
(tint == 5'd25) ? 26'b1111101111111_1111111111111 :
26'b1111111111111_1111111111111;
- always @(posedge clock or posedge reset) begin
- if (reset == 1'b1) begin
+ always @(posedge clock or posedge reset) begin // {
+ if (reset == 1'b1) begin // {
tval <= 7'd0; // Note: trim[0] must be zero for startup to work.
oscbuf <= 3'd0;
prep <= 3'd0;
count0 <= 5'd0;
count1 <= 5'd0;
- end else begin
+ end // }
+ else begin // {
oscbuf <= {oscbuf[1:0], osc};
- if (oscbuf[2] != oscbuf[1]) begin
- count1 <= count0;
- count0 <= 5'b00001;
- prep <= {prep[1:0], 1'b1};
+ if (oscbuf[2] != oscbuf[1]) begin // {
+ count1 <= count0;
+ count0 <= 5'b00001;
+ prep <= {prep[1:0], 1'b1};
- if (prep == 3'b111) begin
- if (sum > div) begin
- if (tval < 127) begin
- tval <= tval + 1;
- end
- end else if (sum < div) begin
- if (tval > 0) begin
- tval <= tval - 1;
- end
- end
- end
- end else begin
- if (count0 != 5'b11111) begin
- count0 <= count0 + 1;
- end
- end
- end
- end
+ if (prep == 3'b111) begin // {
+ if (sum > div) begin // {
+ if (tval < 127) begin // {
+ tval <= tval + 1;
+ end // }
+ end // }
+ else if (sum < div) begin // {
+ if (tval > 0) begin // {
+ tval <= tval - 1;
+ end // }
+ end // }
+ end // }
+ end // }
+ else begin // {
+ if (count0 != 5'b11111) begin // {
+ count0 <= count0 + 1;
+ end // }
+ end // }
+ end // }
+ end // }
endmodule // digital_pll_controller
`default_nettype wire
diff --git a/verilog/rtl/lib/async_fifo.sv b/verilog/rtl/lib/async_fifo.sv
index cedffdb..fb29f42 100755
--- a/verilog/rtl/lib/async_fifo.sv
+++ b/verilog/rtl/lib/async_fifo.sv
@@ -58,7 +58,6 @@
//-------------------------------------------
// async FIFO
//-----------------------------------------------
-`timescale 1ns/1ps
module async_fifo (wr_clk,
wr_reset_n,
@@ -78,7 +77,7 @@
parameter WR_FAST = 1'b1;
parameter RD_FAST = 1'b1;
parameter FULL_DP = DP;
- parameter EMPTY_DP = 1'b0;
+ parameter EMPTY_DP = 'b0;
parameter AW = (DP == 2) ? 1 :
(DP == 4) ? 2 :
@@ -154,7 +153,7 @@
end
wire [AW:0] grey_rd_ptr_dly ;
- assign #1 grey_rd_ptr_dly = grey_rd_ptr;
+ assign grey_rd_ptr_dly = grey_rd_ptr;
// read pointer synchronizer
always @(posedge wr_clk or negedge wr_reset_n) begin
@@ -218,7 +217,7 @@
assign rd_data = (RD_FAST == 1) ? rd_data_c : rd_data_q;
wire [AW:0] grey_wr_ptr_dly ;
- assign #1 grey_wr_ptr_dly = grey_wr_ptr;
+ assign grey_wr_ptr_dly = grey_wr_ptr;
// write pointer synchronizer
always @(posedge rd_clk or negedge rd_reset_n) begin
diff --git a/verilog/rtl/lib/clk_ctl.v b/verilog/rtl/lib/clk_ctl.v
index 7e4478b..5851850 100644
--- a/verilog/rtl/lib/clk_ctl.v
+++ b/verilog/rtl/lib/clk_ctl.v
@@ -135,7 +135,7 @@
end // }
else
begin // {
- high_count <= clk_div_ratio[WD:1] + clk_div_ratio[0];
+ high_count <= clk_div_ratio[WD:1] + {{WD-1{1'b0}},clk_div_ratio[0]};
low_count <= clk_div_ratio[WD:1] + 1;
mclk_div <= ~mclk_div;
end // }
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv
index b1266b7..5dffbf8 100644
--- a/verilog/rtl/pinmux/src/glbl_reg.sv
+++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -53,6 +53,7 @@
input logic user_clock1 ,
input logic user_clock2 ,
input logic int_pll_clock ,
+ input logic cpu_clk ,
input logic xtal_clk ,
output logic usb_clk ,
@@ -61,6 +62,7 @@
// to/from Global Reset FSM
input logic [31:0] system_strap ,
output logic [31:0] strap_sticky ,
+ output logic [1:0] strap_uartm ,
// Global Reset control
@@ -97,7 +99,16 @@
input logic [2:0] timer_intr ,
- input logic [31:0] gpio_intr
+ input logic [31:0] gpio_intr ,
+
+ // Digital PLL I/F
+ output logic cfg_pll_enb , // Enable PLL
+ output logic[4:0] cfg_pll_fed_div , // PLL feedback division ratio
+ output logic cfg_dco_mode , // Run PLL in DCO mode
+ output logic[25:0] cfg_dc_trim , // External trim for DCO mode
+ output logic pll_ref_clk , // Input oscillator to match
+
+ output logic dbg_clk_mon
);
@@ -149,7 +160,7 @@
logic [31:0] reg_31; // Reserved
logic cs_int;
-
+logic [3:0] cfg_mon_sel;
assign sw_addr = reg_addr ;
assign sw_rd_en = reg_cs & !reg_wr;
@@ -298,7 +309,6 @@
glbl_rst_reg #(32'h0) u_reg_1 (
//List of Inputs
- .e_reset_n (e_reset_n ),
.s_reset_n (s_reset_n ),
.rst_in (rst_in ),
.clk (mclk ),
@@ -338,6 +348,7 @@
.data_out (reg_2 )
);
+assign cfg_mon_sel = reg_2[7:4];
assign soft_irq = reg_2[3];
assign user_irq = reg_2[2:0];
assign cfg_riscv_ctrl = reg_2[31:16];
@@ -423,6 +434,48 @@
wire [7:0] cfg_rtc_clk_ctrl = reg_6[7:0];
wire [7:0] cfg_usb_clk_ctrl = reg_6[15:8];
+//-----------------------------------------
+// Reg-7: PLL Control-1
+// PLL register we don't want to reset during system reboot
+// ----------------------------------------
+gen_32b_reg #(32'h8) u_reg_7 (
+ //List of Inputs
+ .reset_n (p_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_7 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_7 )
+ );
+
+assign cfg_pll_enb = reg_7[3];
+wire [2:0] cfg_ref_pll_div = reg_7[2:0];
+//-----------------------------------------
+// Reg-2: PLL Control-2
+// PLL register we don't want to reset during system reboot
+// ----------------------------------------
+gen_32b_reg #({1'b1,5'b00000,26'b0000000000000_1010101101001} ) u_reg_8 (
+ //List of Inputs
+ .reset_n (p_reset_n ),
+ .clk (mclk ),
+ .cs (sw_wr_en_8 ),
+ .we (wr_be ),
+ .data_in (sw_reg_wdata ),
+
+ //List of Outs
+ .data_out (reg_8 )
+ );
+
+//------------------------------------------
+// PLL Trim Value
+//-----------------------------------------
+assign cfg_dco_mode = reg_8[31];
+assign cfg_pll_fed_div = reg_8[30:26];
+assign cfg_dc_trim = reg_8[25:0];
+
+
//-------------------------------------------------
// Strap control
@@ -441,7 +494,8 @@
//List of Outs
.strap_latch (strap_latch ),
- .strap_sticky (strap_sticky)
+ .strap_sticky (strap_sticky),
+ .strap_uartm (strap_uartm)
);
@@ -693,4 +747,38 @@
.clk_div_ratio (cfg_usb_clk_ratio)
);
+// PLL Ref CLock
+
+clk_ctl #(2) u_pll_ref_clk (
+ // Outputs
+ .clk_o (pll_ref_clk ),
+ // Inputs
+ .mclk (user_clock1 ),
+ .reset_n (e_reset_n ),
+ .clk_div_ratio (cfg_ref_pll_div )
+ );
+
+// Debug clock monitor optin
+assign dbg_clk_ref = (cfg_mon_sel == 4'b000) ? user_clock1 :
+ (cfg_mon_sel == 4'b001) ? user_clock2 :
+ (cfg_mon_sel == 4'b010) ? xtal_clk :
+ (cfg_mon_sel == 4'b011) ? int_pll_clock:
+ (cfg_mon_sel == 4'b100) ? mclk :
+ (cfg_mon_sel == 4'b101) ? cpu_clk :
+ (cfg_mon_sel == 4'b110) ? usb_clk :
+ (cfg_mon_sel == 4'b111) ? rtc_clk : 1'b0;
+
+// DIv16 to debug monitor purpose
+
+clk_ctl #(3) u_dbgclk (
+ // Outputs
+ .clk_o (dbg_clk_div16 ),
+ // Inputs
+ .mclk (dbg_clk_ref ),
+ .reset_n (e_reset_n ),
+ .clk_div_ratio (4'hE )
+ );
+
+ctech_clk_buf u_clkbuf_dbg (.A (dbg_clk_div16), . X(dbg_clk_mon));
+
endmodule
diff --git a/verilog/rtl/pinmux/src/glbl_rst_reg.sv b/verilog/rtl/pinmux/src/glbl_rst_reg.sv
index cca7d0b..c0f8019 100644
--- a/verilog/rtl/pinmux/src/glbl_rst_reg.sv
+++ b/verilog/rtl/pinmux/src/glbl_rst_reg.sv
@@ -26,7 +26,6 @@
**********************************************************************************/
module glbl_rst_reg (
- input logic e_reset_n,
input logic s_reset_n,
//List of Inputs
input logic [31:0] rst_in,
@@ -41,22 +40,23 @@
parameter RESET_DEFAULT = 32'h0;
-logic [31:0] data_out_l;
-always @ (posedge clk or negedge e_reset_n) begin
- if (e_reset_n == 1'b0) begin
+logic flag;
+always @ (posedge clk or negedge s_reset_n) begin
+ if (s_reset_n == 1'b0) begin
data_out <= RESET_DEFAULT ;
- data_out_l <= 'h0 ;
- end else if (s_reset_n == 1'b0) begin
- data_out <= RESET_DEFAULT ;
- data_out_l <= rst_in ;
+ flag <= 1'b1;
end else begin
- data_out <= data_out_l;
- if(cs && we[0]) data_out_l[7:0] <= data_in[7:0];
- if(cs && we[1]) data_out_l[15:8] <= data_in[15:8];
- if(cs && we[2]) data_out_l[23:16] <= data_in[23:16];
- if(cs && we[3]) data_out_l[31:24] <= data_in[31:24];
- end
+ flag <= 1'b0;
+ if (flag == 1'b1) begin
+ data_out <= rst_in ;
+ end else begin
+ if(cs && we[0]) data_out[7:0] <= data_in[7:0];
+ if(cs && we[1]) data_out[15:8] <= data_in[15:8];
+ if(cs && we[2]) data_out[23:16] <= data_in[23:16];
+ if(cs && we[3]) data_out[31:24] <= data_in[31:24];
+ end
+ end
end
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv
index 0de5eff..0b3121f 100755
--- a/verilog/rtl/pinmux/src/pinmux_top.sv
+++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -94,10 +94,12 @@
input logic cfg_strap_pad_ctrl ,
input logic [31:0] system_strap ,
output logic [31:0] strap_sticky ,
+ output logic [1:0] strap_uartm ,
input logic user_clock1 ,
input logic user_clock2 ,
input logic int_pll_clock ,
+ input logic cpu_clk ,
output logic xtal_clk ,
output logic usb_clk ,
@@ -182,14 +184,20 @@
input logic spis_miso,
output logic spis_mosi,
- // UART MASTER I/F
- output logic uartm_rxd ,
- input logic uartm_txd ,
+ // UART MASTER I/F
+ output logic uartm_rxd ,
+ input logic uartm_txd ,
- output logic pulse1m_mclk,
- output logic [31:0] pinmux_debug,
+ output logic pulse1m_mclk,
+ output logic [31:0] pinmux_debug,
- input logic dbg_clk_mon
+ // Digital PLL I/F
+ output logic cfg_pll_enb , // Enable PLL
+ output logic[4:0] cfg_pll_fed_div , // PLL feedback division ratio
+ output logic cfg_dco_mode , // Run PLL in DCO mode
+ output logic[25:0] cfg_dc_trim , // External trim for DCO mode
+ output logic pll_ref_clk // Input oscillator to match
+
);
@@ -198,6 +206,7 @@
logic s_reset_ssn; // Sync Reset
logic p_reset_ssn; // Sync Reset
logic [15:0] pad_strap_in;
+logic dbg_clk_mon;
/* clock pulse */
//********************************************************
@@ -344,10 +353,12 @@
.pad_strap_in (pad_strap_in ),
.system_strap (system_strap ),
.strap_sticky (strap_sticky ),
+ .strap_uartm (strap_uartm ),
.user_clock1 (user_clock1 ),
.user_clock2 (user_clock2 ),
.int_pll_clock (int_pll_clock ),
+ .cpu_clk (cpu_clk ),
.xtal_clk (xtal_clk ),
.usb_clk (usb_clk ),
@@ -387,7 +398,17 @@
.timer_intr (timer_intr ),
- .gpio_intr (gpio_intr )
+ .gpio_intr (gpio_intr ),
+
+ // Digital PLL I/F
+ .cfg_pll_enb (cfg_pll_enb ), // Enable PLL
+ .cfg_pll_fed_div (cfg_pll_fed_div ), // PLL feedback division ratio
+ .cfg_dco_mode (cfg_dco_mode ), // Run PLL in DCO mode
+ .cfg_dc_trim (cfg_dc_trim ), // External trim for DCO mode
+ .pll_ref_clk (pll_ref_clk ), // Input oscillator to match
+
+ .dbg_clk_mon (dbg_clk_mon )
+
);
diff --git a/verilog/rtl/pinmux/src/strap_ctrl.sv b/verilog/rtl/pinmux/src/strap_ctrl.sv
index 643a6de..c0405b0 100644
--- a/verilog/rtl/pinmux/src/strap_ctrl.sv
+++ b/verilog/rtl/pinmux/src/strap_ctrl.sv
@@ -68,16 +68,14 @@
01 - 2 Div
10 - 4 Div
11 - 8 Div
- bit [4] - uart master config control
- 0 - load from LA
- 1 - constant value based on system clock selection (Default)
+ bit [4] - Reserved
bit [5] - QSPI SRAM Mode Selection
- 1'b0 - Single (Default)
- 1'b1 - Quad
+ 1'b0 - Single
+ 1'b1 - Quad (Default)
bit [7:6] - QSPI Fash Mode Selection
- 2'b00 - Single (Default)
+ 2'b00 - Single
2'b01 - Double
- 2'b10 - Quad
+ 2'b10 - Quad (Default)
2'b11 - QDDR
bit [8] - Riscv Reset control
0 - Keep Riscv on Reset
@@ -93,6 +91,11 @@
2'b01 - Default value + 2
2'b10 - Default value + 4
2'b11 - Default value - 4
+ bit [4:13] - uart master config control
+ 2'b00 - constant value based on system clock-50Mhz (Default)
+ 2'b01 - constant value based on system clock-40Mhz
+ 2'b10 - constant value based on system clock-60Mhz (USB Ref Clock)
+ 2'b11 - load from LA
bit [14:13] - Reserved
bit [15] - Strap Mode
0 - Normal
@@ -165,7 +168,8 @@
//List of Outs
output logic [15:0] strap_latch ,
- output logic [31:0] strap_sticky
+ output logic [31:0] strap_sticky ,
+ output logic [1:0] strap_uartm // Uart Master Strap Config
);
@@ -195,13 +199,16 @@
pstrap_select[8] , // bit[12] - Riscv Reset control
pstrap_select[7:6] , // bit[11:10] - QSPI FLASH Mode Selection CS#0
pstrap_select[5] , // bit[9] - QSPI SRAM Mode Selection CS#2
- pstrap_select[4] , // bit[8] - uart master config control
+ pstrap_select[4] , // bit[8] - Reserved
pstrap_select[3:2] , // bit[7:6] - riscv clock div
pstrap_select[1:0] , // bit[5:4] - riscv clock source sel
pstrap_select[3:2] , // bit[3:2] - wbs clock division
pstrap_select[1:0] // bit[1:0] - wbs clock source sel
};
+
+assign strap_uartm = strap_latch[`PSTRAP_UARTM_CFG];
+
//------------------------------------
// Generating strap latch
//------------------------------------
diff --git a/verilog/rtl/sspis/src/sspis_if.sv b/verilog/rtl/sspis/src/sspis_if.sv
index 10a5d1d..0a1c4c5 100644
--- a/verilog/rtl/sspis/src/sspis_if.sv
+++ b/verilog/rtl/sspis/src/sspis_if.sv
@@ -100,8 +100,8 @@
// sclk pos and ned edge generation
logic sck_l0,sck_l1,sck_l2;
-assign sck_pdetect = (!sck_l2 && sck_l1) ? 1'b1: 1'b0;
-assign sck_ndetect = (sck_l2 && !sck_l1) ? 1'b1: 1'b0;
+wire sck_pdetect = (!sck_l2 && sck_l1) ? 1'b1: 1'b0;
+wire sck_ndetect = (sck_l2 && !sck_l1) ? 1'b1: 1'b0;
always @ (posedge sys_clk or negedge rst_n) begin
if (!rst_n) begin
diff --git a/verilog/rtl/uart2wb/src/uart_msg_handler.v b/verilog/rtl/uart2wb/src/uart_msg_handler.v
index 471ff88..e6436e5 100755
--- a/verilog/rtl/uart2wb/src/uart_msg_handler.v
+++ b/verilog/rtl/uart2wb/src/uart_msg_handler.v
@@ -316,6 +316,11 @@
TxMsgSize <= TxMsgSize -1;
end
end
+ default: begin
+ State <= `IDLE;
+ NextState <= `IDLE;
+ end
+
endcase
end
end
diff --git a/verilog/rtl/user_params.svh b/verilog/rtl/user_params.svh
index 7664338..a8b8341 100644
--- a/verilog/rtl/user_params.svh
+++ b/verilog/rtl/user_params.svh
@@ -4,13 +4,13 @@
// ASCI Representation of RISC = 32'h8273_8343
parameter CHIP_SIGNATURE = 32'h8273_8343;
// Software Reg-1, Release date: <DAY><MONTH><YEAR>
-parameter CHIP_RELEASE_DATE = 32'h0309_2022;
+parameter CHIP_RELEASE_DATE = 32'h0709_2022;
// Software Reg-2: Poject Revison 5.1 = 0005200
-parameter CHIP_REVISION = 32'h0005_3000;
+parameter CHIP_REVISION = 32'h0005_4000;
parameter SKEW_RESET_VAL = 32'b0000_0000_1000_0111_1001_1000_1001_1000;
-parameter PSTRAP_DEFAULT_VALUE = 15'b000_0111_1011_0000;
+parameter PSTRAP_DEFAULT_VALUE = 15'b000_0111_1010_0000;
/*****************************************************
pad_strap_in decoding
@@ -24,10 +24,7 @@
01 - 2 Div
10 - 4 Div
11 - 8 Div
- bit [4] - uart master config control
- 0 - load from LA
- 1 - constant value based
- on system clock selection (Default)
+ bit [4] - Reserved
bit [5] - QSPI SRAM Mode Selection
1'b0 - Single
1'b1 - Quad (Default)
@@ -50,6 +47,11 @@
2'b01 - Default value + 2
2'b10 - Default value + 4
2'b11 - Default value - 4
+ bit [4:13] - uart master config control
+ 2'b00 - constant value based on system clock-50Mhz (Default)
+ 2'b01 - constant value based on system clock-40Mhz
+ 2'b10 - constant value based on system clock-60Mhz (USB Ref Clock)
+ 2'b11 - load from LA
bit[15] - Strap Mode
0 - [14:0] loaded from pad
@@ -66,6 +68,7 @@
`define PSTRAP_RISCV_CACHE_BYPASS 9
`define PSTRAP_RISCV_SRAM_CLK_EDGE 10
`define PSTRAP_CLK_SKEW 12:11
+`define PSTRAP_UARTM_CFG 14:13
`define PSTRAP_DEFAULT_VALUE 15
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index e7c6c8a..0373cc9 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -182,7 +182,7 @@
//// wishbone slave clock generation config increase from ////
//// 3 to 4 bit support clock source selection ////
//// B. Changed Module: qspim ////
-////// 1. Bug fix in spi rise and fall pulse relation w.r.t ////
+//// 1. Bug fix in spi rise and fall pulse relation w.r.t ////
//// spi_clk. Note: Previous version work only with ////
//// spi clock config = 0x2 ////
//// 2. spi_oen generation fix for different spi mode ////
@@ -261,6 +261,16 @@
//// D. reset fsm is implementation with soft reboot ////
//// option ////
//// E. strap based booting option added for qspi ////
+//// 5.4 Sept 7 2022, Dinesh A ////
+//// A. PLL configuration are moved from wb_host to ////
+//// pinmux to help risc core to do pll config and reboot////
+//// B. PLL configuration are kept in p_reset_n to avoid ////
+//// initialized on soft reboot. ////
+//// C. Master Uart has two strap bit to control the ////
+//// boot up config ////
+//// 2'b00 - 50Mhz, 2'b01 - 40Mhz, 2'b10 - 50Mhz, ////
+//// 2'b11 - LA control ////
+//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
@@ -743,6 +753,7 @@
//---------------------------------------------------------------------
wire [31:0] system_strap ;
wire [31:0] strap_sticky ;
+wire [1:0] strap_uartm ;
wire [1:0] strap_qspi_flash = system_strap[`STRAP_QSPI_FLASH];
wire strap_qspi_sram = system_strap[`STRAP_QSPI_SRAM];
wire strap_qspi_pre_sram = system_strap[`STRAP_QSPI_PRE_SRAM];
@@ -774,6 +785,8 @@
assign la_data_out[127:0] = {pinmux_debug,spi_debug,riscv_debug};
+wire int_pll_clock = pll_clk_out[0];
+
wb_host u_wb_host(
`ifdef USE_POWER_PINS
@@ -782,7 +795,7 @@
`endif
.user_clock1 (wb_clk_i ),
.user_clock2 (user_clock2 ),
- .int_pll_clock (int_pll_clock ),
+ .int_pll_clock (int_pll_clock ),
.cpu_clk (cpu_clk ),
@@ -794,6 +807,7 @@
.cfg_strap_pad_ctrl (cfg_strap_pad_ctrl ),
.system_strap (system_strap ),
.strap_sticky (strap_sticky ),
+ .strap_uartm (strap_uartm ),
.wbd_int_rst_n (wbd_int_rst_n ),
.wbd_pll_rst_n (wbd_pll_rst_n ),
@@ -831,13 +845,6 @@
.cfg_clk_ctrl1 (cfg_clk_ctrl1 ),
- .cfg_pll_enb (cfg_pll_enb ),
- .cfg_pll_fed_div (cfg_pll_fed_div ),
- .cfg_dco_mode (cfg_dco_mode ),
- .cfg_dc_trim (cfg_dc_trim ),
- .pll_ref_clk (pll_ref_clk ),
- .pll_clk_out (pll_clk_out ),
-
.la_data_in (la_data_in[17:0] ),
.uartm_rxd (uartm_rxd ),
@@ -847,9 +854,8 @@
.ssn (sspis_ssn ),
.sdin (sspis_si ),
.sdout (sspis_so ),
- .sdout_oen ( ),
+ .sdout_oen ( )
- .dbg_clk_mon (dbg_clk_mon )
);
@@ -1376,11 +1382,13 @@
.cfg_strap_pad_ctrl (cfg_strap_pad_ctrl ),
.system_strap (system_strap ),
.strap_sticky (strap_sticky ),
+ .strap_uartm (strap_uartm ),
.user_clock1 (wb_clk_i ),
.user_clock2 (user_clock2 ),
.int_pll_clock (int_pll_clock ),
.xtal_clk (xtal_clk ),
+ .cpu_clk (cpu_clk ),
.rtc_clk (rtc_clk ),
@@ -1468,8 +1476,12 @@
.pinmux_debug (pinmux_debug ),
- .dbg_clk_mon (dbg_clk_mon )
+ .cfg_pll_enb (cfg_pll_enb ),
+ .cfg_pll_fed_div (cfg_pll_fed_div ),
+ .cfg_dco_mode (cfg_dco_mode ),
+ .cfg_dc_trim (cfg_dc_trim ),
+ .pll_ref_clk (pll_ref_clk )
);
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v
index 80de782..ff6a316 100644
--- a/verilog/rtl/user_reg_map.v
+++ b/verilog/rtl/user_reg_map.v
@@ -14,6 +14,7 @@
`define ADDR_SPACE_PWM 32'h3002_0100
`define ADDR_SPACE_TIMER 32'h3002_0180
`define ADDR_SPACE_SEMA 32'h3002_0200
+`define ADDR_SPACE_WS281X 32'h3002_0280
`define ADDR_SPACE_WBHOST 32'h3008_0000
//--------------------------------------------------
@@ -23,7 +24,6 @@
`define WBHOST_BANK_SEL 8'h04 // reg_1 - Bank Select
`define WBHOST_CLK_CTRL1 8'h08 // reg_2 - Clock Control-1
`define WBHOST_CLK_CTRL2 8'h0C // reg_3 - Clock Control-2
-`define WBHOST_PLL_CTRL 8'h10 // reg_4 - PLL Control
//--------------------------------------------------
// GLOBAL Register
@@ -35,6 +35,8 @@
`define GLBL_CFG_INTR_STAT 8'h10 // reg_4 - Global Interrupt
`define GLBL_CFG_MUTI_FUNC 8'h14 // reg_5 - Multi functional sel
`define GLBL_CFG_CLK_CTRL 8'h18 // reg_6 - RTC/USB CLK CTRL
+`define GLBL_CFG_PLL_CTRL1 8'h1C // reg_7 - PLL Control-1
+`define GLBL_CFG_PLL_CTRL2 8'h20 // reg_8 - PLL Control-2
`define GLBL_CFG_PAD_STRAP 8'h30 // Strap as seen in Pad
`define GLBL_CFG_STRAP_STICKY 8'h34 // Sticky Strap used in next soft boot
`define GLBL_CFG_SYSTEM_STRAP 8'h38 // Current System Strap
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index df3c656..e35f5cb 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -100,7 +100,7 @@
// to/from Pinmux
- output logic int_pll_clock ,
+ input logic int_pll_clock ,
input logic xtal_clk ,
output logic e_reset_n , // external reset
output logic p_reset_n , // power-on reset
@@ -108,6 +108,7 @@
output logic cfg_strap_pad_ctrl,
output logic [31:0] system_strap ,
input logic [31:0] strap_sticky ,
+ input logic [1:0] strap_uartm ,
// Master Port
@@ -142,13 +143,6 @@
input logic wbs_err_i , // error
output logic [31:0] cfg_clk_ctrl1 ,
- // Digital PLL I/F
- output logic cfg_pll_enb , // Enable PLL
- output logic[4:0] cfg_pll_fed_div , // PLL feedback division ratio
- output logic cfg_dco_mode , // Run PLL in DCO mode
- output logic[25:0] cfg_dc_trim , // External trim for DCO mode
- output logic pll_ref_clk , // Input oscillator to match
- input logic [1:0] pll_clk_out , // Two 90 degree clock phases
input logic [17:0] la_data_in ,
@@ -159,9 +153,8 @@
input logic ssn ,
input logic sdin ,
output logic sdout ,
- output logic sdout_oen ,
+ output logic sdout_oen
- output logic dbg_clk_mon
);
@@ -174,27 +167,10 @@
logic wbs_rst_n;
logic reg_sel ;
-logic [2:0] sw_addr ;
-logic sw_rd_en ;
-logic sw_wr_en ;
logic [31:0] reg_rdata ;
-logic [31:0] reg_out ;
logic reg_ack ;
-logic [7:0] config_reg ;
-logic [31:0] clk_ctrl1 ;
-logic [31:0] clk_ctrl2 ;
-logic sw_wr_en_0;
-logic sw_wr_en_1;
-logic sw_wr_en_2;
-logic sw_wr_en_3;
logic [15:0] cfg_bank_sel;
-logic [31:0] reg_0; // Software_Reg_0
-logic [8:0] cfg_clk_ctrl2;
-logic [31:0] cfg_pll_ctrl;
-logic [3:0] cfg_wb_clk_ctrl;
-logic [3:0] cfg_cpu_clk_ctrl;
-logic [31:0] cfg_glb_ctrl;
// uart Master Port
@@ -235,10 +211,7 @@
logic wb_ack_int ; // acknowlegement
logic wb_err_int ; // error
-logic [3:0] cfg_mon_sel ;
-logic pll_clk_div16 ;
-logic pll_clk_div16_buf ;
-logic [2:0] cfg_ref_pll_div ;
+logic cfg_fast_sim ;
logic arst_n ;
logic soft_reboot ;
logic clk_enb ;
@@ -249,27 +222,6 @@
wire soft_boot_req = strap_sticky[`STRAP_SOFT_REBOOT_REQ];
-//------------------------------------------
-// PLL Trim Value
-//-----------------------------------------
-assign cfg_dco_mode = cfg_pll_ctrl[31];
-assign cfg_pll_fed_div = cfg_pll_ctrl[30:26];
-assign cfg_dc_trim = cfg_pll_ctrl[25:0];
-
-//assign int_pll_clock = pll_clk_out[0];
-ctech_clk_buf u_clkbuf_pll (.A (pll_clk_out[0]), . X(int_pll_clock));
-ctech_clk_buf u_clkbuf_pll_div (.A (pll_clk_div16), . X(pll_clk_div16_buf));
-
-
-// Debug clock monitor optin
-assign dbg_clk_mon = (cfg_mon_sel == 4'b000) ? pll_clk_div16_buf:
- (cfg_mon_sel == 4'b001) ? pll_ref_clk :
- (cfg_mon_sel == 4'b010) ? wbs_clk_out :
- (cfg_mon_sel == 4'b011) ? cpu_clk_int : 1'b0;
-
-
-
-
//--------------------------------------------------------------------------------
// Look like wishbone reset removed early than user Power up sequence
// To control the reset phase, we have added additional control through la[0]
@@ -294,7 +246,7 @@
//------------------------------------------
// Keep WBS in Ref clock during initial boot to strap loading
logic force_refclk;
-wb_reset_fsm u_reset_fsm (
+wbh_reset_fsm u_reset_fsm (
.clk (wbm_clk_i ),
.e_reset_n (e_reset_n ), // external reset
.cfg_fast_sim (cfg_fast_sim),
@@ -312,19 +264,29 @@
//-------------------------------------------------
// UART2WB HOST
// Uart Baud-16x computation
-// Assumption is default wb clock is 40Mhz
+// Assumption is default wb clock is 50Mhz
// For 9600 Baud
-// 40,000,000/(9600*16) = 260;
-// Configured Value = 260-1 = 259
+// 50,000,000/(9600*16) = 324;
+// Configured Value = 325-2 = 324
+// Internally we have used pos and neg counter
+// it has additional 1 cycle additional count,
+// so we are subtracting desired count by 2
+// strap_uartm
+// 2'b00 - 50Mhz - 324
+// 2'b01 - 40Mhz - 258
+// 2'b10 - 60Mhz - 389
+// 2'b11 - Load from LA
//-------------------------------------------------
-wire strap_uart_cfg_mode = system_strap[`STRAP_UARTM_CFG];
-wire cfg_uartm_tx_enable = (strap_uart_cfg_mode==0) ? la_data_in[1] : 1'b1;
-wire cfg_uartm_rx_enable = (strap_uart_cfg_mode==0) ? la_data_in[2] : 1'b1;
-wire cfg_uartm_stop_bit = (strap_uart_cfg_mode==0) ? la_data_in[3] : 1'b1;
-wire [11:0]cfg_uart_baud_16x = (strap_uart_cfg_mode==0) ? la_data_in[15:4] : 258;
-wire [1:0] cfg_uartm_cfg_pri_mod = (strap_uart_cfg_mode==0) ? la_data_in[17:16] : 2'b0;
+wire cfg_uartm_tx_enable = (strap_uartm==2'b11) ? la_data_in[1] : 1'b1;
+wire cfg_uartm_rx_enable = (strap_uartm==2'b11) ? la_data_in[2] : 1'b1;
+wire cfg_uartm_stop_bit = (strap_uartm==2'b11) ? la_data_in[3] : 1'b1;
+wire [1:0] cfg_uartm_cfg_pri_mod = (strap_uartm==2'b11) ? la_data_in[17:16] : 2'b0;
+
+wire [11:0]cfg_uart_baud_16x = (strap_uartm==2'b00) ? 324:
+ (strap_uartm==2'b01) ? 258:
+ (strap_uartm==2'b10) ? 389: la_data_in[15:4];
// UART Master
@@ -450,10 +412,10 @@
ctech_delay_buf u_delay2_stb2 (.X(wb_stb_d3),.A(wb_stb_d2));
always_ff @(negedge s_reset_n or posedge wbm_clk_i) begin
if ( s_reset_n == 1'b0 ) begin
- wb_req <= '0;
- wb_dat_o <= '0;
- wb_ack_o <= '0;
- wb_err_o <= '0;
+ wb_req <= '0;
+ wb_dat_o <= '0;
+ wb_ack_o <= '0;
+ wb_err_o <= '0;
end else begin
wb_req <= wb_stb_d3 && ((wb_ack_o == 0) && (wb_ack_o1 == 0)) ;
wb_ack_o <= wb_ack_o1;
@@ -479,199 +441,58 @@
// ---------------------------------------------------------------------
assign reg_sel = wb_req & (wb_adr_i[19] == 1'b1);
-assign sw_addr = wb_adr_i [4:2];
-assign sw_rd_en = reg_sel & !wb_we_i;
-assign sw_wr_en = reg_sel & wb_we_i;
+wbh_reg u_reg (
+ // System Signals
+ // Inputs
+ .mclk (wbm_clk_i ),
+ .e_reset_n (e_reset_n ), // external reset
+ .p_reset_n (p_reset_n ), // power-on reset
+ .s_reset_n (s_reset_n ), // soft reset
+ .int_pll_clock (int_pll_clock ),
-assign sw_wr_en_0 = sw_wr_en && (sw_addr==0);
-assign sw_wr_en_1 = sw_wr_en && (sw_addr==1);
-assign sw_wr_en_2 = sw_wr_en && (sw_addr==2);
-assign sw_wr_en_3 = sw_wr_en && (sw_addr==3);
-assign sw_wr_en_4 = sw_wr_en && (sw_addr==4);
-assign sw_wr_en_5 = sw_wr_en && (sw_addr==5);
+ .clk_enb (clk_enb ),
+ .force_refclk (force_refclk ),
+ .soft_reboot (soft_reboot ),
+ .system_strap (system_strap ),
+ .strap_sticky (strap_sticky ),
+
+ .user_clock1 (user_clock1 ),
+ .user_clock2 (user_clock2 ),
+ .xtal_clk (xtal_clk ),
-always @ (posedge wbm_clk_i or negedge s_reset_n)
-begin : preg_out_Seq
- if (s_reset_n == 1'b0)
- begin
- reg_rdata <= 'h0;
- reg_ack <= 1'b0;
- end
- else if (sw_rd_en && !reg_ack)
- begin
- reg_rdata <= reg_out ;
- reg_ack <= 1'b1;
- end
- else if (sw_wr_en && !reg_ack)
- reg_ack <= 1'b1;
- else
- begin
- reg_ack <= 1'b0;
- end
-end
+ // Reg Bus Interface Signal
+ .reg_cs (reg_sel ),
+ .reg_wr (wb_we_i ),
+ .reg_addr (wb_adr_i[4:2] ),
+ .reg_wdata (wb_dat_i ),
+ .reg_be (wb_sel_i ),
+
+ // Outputs
+ .reg_rdata (reg_rdata ),
+ .reg_ack (reg_ack ),
-//-------------------------------------
-// Global + Clock Control
-// -------------------------------------
-assign cfg_glb_ctrl = reg_0[31:0];
-// Reset control
-// On Power-up wb & pll power default enabled
-ctech_buf u_buf_wb_rst (.A(cfg_glb_ctrl[0] & s_reset_n),.X(wbd_int_rst_n));
-ctech_buf u_buf_pll_rst (.A(cfg_glb_ctrl[1] & s_reset_n),.X(wbd_pll_rst_n));
+ // Global Reset control
+ .wbd_int_rst_n (wbd_int_rst_n ),
+ .wbd_pll_rst_n (wbd_pll_rst_n ),
-//assign cfg_fast_sim = cfg_glb_ctrl[8];
-ctech_clk_buf u_fastsim_buf (.A (cfg_glb_ctrl[8]), . X(cfg_fast_sim)); // To Bypass Reset FSM initial wait time
+ // CPU Clock and Reset
+ .cpu_clk (cpu_clk ),
-assign cfg_pll_enb = cfg_glb_ctrl[15];
-assign cfg_ref_pll_div = cfg_glb_ctrl[14:12];
-assign cfg_mon_sel = cfg_glb_ctrl[11:8];
+ // WishBone Slave Clkout/in
+ .wbs_clk_out (wbs_clk_out ), // System clock
+ .cfg_bank_sel (cfg_bank_sel ),
+ .cfg_clk_ctrl1 (cfg_clk_ctrl1 ),
-assign cfg_wb_clk_ctrl = cfg_clk_ctrl2[3:0];
-assign cfg_cpu_clk_ctrl = cfg_clk_ctrl2[7:4];
-
-
-always @( *)
-begin
- reg_out [31:0] = 8'd0;
-
- case (sw_addr [1:0])
- 3'b000 : reg_out [31:0] = reg_0;
- 3'b001 : reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]};
- 3'b010 : reg_out [31:0] = cfg_clk_ctrl1 [31:0];
- 3'b011 : reg_out [31:0] = {24'h0,cfg_clk_ctrl2 [7:0]};
- 3'b100 : reg_out [31:0] = cfg_pll_ctrl [31:0];
- 3'b101 : reg_out [31:0] = system_strap [31:0];
- default : reg_out [31:0] = 'h0;
- endcase
-end
+ .cfg_fast_sim (cfg_fast_sim )
+ );
-generic_register #(32,32'h8003 ) u_glb_ctrl (
- .we ({32{sw_wr_en_0}} ),
- .data_in (wb_dat_i[31:0] ),
- .reset_n (e_reset_n ),
- .clk (wbm_clk_i ),
-
- //List of Outs
- .data_out (reg_0[31:0])
- );
-
-generic_register #(16,16'h1000 ) u_bank_sel (
- .we ({16{sw_wr_en_1}} ),
- .data_in (wb_dat_i[15:0] ),
- .reset_n (e_reset_n ),
- .clk (wbm_clk_i ),
-
- //List of Outs
- .data_out (cfg_bank_sel[15:0] )
- );
-
-//-----------------------------------------------
-// clock control-1
-//----------------------------------------------
-
-wire [31:0] rst_clk_ctrl1;
-
-assign rst_clk_ctrl1[3:0] = (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b00) ? SKEW_RESET_VAL[3:0] :
- (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b01) ? SKEW_RESET_VAL[3:0] + 2 :
- (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b10) ? SKEW_RESET_VAL[3:0] + 4 : SKEW_RESET_VAL[3:0]-4;
-
-assign rst_clk_ctrl1[7:4] = (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b00) ? SKEW_RESET_VAL[7:4] :
- (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b01) ? SKEW_RESET_VAL[7:4] + 2 :
- (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b10) ? SKEW_RESET_VAL[7:4] + 4 : SKEW_RESET_VAL[7:4]-4;
-
-assign rst_clk_ctrl1[11:8] = (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b00) ? SKEW_RESET_VAL[11:8] :
- (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b01) ? SKEW_RESET_VAL[11:8] + 2 :
- (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b10) ? SKEW_RESET_VAL[11:8] + 4 : SKEW_RESET_VAL[11:8]-4;
-
-assign rst_clk_ctrl1[15:12] = (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b00) ? SKEW_RESET_VAL[15:12] :
- (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b01) ? SKEW_RESET_VAL[15:12] + 2 :
- (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b10) ? SKEW_RESET_VAL[15:12] + 4 : SKEW_RESET_VAL[15:12]-4;
-
-assign rst_clk_ctrl1[19:16] = (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b00) ? SKEW_RESET_VAL[19:16] :
- (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b01) ? SKEW_RESET_VAL[19:16] + 2 :
- (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b10) ? SKEW_RESET_VAL[19:16] + 4 : SKEW_RESET_VAL[19:16]-4;
-
-assign rst_clk_ctrl1[23:20] = (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b00) ? SKEW_RESET_VAL[23:20] :
- (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b01) ? SKEW_RESET_VAL[23:20] + 2 :
- (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b10) ? SKEW_RESET_VAL[23:20] + 4 : SKEW_RESET_VAL[23:20]-4;
-
-assign rst_clk_ctrl1[27:24] = (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b00) ? SKEW_RESET_VAL[27:24] :
- (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b01) ? SKEW_RESET_VAL[27:24] + 2 :
- (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b10) ? SKEW_RESET_VAL[27:24] + 4 : SKEW_RESET_VAL[27:24]-4;
-
-assign rst_clk_ctrl1[31:28] = 4'b0;
-
-
-always @ (posedge wbm_clk_i ) begin
- if (p_reset_n == 1'b0) begin
- cfg_clk_ctrl1 <= rst_clk_ctrl1 ;
- end
- else begin
- if(sw_wr_en_2 )
- cfg_clk_ctrl1 <= wb_dat_i[31:0];
- end
-end
-
-//--------------------------------
-// clock control-2
-//--------------------------------
-always @ (posedge wbm_clk_i) begin
- if (p_reset_n == 1'b0) begin
- cfg_clk_ctrl2 <= strap_sticky[7:0] ;
- end
- else begin
- if(sw_wr_en_3 )
- cfg_clk_ctrl2 <= wb_dat_i[7:0];
- end
-end
-//--------------------------------
-// Pll Control
-//--------------------------------
-// PLL clock : 199.680 Mhz Period: 5.008 & bcount: 7, period
-// cfg_dc_trim = 26'b0000000000000_1010101101001
-// cfg_pll_fed_div = 5'b00000
-// cfg_dco_mode = 1'b1
-
-generic_register #(32,{1'b1,5'b00000,26'b0000000000000_1010101101001} ) u_pll_ctrl (
- .we ({32{sw_wr_en_4}} ),
- .data_in (wb_dat_i[31:0] ),
- .reset_n (e_reset_n ),
- .clk (wbm_clk_i ),
-
- //List of Outs
- .data_out (cfg_pll_ctrl[31:0])
- );
-
-
-always @ (posedge wbm_clk_i ) begin
- if (p_reset_n == 1'b0) begin
- cfg_clk_ctrl2 <= strap_sticky[7:0] ;
- end
- else begin
- if(sw_wr_en_3 )
- cfg_clk_ctrl2 <= wb_dat_i[7:0];
- end
-end
-//-------------------------------------------------------------
-// Note: system_strap reset (p_reset_n) will be released
-// eariler than s_reset_n to take care of strap loading
-//--------------------------------------------------------------
-always @ (posedge wbm_clk_i) begin
- if (s_reset_n == 1'b0) begin
- system_strap <= {soft_reboot,strap_sticky[30:0]};
- end
- else if(sw_wr_en_5 ) begin
- system_strap <= wb_dat_i;
- end
-end
-
-
-//--------------------- End of Register Bank ------------------------
-
+//-----------------------------------------------------------------
+// Wishbone Slave Interface Logic starts here
+//-----------------------------------------------------------------
assign wb_stb_int = wb_req & !reg_sel;
@@ -708,93 +529,4 @@
);
-// PLL Ref CLock
-
-clk_ctl #(2) u_pll_ref_clk (
- // Outputs
- .clk_o (pll_ref_clk ),
- // Inputs
- .mclk (user_clock1 ),
- .reset_n (e_reset_n ),
- .clk_div_ratio (cfg_ref_pll_div )
- );
-
-// PLL DIv16 to debug monitor purpose
-
-clk_ctl #(3) u_pllclk (
- // Outputs
- .clk_o (pll_clk_div16 ),
- // Inputs
- .mclk (int_pll_clock ),
- .reset_n (e_reset_n ),
- .clk_div_ratio (4'hF )
- );
-
-//----------------------------------
-// Generate Internal WishBone Clock
-//----------------------------------
-logic wb_clk_div;
-logic wbs_ref_clk_int;
-logic wbs_ref_clk;
-
-wire [1:0] cfg_wb_clk_src_sel = cfg_wb_clk_ctrl[1:0];
-wire [1:0] cfg_wb_clk_ratio = cfg_wb_clk_ctrl[3:2];
-
- // Keep WBS in Ref clock during initial boot to strap loading
-assign wbs_ref_clk_int = (cfg_wb_clk_src_sel ==2'b00) ? user_clock1 :
- (cfg_wb_clk_src_sel ==2'b01) ? user_clock2 :
- (cfg_wb_clk_src_sel ==2'b10) ? int_pll_clock : xtal_clk;
-
-ctech_clk_buf u_wbs_ref_clkbuf (.A (wbs_ref_clk_int), . X(wbs_ref_clk));
-ctech_clk_gate u_clkgate_wbs (.GATE (clk_enb), . CLK(wbs_clk_div), .GCLK(wbs_clk_out));
-
-assign wbs_clk_div =(force_refclk) ? user_clock1 :
- (cfg_wb_clk_ratio == 2'b00) ? wbs_ref_clk :
- (cfg_wb_clk_ratio == 2'b01) ? wbs_ref_clk_div_2 :
- (cfg_wb_clk_ratio == 2'b10) ? wbs_ref_clk_div_4 : wbs_ref_clk_div_8;
-
-clk_div8 u_wbclk (
- // Outputs
- .clk_div_8 (wbs_ref_clk_div_8 ),
- .clk_div_4 (wbs_ref_clk_div_4 ),
- .clk_div_2 (wbs_ref_clk_div_2 ),
- // Inputs
- .mclk (wbs_ref_clk ),
- .reset_n (p_reset_n )
- );
-
-
-//----------------------------------
-// Generate CORE Clock Generation
-//----------------------------------
-wire cpu_clk_div;
-wire cpu_ref_clk_int;
-wire cpu_ref_clk;
-wire cpu_clk_int;
-
-wire [1:0] cfg_cpu_clk_src_sel = cfg_cpu_clk_ctrl[1:0];
-wire [1:0] cfg_cpu_clk_ratio = cfg_cpu_clk_ctrl[3:2];
-
-assign cpu_ref_clk_int = (cfg_cpu_clk_src_sel ==2'b00) ? user_clock1 :
- (cfg_cpu_clk_src_sel ==2'b01) ? user_clock2 :
- (cfg_cpu_clk_src_sel ==2'b10) ? int_pll_clock : xtal_clk;
-
-ctech_clk_buf u_cpu_ref_clkbuf (.A (cpu_ref_clk_int), . X(cpu_ref_clk));
-
-ctech_clk_gate u_clkgate_cpu (.GATE (clk_enb), . CLK(cpu_clk_div), .GCLK(cpu_clk));
-
-assign cpu_clk_div = (cfg_wb_clk_ratio == 2'b00) ? cpu_ref_clk :
- (cfg_wb_clk_ratio == 2'b01) ? cpu_ref_clk_div_2 :
- (cfg_wb_clk_ratio == 2'b10) ? cpu_ref_clk_div_4 : cpu_ref_clk_div_8;
-
-
-clk_div8 u_cpuclk (
- // Outputs
- .clk_div_8 (cpu_ref_clk_div_8 ),
- .clk_div_4 (cpu_ref_clk_div_4 ),
- .clk_div_2 (cpu_ref_clk_div_2 ),
- // Inputs
- .mclk (cpu_ref_clk ),
- .reset_n (p_reset_n )
- );
endmodule
diff --git a/verilog/rtl/wb_host/src/wbh_reg.sv b/verilog/rtl/wb_host/src/wbh_reg.sv
new file mode 100644
index 0000000..5985135
--- /dev/null
+++ b/verilog/rtl/wb_host/src/wbh_reg.sv
@@ -0,0 +1,337 @@
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com>
+//
+//////////////////////////////////////////////////////////////////////
+
+`include "user_params.svh"
+module wbh_reg (
+ // System Signals
+ // Inputs
+ input logic mclk ,
+ input logic e_reset_n , // external reset
+ input logic p_reset_n , // power-on reset
+ input logic s_reset_n , // soft reset
+ input logic int_pll_clock ,
+
+ input logic clk_enb ,
+ input logic force_refclk ,
+ input logic soft_reboot ,
+ output logic [31:0] system_strap ,
+ input logic [31:0] strap_sticky ,
+
+ input logic user_clock1 ,
+ input logic user_clock2 ,
+ input logic xtal_clk ,
+
+ // Reg Bus Interface Signal
+ input logic reg_cs ,
+ input logic reg_wr ,
+ input logic [2:0] reg_addr ,
+ input logic [31:0] reg_wdata ,
+ input logic [3:0] reg_be ,
+
+ // Outputs
+ output logic [31:0] reg_rdata ,
+ output logic reg_ack ,
+
+
+ // Global Reset control
+ output logic wbd_int_rst_n ,
+ output logic wbd_pll_rst_n ,
+
+ // CPU Clock and Reset
+ output logic cpu_clk ,
+
+ // WishBone Slave Clkout/in
+ output logic wbs_clk_out , // System clock
+
+
+ output logic [15:0] cfg_bank_sel ,
+ output logic [31:0] cfg_clk_ctrl1 ,
+
+ output logic cfg_fast_sim
+ );
+
+logic [2:0] sw_addr ;
+logic sw_rd_en ;
+logic sw_wr_en ;
+logic sw_wr_en_0 ;
+logic sw_wr_en_1 ;
+logic sw_wr_en_2 ;
+logic sw_wr_en_3 ;
+logic sw_wr_en_4 ;
+logic sw_wr_en_5 ;
+logic [31:0] reg_out ;
+
+logic [31:0] reg_0 ; // Software_Reg_0
+logic [7:0] cfg_clk_ctrl2 ;
+logic [3:0] cfg_wb_clk_ctrl ;
+logic [3:0] cfg_cpu_clk_ctrl ;
+logic [31:0] cfg_glb_ctrl ;
+logic wbs_clk_div ;
+logic wbs_ref_clk_div_2 ;
+logic wbs_ref_clk_div_4 ;
+logic wbs_ref_clk_div_8 ;
+
+
+assign sw_addr = reg_addr ;
+assign sw_rd_en = reg_cs & !reg_wr;
+assign sw_wr_en = reg_cs & reg_wr;
+
+assign sw_wr_en_0 = sw_wr_en && (sw_addr==0);
+assign sw_wr_en_1 = sw_wr_en && (sw_addr==1);
+assign sw_wr_en_2 = sw_wr_en && (sw_addr==2);
+assign sw_wr_en_3 = sw_wr_en && (sw_addr==3);
+assign sw_wr_en_4 = sw_wr_en && (sw_addr==4);
+assign sw_wr_en_5 = sw_wr_en && (sw_addr==5);
+
+always @ (posedge mclk or negedge p_reset_n)
+begin : preg_out_Seq
+ if (p_reset_n == 1'b0)
+ begin
+ reg_rdata <= 'h0;
+ reg_ack <= 1'b0;
+ end
+ else if (sw_rd_en && !reg_ack)
+ begin
+ reg_rdata <= reg_out ;
+ reg_ack <= 1'b1;
+ end
+ else if (sw_wr_en && !reg_ack)
+ reg_ack <= 1'b1;
+ else
+ begin
+ reg_ack <= 1'b0;
+ end
+end
+
+
+//-------------------------------------
+// Global + Clock Control
+// -------------------------------------
+assign cfg_glb_ctrl = reg_0[31:0];
+// Reset control
+// On Power-up wb & pll power default enabled
+ctech_buf u_buf_wb_rst (.A(cfg_glb_ctrl[0] & s_reset_n),.X(wbd_int_rst_n));
+// Change to p_reset to avoid pll reset on every system reset
+ctech_buf u_buf_pll_rst (.A(cfg_glb_ctrl[1] & p_reset_n),.X(wbd_pll_rst_n));
+
+//assign cfg_fast_sim = cfg_glb_ctrl[8];
+ctech_clk_buf u_fastsim_buf (.A (cfg_glb_ctrl[8]), . X(cfg_fast_sim)); // To Bypass Reset FSM initial wait time
+
+
+assign cfg_wb_clk_ctrl = cfg_clk_ctrl2[3:0];
+assign cfg_cpu_clk_ctrl = cfg_clk_ctrl2[7:4];
+
+
+always @( *)
+begin
+ reg_out [31:0] = 'h0;
+
+ case (sw_addr [2:0])
+ 3'b000 : reg_out [31:0] = reg_0;
+ 3'b001 : reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]};
+ 3'b010 : reg_out [31:0] = cfg_clk_ctrl1 [31:0];
+ 3'b011 : reg_out [31:0] = {24'h0,cfg_clk_ctrl2 [7:0]};
+ 3'b101 : reg_out [31:0] = system_strap [31:0];
+ default : reg_out [31:0] = 'h0;
+ endcase
+end
+
+
+
+generic_register #(32,32'h3 ) u_glb_ctrl (
+ .we ({32{sw_wr_en_0}} ),
+ .data_in (reg_wdata[31:0] ),
+ .reset_n (e_reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (reg_0[31:0])
+ );
+
+generic_register #(16,16'h1000 ) u_bank_sel (
+ .we ({16{sw_wr_en_1}} ),
+ .data_in (reg_wdata[15:0] ),
+ .reset_n (e_reset_n ),
+ .clk (mclk ),
+
+ //List of Outs
+ .data_out (cfg_bank_sel[15:0] )
+ );
+
+//-----------------------------------------------
+// clock control-1
+//----------------------------------------------
+
+wire [31:0] rst_clk_ctrl1;
+
+assign rst_clk_ctrl1[3:0] = (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b00) ? SKEW_RESET_VAL[3:0] :
+ (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b01) ? SKEW_RESET_VAL[3:0] + 2 :
+ (strap_sticky[`STRAP_CLK_SKEW_WI] == 2'b10) ? SKEW_RESET_VAL[3:0] + 4 : SKEW_RESET_VAL[3:0]-4;
+
+assign rst_clk_ctrl1[7:4] = (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b00) ? SKEW_RESET_VAL[7:4] :
+ (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b01) ? SKEW_RESET_VAL[7:4] + 2 :
+ (strap_sticky[`STRAP_CLK_SKEW_WH] == 2'b10) ? SKEW_RESET_VAL[7:4] + 4 : SKEW_RESET_VAL[7:4]-4;
+
+assign rst_clk_ctrl1[11:8] = (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b00) ? SKEW_RESET_VAL[11:8] :
+ (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b01) ? SKEW_RESET_VAL[11:8] + 2 :
+ (strap_sticky[`STRAP_CLK_SKEW_RISCV] == 2'b10) ? SKEW_RESET_VAL[11:8] + 4 : SKEW_RESET_VAL[11:8]-4;
+
+assign rst_clk_ctrl1[15:12] = (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b00) ? SKEW_RESET_VAL[15:12] :
+ (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b01) ? SKEW_RESET_VAL[15:12] + 2 :
+ (strap_sticky[`STRAP_CLK_SKEW_QSPI] == 2'b10) ? SKEW_RESET_VAL[15:12] + 4 : SKEW_RESET_VAL[15:12]-4;
+
+assign rst_clk_ctrl1[19:16] = (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b00) ? SKEW_RESET_VAL[19:16] :
+ (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b01) ? SKEW_RESET_VAL[19:16] + 2 :
+ (strap_sticky[`STRAP_CLK_SKEW_UART] == 2'b10) ? SKEW_RESET_VAL[19:16] + 4 : SKEW_RESET_VAL[19:16]-4;
+
+assign rst_clk_ctrl1[23:20] = (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b00) ? SKEW_RESET_VAL[23:20] :
+ (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b01) ? SKEW_RESET_VAL[23:20] + 2 :
+ (strap_sticky[`STRAP_CLK_SKEW_PINMUX] == 2'b10) ? SKEW_RESET_VAL[23:20] + 4 : SKEW_RESET_VAL[23:20]-4;
+
+assign rst_clk_ctrl1[27:24] = (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b00) ? SKEW_RESET_VAL[27:24] :
+ (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b01) ? SKEW_RESET_VAL[27:24] + 2 :
+ (strap_sticky[`STRAP_CLK_SKEW_QSPI_CO] == 2'b10) ? SKEW_RESET_VAL[27:24] + 4 : SKEW_RESET_VAL[27:24]-4;
+
+assign rst_clk_ctrl1[31:28] = 4'b0;
+
+
+always @ (posedge mclk ) begin
+ if (p_reset_n == 1'b0) begin
+ cfg_clk_ctrl1 <= rst_clk_ctrl1 ;
+ end
+ else begin
+ if(sw_wr_en_2 )
+ cfg_clk_ctrl1 <= reg_wdata[31:0];
+ end
+end
+
+//--------------------------------
+// clock control-2
+//--------------------------------
+always @ (posedge mclk) begin
+ if (p_reset_n == 1'b0) begin
+ cfg_clk_ctrl2 <= strap_sticky[7:0] ;
+ end
+ else begin
+ if(sw_wr_en_3 )
+ cfg_clk_ctrl2 <= reg_wdata[7:0];
+ end
+end
+
+
+always @ (posedge mclk ) begin
+ if (p_reset_n == 1'b0) begin
+ cfg_clk_ctrl2 <= strap_sticky[7:0] ;
+ end
+ else begin
+ if(sw_wr_en_3 )
+ cfg_clk_ctrl2 <= reg_wdata[7:0];
+ end
+end
+//-------------------------------------------------------------
+// Note: system_strap reset (p_reset_n) will be released
+// eariler than s_reset_n to take care of strap loading
+//--------------------------------------------------------------
+always @ (posedge mclk) begin
+ if (s_reset_n == 1'b0) begin
+ system_strap <= {soft_reboot,strap_sticky[30:0]};
+ end
+ else if(sw_wr_en_5 ) begin
+ system_strap <= reg_wdata;
+ end
+end
+
+
+
+//----------------------------------
+// Generate Internal WishBone Clock
+//----------------------------------
+logic wb_clk_div;
+logic wbs_ref_clk_int;
+logic wbs_ref_clk;
+
+wire [1:0] cfg_wb_clk_src_sel = cfg_wb_clk_ctrl[1:0];
+wire [1:0] cfg_wb_clk_ratio = cfg_wb_clk_ctrl[3:2];
+
+ // Keep WBS in Ref clock during initial boot to strap loading
+assign wbs_ref_clk_int = (cfg_wb_clk_src_sel ==2'b00) ? user_clock1 :
+ (cfg_wb_clk_src_sel ==2'b01) ? user_clock2 :
+ (cfg_wb_clk_src_sel ==2'b10) ? int_pll_clock : xtal_clk;
+
+ctech_clk_buf u_wbs_ref_clkbuf (.A (wbs_ref_clk_int), . X(wbs_ref_clk));
+ctech_clk_gate u_clkgate_wbs (.GATE (clk_enb), . CLK(wbs_clk_div), .GCLK(wbs_clk_out));
+
+assign wbs_clk_div =(force_refclk) ? user_clock1 :
+ (cfg_wb_clk_ratio == 2'b00) ? wbs_ref_clk :
+ (cfg_wb_clk_ratio == 2'b01) ? wbs_ref_clk_div_2 :
+ (cfg_wb_clk_ratio == 2'b10) ? wbs_ref_clk_div_4 : wbs_ref_clk_div_8;
+
+clk_div8 u_wbclk (
+ // Outputs
+ .clk_div_8 (wbs_ref_clk_div_8 ),
+ .clk_div_4 (wbs_ref_clk_div_4 ),
+ .clk_div_2 (wbs_ref_clk_div_2 ),
+ // Inputs
+ .mclk (wbs_ref_clk ),
+ .reset_n (p_reset_n )
+ );
+
+
+//----------------------------------
+// Generate CORE Clock Generation
+//----------------------------------
+wire cpu_clk_div;
+wire cpu_ref_clk_int;
+wire cpu_ref_clk;
+wire cpu_clk_int;
+wire cpu_ref_clk_div_2;
+wire cpu_ref_clk_div_4;
+wire cpu_ref_clk_div_8;
+
+wire [1:0] cfg_cpu_clk_src_sel = cfg_cpu_clk_ctrl[1:0];
+wire [1:0] cfg_cpu_clk_ratio = cfg_cpu_clk_ctrl[3:2];
+
+assign cpu_ref_clk_int = (cfg_cpu_clk_src_sel ==2'b00) ? user_clock1 :
+ (cfg_cpu_clk_src_sel ==2'b01) ? user_clock2 :
+ (cfg_cpu_clk_src_sel ==2'b10) ? int_pll_clock : xtal_clk;
+
+ctech_clk_buf u_cpu_ref_clkbuf (.A (cpu_ref_clk_int), . X(cpu_ref_clk));
+
+ctech_clk_gate u_clkgate_cpu (.GATE (clk_enb), . CLK(cpu_clk_div), .GCLK(cpu_clk));
+
+assign cpu_clk_div = (cfg_wb_clk_ratio == 2'b00) ? cpu_ref_clk :
+ (cfg_wb_clk_ratio == 2'b01) ? cpu_ref_clk_div_2 :
+ (cfg_wb_clk_ratio == 2'b10) ? cpu_ref_clk_div_4 : cpu_ref_clk_div_8;
+
+
+clk_div8 u_cpuclk (
+ // Outputs
+ .clk_div_8 (cpu_ref_clk_div_8 ),
+ .clk_div_4 (cpu_ref_clk_div_4 ),
+ .clk_div_2 (cpu_ref_clk_div_2 ),
+ // Inputs
+ .mclk (cpu_ref_clk ),
+ .reset_n (p_reset_n )
+ );
+
+
+
+
+
+endmodule
diff --git a/verilog/rtl/wb_host/src/wb_reset_fsm.sv b/verilog/rtl/wb_host/src/wbh_reset_fsm.sv
similarity index 83%
rename from verilog/rtl/wb_host/src/wb_reset_fsm.sv
rename to verilog/rtl/wb_host/src/wbh_reset_fsm.sv
index 23fd015..9a53d75 100644
--- a/verilog/rtl/wb_host/src/wb_reset_fsm.sv
+++ b/verilog/rtl/wb_host/src/wbh_reset_fsm.sv
@@ -1,4 +1,21 @@
-
+//////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText: 2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Created by Dinesh Annayya <dinesh.annayya@gmail.com>
+//
+//////////////////////////////////////////////////////////////////////
/*************************************************************************
This block control the reset sequence
@@ -23,7 +40,7 @@
************************************************************************************************************/
-module wb_reset_fsm (
+module wbh_reset_fsm (
input logic clk ,
input logic e_reset_n , // external reset
input logic cfg_fast_sim ,
@@ -135,6 +152,7 @@
clk_cnt <= clk_cnt + 1;
end
end
+ default : state <= FSM_POWER_UP;
endcase
diff --git a/verilog/rtl/wb_interconnect/src/wb_arb.sv b/verilog/rtl/wb_interconnect/src/wb_arb.sv
index aefac4a..a67047b 100644
--- a/verilog/rtl/wb_interconnect/src/wb_arb.sv
+++ b/verilog/rtl/wb_interconnect/src/wb_arb.sv
@@ -78,10 +78,10 @@
parameter [1:0]
- grant0 = 3'h0,
- grant1 = 3'h1,
- grant2 = 3'h2,
- grant3 = 3'h3;
+ grant0 = 2'h0,
+ grant1 = 2'h1,
+ grant2 = 2'h2,
+ grant3 = 2'h3;
///////////////////////////////////////////////////////////////////////
// Local Registers and Wires
