commit	cd90372db65fd229a2f9750179e3cb6e457507ee	[log] [tgz]
author	Maximo <maximo@balestrini.com.ar>	Mon Mar 21 00:18:39 2022 -0300
committer	Maximo <maximo@balestrini.com.ar>	Mon Mar 21 00:18:39 2022 -0300
tree	7e2db5a98fec5d551a016d04a9e1a7ba17eccf47
parent	b3ac77dd3737f2aa461199484538fd91c363deed [diff]

Initial commit

Makefile[diff]
def/user_proj_example.def[Deleted - diff]
def/user_project_wrapper.def[diff]
gds/user_proj_example.gds[Deleted - diff]
gds/user_project_wrapper.gds[Deleted - diff]
gds/user_project_wrapper.gds.gz[Added - diff]
gds/wrapped_hack_soc_dffram.gds.gz[Added - diff]
lef/user_proj_example.lef[Deleted - diff]
lef/user_project_wrapper.lef[diff]
lef/wrapped_hack_soc_dffram.lef[Added - diff]
mag/user_proj_example.mag[Deleted - diff]
mag/user_project_wrapper.mag[diff]
maglef/user_proj_example.mag[Deleted - diff]
maglef/user_project_wrapper.mag[diff]
my_timing_tests/CUSTOM_caravel_timing_typ.tcl[Added - diff]
my_timing_tests/sta_results_220318_201333.log[Added - diff]
my_timing_tests/sta_results_220318_233925.log[Added - diff]
my_timing_tests/sta_results_220318_234319.log[Added - diff]
my_timing_tests/sta_results_220319_000400.log[Added - diff]
my_timing_tests/sta_results_220319_115831.log[Added - diff]
openlane/user_proj_example/config.json[Deleted - diff]
openlane/user_proj_example/config.tcl[Deleted - diff]
openlane/user_proj_example/pin_order.cfg[Deleted - diff]
openlane/user_project_wrapper/config.tcl[diff]
openlane/user_project_wrapper/macro.cfg[diff]
sdc/user_project_wrapper.sdc[Added - diff]
sdf/user_project_wrapper.sdf[Added - diff]
signoff/user_proj_example/final_summary_report.csv[diff]
signoff/user_project_wrapper/final_summary_report.csv[diff]
signoff/wrapped_hack_soc_caravel/OPENLANE_VERSION[Added - diff]
signoff/wrapped_hack_soc_caravel/PDK_SOURCES[Added - diff]
signoff/wrapped_hack_soc_caravel/final_summary_report.csv[Added - diff]
spef/DFFRF_2R1W.spef[Added - diff]
spef/user_project_wrapper.spef[Added - diff]
spef/wrapped_hack_soc_dffram.spef[Added - diff]
spi/lvs/user_proj_example.spice[Deleted - diff]
spi/lvs/user_project_wrapper.spice[diff]
verilog/dv/caravel_wrapped_hack_soc_test/Makefile[Added - diff]
verilog/dv/caravel_wrapped_hack_soc_test/__pycache__/wrapped_hack_soc_test.cpython-38.pyc[Added - diff]
verilog/dv/caravel_wrapped_hack_soc_test/__pycache__/wrapped_hack_soc_test_2.cpython-38.pyc[Added - diff]
verilog/dv/caravel_wrapped_hack_soc_test/caravel_test_hack_program.c[Added - diff]
verilog/dv/caravel_wrapped_hack_soc_test/results.xml[Added - diff]
verilog/dv/caravel_wrapped_hack_soc_test/rom_23LC1024.v[Added - diff]
verilog/dv/caravel_wrapped_hack_soc_test/sim_build/sim.vvp[Added - diff]
verilog/dv/caravel_wrapped_hack_soc_test/wrapped_hack_soc_test.c[Added - diff]
verilog/dv/caravel_wrapped_hack_soc_test/wrapped_hack_soc_test.py[Added - diff]
verilog/dv/caravel_wrapped_hack_soc_test/wrapped_hack_soc_test_tb.v[Added - diff]
verilog/gl/DFFRF_2R1W.powered.nl.v[Added - diff]
verilog/gl/user_proj_example.v[Deleted - diff]
verilog/gl/user_project_wrapper.v[diff]
verilog/gl/wrapped_hack_soc_dffram.v[Added - diff]
verilog/includes/includes.gl+sdf.caravel_user_project[diff]
verilog/includes/includes.gl.caravel_user_project[diff]
verilog/includes/includes.rtl.caravel_user_project[diff]
verilog/rtl/user_proj_example.v[Deleted - diff]
verilog/rtl/user_project_wrapper.v[diff]
verilog/rtl/wrapped_hack_soc/hack_soc/DFFRF_2R1W.v[Added - diff]
verilog/rtl/wrapped_hack_soc/hack_soc/boot_logo.v[Added - diff]
verilog/rtl/wrapped_hack_soc/hack_soc/dmux8way.v[Added - diff]
verilog/rtl/wrapped_hack_soc/hack_soc/hack_alu.v[Added - diff]
verilog/rtl/wrapped_hack_soc/hack_soc/hack_clock.v[Added - diff]
verilog/rtl/wrapped_hack_soc/hack_soc/hack_cpu.v[Added - diff]
verilog/rtl/wrapped_hack_soc/hack_soc/hack_soc.v[Added - diff]
verilog/rtl/wrapped_hack_soc/hack_soc/pc.v[Added - diff]
verilog/rtl/wrapped_hack_soc/hack_soc/register.v[Added - diff]
verilog/rtl/wrapped_hack_soc/hack_soc/rom_stream_loader.v[Added - diff]
verilog/rtl/wrapped_hack_soc/hack_soc/spi_sram_encoder.v[Added - diff]
verilog/rtl/wrapped_hack_soc/hack_soc/spi_video_ram_2.v[Added - diff]
verilog/rtl/wrapped_hack_soc/hack_soc/video_signal_generator_640x480.v[Added - diff]
verilog/rtl/wrapped_hack_soc/hack_soc/vram_write_fifo.v[Added - diff]
verilog/rtl/wrapped_hack_soc/wrapped_hack_soc_dffram.v[Added - diff]

71 files changed

tree: 7e2db5a98fec5d551a016d04a9e1a7ba17eccf47

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.