commit	f0972d5de4fac9f2e94004dc5db917fbd80eefb1	[log] [tgz]
author	Ali Imran <ali1120001@outlook.com>	Sun Mar 20 09:53:46 2022 +0500
committer	Ali Imran <ali1120001@outlook.com>	Sun Mar 20 09:53:46 2022 +0500
tree	4078e900ed238a28e12ef091be81aa140d7a3d94
parent	0ed11cca127cb2c3354fbc4e3e65a76695b085e0 [diff]

WB_Interconnect Verilog updated

def/Core.def[Deleted - diff]
def/Motor_Top.def[Deleted - diff]
def/SPI.def[Deleted - diff]
def/UART.def[Deleted - diff]
def/WBM_DBus.def[Deleted - diff]
def/WB_InterConnect.def[Deleted - diff]
gds/Core.gds[Deleted - diff]
gds/Motor_Top.gds[Deleted - diff]
gds/SPI.gds[Deleted - diff]
gds/UART.gds[Deleted - diff]
gds/WBM_DBus.gds[Deleted - diff]
gds/WB_InterConnect.gds[Deleted - diff]
gds/extract_BMem.log[Deleted - diff]
gds/extract_BMem.tcl[Deleted - diff]
lef/Core.lef[Deleted - diff]
lef/Motor_Top.lef[Deleted - diff]
lef/SPI.lef[Deleted - diff]
lef/UART.lef[Deleted - diff]
lef/WBM_DBus.lef[Deleted - diff]
lef/WB_InterConnect.lef[Deleted - diff]
mag/Core.mag[Deleted - diff]
mag/Motor_Top.mag[Deleted - diff]
mag/SPI.mag[Deleted - diff]
mag/UART.mag[Deleted - diff]
mag/WBM_DBus.mag[Deleted - diff]
mag/WB_InterConnect.mag[Deleted - diff]
maglef/Core.mag[Deleted - diff]
maglef/Motor_Top.mag[Deleted - diff]
maglef/SPI.mag[Deleted - diff]
maglef/UART.mag[Deleted - diff]
maglef/WBM_DBus.mag[Deleted - diff]
maglef/WB_InterConnect.mag[Deleted - diff]
sdc/Core.sdc[Deleted - diff]
sdc/Motor_Top.sdc[Deleted - diff]
sdc/SPI.sdc[Deleted - diff]
sdc/UART.sdc[Deleted - diff]
sdc/WBM_DBus.sdc[Deleted - diff]
sdc/WB_InterConnect.sdc[Deleted - diff]
sdf/Core.sdf[Deleted - diff]
sdf/Motor_Top.sdf[Deleted - diff]
sdf/SPI.sdf[Deleted - diff]
sdf/UART.sdf[Deleted - diff]
sdf/WBM_DBus.sdf[Deleted - diff]
sdf/WB_InterConnect.sdf[Deleted - diff]
signoff/Core/OPENLANE_VERSION[Deleted - diff]
signoff/Core/PDK_SOURCES[Deleted - diff]
signoff/Core/final_summary_report.csv[Deleted - diff]
signoff/Motor_Top/OPENLANE_VERSION[Deleted - diff]
signoff/Motor_Top/PDK_SOURCES[Deleted - diff]
signoff/Motor_Top/final_summary_report.csv[Deleted - diff]
signoff/SPI/OPENLANE_VERSION[Deleted - diff]
signoff/SPI/PDK_SOURCES[Deleted - diff]
signoff/SPI/final_summary_report.csv[Deleted - diff]
signoff/UART/OPENLANE_VERSION[Deleted - diff]
signoff/UART/PDK_SOURCES[Deleted - diff]
signoff/UART/final_summary_report.csv[Deleted - diff]
signoff/WBM_DBus/OPENLANE_VERSION[Deleted - diff]
signoff/WBM_DBus/PDK_SOURCES[Deleted - diff]
signoff/WBM_DBus/final_summary_report.csv[Deleted - diff]
signoff/Wishbone_InterConnect/OPENLANE_VERSION[Deleted - diff]
signoff/Wishbone_InterConnect/PDK_SOURCES[Deleted - diff]
signoff/Wishbone_InterConnect/final_summary_report.csv[Deleted - diff]
spef/Core.spef[Deleted - diff]
spef/Motor_Top.spef[Deleted - diff]
spef/SPI.spef[Deleted - diff]
spef/UART.spef[Deleted - diff]
spef/WBM_DBus.spef[Deleted - diff]
spef/WB_InterConnect.spef[Deleted - diff]
spi/lvs/Core.spice[Deleted - diff]
spi/lvs/Motor_Top.spice[Deleted - diff]
spi/lvs/SPI.spice[Deleted - diff]
spi/lvs/UART.spice[Deleted - diff]
spi/lvs/WBM_DBus.spice[Deleted - diff]
spi/lvs/WB_InterConnect.spice[Deleted - diff]
spi/lvs/tmp/BMem.lvs.summary.log[Deleted - diff]
spi/lvs/tmp/BMem.v_comp.json[Deleted - diff]
spi/lvs/tmp/BMem.v_comp.out[Deleted - diff]
spi/lvs/tmp/BMem.v_comp_lvs.log[Deleted - diff]
spi/lvs/user_proj_example.spice[Deleted - diff]
spi/lvs/user_project_wrapper.spice[Deleted - diff]
verilog/dv/WB_InterConnect.v[Renamed from verilog/rtl/WB_InterConnect.v - diff]
verilog/gl/Core.v[Deleted - diff]
verilog/gl/Motor_Top.v[Deleted - diff]
verilog/gl/SPI.v[Deleted - diff]
verilog/gl/UART.v[Deleted - diff]
verilog/gl/WBM_DBus.v[Deleted - diff]
verilog/gl/WB_InterConnect.v[Deleted - diff]
verilog/includes/includes.gl+sdf.caravel_user_project[Deleted - diff]
verilog/includes/includes.gl.caravel_user_project[Deleted - diff]
verilog/includes/includes.rtl.caravel_user_project[Deleted - diff]
verilog/rtl/BMem.v[Deleted - diff]
verilog/rtl/Core.v[Deleted - diff]
verilog/rtl/DMem_Interface.v[Deleted - diff]
verilog/rtl/IMem_Interface.v[Deleted - diff]
verilog/rtl/Motor_Top.v[Deleted - diff]
verilog/rtl/Processor_Tile.v[Deleted - diff]
verilog/rtl/SPI.v[Deleted - diff]
verilog/rtl/UART.v[Deleted - diff]
verilog/rtl/WBM_DBus.v[Deleted - diff]

99 files changed

tree: 4078e900ed238a28e12ef091be81aa140d7a3d94

README.md

UETRV-ecore

Here is the toplevel block diagram of ECORE

alt text

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.