| ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY |
| 0,/home/em/mpw/UETRV-ECORE/openlane/Motor_Top,Motor_Top,Motor_Top,flow completed,0h18m0s0ms,0h13m34s0ms,45752.0,0.25,22876.0,23.53,1277.89,5719,0,0,0,0,0,0,0,5,0,0,-1,215118,44480,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,178697868.0,0.0,32.02,26.28,5.15,6.64,-1,8028,17050,2135,11157,0,0,0,6389,145,35,240,349,509,1102,421,553,466,449,46,350,3274,0,3624,50.0,20.0,20,AREA 0,5,50,1,153.6,153.18,0.4,0.3,sky130_fd_sc_hd,2,4 |
