commit	0ed11cca127cb2c3354fbc4e3e65a76695b085e0	[log] [tgz]
author	EmJunaid <2018ee71@student.uet.edu.pk>	Sun Mar 20 01:16:22 2022 +0500
committer	EmJunaid <2018ee71@student.uet.edu.pk>	Sun Mar 20 01:16:22 2022 +0500
tree	b650eb4f241076f0020702b26e7486df15892237
parent	8eccac9e4199c493c157faacdfbbc0bb5046cc48 [diff]

Wishbone InterConnect Hardened

def/WB_InterConnect.def[Added - diff]
gds/WB_InterConnect.gds[Added - diff]
lef/WB_InterConnect.lef[Added - diff]
mag/WB_InterConnect.mag[Added - diff]
maglef/WB_InterConnect.mag[Added - diff]
openlane/Motor_Top/config.tcl[Deleted - diff]
openlane/Motor_Top/pin_order.cfg[Deleted - diff]
openlane/SPI/config.tcl[Deleted - diff]
openlane/UART/config.tcl[Deleted - diff]
openlane/WBM_DBus/config.tcl[Deleted - diff]
openlane/Wishbone_InterConnect/config.tcl[Renamed from openlane/Core/config.tcl - diff]
sdc/WB_InterConnect.sdc[Added - diff]
sdf/WB_InterConnect.sdf[Added - diff]
signoff/Wishbone_InterConnect/OPENLANE_VERSION[Added - diff]
signoff/Wishbone_InterConnect/PDK_SOURCES[Added - diff]
signoff/Wishbone_InterConnect/final_summary_report.csv[Added - diff]
spef/WB_InterConnect.spef[Added - diff]
spi/lvs/WB_InterConnect.spice[Added - diff]
verilog/gl/WB_InterConnect.v[Added - diff]
verilog/rtl/WB_InterConnect.v[Added - diff]
verilog/rtl/WB_Interconnect.v[Deleted - diff]

21 files changed

tree: b650eb4f241076f0020702b26e7486df15892237

README.md

UETRV-ecore

Here is the toplevel block diagram of ECORE

alt text

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.