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foss-eda-tools / third_party / shuttle / sky130 / mpw-004 / slot-014 / 5bc74d2ea9a76fb7eab6a15fb191e8b88bad3e88 / verilog
  1. 5bc74d2 synthesis with latest yosys with $ netname avoidance fix by dineshannayya · 3 years, 7 months ago
  2. c6a2a5d antenna fix by dineshannayya · 3 years, 7 months ago
  3. c057bac efabless/dv_setup moved as dineshannayya/dvsetup with updating latest iverilog + 64bit riscv gcc compile support, efabless core compile also moved from 32 bit to 64bit by dineshannayya · 3 years, 7 months ago
  4. fbc351b SPDX Non compliant text fix by dineshannayya · 3 years, 8 months ago
  5. 3ae1a2b usb1 host is integrated by dineshannayya · 3 years, 8 months ago
  6. 1bfec4f Register Map detail updated by dineshannayya · 3 years, 8 months ago
  7. 8adb7e4 Register Map updated in Readme by dineshannayya · 3 years, 8 months ago
  8. 4f74e2f i2cm integrated and share same uart io by dineshannayya · 3 years, 8 months ago
  9. 80d1ad8 spi master with qddr mode support added by dineshannayya · 3 years, 8 months ago
  10. 9fdcbca syntacore timing fix by dineshannayya · 3 years, 8 months ago
  11. 77ce327 syntacore rtl changes to improve timing closure from 25Mhz to 50Mhz by dineshannayya · 3 years, 8 months ago
  12. 8db2585 syntacore timing optimization, timing stage added at scr1_pipe_mrpf by dineshannayya · 3 years, 8 months ago
  13. 9242ac2 SPI Preftech logic added by dineshannayya · 3 years, 8 months ago
  14. a8d6590 Power Ring is now 8 + Power Mesh is 2 (vccd1 & vssd1) by dineshannayya · 3 years, 8 months ago
  15. 93bc315 clk_skew power hook fix by dineshannayya · 3 years, 8 months ago
  16. 14f70c6 sta clean up, global clock buf and reset buf added by dineshannayya · 3 years, 8 months ago
  17. 5ac4e7d full chip sta clean-up: cpu,spi,rtc clock generation moved from glbl_cfg to wb_host by dineshannayya · 3 years, 8 months ago
  18. daa4343 sdram clock connectivity correction at u_skew hookup by dineshannayya · 3 years, 8 months ago
  19. 4c022a3 spi unused input pin io_in[1:0] removed by dineshannayya · 3 years, 8 months ago
  20. ae23e25 Timing Closure related clean-up. Hold fix added at spi-master and clock delay adjusted inside the clock_skew module by dineshannayya · 3 years, 8 months ago
  21. 63db20d Clean GateSim and RTL Sim + Updated SPI Master by dineshannayya · 3 years, 8 months ago
  22. dcf9534 first version of pre-check clean database by dineshannayya · 3 years, 9 months ago
  23. a25bcff Clock Skew adjust network added + Inside SDRAM WB Stagging FF added by dineshannayya · 3 years, 9 months ago
  24. 311a4e0 precheck cleanup by dineshannayya · 3 years, 9 months ago
  25. c184ad2 License Text Added by dineshannayya · 3 years, 9 months ago
  26. 76d58fb DRC clean user_project_wrapper by dineshannayya · 3 years, 9 months ago
  27. a908000 updated database by dineshannayya · 3 years, 9 months ago
  28. 81d24ed wb_host rtl and openlane setup added by dineshannayya · 3 years, 9 months ago
  29. feb1877 backand cleanup by dineshannayya · 3 years, 9 months ago
  30. 9112eeb user project def,lef,gds added by dineshannayya · 3 years, 9 months ago
  31. ed94965 database update by dineshannayya · 3 years, 9 months ago
  32. 3f698f9 script update by dineshannayya · 3 years, 9 months ago
  33. 1431d7b def,gds,lef addition by dineshannayya · 3 years, 9 months ago
  34. e08e2a5 uart test case integration by dineshannayya · 3 years, 9 months ago
  35. b547314 uart test case integration by dineshannayya · 3 years, 9 months ago
  36. 46bd181 uart integrated into SOC by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
  37. ea1e6f3 floor planning cleanup by dineshannayya · 3 years, 9 months ago
  38. a040531 risc core and wishbone domain seperated + Stagging FF added at wishbone interconnect by dineshannayya · 3 years, 9 months ago
  39. 44e67e1 first user project lvs clean database by dineshannayya · 3 years, 9 months ago
  40. 54e49ce spi rtl issue fix in clkgen by dineshannayya · 3 years, 9 months ago
  41. b2b810b Design Document added by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
  42. aade2f4 ReadMe updated by dineshannayya · 3 years, 9 months ago
  43. 21e5ba9 test bench update by dinesha · 3 years, 9 months ago
  44. d4c716c Simulation clean up and wishbone interconnect added by dinesha · 3 years, 9 months ago
  45. 02225fd digital core added into svn by dinesha · 3 years, 9 months ago
  46. 3db5035 sdram control added by dinesha · 3 years, 9 months ago
  47. 25e2d74 spi master added by dinesha · 3 years, 9 months ago
  48. 0fe51f6 syntacore_scr1 directory removal by dinesha · 3 years, 9 months ago
  49. 69e9dbc syntacore_scr1 directory removal by dinesha · 3 years, 9 months ago
  50. 245c221 syntacore_scr1 directory removal by dinesha · 3 years, 9 months ago
  51. f85cc4d syntacore_scr1 directory removal by dinesha · 3 years, 9 months ago
  52. 54f19fa syntacore directory update by dinesha · 3 years, 9 months ago
  53. 2c40dc7 syntacore interface change to wishbone by dinesha · 3 years, 9 months ago
  54. b9d888a synthesis script update by dinesha · 3 years, 9 months ago
  55. fa7d31f synth script clean up by dinesha · 3 years, 9 months ago
  56. ca4eda2 first yosys synthesisizable rtl by dinesha · 3 years, 9 months ago
  57. 571e20d Webstone interface update by dinesha · 3 years, 9 months ago
  58. d7ec97d Removed Git igonore command file by dinesha · 3 years, 9 months ago
  59. 4f0afc4 1. Initial version of westbone interface files copied from turbo8051 open core project by dinesha · 3 years, 9 months ago
  60. 9e5d826 Initial version of efabless caravel user project by dinesha · 3 years, 9 months ago