- 5bc74d2 synthesis with latest yosys with $ netname avoidance fix by dineshannayya · 3 years, 7 months ago
- c6a2a5d antenna fix by dineshannayya · 3 years, 7 months ago
- c88cc9d openlane link pointing to dineshannaya/openlane by dineshannayya · 3 years, 7 months ago
- c3362ee efabless/dv_setup moved as dineshannayya/dvsetup with updating latest iverilog + 64bit riscv gcc compile support, efabless core compile also moved from 32 bit to 64bit by dineshannayya · 3 years, 7 months ago
- c057bac efabless/dv_setup moved as dineshannayya/dvsetup with updating latest iverilog + 64bit riscv gcc compile support, efabless core compile also moved from 32 bit to 64bit by dineshannayya · 3 years, 7 months ago
- 47e853b block diagram updated by dineshannayya · 3 years, 8 months ago
- fbc351b SPDX Non compliant text fix by dineshannayya · 3 years, 8 months ago
- 3ae1a2b usb1 host is integrated by dineshannayya · 3 years, 8 months ago
- 1bfec4f Register Map detail updated by dineshannayya · 3 years, 8 months ago
- 8adb7e4 Register Map updated in Readme by dineshannayya · 3 years, 8 months ago
- 9daed32 README updated with i2c info by dineshannayya · 3 years, 8 months ago
- 4a4e2b8 YiFive Block Diagram Updated, Added I2C Master by dineshannayya · 3 years, 8 months ago
- 4f74e2f i2cm integrated and share same uart io by dineshannayya · 3 years, 8 months ago
- 80d1ad8 spi master with qddr mode support added by dineshannayya · 3 years, 8 months ago
- 9fdcbca syntacore timing fix by dineshannayya · 3 years, 8 months ago
- 77ce327 syntacore rtl changes to improve timing closure from 25Mhz to 50Mhz by dineshannayya · 3 years, 8 months ago
- 8db2585 syntacore timing optimization, timing stage added at scr1_pipe_mrpf by dineshannayya · 3 years, 8 months ago
- 9242ac2 SPI Preftech logic added by dineshannayya · 3 years, 8 months ago
- a8d6590 Power Ring is now 8 + Power Mesh is 2 (vccd1 & vssd1) by dineshannayya · 3 years, 8 months ago
- 93bc315 clk_skew power hook fix by dineshannayya · 3 years, 8 months ago
- 14f70c6 sta clean up, global clock buf and reset buf added by dineshannayya · 3 years, 8 months ago
- 5ac4e7d full chip sta clean-up: cpu,spi,rtc clock generation moved from glbl_cfg to wb_host by dineshannayya · 3 years, 8 months ago
- daa4343 sdram clock connectivity correction at u_skew hookup by dineshannayya · 3 years, 8 months ago
- 4c022a3 spi unused input pin io_in[1:0] removed by dineshannayya · 3 years, 8 months ago
- ae23e25 Timing Closure related clean-up. Hold fix added at spi-master and clock delay adjusted inside the clock_skew module by dineshannayya · 3 years, 8 months ago
- 63db20d Clean GateSim and RTL Sim + Updated SPI Master by dineshannayya · 3 years, 8 months ago
- dcf9534 first version of pre-check clean database by dineshannayya · 3 years, 9 months ago
- a25bcff Clock Skew adjust network added + Inside SDRAM WB Stagging FF added by dineshannayya · 3 years, 9 months ago
- 311a4e0 precheck cleanup by dineshannayya · 3 years, 9 months ago
- c184ad2 License Text Added by dineshannayya · 3 years, 9 months ago
- 76d58fb DRC clean user_project_wrapper by dineshannayya · 3 years, 9 months ago
- a908000 updated database by dineshannayya · 3 years, 9 months ago
- 81d24ed wb_host rtl and openlane setup added by dineshannayya · 3 years, 9 months ago
- feb1877 backand cleanup by dineshannayya · 3 years, 9 months ago
- 9112eeb user project def,lef,gds added by dineshannayya · 3 years, 9 months ago
- ed94965 database update by dineshannayya · 3 years, 9 months ago
- 3f698f9 script update by dineshannayya · 3 years, 9 months ago
- 1431d7b def,gds,lef addition by dineshannayya · 3 years, 9 months ago
- e08e2a5 uart test case integration by dineshannayya · 3 years, 9 months ago
- b547314 uart test case integration by dineshannayya · 3 years, 9 months ago
- 46bd181 uart integrated into SOC by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- 35b181f Merge branch 'master' of https://github.com/dineshannayya/yifive_r0 by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- ea1e6f3 floor planning cleanup by dineshannayya · 3 years, 9 months ago
- a040531 risc core and wishbone domain seperated + Stagging FF added at wishbone interconnect by dineshannayya · 3 years, 9 months ago
- 723ff6c prec-check clean-up .docx and .obd file removes from doc folder by dineshannayya · 3 years, 9 months ago
- 42f8786 readme added by dineshannayya · 3 years, 9 months ago
- 493d018 def,lef,gds,mag,spi,magled added by dineshannayya · 3 years, 9 months ago
- 44e67e1 first user project lvs clean database by dineshannayya · 3 years, 9 months ago
- 54e49ce spi rtl issue fix in clkgen by dineshannayya · 3 years, 9 months ago
- f21e9b6 info update by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- 6330d33 carvel submodel added by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- 0a0119f signoff added by dineshannayya · 3 years, 9 months ago
- b2b810b Design Document added by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- c0f4d4f readme updated by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- c9f1ae3 readme updated by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- 3ee6a19 readme updated by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- fdfa50d readme updated by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- 26c10d3 readme updated by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- c27c399 readme updated by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- feb001d readme updated by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- 19d0960 Read me update with Soc Pin Map by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- a3c31b0 readme updated by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- fded6d7 readme updated by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- 2eebfb2 readme updated by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- 15da101 Readme update by DESKTOP-QFPBD39\dinesha · 3 years, 9 months ago
- 9ca8009 pin order update for sdram & syntacore by dineshannayya · 3 years, 9 months ago
- b051167 Readme update by dineshannayya · 3 years, 9 months ago
- 3767e91 Readme update by dineshannayya · 3 years, 9 months ago
- 9741649 ReadMe update by dineshannayya · 3 years, 9 months ago
- 3adf542 Read Me update by dineshannayya · 3 years, 9 months ago
- aade2f4 ReadMe updated by dineshannayya · 3 years, 9 months ago
- 2e2fad8 sdram added by dinesha · 3 years, 9 months ago
- 21e5ba9 test bench update by dinesha · 3 years, 9 months ago
- d4c716c Simulation clean up and wishbone interconnect added by dinesha · 3 years, 9 months ago
- 02225fd digital core added into svn by dinesha · 3 years, 9 months ago
- 3db5035 sdram control added by dinesha · 3 years, 9 months ago
- 25e2d74 spi master added by dinesha · 3 years, 9 months ago
- 5a0c9d6 syntacore_scr1 directory removal by dinesha · 3 years, 9 months ago
- 0fe51f6 syntacore_scr1 directory removal by dinesha · 3 years, 9 months ago
- 69e9dbc syntacore_scr1 directory removal by dinesha · 3 years, 9 months ago
- cf5334a syntacore_scr1 directory removal by dinesha · 3 years, 9 months ago
- 245c221 syntacore_scr1 directory removal by dinesha · 3 years, 9 months ago
- f85cc4d syntacore_scr1 directory removal by dinesha · 3 years, 9 months ago
- 54f19fa syntacore directory update by dinesha · 3 years, 9 months ago
- 2c40dc7 syntacore interface change to wishbone by dinesha · 3 years, 9 months ago
- fc4b9c4 syntacore added by dinesha · 3 years, 9 months ago
- b9d888a synthesis script update by dinesha · 3 years, 9 months ago
- fa7d31f synth script clean up by dinesha · 3 years, 9 months ago
- ca4eda2 first yosys synthesisizable rtl by dinesha · 3 years, 9 months ago
- 571e20d Webstone interface update by dinesha · 3 years, 9 months ago
- d7ec97d Removed Git igonore command file by dinesha · 3 years, 9 months ago
- 4f0afc4 1. Initial version of westbone interface files copied from turbo8051 open core project by dinesha · 3 years, 9 months ago
- 9e5d826 Initial version of efabless caravel user project by dinesha · 3 years, 9 months ago
