commit: 3db503544fb07642eca32e063509144f25b6bdbd
[log] [tgz]
author: dinesha <dineshannayya@users.noreply.github.com>
Tue Jun 08 11:20:32 2021 +0000
committer: dinesha <dineshannayya@users.noreply.github.com>
Tue Jun 08 11:20:32 2021 +0000
tree: 305292b1576e4a7e08ceaa602d76b57e39163104
parent: 25e2d746de87b228a1851832682cfcbf9239e33d [diff]

sdram control added

verilog/rtl/lib/async_fifo.sv[Added - diff]
verilog/rtl/lib/sync_fifo.sv[diff]
verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v[Added - diff]
verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v[Added - diff]
verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v[Added - diff]
verilog/rtl/sdram_ctrl/src/core/sdrc_core.v[Added - diff]
verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v[Added - diff]
verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v[Added - diff]
verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v[Added - diff]
verilog/rtl/sdram_ctrl/src/filelist_rtl.f[Added - diff]
verilog/rtl/sdram_ctrl/src/run_modelsim[Added - diff]
verilog/rtl/sdram_ctrl/src/top/sdrc_top.v[Added - diff]
verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v[Added - diff]
verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv[diff]
verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv[diff]
verilog/rtl/syntacore/scr1/src/wb_top.files[diff]

16 files changed

tree: 305292b1576e4a7e08ceaa602d76b57e39163104

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for this sample project documentation.