commit	69e9dbcb292103dc645fa473148ceaef2c1bbe0e	[log] [tgz]
author	dinesha <dineshannayya@users.noreply.github.com>	Mon Jun 07 16:02:13 2021 +0000
committer	dinesha <dineshannayya@users.noreply.github.com>	Mon Jun 07 16:02:13 2021 +0000
tree	97304229dbae3f74cc6a98fe8600eda3d692ae58
parent	cf5334a15eff8896dc00a7a32e7667caed1305e8 [diff]

syntacore_scr1 directory removal

verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_exu.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_hdu.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ialu.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ifu.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_lsu.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_mprf.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_tdu.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_top.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_tracelog.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/primitives/scr1_cg.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/primitives/scr1_reset_cells.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_clk_ctrl.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_core_top.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_dm.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_dmi.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_scu.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_tapc.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_tapc_shift_reg.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/core/scr1_tapc_synchronizer.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_ahb.svh[Deleted - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_arch_description.svh[Deleted - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_arch_types.svh[Deleted - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_csr.svh[Deleted - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_dm.svh[Deleted - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_hdu.svh[Deleted - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_ipic.svh[Deleted - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_memif.svh[Deleted - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_riscv_isa_decoding.svh[Deleted - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_scu.svh[Deleted - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_search_ms1.svh[Deleted - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_tapc.svh[Deleted - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_tdu.svh[Deleted - diff]
verilog/rtl/syntacore_scr1/src/includes/scr1_wb.svh[Deleted - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_dmem_ahb.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_dmem_router.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_dmem_wb.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_dp_memory.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_imem_ahb.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_imem_router.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_imem_wb.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_mem_axi.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_tcm.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_timer.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_top_ahb.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_top_axi.sv[Deleted - diff]
verilog/rtl/syntacore_scr1/src/top/scr1_top_wb.sv[Deleted - diff]

49 files changed

tree: 97304229dbae3f74cc6a98fe8600eda3d692ae58

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