4x SRAM + 4x MBIST integrated with wishbone interconnect

commit: c928ee3b18cb4dcb77c15ce375cdfc78f9d18ef2 [log] [tgz]
author: dineshannayya <dinesh.annayya@gmail.com> Fri Nov 19 21:20:20 2021 +0530
committer: dineshannayya <dinesh.annayya@gmail.com> Fri Nov 19 21:20:20 2021 +0530
tree: f306da5cd1908a4e5171ca0482c28567707d8117
parent: 7e64246e9aeac33073daa9f5b9ef7b376d34d7b7 [diff]
diff --git a/def/glbl_cfg.def.gz b/def/glbl_cfg.def.gz
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diff --git a/def/mbist.def.gz b/def/mbist.def.gz
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diff --git a/def/mbist1.def.gz b/def/mbist1.def.gz
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diff --git a/def/mbist2.def.gz b/def/mbist2.def.gz
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diff --git a/def/user_project_wrapper.def.gz b/def/user_project_wrapper.def.gz
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diff --git a/def/wb_host.def.gz b/def/wb_host.def.gz
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diff --git a/def/wb_interconnect.def.gz b/def/wb_interconnect.def.gz
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diff --git a/gds/glbl_cfg.gds.gz b/gds/glbl_cfg.gds.gz
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diff --git a/gds/mbist.gds.gz b/gds/mbist.gds.gz
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diff --git a/gds/mbist2.gds.gz b/gds/mbist2.gds.gz
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diff --git a/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds.gz b/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds.gz
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diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
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diff --git a/gds/wb_host.gds.gz b/gds/wb_host.gds.gz
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diff --git a/gds/wb_interconnect.gds.gz b/gds/wb_interconnect.gds.gz
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diff --git a/lef/glbl_cfg.lef.gz b/lef/glbl_cfg.lef.gz
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diff --git a/lef/mbist.lef.gz b/lef/mbist.lef.gz
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diff --git a/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef.gz b/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef.gz
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diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
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diff --git a/lef/wb_host.lef.gz b/lef/wb_host.lef.gz
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diff --git a/lef/wb_interconnect.lef.gz b/lef/wb_interconnect.lef.gz
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diff --git a/lib/sram_1rw1r_32_256_8_sky130_FF_1p8V_25C.lib b/lib/sram_1rw1r_32_256_8_sky130_FF_1p8V_25C.lib
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index 0000000..6548c39
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@@ -0,0 +1,575 @@
+library (sram_1rw1r_32_256_8_sky130_FF_1p8V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 1.8 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 1.8;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 1.8 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.00125, 0.005, 0.04");
+        index_2("0.0017225, 0.00689, 0.02756");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.00125, 0.005, 0.04");
+        index_2("0.00125, 0.005, 0.04");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 32;
+    bit_from : 0;
+    bit_to : 31;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 8;
+    bit_from : 0;
+    bit_to : 7;
+    }
+
+    type (wmask){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+cell (sram_1rw1r_32_256_8_sky130){
+    memory(){ 
+    type : ram;
+    address_width : 8;
+    word_width : 32;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 167998.5528;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.009512;
+    }
+    cell_leakage_power : 0.009512;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[31:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.027559999999999998;  
+        min_capacitance : 0.0017224999999999999;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[31:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.404, 0.43, 0.535",\
+                   "0.404, 0.43, 0.535",\
+                   "0.404, 0.43, 0.535");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.404, 0.43, 0.535",\
+                   "0.404, 0.43, 0.535",\
+                   "0.404, 0.43, 0.535");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(addr0[7:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    bus(wmask0){
+        bus_type  : wmask; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(wmask0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.114785e+01");
+            }
+            fall_power(scalar){
+                values("2.114785e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("2.114785e+01");
+            }
+            fall_power(scalar){
+                values("2.114785e+01");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("2.114785e+01");
+            }
+            fall_power(scalar){
+                values("2.114785e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("2.114785e+01");
+            }
+            fall_power(scalar){
+                values("2.114785e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.0535"); 
+            }
+            fall_constraint(scalar) {
+                values("0.0535"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.107"); 
+            }
+            fall_constraint(scalar) {
+                values("0.107"); 
+            }
+         }
+    }
+
+    bus(dout1){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.027559999999999998;  
+        min_capacitance : 0.0017224999999999999;  
+        memory_read(){ 
+            address : addr1; 
+        }
+        pin(dout1[31:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk1"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.404, 0.43, 0.535",\
+                   "0.404, 0.43, 0.535",\
+                   "0.404, 0.43, 0.535");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.404, 0.43, 0.535",\
+                   "0.404, 0.43, 0.535",\
+                   "0.404, 0.43, 0.535");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015",\
+                   "0.002, 0.004, 0.015");
+            }
+        }
+        }
+    }
+
+    bus(addr1){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(addr1[7:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    bus(wmask1){
+        bus_type  : wmask; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(wmask1[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    pin(csb1){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(clk1){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        internal_power(){
+            when : "!csb1"; 
+            rise_power(scalar){
+                values("2.114785e+01");
+            }
+            fall_power(scalar){
+                values("2.114785e+01");
+            }
+        }
+        internal_power(){
+            when : "csb1"; 
+            rise_power(scalar){
+                values("2.114785e+01");
+            }
+            fall_power(scalar){
+                values("2.114785e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk1; 
+            rise_constraint(scalar) {
+                values("0.0535"); 
+            }
+            fall_constraint(scalar) {
+                values("0.0535"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk1; 
+            rise_constraint(scalar) {
+                values("0.107"); 
+            }
+            fall_constraint(scalar) {
+                values("0.107"); 
+            }
+         }
+    }
+
+    }
+}

diff --git a/lib/sram_1rw1r_32_256_8_sky130_SS_1p8V_25C.lib b/lib/sram_1rw1r_32_256_8_sky130_SS_1p8V_25C.lib
new file mode 100644
index 0000000..2403478
--- /dev/null
+++ b/lib/sram_1rw1r_32_256_8_sky130_SS_1p8V_25C.lib

@@ -0,0 +1,575 @@
+library (sram_1rw1r_32_256_8_sky130_SS_1p8V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 1.8 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 1.8;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 1.8 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.00125, 0.005, 0.04");
+        index_2("0.0017225, 0.00689, 0.02756");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.00125, 0.005, 0.04");
+        index_2("0.00125, 0.005, 0.04");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 32;
+    bit_from : 0;
+    bit_to : 31;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 8;
+    bit_from : 0;
+    bit_to : 7;
+    }
+
+    type (wmask){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+cell (sram_1rw1r_32_256_8_sky130){
+    memory(){ 
+    type : ram;
+    address_width : 8;
+    word_width : 32;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 167998.5528;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.009512;
+    }
+    cell_leakage_power : 0.009512;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[31:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.027559999999999998;  
+        min_capacitance : 0.0017224999999999999;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[31:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.494, 0.526, 0.654",\
+                   "0.494, 0.526, 0.654",\
+                   "0.494, 0.526, 0.654");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.494, 0.526, 0.654",\
+                   "0.494, 0.526, 0.654",\
+                   "0.494, 0.526, 0.654");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(addr0[7:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    bus(wmask0){
+        bus_type  : wmask; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(wmask0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("1.730279e+01");
+            }
+            fall_power(scalar){
+                values("1.730279e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("1.730279e+01");
+            }
+            fall_power(scalar){
+                values("1.730279e+01");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("1.730279e+01");
+            }
+            fall_power(scalar){
+                values("1.730279e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("1.730279e+01");
+            }
+            fall_power(scalar){
+                values("1.730279e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.0655"); 
+            }
+            fall_constraint(scalar) {
+                values("0.0655"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.131"); 
+            }
+            fall_constraint(scalar) {
+                values("0.131"); 
+            }
+         }
+    }
+
+    bus(dout1){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.027559999999999998;  
+        min_capacitance : 0.0017224999999999999;  
+        memory_read(){ 
+            address : addr1; 
+        }
+        pin(dout1[31:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk1"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.494, 0.526, 0.654",\
+                   "0.494, 0.526, 0.654",\
+                   "0.494, 0.526, 0.654");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.494, 0.526, 0.654",\
+                   "0.494, 0.526, 0.654",\
+                   "0.494, 0.526, 0.654");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018",\
+                   "0.002, 0.005, 0.018");
+            }
+        }
+        }
+    }
+
+    bus(addr1){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(addr1[7:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    bus(wmask1){
+        bus_type  : wmask; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(wmask1[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    pin(csb1){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(clk1){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        internal_power(){
+            when : "!csb1"; 
+            rise_power(scalar){
+                values("1.730279e+01");
+            }
+            fall_power(scalar){
+                values("1.730279e+01");
+            }
+        }
+        internal_power(){
+            when : "csb1"; 
+            rise_power(scalar){
+                values("1.730279e+01");
+            }
+            fall_power(scalar){
+                values("1.730279e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk1; 
+            rise_constraint(scalar) {
+                values("0.0655"); 
+            }
+            fall_constraint(scalar) {
+                values("0.0655"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk1; 
+            rise_constraint(scalar) {
+                values("0.131"); 
+            }
+            fall_constraint(scalar) {
+                values("0.131"); 
+            }
+         }
+    }
+
+    }
+}

diff --git a/lib/sram_1rw1r_32_256_8_sky130_TT_1p8V_25C.lib b/lib/sram_1rw1r_32_256_8_sky130_TT_1p8V_25C.lib
new file mode 100644
index 0000000..2c15e06
--- /dev/null
+++ b/lib/sram_1rw1r_32_256_8_sky130_TT_1p8V_25C.lib

@@ -0,0 +1,575 @@
+library (sram_1rw1r_32_256_8_sky130_TT_1p8V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1V" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1, pF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 1.8 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 1.8;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    voltage_map ( VDD, 1.8 );
+    voltage_map ( GND, 0 );
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.00125, 0.005, 0.04");
+        index_2("0.0017225, 0.00689, 0.02756");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.00125, 0.005, 0.04");
+        index_2("0.00125, 0.005, 0.04");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (data){
+    base_type : array;
+    data_type : bit;
+    bit_width : 32;
+    bit_from : 0;
+    bit_to : 31;
+    }
+
+    type (addr){
+    base_type : array;
+    data_type : bit;
+    bit_width : 8;
+    bit_from : 0;
+    bit_to : 7;
+    }
+
+    type (wmask){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+cell (sram_1rw1r_32_256_8_sky130){
+    memory(){ 
+    type : ram;
+    address_width : 8;
+    word_width : 32;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 167998.5528;
+
+    pg_pin(vdd) {
+         voltage_name : VDD;
+         pg_type : primary_power;
+    }
+
+    pg_pin(gnd) {
+         voltage_name : GND;
+         pg_type : primary_ground;
+    }
+
+    leakage_power () {
+      value : 0.009512;
+    }
+    cell_leakage_power : 0.009512;
+    bus(din0){
+        bus_type  : data; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        memory_write(){ 
+            address : addr0; 
+            clocked_on  : clk0; 
+        }
+        pin(din0[31:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+    bus(dout0){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.027559999999999998;  
+        min_capacitance : 0.0017224999999999999;  
+        memory_read(){ 
+            address : addr0; 
+        }
+        pin(dout0[31:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk0"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.449, 0.478, 0.595",\
+                   "0.449, 0.478, 0.595",\
+                   "0.449, 0.478, 0.595");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.449, 0.478, 0.595",\
+                   "0.449, 0.478, 0.595",\
+                   "0.449, 0.478, 0.595");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016");
+            }
+        }
+        }
+    }
+
+    bus(addr0){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(addr0[7:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    bus(wmask0){
+        bus_type  : wmask; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(wmask0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    pin(csb0){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(web0){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk0"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(clk0){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        internal_power(){
+            when : "!csb0 & !web0"; 
+            rise_power(scalar){
+                values("1.903307e+01");
+            }
+            fall_power(scalar){
+                values("1.903307e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & !web0"; 
+            rise_power(scalar){
+                values("1.903307e+01");
+            }
+            fall_power(scalar){
+                values("1.903307e+01");
+            }
+        }
+        internal_power(){
+            when : "!csb0 & web0"; 
+            rise_power(scalar){
+                values("1.903307e+01");
+            }
+            fall_power(scalar){
+                values("1.903307e+01");
+            }
+        }
+        internal_power(){
+            when : "csb0 & web0"; 
+            rise_power(scalar){
+                values("1.903307e+01");
+            }
+            fall_power(scalar){
+                values("1.903307e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.0595"); 
+            }
+            fall_constraint(scalar) {
+                values("0.0595"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk0; 
+            rise_constraint(scalar) {
+                values("0.119"); 
+            }
+            fall_constraint(scalar) {
+                values("0.119"); 
+            }
+         }
+    }
+
+    bus(dout1){
+        bus_type  : data; 
+        direction  : output; 
+        max_capacitance : 0.027559999999999998;  
+        min_capacitance : 0.0017224999999999999;  
+        memory_read(){ 
+            address : addr1; 
+        }
+        pin(dout1[31:0]){
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk1"; 
+            timing_type : falling_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.449, 0.478, 0.595",\
+                   "0.449, 0.478, 0.595",\
+                   "0.449, 0.478, 0.595");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.449, 0.478, 0.595",\
+                   "0.449, 0.478, 0.595",\
+                   "0.449, 0.478, 0.595");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016",\
+                   "0.002, 0.005, 0.016");
+            }
+        }
+        }
+    }
+
+    bus(addr1){
+        bus_type  : addr; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(addr1[7:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    bus(wmask1){
+        bus_type  : wmask; 
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        max_transition       : 0.04;
+        pin(wmask1[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+        }
+    }
+
+    pin(csb1){
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165",\
+                   "0.165, 0.165, 0.165");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk1"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052",\
+                   "-0.052, -0.052, -0.052");
+            }
+        }
+    }
+
+    pin(clk1){
+        clock             : true;
+        direction  : input; 
+        capacitance : 0.006889999999999999;  
+        internal_power(){
+            when : "!csb1"; 
+            rise_power(scalar){
+                values("1.903307e+01");
+            }
+            fall_power(scalar){
+                values("1.903307e+01");
+            }
+        }
+        internal_power(){
+            when : "csb1"; 
+            rise_power(scalar){
+                values("1.903307e+01");
+            }
+            fall_power(scalar){
+                values("1.903307e+01");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk1; 
+            rise_constraint(scalar) {
+                values("0.0595"); 
+            }
+            fall_constraint(scalar) {
+                values("0.0595"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk1; 
+            rise_constraint(scalar) {
+                values("0.119"); 
+            }
+            fall_constraint(scalar) {
+                values("0.119"); 
+            }
+         }
+    }
+
+    }
+}

diff --git a/mag/glbl_cfg.mag.gz b/mag/glbl_cfg.mag.gz
new file mode 100644
index 0000000..d82ae93
--- /dev/null
+++ b/mag/glbl_cfg.mag.gz
Binary files differ

diff --git a/mag/mbist.mag.gz b/mag/mbist.mag.gz
deleted file mode 100644
index 9cac8de..0000000
--- a/mag/mbist.mag.gz
+++ /dev/null
Binary files differ

diff --git a/mag/mbist1.mag.gz b/mag/mbist1.mag.gz
new file mode 100644
index 0000000..9d9d7b0
--- /dev/null
+++ b/mag/mbist1.mag.gz
Binary files differ

diff --git a/mag/mbist2.mag.gz b/mag/mbist2.mag.gz
new file mode 100644
index 0000000..0f48c38
--- /dev/null
+++ b/mag/mbist2.mag.gz
Binary files differ

diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz
index e4f4c35..cbcbb2c 100644
--- a/mag/user_project_wrapper.mag.gz
+++ b/mag/user_project_wrapper.mag.gz
Binary files differ

diff --git a/mag/wb_host.mag.gz b/mag/wb_host.mag.gz
index ed653e6..6bd75c9 100644
--- a/mag/wb_host.mag.gz
+++ b/mag/wb_host.mag.gz
Binary files differ

diff --git a/mag/wb_interconnect.mag.gz b/mag/wb_interconnect.mag.gz
new file mode 100644
index 0000000..bbcb81f
--- /dev/null
+++ b/mag/wb_interconnect.mag.gz
Binary files differ

diff --git a/maglef/glbl_cfg.mag.gz b/maglef/glbl_cfg.mag.gz
new file mode 100644
index 0000000..9424d76
--- /dev/null
+++ b/maglef/glbl_cfg.mag.gz
Binary files differ

diff --git a/maglef/mbist.mag.gz b/maglef/mbist.mag.gz
deleted file mode 100644
index 2522a5c..0000000
--- a/maglef/mbist.mag.gz
+++ /dev/null
Binary files differ

diff --git a/maglef/mbist1.mag.gz b/maglef/mbist1.mag.gz
new file mode 100644
index 0000000..208be25
--- /dev/null
+++ b/maglef/mbist1.mag.gz
Binary files differ

diff --git a/maglef/mbist2.mag.gz b/maglef/mbist2.mag.gz
new file mode 100644
index 0000000..6c0e240
--- /dev/null
+++ b/maglef/mbist2.mag.gz
Binary files differ

diff --git a/maglef/user_project_wrapper.mag.gz b/maglef/user_project_wrapper.mag.gz
index e1330a6..c25b8ed 100644
--- a/maglef/user_project_wrapper.mag.gz
+++ b/maglef/user_project_wrapper.mag.gz
Binary files differ

diff --git a/maglef/wb_host.mag.gz b/maglef/wb_host.mag.gz
index 3673adb..4cd149d 100644
--- a/maglef/wb_host.mag.gz
+++ b/maglef/wb_host.mag.gz
Binary files differ

diff --git a/maglef/wb_interconnect.mag.gz b/maglef/wb_interconnect.mag.gz
new file mode 100644
index 0000000..6bbfd7f
--- /dev/null
+++ b/maglef/wb_interconnect.mag.gz
Binary files differ

diff --git a/openlane/Makefile b/openlane/Makefile
index 161a80b..fea7090 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile

@@ -14,6 +14,7 @@
 #//
 #// SPDX-License-Identifier: Apache-2.0
 
+#SHELL = sh -xv
 BLOCKS = $(shell find * -maxdepth 0 -type d)
 CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
 CLEAN = $(foreach block,$(BLOCKS), clean-$(block))

diff --git a/openlane/glbl_cfg/base.sdc b/openlane/glbl_cfg/base.sdc
new file mode 100644
index 0000000..b9b1472
--- /dev/null
+++ b/openlane/glbl_cfg/base.sdc

@@ -0,0 +1,601 @@
+###############################################################################
+# Created by write_sdc
+# Sat Nov 13 06:33:41 2021
+###############################################################################
+current_design glbl_cfg
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name mclk -period 10.0000 [get_ports {mclk}]
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]  -setup 0.2000
+
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[1]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[2]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[3]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[4]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[5]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[6]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[7]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[1]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[2]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[3]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reset_n}]
+set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {sdr_init_done}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[0]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[1]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[2]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[3]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[4]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[5]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[6]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[7]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[0]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[1]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[2]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[3]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[0]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[10]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[11]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[12]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[13]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[14]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[15]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[16]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[17]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[18]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[19]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[1]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[20]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[21]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[22]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[23]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[24]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[25]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[26]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[27]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[28]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[29]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[2]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[30]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[31]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[3]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[4]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[5]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[6]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[7]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[8]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[9]}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reset_n}]
+set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {sdr_init_done}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_colbits[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_colbits[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_req_depth[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_req_depth[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_en}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[10]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[11]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[12]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[4]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[5]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[6]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[7]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[8]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[9]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[10]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[11]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[4]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[5]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[6]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[7]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[8]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[9]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_width[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_width[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[10]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[11]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[12]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[13]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[14]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[15]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[16]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[17]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[18]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[19]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[20]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[21]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[22]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[23]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[24]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[25]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[26]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[27]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[28]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[29]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[30]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[31]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[4]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[5]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[6]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[7]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[8]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[9]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[10]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[11]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[12]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[13]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[14]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[15]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[4]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[5]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[6]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[7]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[8]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[9]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {soft_irq}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[0]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[1]}]
+set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[2]}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_colbits[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_colbits[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_req_depth[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_req_depth[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_cas[2]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_en}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[10]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[11]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[12]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[2]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[3]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[4]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[5]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[6]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[7]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[8]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_mode_reg[9]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[10]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[11]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[2]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[3]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[4]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[5]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[6]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[7]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[8]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_rfsh[9]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[2]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_tras_d[3]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[2]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcar_d[3]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[2]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trcd_d[3]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[2]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_trp_d[3]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[2]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_twr_d[3]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_width[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {cfg_sdr_width[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[10]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[11]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[12]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[13]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[14]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[15]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[16]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[17]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[18]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[19]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[20]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[21]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[22]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[23]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[24]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[25]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[26]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[27]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[28]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[29]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[2]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[30]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[31]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[3]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[4]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[5]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[6]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[7]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[8]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {fuse_mhartid[9]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[10]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[11]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[12]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[13]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[14]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[15]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[2]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[3]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[4]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[5]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[6]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[7]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[8]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {irq_lines[9]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[10]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[11]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[12]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[13]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[14]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[15]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[16]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[17]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[18]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[19]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[20]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[21]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[22]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[23]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[24]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[25]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[26]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[27]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[28]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[29]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[2]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[30]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[31]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[3]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[4]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[5]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[6]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[7]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[8]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[9]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {soft_irq}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {user_irq[2]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_en}]
+set_load -pin_load 0.0334 [get_ports {reg_ack}]
+set_load -pin_load 0.0334 [get_ports {soft_irq}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_glbl}]
+set_load -pin_load 0.0334 [get_ports {cfg_colbits[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_colbits[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_req_depth[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_req_depth[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_cas[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_cas[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_cas[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[12]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfmax[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfmax[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfmax[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[11]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[10]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[9]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[8]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[7]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[6]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[5]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[4]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_tras_d[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_tras_d[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_tras_d[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_tras_d[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcar_d[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcar_d[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcar_d[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcar_d[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcd_d[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcd_d[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcd_d[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcd_d[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_trp_d[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_trp_d[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_trp_d[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_trp_d[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_twr_d[3]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_twr_d[2]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_twr_d[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_twr_d[0]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_width[1]}]
+set_load -pin_load 0.0334 [get_ports {cfg_sdr_width[0]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[31]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[30]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[29]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[28]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[27]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[26]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[25]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[24]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[23]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[22]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[21]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[20]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[19]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[18]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[17]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[16]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[15]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[14]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[13]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[12]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[11]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[10]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[9]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[8]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[7]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[6]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[5]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[4]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[3]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[2]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[1]}]
+set_load -pin_load 0.0334 [get_ports {fuse_mhartid[0]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[15]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[14]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[13]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[12]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[11]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[10]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[9]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[8]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[7]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[6]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[5]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[4]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[3]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[2]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[1]}]
+set_load -pin_load 0.0334 [get_ports {irq_lines[0]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
+set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reset_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sdr_init_done}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+###############################################################################
+# Design Rules
+###############################################################################

diff --git a/openlane/mbist/config.tcl b/openlane/glbl_cfg/config.tcl
similarity index 64%
copy from openlane/mbist/config.tcl
copy to openlane/glbl_cfg/config.tcl
index de3c917..309115b 100755
--- a/openlane/mbist/config.tcl
+++ b/openlane/glbl_cfg/config.tcl

@@ -19,14 +19,14 @@
 
 set script_dir [file dirname [file normalize [info script]]]
 # Name
-
-set ::env(DESIGN_NAME) mbist_top
+set ::env(DESIGN_NAME) glbl_cfg
 
 set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
 
 # Timing configuration
-set ::env(CLOCK_PERIOD) "8"
-set ::env(CLOCK_PORT) "bist_clk u_mem_sel.u_cts_mem_clk_a/X u_mem_sel.u_cts_mem_clk_a/X"
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "mclk"
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
@@ -35,20 +35,12 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
-     $script_dir/../../verilog/rtl/mbist/src/mbist_addr_gen.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_fsm.sv     \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_op_sel.sv  \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_repair_addr.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_top.sv  \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_sti_sel.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_pat_sel.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_mux.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_data_cmp.sv \
-     $script_dir/../../verilog/rtl/lib/ctech_cells.sv     \
-     $script_dir/../../verilog/rtl/lib/reset_sync.sv \
-	     "
-
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/mbist/include ]
+        $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+        $script_dir/../../verilog/rtl/lib/registers.v          \
+        $script_dir/../../verilog/rtl/lib/clk_ctl.v            \
+        $script_dir/../../verilog/rtl/lib/ser_inf_32b.sv       \
+        $script_dir/../../verilog/rtl/glbl/src/glbl_cfg.sv     \
+	"
 
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 set ::env(SDC_FILE) "$script_dir/base.sdc"
@@ -60,25 +52,27 @@
 set ::env(GND_PIN) [list {vssd1}]
 
 
+
 # Floorplanning
 # -------------
 
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 200"
+set ::env(DIE_AREA) "0 0 250 250"
 
 
 # If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 1
+set ::env(RUN_CVC) 0
 
 #set ::env(PDN_CFG) $script_dir/pdn.tcl
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.30"
+set ::env(PL_TARGET_DENSITY) "0.35"
 
-
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
 
 set ::env(FP_IO_VEXTEND) 4
 set ::env(FP_IO_HEXTEND) 4
@@ -90,7 +84,6 @@
 
 set ::env(GLB_RT_MAXLAYER) 5
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
 

diff --git a/openlane/glbl_cfg/pdn.tcl b/openlane/glbl_cfg/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/glbl_cfg/pdn.tcl

@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    power_pins "VPWR"
+    ground_pins "VGND"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;

diff --git a/openlane/glbl_cfg/pin_order.cfg b/openlane/glbl_cfg/pin_order.cfg
new file mode 100644
index 0000000..6ce2f7d
--- /dev/null
+++ b/openlane/glbl_cfg/pin_order.cfg

@@ -0,0 +1,154 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#N
+reset_n               0000 0        
+
+#W
+cfg_cska_glbl\[3\]     0150 0
+cfg_cska_glbl\[2\]
+cfg_cska_glbl\[1\]
+cfg_cska_glbl\[0\]
+wbd_clk_int
+wbd_clk_glbl
+mclk                   
+
+
+#E
+reg_cs               0000 0
+reg_wr               
+reg_addr\[7\]        
+reg_addr\[6\]        
+reg_addr\[5\]        
+reg_addr\[4\]        
+reg_addr\[3\]        
+reg_addr\[2\]        
+reg_addr\[1\]        
+reg_addr\[0\]        
+reg_be\[3\]          
+reg_be\[2\]          
+reg_be\[1\]          
+reg_be\[0\]          
+reg_wdata\[31\]      
+reg_wdata\[30\]      
+reg_wdata\[29\]      
+reg_wdata\[28\]      
+reg_wdata\[27\]      
+reg_wdata\[26\]      
+reg_wdata\[25\]      
+reg_wdata\[24\]      
+reg_wdata\[23\]      
+reg_wdata\[22\]      
+reg_wdata\[21\]      
+reg_wdata\[20\]      
+reg_wdata\[19\]      
+reg_wdata\[18\]      
+reg_wdata\[17\]      
+reg_wdata\[16\]      
+reg_wdata\[15\]      
+reg_wdata\[14\]      
+reg_wdata\[13\]      
+reg_wdata\[12\]      
+reg_wdata\[11\]      
+reg_wdata\[10\]      
+reg_wdata\[9\]      
+reg_wdata\[8\]      
+reg_wdata\[7\]      
+reg_wdata\[6\]      
+reg_wdata\[5\]      
+reg_wdata\[4\]      
+reg_wdata\[3\]      
+reg_wdata\[2\]      
+reg_wdata\[1\]      
+reg_wdata\[0\]      
+reg_rdata\[31\]     
+reg_rdata\[30\]     
+reg_rdata\[29\]     
+reg_rdata\[28\]     
+reg_rdata\[27\]     
+reg_rdata\[26\]     
+reg_rdata\[25\]     
+reg_rdata\[24\]     
+reg_rdata\[23\]     
+reg_rdata\[22\]     
+reg_rdata\[21\]     
+reg_rdata\[20\]     
+reg_rdata\[19\]     
+reg_rdata\[18\]     
+reg_rdata\[17\]     
+reg_rdata\[16\]     
+reg_rdata\[15\]     
+reg_rdata\[14\]     
+reg_rdata\[13\]     
+reg_rdata\[12\]     
+reg_rdata\[11\]     
+reg_rdata\[10\]     
+reg_rdata\[9\]      
+reg_rdata\[8\]      
+reg_rdata\[7\]      
+reg_rdata\[6\]      
+reg_rdata\[5\]      
+reg_rdata\[4\]      
+reg_rdata\[3\]      
+reg_rdata\[2\]      
+reg_rdata\[1\]      
+reg_rdata\[0\]      
+reg_ack             
+
+bist_en\[3\]         150 0 2
+bist_run\[3\]
+bist_load\[3\]
+bist_sdi\[3\]
+bist_shift\[3\]
+bist_sdo\[3\]
+bist_done\[3\]
+bist_error\[3\]
+bist_correct\[3\]
+bist_error_cnt3\[3\]
+bist_error_cnt3\[2\]
+bist_error_cnt3\[1\]
+bist_error_cnt3\[0\]
+
+bist_en\[2\]         
+bist_run\[2\]
+bist_load\[2\]
+bist_sdi\[2\]
+bist_shift\[2\]
+bist_sdo\[2\]
+bist_done\[2\]
+bist_error\[2\]
+bist_correct\[2\]
+bist_error_cnt2\[3\]
+bist_error_cnt2\[2\]
+bist_error_cnt2\[1\]
+bist_error_cnt2\[0\]
+
+bist_en\[1\]         
+bist_run\[1\]
+bist_load\[1\]
+bist_sdi\[1\]
+bist_shift\[1\]
+bist_sdo\[1\]
+bist_done\[1\]
+bist_error\[1\]
+bist_correct\[1\]
+bist_error_cnt1\[3\]
+bist_error_cnt1\[2\]
+bist_error_cnt1\[1\]
+bist_error_cnt1\[0\]
+
+
+bist_en\[0\]         
+bist_run\[0\]
+bist_load\[0\]
+bist_sdi\[0\]
+bist_shift\[0\]
+bist_sdo\[0\]
+bist_done\[0\]
+bist_error\[0\]
+bist_correct\[0\]
+bist_error_cnt0\[3\]
+bist_error_cnt0\[2\]
+bist_error_cnt0\[1\]
+bist_error_cnt0\[0\]

diff --git a/openlane/mbist/base.sdc b/openlane/mbist/base.sdc
deleted file mode 100644
index eea24b8..0000000
--- a/openlane/mbist/base.sdc
+++ /dev/null

@@ -1,876 +0,0 @@
-###############################################################################
-# Created by write_sdc
-# Sun Nov 14 09:33:23 2021
-###############################################################################
-current_design mbist_top
-###############################################################################
-# Timing Constraints
-###############################################################################
-create_clock -name bist_clk -period 8.0000 [get_ports {bist_clk}]
-create_clock -name func_clk_a -period 8.0000 [get_ports {func_clk_a}]
-create_clock -name func_clk_b -period 8.0000 [get_ports {func_clk_b}]
-create_generated_clock -name bist_mem_clk_a -add -source [get_ports {bist_clk}] -master_clock [get_clocks bist_clk] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a]
-create_generated_clock -name bist_mem_clk_b -add -source [get_ports {bist_clk}] -master_clock [get_clocks bist_clk] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b]
-
-create_generated_clock -name func_mem_clk_a -add -source [get_ports {func_clk_a}] -master_clock [get_clocks func_clk_a] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a]
-create_generated_clock -name func_mem_clk_b -add -source [get_ports {func_clk_b}] -master_clock [get_clocks func_clk_b] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b]
-
-set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks {bist_clk bist_mem_clk_a bist_mem_clk_b}] -group [get_clocks {func_clk_a func_mem_clk_a}] -group [get_clocks {func_clk_b func_mem_clk_b}] 
-
-set_clock_transition 0.1500 [get_clocks {bist_clk}]
-set_clock_uncertainty -setup 0.2500 bist_clk
-set_clock_uncertainty -setup 0.2500 mem_clk_a
-set_clock_uncertainty -setup 0.2500 mem_clk_b
-set_clock_uncertainty -setup 0.2500 func_mem_clk_a
-set_clock_uncertainty -setup 0.2500 func_mem_clk_b
-set_clock_uncertainty -setup 0.2500 func_clk_a
-set_clock_uncertainty -setup 0.2500 func_clk_b
-
-set_clock_uncertainty -hold 0.1500 bist_clk
-set_clock_uncertainty -hold 0.1500 mem_clk_a
-set_clock_uncertainty -hold 0.1500 mem_clk_b
-set_clock_uncertainty -hold 0.1500 func_mem_clk_a
-set_clock_uncertainty -hold 0.1500 func_mem_clk_b
-set_clock_uncertainty -hold 0.1500 func_clk_a
-set_clock_uncertainty -hold 0.1500 func_clk_b
-
-set_input_delay  -max 5.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {rst_n}]
-set_input_delay  -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {rst_n}]
-
-set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_correct}]
-set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_done}]
-set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error}]
-set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[3]}]
-set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_sdo}]
-
-set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_correct}]
-set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_done}]
-set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error}]
-set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[0]}]
-set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[1]}]
-set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[2]}]
-set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[3]}]
-set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_sdo}]
-
-set_false_path -from [get_ports {bist_en}]
-set_input_delay -max 4 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_load}]
-set_input_delay -max 4 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_run}]
-set_input_delay -max 4 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_sdi}]
-set_input_delay -max 4 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_shift}]
-
-set_input_delay -min 2 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_en}]
-set_input_delay -min 2 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_load}]
-set_input_delay -min 2 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_run}]
-set_input_delay -min 2 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_sdi}]
-set_input_delay -min 2 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_shift}]
-
-## Functional Inputs
-set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[0]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[1]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[2]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[3]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[4]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[5]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[6]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[7]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[8]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_cen_a}]      
-
-set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[0]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[1]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[2]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[3]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[4]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[5]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[6]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[7]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[8]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_cen_a}]      
-
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[0]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[1]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[2]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[3]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[4]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[5]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[6]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[7]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[8]}]  
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_cen_b}]      
-
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[0]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[1]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[2]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[3]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[4]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[5]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[6]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[7]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[8]}]  
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_cen_b}]      
-
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[0]}] 
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[10]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[11]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[12]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[13]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[14]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[15]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[16]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[17]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[18]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[19]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[1]}] 
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[20]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[21]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[22]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[23]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[24]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[25]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[26]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[27]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[28]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[29]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[2]}] 
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[30]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[31]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[3]}] 
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[4]}] 
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[5]}] 
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[6]}] 
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[7]}] 
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[8]}] 
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[9]}] 
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[0]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[1]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[2]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[3]}]
-set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_web_b}]     
-
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[0]}] 
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[10]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[11]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[12]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[13]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[14]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[15]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[16]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[17]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[18]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[19]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[1]}] 
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[20]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[21]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[22]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[23]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[24]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[25]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[26]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[27]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[28]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[29]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[2]}] 
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[30]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[31]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[3]}] 
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[4]}] 
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[5]}] 
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[6]}] 
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[7]}] 
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[8]}] 
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[9]}] 
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[0]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[1]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[2]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[3]}]
-set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_web_b}]     
-
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[0]}]  
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[10]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[11]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[12]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[13]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[14]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[15]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[16]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[17]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[18]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[19]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[1]}]  
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[20]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[21]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[22]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[23]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[24]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[25]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[26]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[27]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[28]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[29]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[2]}]  
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[30]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[31]}] 
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[3]}]  
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[4]}]  
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[5]}]  
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[6]}]  
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[7]}]  
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[8]}]  
-set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[9]}]  
-
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[0]}]  
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[10]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[11]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[12]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[13]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[14]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[15]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[16]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[17]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[18]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[19]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[1]}]  
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[20]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[21]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[22]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[23]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[24]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[25]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[26]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[27]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[28]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[29]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[2]}]  
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[30]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[31]}] 
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[3]}]  
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[4]}]  
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[5]}]  
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[6]}]  
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[7]}]  
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[8]}]  
-set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[9]}]  
-
-
-## Towards MEMORY from MBIST CLOCK
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[0]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[10]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[11]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[12]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[13]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[14]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[15]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[16]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[17]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[18]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[19]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[1]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[20]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[21]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[22]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[23]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[24]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[25]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[26]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[27]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[28]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[29]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[2]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[30]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[31]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[3]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[4]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[5]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[6]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[7]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[8]}]
-set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[9]}]
-
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[0]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[10]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[11]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[12]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[13]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[14]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[15]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[16]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[17]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[18]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[19]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[1]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[20]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[21]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[22]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[23]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[24]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[25]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[26]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[27]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[28]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[29]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[2]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[30]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[31]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[3]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[4]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[5]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[6]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[7]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[8]}]
-set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[9]}]
-
-
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[0]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[1]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[2]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[3]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[4]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[5]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[6]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[7]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[8]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
-
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[0]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[1]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[2]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[3]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[4]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[5]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[6]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[7]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[8]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
-
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[0]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[1]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[2]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[3]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[4]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[5]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[6]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[7]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[8]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[0]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[1]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[2]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[3]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[4]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[5]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[6]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[7]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[8]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_b}]
-
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_b}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[0]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[1]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[2]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[3]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[4]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[5]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[6]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[7]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[8]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[9]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[10]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[11]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[12]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[13]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[14]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[15]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[16]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[17]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[18]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[19]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[20]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[21]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[22]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[23]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[24]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[25]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[26]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[27]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[28]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[29]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[30]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[31]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[0]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[1]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[2]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[3]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_web_b}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[0]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[1]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[2]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[3]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[4]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[5]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[6]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[7]}]
-set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[8]}]
-
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_b}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[0]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[1]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[2]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[3]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[4]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[5]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[6]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[7]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[8]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[9]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[10]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[11]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[12]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[13]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[14]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[15]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[16]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[17]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[18]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[19]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[20]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[21]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[22]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[23]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[24]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[25]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[26]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[27]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[28]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[29]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[30]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[31]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[0]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[1]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[2]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[3]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_web_b}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[0]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[1]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[2]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[3]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[4]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[5]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[6]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[7]}]
-set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[8]}]
-
-#MEM I/F from Functional Clock
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[0]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[10]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[11]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[12]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[13]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[14]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[15]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[16]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[17]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[18]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[19]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[1]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[20]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[21]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[22]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[23]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[24]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[25]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[26]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[27]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[28]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[29]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[2]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[30]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[31]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[3]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[4]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[5]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[6]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[7]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[8]}]
-set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[9]}]
-
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[0]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[10]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[11]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[12]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[13]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[14]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[15]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[16]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[17]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[18]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[19]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[1]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[20]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[21]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[22]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[23]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[24]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[25]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[26]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[27]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[28]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[29]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[2]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[30]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[31]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[3]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[4]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[5]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[6]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[7]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[8]}]
-set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[9]}]
-
-
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[0]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[1]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[2]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[3]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[4]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[5]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[6]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[7]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[8]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
-
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[0]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[1]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[2]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[3]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[4]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[5]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[6]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[7]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[8]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
-
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[0]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[1]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[2]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[3]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[4]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[5]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[6]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[7]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[8]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[0]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[1]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[2]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[3]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[4]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[5]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[6]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[7]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[8]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_cen_b}]
-
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_cen_b}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[0]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[1]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[2]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[3]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[4]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[5]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[6]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[7]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[8]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[9]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[10]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[11]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[12]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[13]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[14]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[15]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[16]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[17]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[18]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[19]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[20]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[21]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[22]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[23]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[24]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[25]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[26]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[27]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[28]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[29]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[30]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[31]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[0]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[1]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[2]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[3]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_web_b}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[0]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[1]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[2]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[3]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[4]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[5]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[6]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[7]}]
-set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[8]}]
-
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_cen_b}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[0]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[1]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[2]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[3]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[4]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[5]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[6]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[7]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[8]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[9]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[10]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[11]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[12]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[13]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[14]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[15]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[16]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[17]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[18]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[19]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[20]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[21]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[22]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[23]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[24]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[25]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[26]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[27]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[28]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[29]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[30]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[31]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[0]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[1]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[2]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[3]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_web_b}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[0]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[1]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[2]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[3]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[4]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[5]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[6]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[7]}]
-set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[8]}]
-###############################################################################
-# Environment
-###############################################################################
-set_load -pin_load 0.0334 [get_ports {bist_correct}]
-set_load -pin_load 0.0334 [get_ports {bist_done}]
-set_load -pin_load 0.0334 [get_ports {bist_error}]
-set_load -pin_load 0.0334 [get_ports {bist_sdo}]
-set_load -pin_load 0.0334 [get_ports {mem_cen_a}]
-set_load -pin_load 0.0334 [get_ports {mem_cen_b}]
-set_load -pin_load 0.0334 [get_ports {mem_clk_a}]
-set_load -pin_load 0.0334 [get_ports {mem_clk_b}]
-set_load -pin_load 0.0334 [get_ports {mem_web_b}]
-set_load -pin_load 0.0334 [get_ports {bist_error_cnt[3]}]
-set_load -pin_load 0.0334 [get_ports {bist_error_cnt[2]}]
-set_load -pin_load 0.0334 [get_ports {bist_error_cnt[1]}]
-set_load -pin_load 0.0334 [get_ports {bist_error_cnt[0]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[31]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[30]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[29]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[28]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[27]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[26]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[25]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[24]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[23]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[22]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[21]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[20]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[19]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[18]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[17]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[16]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[15]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[14]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[13]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[12]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[11]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[10]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[9]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[8]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[7]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[6]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[5]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[4]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[3]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[2]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[1]}]
-set_load -pin_load 0.0334 [get_ports {func_dout_a[0]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_a[8]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_a[7]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_a[6]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_a[5]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_a[4]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_a[3]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_a[2]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_a[1]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_a[0]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_b[8]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_b[7]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_b[6]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_b[5]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_b[4]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_b[3]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_b[2]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_b[1]}]
-set_load -pin_load 0.0334 [get_ports {mem_addr_b[0]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[31]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[30]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[29]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[28]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[27]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[26]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[25]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[24]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[23]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[22]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[21]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[20]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[19]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[18]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[17]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[16]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[15]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[14]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[13]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[12]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[11]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[10]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[9]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[8]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[7]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[6]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[5]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[4]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[3]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[2]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[1]}]
-set_load -pin_load 0.0334 [get_ports {mem_din_b[0]}]
-set_load -pin_load 0.0334 [get_ports {mem_mask_b[3]}]
-set_load -pin_load 0.0334 [get_ports {mem_mask_b[2]}]
-set_load -pin_load 0.0334 [get_ports {mem_mask_b[1]}]
-set_load -pin_load 0.0334 [get_ports {mem_mask_b[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_clk}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_en}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_load}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_run}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdi}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_shift}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_cen_a}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_cen_b}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_clk_a}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_clk_b}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_web_b}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_mask_b[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_mask_b[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_mask_b[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_mask_b[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[0]}]
-set_timing_derate -early 0.9500
-set_timing_derate -late 1.0500
-###############################################################################
-# Design Rules
-###############################################################################
-set_max_fanout 4.0000 [current_design]

diff --git a/openlane/mbist/pin_order.cfg b/openlane/mbist/pin_order.cfg
deleted file mode 100644
index 0503337..0000000
--- a/openlane/mbist/pin_order.cfg
+++ /dev/null

@@ -1,214 +0,0 @@
-#BUS_SORT
-
-#MANUAL_PLACE
-
-
-#W
-bist_clk           0000 0 4
-rst_n
-bist_en
-bist_run
-bist_shift
-bist_load
-bist_done
-bist_error
-bist_correct
-bist_error_cnt\[3\]
-bist_error_cnt\[2\]
-bist_error_cnt\[1\]
-bist_error_cnt\[0\]
-bist_sdi
-bist_sdo
-
-
-#S
-func_clk_a         0000 2 2
-func_cen_a
-func_addr_a\[8\]
-func_addr_a\[7\]
-func_addr_a\[6\]
-func_addr_a\[5\]
-func_addr_a\[4\]
-func_addr_a\[3\]
-func_addr_a\[2\]
-func_addr_a\[1\]
-func_addr_a\[0\]
-func_dout_a\[31\]
-func_dout_a\[30\]
-func_dout_a\[29\]
-func_dout_a\[28\]
-func_dout_a\[27\]
-func_dout_a\[26\]
-func_dout_a\[25\]
-func_dout_a\[24\]
-func_dout_a\[23\]
-func_dout_a\[22\]
-func_dout_a\[21\]
-func_dout_a\[20\]
-func_dout_a\[19\]
-func_dout_a\[18\]
-func_dout_a\[17\]
-func_dout_a\[16\]
-func_dout_a\[15\]
-func_dout_a\[14\]
-func_dout_a\[13\]
-func_dout_a\[12\]
-func_dout_a\[11\]
-func_dout_a\[10\]
-func_dout_a\[9\]
-func_dout_a\[8\]
-func_dout_a\[7\]
-func_dout_a\[6\]
-func_dout_a\[5\]
-func_dout_a\[4\]
-func_dout_a\[3\]
-func_dout_a\[2\]
-func_dout_a\[1\]
-func_dout_a\[0\]
-
-func_clk_b        0200 0 2
-func_cen_b
-func_web_b
-func_mask_b\[3\]
-func_mask_b\[2\]
-func_mask_b\[1\]
-func_mask_b\[0\]
-func_addr_b\[8\]
-func_addr_b\[7\]
-func_addr_b\[6\]
-func_addr_b\[5\]
-func_addr_b\[4\]
-func_addr_b\[3\]
-func_addr_b\[2\]
-func_addr_b\[1\]
-func_addr_b\[0\]
-func_din_b\[31\]
-func_din_b\[30\]
-func_din_b\[29\]
-func_din_b\[28\]
-func_din_b\[27\]
-func_din_b\[26\]
-func_din_b\[25\]
-func_din_b\[24\]
-func_din_b\[23\]
-func_din_b\[22\]
-func_din_b\[21\]
-func_din_b\[20\]
-func_din_b\[19\]
-func_din_b\[18\]
-func_din_b\[17\]
-func_din_b\[16\]
-func_din_b\[15\]
-func_din_b\[14\]
-func_din_b\[13\]
-func_din_b\[12\]
-func_din_b\[11\]
-func_din_b\[10\]
-func_din_b\[9\]
-func_din_b\[8\]
-func_din_b\[7\]
-func_din_b\[6\]
-func_din_b\[5\]
-func_din_b\[4\]
-func_din_b\[3\]
-func_din_b\[2\]
-func_din_b\[1\]
-func_din_b\[0\]
-
-#N
-
-mem_clk_b       0000 0 2
-mem_cen_b
-mem_web_b
-mem_mask_b\[0\]
-mem_mask_b\[1\]
-mem_mask_b\[2\]
-mem_mask_b\[3\]
-mem_addr_b\[0\]
-mem_addr_b\[1\]
-mem_addr_b\[2\]
-mem_addr_b\[3\]
-mem_addr_b\[4\]
-mem_addr_b\[5\]
-mem_addr_b\[6\]
-mem_addr_b\[7\]
-mem_addr_b\[8\]
-mem_din_b\[0\]
-mem_din_b\[1\]
-mem_din_b\[2\]
-mem_din_b\[3\]
-mem_din_b\[4\]
-mem_din_b\[5\]
-mem_din_b\[6\]
-mem_din_b\[7\]
-mem_din_b\[8\]
-mem_din_b\[9\]
-mem_din_b\[10\]
-mem_din_b\[11\]
-mem_din_b\[12\]
-mem_din_b\[13\]
-mem_din_b\[14\]
-mem_din_b\[15\]
-mem_din_b\[16\]
-mem_din_b\[17\]
-mem_din_b\[18\]
-mem_din_b\[19\]
-mem_din_b\[20\]
-mem_din_b\[21\]
-mem_din_b\[22\]
-mem_din_b\[23\]
-mem_din_b\[24\]
-mem_din_b\[25\]
-mem_din_b\[26\]
-mem_din_b\[27\]
-mem_din_b\[28\]
-mem_din_b\[29\]
-mem_din_b\[30\]
-mem_din_b\[31\]
-
-
-mem_dout_a\[0\]  0100 0 2
-mem_dout_a\[1\]
-mem_dout_a\[2\]
-mem_dout_a\[3\]
-mem_dout_a\[4\]
-mem_dout_a\[5\]
-mem_dout_a\[6\]
-mem_dout_a\[7\]
-mem_dout_a\[8\]
-mem_dout_a\[9\]
-mem_dout_a\[10\]
-mem_dout_a\[11\]
-mem_dout_a\[12\]
-mem_dout_a\[13\]
-mem_dout_a\[14\]
-mem_dout_a\[15\]
-mem_dout_a\[16\]
-mem_dout_a\[17\]
-mem_dout_a\[18\]
-mem_dout_a\[19\]
-mem_dout_a\[20\]
-mem_dout_a\[21\]
-mem_dout_a\[22\]
-mem_dout_a\[23\]
-mem_dout_a\[24\]
-mem_dout_a\[25\]
-mem_dout_a\[26\]
-mem_dout_a\[27\]
-mem_dout_a\[28\]
-mem_dout_a\[29\]
-mem_dout_a\[30\]
-mem_dout_a\[31\]
-
-
-mem_clk_a          0200 0 2
-mem_cen_a
-mem_addr_a\[8\]
-mem_addr_a\[7\]
-mem_addr_a\[6\]
-mem_addr_a\[5\]
-mem_addr_a\[4\]
-mem_addr_a\[3\]
-mem_addr_a\[2\]
-mem_addr_a\[1\]
-mem_addr_a\[0\]

diff --git a/openlane/mbist1/base.sdc b/openlane/mbist1/base.sdc
new file mode 100644
index 0000000..4689f62
--- /dev/null
+++ b/openlane/mbist1/base.sdc

@@ -0,0 +1,151 @@
+###############################################################################
+# Created by write_sdc
+# Sun Nov 14 09:33:23 2021
+###############################################################################
+current_design mbist_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wb_clk_i -period 8.0000 [get_ports {wb_clk_i}]
+create_generated_clock -name bist_mem_clk_a -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks wb_clk_i] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a]
+create_generated_clock -name bist_mem_clk_b -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks wb_clk_i] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b]
+
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks {wb_clk_i bist_mem_clk_a bist_mem_clk_b}]  
+
+set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
+set_clock_uncertainty -setup 0.2500 wb_clk_i
+set_clock_uncertainty -setup 0.2500 mem_clk_a
+set_clock_uncertainty -setup 0.2500 mem_clk_b
+
+set_clock_uncertainty -hold 0.1500 wb_clk_i
+set_clock_uncertainty -hold 0.1500 mem_clk_a
+set_clock_uncertainty -hold 0.1500 mem_clk_b
+
+set_input_delay  -max 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}]
+set_input_delay  -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}]
+
+set_false_path -from [get_ports {bist_en}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}]
+
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_en}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}]
+
+## Functional Inputs
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_adr_i[*]}]  
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_stb_i}]      
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_cyc_i}]      
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_we_i}]      
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wbd_mbist1_dat_o[*]}] 
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_sel_i[*]}]
+
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_adr_i[*]}]  
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_stb_i}]      
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_cyc_i}]      
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_we_i}]      
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wbd_mbist1_dat_o[*]}] 
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_sel_i[*]}]
+
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_dat_o[*]}]  
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_ack_o}]  
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_err_o}]  
+
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_dat_o[*]}]  
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_ack_o}]  
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_err_o}]  
+
+## Towards MEMORY from MBIST CLOCK
+## PORT-A
+set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}]
+
+
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
+
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
+
+
+
+## PORT-B
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}]
+
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {bist_correct}]
+set_load -pin_load 0.0334 [get_ports {bist_done}]
+set_load -pin_load 0.0334 [get_ports {bist_error}]
+set_load -pin_load 0.0334 [get_ports {bist_sdo}]
+set_load -pin_load 0.0334 [get_ports {mem_cen_a}]
+set_load -pin_load 0.0334 [get_ports {mem_cen_b}]
+set_load -pin_load 0.0334 [get_ports {mem_clk_a}]
+set_load -pin_load 0.0334 [get_ports {mem_clk_b}]
+set_load -pin_load 0.0334 [get_ports {mem_web_b}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[3]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[2]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[1]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_cyc_i}]
+set_load -pin_load 0.0334 [get_ports {wb_stb_i}]
+set_load -pin_load 0.0334 [get_ports {wb_adr_i[*]}]
+set_load -pin_load 0.0334 [get_ports {wb_we_i}]
+set_load -pin_load 0.0334 [get_ports {wb_dat_i[*]}]
+set_load -pin_load 0.0334 [get_ports {wb_sel_i[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_addr_a[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_addr_b[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_din_b[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_mask_b[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_en}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_load}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_run}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdi}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_shift}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[*]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]

diff --git a/openlane/mbist/config.tcl b/openlane/mbist1/config.tcl
similarity index 65%
copy from openlane/mbist/config.tcl
copy to openlane/mbist1/config.tcl
index de3c917..472b336 100755
--- a/openlane/mbist/config.tcl
+++ b/openlane/mbist1/config.tcl

@@ -20,13 +20,13 @@
 set script_dir [file dirname [file normalize [info script]]]
 # Name
 
-set ::env(DESIGN_NAME) mbist_top
+set ::env(DESIGN_NAME) mbist_top1
 
 set ::env(DESIGN_IS_CORE) "0"
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "8"
-set ::env(CLOCK_PORT) "bist_clk u_mem_sel.u_cts_mem_clk_a/X u_mem_sel.u_cts_mem_clk_a/X"
+set ::env(CLOCK_PORT) "wb_clk_i u_mem_sel.u_cts_mem_clk_a/X u_mem_sel.u_cts_mem_clk_a/X"
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
@@ -35,21 +35,33 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
-     $script_dir/../../verilog/rtl/mbist/src/mbist_addr_gen.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_fsm.sv     \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_op_sel.sv  \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_repair_addr.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_top.sv  \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_sti_sel.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_pat_sel.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_mux.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_data_cmp.sv \
+     $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_addr_gen.sv \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_fsm.sv     \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_op_sel.sv  \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_repair_addr.sv \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_sti_sel.sv \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_pat_sel.sv \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_mux.sv \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_data_cmp.sv \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv \
+     $script_dir/../../verilog/rtl/mbist/src/top/mbist_top1.sv  \
      $script_dir/../../verilog/rtl/lib/ctech_cells.sv     \
      $script_dir/../../verilog/rtl/lib/reset_sync.sv \
 	     "
 
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/mbist/include ]
 
+
+set ::env(SYNTH_PARAMS) "BIST_ADDR_WD 9,\
+	                 BIST_DATA_WD 32,\
+		         BIST_ADDR_START 9'h000,\
+			 BIST_ADDR_END 9'h1FB,\
+			 BIST_REPAIR_ADDR_START 9'h1FC,\
+			 BIST_RAD_WD_I 9,\
+			 BIST_RAD_WD_O 9\
+			 "
+
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 set ::env(SDC_FILE) "$script_dir/base.sdc"
 set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
@@ -66,7 +78,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 200"
+set ::env(DIE_AREA) "0 0 200 250"
 
 
 # If you're going to use multiple power domains, then keep this disabled.
@@ -76,7 +88,7 @@
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.30"
+set ::env(PL_TARGET_DENSITY) "0.40"
 
 
 

diff --git a/openlane/mbist1/interactive.tcl b/openlane/mbist1/interactive.tcl
new file mode 100644
index 0000000..32f160d
--- /dev/null
+++ b/openlane/mbist1/interactive.tcl

@@ -0,0 +1,407 @@
+#!/usr/bin/tclsh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# Copyright 2020 Efabless Corporation
+# Copyright 2020 Sylvain Munaut
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+package require openlane;
+
+
+proc run_placement_step {args} {
+    # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
+    # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
+    # set_def $pdndef
+    puts "\[INFO\]: Running Placement Step"
+    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+    }
+
+    run_placement
+}
+
+proc run_cts_step {args} {
+    # set_def $::env(opendp_result_file_tag).def
+    puts "\[INFO\]: Running CTS"
+    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+    }
+
+    run_cts
+    run_resizer_timing
+}
+
+proc run_routing_step {args} {
+    # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
+    # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
+    # set_def $resizerdef
+    puts "\[INFO\]: Running Routing"
+    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+    }
+    run_routing
+}
+
+proc run_diode_insertion_2_5_step {args} {
+    puts "\[INFO\]: Running Diode Insertion"
+    # set_def $::env(tritonRoute_result_file_tag).def
+    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+    }
+	if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+		run_antenna_check
+		heal_antenna_violators; # modifies the routed DEF
+	}
+
+}
+
+proc run_power_pins_insertion_step {args} {
+    puts "\[INFO\]:Running Power Pin Insertion"
+    # set_def $::env(tritonRoute_result_file_tag).def
+    if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
+        set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
+    }
+    if { $::env(LVS_INSERT_POWER_PINS) } {
+		write_powered_verilog
+		set_netlist $::env(lvs_result_file_tag).powered.v
+    }
+
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+    # set_def $::env(tritonRoute_result_file_tag).def
+    puts "\[INFO\]:Running LVS Step"
+    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+    }
+	if { $lvs_enabled } {
+		run_magic_spice_export
+		run_lvs; # requires run_magic_spice_export
+	}
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+    puts "\[INFO\]:Running DRC"
+    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+    }
+	if { $drc_enabled } {
+		run_magic_drc
+		run_klayout_drc
+	}
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+    puts "\[INFO\]: Running Antenna checl"
+    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+    }
+	if { $antenna_check_enabled } {
+		run_antenna_check
+	}
+}
+
+proc gen_pdn_new {args} {
+    puts_info "Generating PDN..."
+    TIMER::timer_start
+	
+    set ::env(SAVE_DEF) [index_file $::env(pdn_tmp_file_tag).def]
+    set ::env(PGA_RPT_FILE) [index_file $::env(pdn_report_file_tag).pga.rpt]
+
+    try_catch $::env(OPENROAD_BIN) -exit $::env(SCRIPTS_DIR)/openroad/or_pdn.tcl \
+	|& tee $::env(TERMINAL_OUTPUT) [index_file $::env(pdn_log_file_tag).log 0]
+
+
+    TIMER::timer_stop
+    exec echo "[TIMER::get_runtime]" >> [index_file $::env(pdn_log_file_tag)_runtime.txt 0]
+
+	quit_on_unconnected_pdn_nodes
+
+    set_def $::env(SAVE_DEF)
+}
+
+proc run_power_grid_generation_new {args} {
+	if { [info exists ::env(VDD_NETS)] || [info exists ::env(GND_NETS)] } {
+		# they both must exist and be equal in length
+		# current assumption: they cannot have a common ground
+		if { ! [info exists ::env(VDD_NETS)] || ! [info exists ::env(GND_NETS)] } {
+			puts_err "VDD_NETS and GND_NETS must *both* either be defined or undefined"
+			return -code error
+		}
+		# standard cell power and ground nets are assumed to be the first net 
+		set ::env(VDD_PIN) [lindex $::env(VDD_NETS) 0]
+		set ::env(GND_PIN) [lindex $::env(GND_NETS) 0]
+	} elseif { [info exists ::env(SYNTH_USE_PG_PINS_DEFINES)] } {
+		set ::env(VDD_NETS) [list]
+		set ::env(GND_NETS) [list]
+		# get the pins that are in $yosys_tmp_file_tag.pg_define.v
+		# that are not in $yosys_result_file_tag.v
+		#
+		set full_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_tmp_file_tag).pg_define.v]
+		puts_info $full_pins
+
+		set non_pg_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_result_file_tag).v]
+		puts_info $non_pg_pins
+
+		# assumes the pins are ordered correctly (e.g., vdd1, vss1, vcc1, vss1, ...)
+		foreach {vdd gnd} $full_pins {
+			if { $vdd ne "" && $vdd ni $non_pg_pins } {
+				lappend ::env(VDD_NETS) $vdd
+			}
+			if { $gnd ne "" && $gnd ni $non_pg_pins } {
+				lappend ::env(GND_NETS) $gnd
+			}
+		}
+	} else {
+		set ::env(VDD_NETS) $::env(VDD_PIN)
+		set ::env(GND_NETS) $::env(GND_PIN)
+	}
+
+	puts_info "Power planning the following nets"
+	puts_info "Power: $::env(VDD_NETS)"
+	puts_info "Ground: $::env(GND_NETS)"
+
+	if { [llength $::env(VDD_NETS)] != [llength $::env(GND_NETS)] } {
+		puts_err "VDD_NETS and GND_NETS must be of equal lengths"
+		return -code error
+	}
+
+	# internal macros power connections 
+	if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} {
+		set macro_hooks [dict create]
+		set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
+		foreach pdn_hook $pdn_hooks {
+			set instance_name [lindex $pdn_hook 0]
+			set power_net [lindex $pdn_hook 1]
+			set ground_net [lindex $pdn_hook 2]
+			dict append macro_hooks $instance_name [subst {$power_net $ground_net}]
+		}
+		
+		set power_net_indx [lsearch $::env(VDD_NETS) $power_net]
+		set ground_net_indx [lsearch $::env(GND_NETS) $ground_net]
+
+		# make sure that the specified power domains exist.
+		if { $power_net_indx == -1  || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } {
+			puts_err "Can't find $power_net and $ground_net domain. \
+			Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)." 
+		} 
+	}
+	
+	# generate multiple power grids per pair of (VDD,GND)
+	# offseted by WIDTH + SPACING
+	foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
+		set ::env(VDD_NET) $vdd
+		set ::env(GND_NET) $gnd
+                puts "\[INFO\]: Processing Power Nets: $vdd and $gnd."
+
+		# internal macros power connections
+		set ::env(FP_PDN_MACROS) ""
+		if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 } {
+			# if macros connections to power are explicitly set
+			# default behavoir macro pins will be connected to the first power domain
+			if { [info exists ::env(FP_PDN_MACRO_HOOKS)] } {
+				set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
+				foreach {instance_name hooks} $macro_hooks {
+					set power [lindex $hooks 0]
+					set ground [lindex $hooks 1]			 
+					if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } {
+						set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
+						puts_info "Connecting $instance_name to $power and $ground nets."
+						lappend ::env(FP_PDN_MACROS) $instance_name
+					}
+				}
+			} 
+                   puts "\[INFO\]: FP_PDN_MACROS: $::env(FP_PDN_MACROS) ."
+		} else {
+			puts_warn "All internal macros will not be connected to power."
+		}
+		
+		gen_pdn_new
+
+		set ::env(FP_PDN_ENABLE_RAILS) 0
+		set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
+
+		# allow failure until open_pdks is up to date...
+		catch {set ::env(FP_PDN_VOFFSET) [expr $::env(FP_PDN_VOFFSET)+$::env(FP_PDN_VWIDTH)+$::env(FP_PDN_VSPACING)]}
+		catch {set ::env(FP_PDN_HOFFSET) [expr $::env(FP_PDN_HOFFSET)+$::env(FP_PDN_HWIDTH)+$::env(FP_PDN_HSPACING)]}
+
+		catch {set ::env(FP_PDN_CORE_RING_VOFFSET) \
+			[expr $::env(FP_PDN_CORE_RING_VOFFSET)\
+			+2*($::env(FP_PDN_CORE_RING_VWIDTH)\
+			+max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
+		catch {set ::env(FP_PDN_CORE_RING_HOFFSET) [expr $::env(FP_PDN_CORE_RING_HOFFSET)\
+			+2*($::env(FP_PDN_CORE_RING_HWIDTH)+\
+			max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
+	}
+	set ::env(FP_PDN_ENABLE_RAILS) 1
+}
+
+proc run_floorplan_new {args} {
+		puts_info "Running Floorplanning..."
+		# |----------------------------------------------------|
+		# |----------------   2. FLOORPLAN   ------------------|
+		# |----------------------------------------------------|
+		#
+		# intial fp
+		init_floorplan
+
+
+		# place io
+		if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+				place_io_ol
+		} else {
+			if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+				place_io
+				global_placement_or
+				place_contextualized_io \
+					-lef $::env(FP_CONTEXT_LEF) \
+					-def $::env(FP_CONTEXT_DEF)
+			} else {
+				place_io
+			}
+		}
+
+		apply_def_template
+
+		if { [info exist ::env(EXTRA_LEFS)] } {
+			if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+				file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(TMP_DIR)/macro_placement.cfg
+				manual_macro_placement f
+			} else {
+				global_placement_or
+				basic_macro_placement
+			}
+		}
+
+		# tapcell
+		tap_decap_or
+		scrot_klayout -layout $::env(CURRENT_DEF)
+		# power grid generation
+		run_power_grid_generation_new
+}
+
+
+proc run_flow {args} {
+       set script_dir [file dirname [file normalize [info script]]]
+
+		set options {
+		{-design required}
+		{-save_path optional}
+		{-no_lvs optional}
+	    {-no_drc optional}
+	    {-no_antennacheck optional}
+	}
+	set flags {-save}
+	parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
+
+	prep {*}$args
+
+        set LVS_ENABLED 1
+        set DRC_ENABLED 0
+        set ANTENNACHECK_ENABLED 1
+
+        set steps [dict create "synthesis" {run_synthesis "" } \
+                "floorplan" {run_floorplan ""} \
+                "placement" {run_placement_step ""} \
+                "cts" {run_cts_step ""} \
+                "routing" {run_routing_step ""}\
+                "diode_insertion" {run_diode_insertion_2_5_step ""} \
+                "power_pins_insertion" {run_power_pins_insertion_step ""} \
+                "gds_magic" {run_magic ""} \
+                "gds_drc_klayout" {run_klayout ""} \
+                "gds_xor_klayout" {run_klayout_gds_xor ""} \
+                "lvs" "run_lvs_step $LVS_ENABLED" \
+                "drc" "run_drc_step $DRC_ENABLED" \
+                "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
+                "cvc" {run_lef_cvc}
+        ]
+
+       set_if_unset arg_values(-to) "cvc";
+
+       if {  [info exists ::env(CURRENT_STEP) ] } {
+           puts "\[INFO\]:Picking up where last execution left off"
+           puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
+       } else {
+           set ::env(CURRENT_STEP) "synthesis";
+       }
+       set_if_unset arg_values(-from) $::env(CURRENT_STEP);
+       set exe 0;
+       dict for {step_name step_exe} $steps {
+           if { [ string equal $arg_values(-from) $step_name ] } {
+               set exe 1;
+           }
+
+           if { $exe } {
+               # For when it fails
+               set ::env(CURRENT_STEP) $step_name
+               [lindex $step_exe 0] [lindex $step_exe 1] ;
+           }
+
+           if { [ string equal $arg_values(-to) $step_name ] } {
+               set exe 0:
+               break;
+           }
+
+       }
+
+       # for when it resumes
+       set steps_as_list [dict keys $steps]
+       set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+       set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+	if {  [info exists flags_map(-save) ] } {
+		if { ! [info exists arg_values(-save_path)] } {
+			set arg_values(-save_path) ""
+		}
+		save_views 	-lef_path $::env(magic_result_file_tag).lef \
+			-def_path $::env(CURRENT_DEF) \
+			-gds_path $::env(magic_result_file_tag).gds \
+			-mag_path $::env(magic_result_file_tag).mag \
+			-maglef_path $::env(magic_result_file_tag).lef.mag \
+			-spice_path $::env(magic_result_file_tag).spice \
+			-spef_path $::env(CURRENT_SPEF) \
+			-verilog_path $::env(CURRENT_NETLIST) \
+			-save_path $arg_values(-save_path) \
+			-tag $::env(RUN_TAG)
+	}
+
+
+	calc_total_runtime
+	save_state
+	generate_final_summary_report
+	
+	check_timing_violations
+
+	puts_success "Flow Completed Without Fatal Errors."
+
+}
+
+run_flow {*}$argv

diff --git a/openlane/mbist1/pin_order.cfg b/openlane/mbist1/pin_order.cfg
new file mode 100644
index 0000000..40431b0
--- /dev/null
+++ b/openlane/mbist1/pin_order.cfg

@@ -0,0 +1,209 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+
+#N
+cfg_cska_mbist\[3\]  0000 0 4
+cfg_cska_mbist\[2\]
+cfg_cska_mbist\[1\]
+cfg_cska_mbist\[0\]
+wbd_clk_int
+wbd_clk_mbist
+wb_clk_i           
+rst_n
+bist_en
+bist_run
+bist_shift
+bist_load
+bist_done
+bist_error
+bist_correct
+bist_error_cnt\[3\]
+bist_error_cnt\[2\]
+bist_error_cnt\[1\]
+bist_error_cnt\[0\]
+bist_sdi
+bist_sdo
+
+
+#W
+wb_cyc_i         0000 2 2
+wb_stb_i
+wb_we_i
+wb_adr_i\[8\]
+wb_adr_i\[7\]
+wb_adr_i\[6\]
+wb_adr_i\[5\]
+wb_adr_i\[4\]
+wb_adr_i\[3\]
+wb_adr_i\[2\]
+wb_adr_i\[1\]
+wb_adr_i\[0\]
+wb_dat_i\[31\]
+wb_dat_i\[30\]
+wb_dat_i\[29\]
+wb_dat_i\[28\]
+wb_dat_i\[27\]
+wb_dat_i\[26\]
+wb_dat_i\[25\]
+wb_dat_i\[24\]
+wb_dat_i\[23\]
+wb_dat_i\[22\]
+wb_dat_i\[21\]
+wb_dat_i\[20\]
+wb_dat_i\[19\]
+wb_dat_i\[18\]
+wb_dat_i\[17\]
+wb_dat_i\[16\]
+wb_dat_i\[15\]
+wb_dat_i\[14\]
+wb_dat_i\[13\]
+wb_dat_i\[12\]
+wb_dat_i\[11\]
+wb_dat_i\[10\]
+wb_dat_i\[9\]
+wb_dat_i\[8\]
+wb_dat_i\[7\]
+wb_dat_i\[6\]
+wb_dat_i\[5\]
+wb_dat_i\[4\]
+wb_dat_i\[3\]
+wb_dat_i\[2\]
+wb_dat_i\[1\]
+wb_dat_i\[0\]
+wb_sel_i\[3\]
+wb_sel_i\[2\]
+wb_sel_i\[1\]
+wb_sel_i\[0\]
+wb_dat_o\[31\]
+wb_dat_o\[30\]
+wb_dat_o\[29\]
+wb_dat_o\[28\]
+wb_dat_o\[27\]
+wb_dat_o\[26\]
+wb_dat_o\[25\]
+wb_dat_o\[24\]
+wb_dat_o\[23\]
+wb_dat_o\[22\]
+wb_dat_o\[21\]
+wb_dat_o\[20\]
+wb_dat_o\[19\]
+wb_dat_o\[18\]
+wb_dat_o\[17\]
+wb_dat_o\[16\]
+wb_dat_o\[15\]
+wb_dat_o\[14\]
+wb_dat_o\[13\]
+wb_dat_o\[12\]
+wb_dat_o\[11\]
+wb_dat_o\[10\]
+wb_dat_o\[9\]
+wb_dat_o\[8\]
+wb_dat_o\[7\]
+wb_dat_o\[6\]
+wb_dat_o\[5\]
+wb_dat_o\[4\]
+wb_dat_o\[3\]
+wb_dat_o\[2\]
+wb_dat_o\[1\]
+wb_dat_o\[0\]
+wb_ack_o
+wb_err_o
+
+#E
+mem_clk_b       0000 0 2
+mem_cen_b
+mem_web_b
+mem_mask_b\[0\]
+mem_mask_b\[1\]
+mem_mask_b\[2\]
+mem_mask_b\[3\]
+mem_addr_b\[0\]
+mem_addr_b\[1\]
+mem_addr_b\[2\]
+mem_addr_b\[3\]
+mem_addr_b\[4\]
+mem_addr_b\[5\]
+mem_addr_b\[6\]
+mem_addr_b\[7\]
+mem_addr_b\[8\]
+mem_din_b\[0\]
+mem_din_b\[1\]
+mem_din_b\[2\]
+mem_din_b\[3\]
+mem_din_b\[4\]
+mem_din_b\[5\]
+mem_din_b\[6\]
+mem_din_b\[7\]
+mem_din_b\[8\]
+mem_din_b\[9\]
+mem_din_b\[10\]
+mem_din_b\[11\]
+mem_din_b\[12\]
+mem_din_b\[13\]
+mem_din_b\[14\]
+mem_din_b\[15\]
+mem_din_b\[16\]
+mem_din_b\[17\]
+mem_din_b\[18\]
+mem_din_b\[19\]
+mem_din_b\[20\]
+mem_din_b\[21\]
+mem_din_b\[22\]
+mem_din_b\[23\]
+mem_din_b\[24\]
+mem_din_b\[25\]
+mem_din_b\[26\]
+mem_din_b\[27\]
+mem_din_b\[28\]
+mem_din_b\[29\]
+mem_din_b\[30\]
+mem_din_b\[31\]
+
+
+mem_dout_a\[0\]  0100 0 2
+mem_dout_a\[1\]
+mem_dout_a\[2\]
+mem_dout_a\[3\]
+mem_dout_a\[4\]
+mem_dout_a\[5\]
+mem_dout_a\[6\]
+mem_dout_a\[7\]
+mem_dout_a\[8\]
+mem_dout_a\[9\]
+mem_dout_a\[10\]
+mem_dout_a\[11\]
+mem_dout_a\[12\]
+mem_dout_a\[13\]
+mem_dout_a\[14\]
+mem_dout_a\[15\]
+mem_dout_a\[16\]
+mem_dout_a\[17\]
+mem_dout_a\[18\]
+mem_dout_a\[19\]
+mem_dout_a\[20\]
+mem_dout_a\[21\]
+mem_dout_a\[22\]
+mem_dout_a\[23\]
+mem_dout_a\[24\]
+mem_dout_a\[25\]
+mem_dout_a\[26\]
+mem_dout_a\[27\]
+mem_dout_a\[28\]
+mem_dout_a\[29\]
+mem_dout_a\[30\]
+mem_dout_a\[31\]
+
+
+mem_clk_a          0200 0 2
+mem_cen_a
+mem_addr_a\[8\]
+mem_addr_a\[7\]
+mem_addr_a\[6\]
+mem_addr_a\[5\]
+mem_addr_a\[4\]
+mem_addr_a\[3\]
+mem_addr_a\[2\]
+mem_addr_a\[1\]
+mem_addr_a\[0\]

diff --git a/openlane/mbist/sta.tcl b/openlane/mbist1/sta.tcl
similarity index 100%
rename from openlane/mbist/sta.tcl
rename to openlane/mbist1/sta.tcl


diff --git a/openlane/mbist2/base.sdc b/openlane/mbist2/base.sdc
new file mode 100644
index 0000000..4689f62
--- /dev/null
+++ b/openlane/mbist2/base.sdc

@@ -0,0 +1,151 @@
+###############################################################################
+# Created by write_sdc
+# Sun Nov 14 09:33:23 2021
+###############################################################################
+current_design mbist_top
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name wb_clk_i -period 8.0000 [get_ports {wb_clk_i}]
+create_generated_clock -name bist_mem_clk_a -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks wb_clk_i] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a]
+create_generated_clock -name bist_mem_clk_b -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks wb_clk_i] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b]
+
+set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks {wb_clk_i bist_mem_clk_a bist_mem_clk_b}]  
+
+set_clock_transition 0.1500 [get_clocks {wb_clk_i}]
+set_clock_uncertainty -setup 0.2500 wb_clk_i
+set_clock_uncertainty -setup 0.2500 mem_clk_a
+set_clock_uncertainty -setup 0.2500 mem_clk_b
+
+set_clock_uncertainty -hold 0.1500 wb_clk_i
+set_clock_uncertainty -hold 0.1500 mem_clk_a
+set_clock_uncertainty -hold 0.1500 mem_clk_b
+
+set_input_delay  -max 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}]
+set_input_delay  -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}]
+
+set_false_path -from [get_ports {bist_en}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}]
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}]
+
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_en}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}]
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}]
+
+## Functional Inputs
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_adr_i[*]}]  
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_stb_i}]      
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_cyc_i}]      
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_we_i}]      
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wbd_mbist1_dat_o[*]}] 
+set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_sel_i[*]}]
+
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_adr_i[*]}]  
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_stb_i}]      
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_cyc_i}]      
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_we_i}]      
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wbd_mbist1_dat_o[*]}] 
+set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay   [get_ports {wb_sel_i[*]}]
+
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_dat_o[*]}]  
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_ack_o}]  
+set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_err_o}]  
+
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_dat_o[*]}]  
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_ack_o}]  
+set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay     [get_ports {wb_err_o}]  
+
+## Towards MEMORY from MBIST CLOCK
+## PORT-A
+set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}]
+set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}]
+
+
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
+
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
+
+
+
+## PORT-B
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}]
+set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}]
+
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}]
+set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}]
+
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {bist_correct}]
+set_load -pin_load 0.0334 [get_ports {bist_done}]
+set_load -pin_load 0.0334 [get_ports {bist_error}]
+set_load -pin_load 0.0334 [get_ports {bist_sdo}]
+set_load -pin_load 0.0334 [get_ports {mem_cen_a}]
+set_load -pin_load 0.0334 [get_ports {mem_cen_b}]
+set_load -pin_load 0.0334 [get_ports {mem_clk_a}]
+set_load -pin_load 0.0334 [get_ports {mem_clk_b}]
+set_load -pin_load 0.0334 [get_ports {mem_web_b}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[3]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[2]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[1]}]
+set_load -pin_load 0.0334 [get_ports {bist_error_cnt[0]}]
+set_load -pin_load 0.0334 [get_ports {wb_cyc_i}]
+set_load -pin_load 0.0334 [get_ports {wb_stb_i}]
+set_load -pin_load 0.0334 [get_ports {wb_adr_i[*]}]
+set_load -pin_load 0.0334 [get_ports {wb_we_i}]
+set_load -pin_load 0.0334 [get_ports {wb_dat_i[*]}]
+set_load -pin_load 0.0334 [get_ports {wb_sel_i[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_addr_a[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_addr_b[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_din_b[*]}]
+set_load -pin_load 0.0334 [get_ports {mem_mask_b[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_en}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_load}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_run}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdi}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_shift}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[*]}]
+set_timing_derate -early 0.9500
+set_timing_derate -late 1.0500
+###############################################################################
+# Design Rules
+###############################################################################
+set_max_fanout 4.0000 [current_design]

diff --git a/openlane/mbist/config.tcl b/openlane/mbist2/config.tcl
similarity index 65%
rename from openlane/mbist/config.tcl
rename to openlane/mbist2/config.tcl
index de3c917..178f02a 100755
--- a/openlane/mbist/config.tcl
+++ b/openlane/mbist2/config.tcl

@@ -20,13 +20,13 @@
 set script_dir [file dirname [file normalize [info script]]]
 # Name
 
-set ::env(DESIGN_NAME) mbist_top
+set ::env(DESIGN_NAME) mbist_top2
 
 set ::env(DESIGN_IS_CORE) "0"
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "8"
-set ::env(CLOCK_PORT) "bist_clk u_mem_sel.u_cts_mem_clk_a/X u_mem_sel.u_cts_mem_clk_a/X"
+set ::env(CLOCK_PORT) "wb_clk_i u_mem_sel.u_cts_mem_clk_a/X u_mem_sel.u_cts_mem_clk_a/X"
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
@@ -35,21 +35,33 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
-     $script_dir/../../verilog/rtl/mbist/src/mbist_addr_gen.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_fsm.sv     \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_op_sel.sv  \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_repair_addr.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_top.sv  \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_sti_sel.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_pat_sel.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_mux.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_data_cmp.sv \
+     $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_addr_gen.sv \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_fsm.sv     \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_op_sel.sv  \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_repair_addr.sv \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_sti_sel.sv \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_pat_sel.sv \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_mux.sv \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_data_cmp.sv \
+     $script_dir/../../verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv \
+     $script_dir/../../verilog/rtl/mbist/src/top/mbist_top2.sv  \
      $script_dir/../../verilog/rtl/lib/ctech_cells.sv     \
      $script_dir/../../verilog/rtl/lib/reset_sync.sv \
 	     "
 
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/mbist/include ]
 
+
+set ::env(SYNTH_PARAMS) "BIST_ADDR_WD 8,\
+	                 BIST_DATA_WD 32,\
+		         BIST_ADDR_START 8'h000,\
+			 BIST_ADDR_END 8'h0FB,\
+			 BIST_REPAIR_ADDR_START 8'h0FC,\
+			 BIST_RAD_WD_I 8,\
+			 BIST_RAD_WD_O 8\
+			 "
+
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 set ::env(SDC_FILE) "$script_dir/base.sdc"
 set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
@@ -66,7 +78,7 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 200"
+set ::env(DIE_AREA) "0 0 200 250"
 
 
 # If you're going to use multiple power domains, then keep this disabled.
@@ -76,7 +88,7 @@
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.30"
+set ::env(PL_TARGET_DENSITY) "0.40"
 
 
 

diff --git a/openlane/mbist2/interactive.tcl b/openlane/mbist2/interactive.tcl
new file mode 100644
index 0000000..32f160d
--- /dev/null
+++ b/openlane/mbist2/interactive.tcl

@@ -0,0 +1,407 @@
+#!/usr/bin/tclsh
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# Copyright 2020 Efabless Corporation
+# Copyright 2020 Sylvain Munaut
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+package require openlane;
+
+
+proc run_placement_step {args} {
+    # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def]
+    # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0]
+    # set_def $pdndef
+    puts "\[INFO\]: Running Placement Step"
+    if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+        set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+    }
+
+    run_placement
+}
+
+proc run_cts_step {args} {
+    # set_def $::env(opendp_result_file_tag).def
+    puts "\[INFO\]: Running CTS"
+    if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+        set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+    }
+
+    run_cts
+    run_resizer_timing
+}
+
+proc run_routing_step {args} {
+    # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def]
+    # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0]
+    # set_def $resizerdef
+    puts "\[INFO\]: Running Routing"
+    if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+        set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+    }
+    run_routing
+}
+
+proc run_diode_insertion_2_5_step {args} {
+    puts "\[INFO\]: Running Diode Insertion"
+    # set_def $::env(tritonRoute_result_file_tag).def
+    if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+        set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+    }
+	if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
+		run_antenna_check
+		heal_antenna_violators; # modifies the routed DEF
+	}
+
+}
+
+proc run_power_pins_insertion_step {args} {
+    puts "\[INFO\]:Running Power Pin Insertion"
+    # set_def $::env(tritonRoute_result_file_tag).def
+    if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } {
+        set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF)
+    }
+    if { $::env(LVS_INSERT_POWER_PINS) } {
+		write_powered_verilog
+		set_netlist $::env(lvs_result_file_tag).powered.v
+    }
+
+}
+
+proc run_lvs_step {{ lvs_enabled 1 }} {
+    # set_def $::env(tritonRoute_result_file_tag).def
+    puts "\[INFO\]:Running LVS Step"
+    if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+        set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+    }
+	if { $lvs_enabled } {
+		run_magic_spice_export
+		run_lvs; # requires run_magic_spice_export
+	}
+
+}
+
+proc run_drc_step {{ drc_enabled 1 }} {
+    puts "\[INFO\]:Running DRC"
+    if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+        set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+    }
+	if { $drc_enabled } {
+		run_magic_drc
+		run_klayout_drc
+	}
+}
+
+proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
+    puts "\[INFO\]: Running Antenna checl"
+    if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+        set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+    } else {
+        set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+    }
+	if { $antenna_check_enabled } {
+		run_antenna_check
+	}
+}
+
+proc gen_pdn_new {args} {
+    puts_info "Generating PDN..."
+    TIMER::timer_start
+	
+    set ::env(SAVE_DEF) [index_file $::env(pdn_tmp_file_tag).def]
+    set ::env(PGA_RPT_FILE) [index_file $::env(pdn_report_file_tag).pga.rpt]
+
+    try_catch $::env(OPENROAD_BIN) -exit $::env(SCRIPTS_DIR)/openroad/or_pdn.tcl \
+	|& tee $::env(TERMINAL_OUTPUT) [index_file $::env(pdn_log_file_tag).log 0]
+
+
+    TIMER::timer_stop
+    exec echo "[TIMER::get_runtime]" >> [index_file $::env(pdn_log_file_tag)_runtime.txt 0]
+
+	quit_on_unconnected_pdn_nodes
+
+    set_def $::env(SAVE_DEF)
+}
+
+proc run_power_grid_generation_new {args} {
+	if { [info exists ::env(VDD_NETS)] || [info exists ::env(GND_NETS)] } {
+		# they both must exist and be equal in length
+		# current assumption: they cannot have a common ground
+		if { ! [info exists ::env(VDD_NETS)] || ! [info exists ::env(GND_NETS)] } {
+			puts_err "VDD_NETS and GND_NETS must *both* either be defined or undefined"
+			return -code error
+		}
+		# standard cell power and ground nets are assumed to be the first net 
+		set ::env(VDD_PIN) [lindex $::env(VDD_NETS) 0]
+		set ::env(GND_PIN) [lindex $::env(GND_NETS) 0]
+	} elseif { [info exists ::env(SYNTH_USE_PG_PINS_DEFINES)] } {
+		set ::env(VDD_NETS) [list]
+		set ::env(GND_NETS) [list]
+		# get the pins that are in $yosys_tmp_file_tag.pg_define.v
+		# that are not in $yosys_result_file_tag.v
+		#
+		set full_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_tmp_file_tag).pg_define.v]
+		puts_info $full_pins
+
+		set non_pg_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_result_file_tag).v]
+		puts_info $non_pg_pins
+
+		# assumes the pins are ordered correctly (e.g., vdd1, vss1, vcc1, vss1, ...)
+		foreach {vdd gnd} $full_pins {
+			if { $vdd ne "" && $vdd ni $non_pg_pins } {
+				lappend ::env(VDD_NETS) $vdd
+			}
+			if { $gnd ne "" && $gnd ni $non_pg_pins } {
+				lappend ::env(GND_NETS) $gnd
+			}
+		}
+	} else {
+		set ::env(VDD_NETS) $::env(VDD_PIN)
+		set ::env(GND_NETS) $::env(GND_PIN)
+	}
+
+	puts_info "Power planning the following nets"
+	puts_info "Power: $::env(VDD_NETS)"
+	puts_info "Ground: $::env(GND_NETS)"
+
+	if { [llength $::env(VDD_NETS)] != [llength $::env(GND_NETS)] } {
+		puts_err "VDD_NETS and GND_NETS must be of equal lengths"
+		return -code error
+	}
+
+	# internal macros power connections 
+	if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} {
+		set macro_hooks [dict create]
+		set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
+		foreach pdn_hook $pdn_hooks {
+			set instance_name [lindex $pdn_hook 0]
+			set power_net [lindex $pdn_hook 1]
+			set ground_net [lindex $pdn_hook 2]
+			dict append macro_hooks $instance_name [subst {$power_net $ground_net}]
+		}
+		
+		set power_net_indx [lsearch $::env(VDD_NETS) $power_net]
+		set ground_net_indx [lsearch $::env(GND_NETS) $ground_net]
+
+		# make sure that the specified power domains exist.
+		if { $power_net_indx == -1  || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } {
+			puts_err "Can't find $power_net and $ground_net domain. \
+			Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)." 
+		} 
+	}
+	
+	# generate multiple power grids per pair of (VDD,GND)
+	# offseted by WIDTH + SPACING
+	foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
+		set ::env(VDD_NET) $vdd
+		set ::env(GND_NET) $gnd
+                puts "\[INFO\]: Processing Power Nets: $vdd and $gnd."
+
+		# internal macros power connections
+		set ::env(FP_PDN_MACROS) ""
+		if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 } {
+			# if macros connections to power are explicitly set
+			# default behavoir macro pins will be connected to the first power domain
+			if { [info exists ::env(FP_PDN_MACRO_HOOKS)] } {
+				set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
+				foreach {instance_name hooks} $macro_hooks {
+					set power [lindex $hooks 0]
+					set ground [lindex $hooks 1]			 
+					if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } {
+						set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
+						puts_info "Connecting $instance_name to $power and $ground nets."
+						lappend ::env(FP_PDN_MACROS) $instance_name
+					}
+				}
+			} 
+                   puts "\[INFO\]: FP_PDN_MACROS: $::env(FP_PDN_MACROS) ."
+		} else {
+			puts_warn "All internal macros will not be connected to power."
+		}
+		
+		gen_pdn_new
+
+		set ::env(FP_PDN_ENABLE_RAILS) 0
+		set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
+
+		# allow failure until open_pdks is up to date...
+		catch {set ::env(FP_PDN_VOFFSET) [expr $::env(FP_PDN_VOFFSET)+$::env(FP_PDN_VWIDTH)+$::env(FP_PDN_VSPACING)]}
+		catch {set ::env(FP_PDN_HOFFSET) [expr $::env(FP_PDN_HOFFSET)+$::env(FP_PDN_HWIDTH)+$::env(FP_PDN_HSPACING)]}
+
+		catch {set ::env(FP_PDN_CORE_RING_VOFFSET) \
+			[expr $::env(FP_PDN_CORE_RING_VOFFSET)\
+			+2*($::env(FP_PDN_CORE_RING_VWIDTH)\
+			+max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
+		catch {set ::env(FP_PDN_CORE_RING_HOFFSET) [expr $::env(FP_PDN_CORE_RING_HOFFSET)\
+			+2*($::env(FP_PDN_CORE_RING_HWIDTH)+\
+			max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
+	}
+	set ::env(FP_PDN_ENABLE_RAILS) 1
+}
+
+proc run_floorplan_new {args} {
+		puts_info "Running Floorplanning..."
+		# |----------------------------------------------------|
+		# |----------------   2. FLOORPLAN   ------------------|
+		# |----------------------------------------------------|
+		#
+		# intial fp
+		init_floorplan
+
+
+		# place io
+		if { [info exists ::env(FP_PIN_ORDER_CFG)] } {
+				place_io_ol
+		} else {
+			if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } {
+				place_io
+				global_placement_or
+				place_contextualized_io \
+					-lef $::env(FP_CONTEXT_LEF) \
+					-def $::env(FP_CONTEXT_DEF)
+			} else {
+				place_io
+			}
+		}
+
+		apply_def_template
+
+		if { [info exist ::env(EXTRA_LEFS)] } {
+			if { [info exist ::env(MACRO_PLACEMENT_CFG)] } {
+				file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(TMP_DIR)/macro_placement.cfg
+				manual_macro_placement f
+			} else {
+				global_placement_or
+				basic_macro_placement
+			}
+		}
+
+		# tapcell
+		tap_decap_or
+		scrot_klayout -layout $::env(CURRENT_DEF)
+		# power grid generation
+		run_power_grid_generation_new
+}
+
+
+proc run_flow {args} {
+       set script_dir [file dirname [file normalize [info script]]]
+
+		set options {
+		{-design required}
+		{-save_path optional}
+		{-no_lvs optional}
+	    {-no_drc optional}
+	    {-no_antennacheck optional}
+	}
+	set flags {-save}
+	parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume
+
+	prep {*}$args
+
+        set LVS_ENABLED 1
+        set DRC_ENABLED 0
+        set ANTENNACHECK_ENABLED 1
+
+        set steps [dict create "synthesis" {run_synthesis "" } \
+                "floorplan" {run_floorplan ""} \
+                "placement" {run_placement_step ""} \
+                "cts" {run_cts_step ""} \
+                "routing" {run_routing_step ""}\
+                "diode_insertion" {run_diode_insertion_2_5_step ""} \
+                "power_pins_insertion" {run_power_pins_insertion_step ""} \
+                "gds_magic" {run_magic ""} \
+                "gds_drc_klayout" {run_klayout ""} \
+                "gds_xor_klayout" {run_klayout_gds_xor ""} \
+                "lvs" "run_lvs_step $LVS_ENABLED" \
+                "drc" "run_drc_step $DRC_ENABLED" \
+                "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
+                "cvc" {run_lef_cvc}
+        ]
+
+       set_if_unset arg_values(-to) "cvc";
+
+       if {  [info exists ::env(CURRENT_STEP) ] } {
+           puts "\[INFO\]:Picking up where last execution left off"
+           puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)]
+       } else {
+           set ::env(CURRENT_STEP) "synthesis";
+       }
+       set_if_unset arg_values(-from) $::env(CURRENT_STEP);
+       set exe 0;
+       dict for {step_name step_exe} $steps {
+           if { [ string equal $arg_values(-from) $step_name ] } {
+               set exe 1;
+           }
+
+           if { $exe } {
+               # For when it fails
+               set ::env(CURRENT_STEP) $step_name
+               [lindex $step_exe 0] [lindex $step_exe 1] ;
+           }
+
+           if { [ string equal $arg_values(-to) $step_name ] } {
+               set exe 0:
+               break;
+           }
+
+       }
+
+       # for when it resumes
+       set steps_as_list [dict keys $steps]
+       set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1]
+       set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx]
+
+	if {  [info exists flags_map(-save) ] } {
+		if { ! [info exists arg_values(-save_path)] } {
+			set arg_values(-save_path) ""
+		}
+		save_views 	-lef_path $::env(magic_result_file_tag).lef \
+			-def_path $::env(CURRENT_DEF) \
+			-gds_path $::env(magic_result_file_tag).gds \
+			-mag_path $::env(magic_result_file_tag).mag \
+			-maglef_path $::env(magic_result_file_tag).lef.mag \
+			-spice_path $::env(magic_result_file_tag).spice \
+			-spef_path $::env(CURRENT_SPEF) \
+			-verilog_path $::env(CURRENT_NETLIST) \
+			-save_path $arg_values(-save_path) \
+			-tag $::env(RUN_TAG)
+	}
+
+
+	calc_total_runtime
+	save_state
+	generate_final_summary_report
+	
+	check_timing_violations
+
+	puts_success "Flow Completed Without Fatal Errors."
+
+}
+
+run_flow {*}$argv

diff --git a/openlane/mbist2/pin_order.cfg b/openlane/mbist2/pin_order.cfg
new file mode 100644
index 0000000..b5ec9a8
--- /dev/null
+++ b/openlane/mbist2/pin_order.cfg

@@ -0,0 +1,206 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+
+#N
+cfg_cska_mbist\[3\]  0000 0 4
+cfg_cska_mbist\[2\]
+cfg_cska_mbist\[1\]
+cfg_cska_mbist\[0\]
+wbd_clk_int
+wbd_clk_mbist
+wb_clk_i           
+rst_n
+bist_en
+bist_run
+bist_shift
+bist_load
+bist_done
+bist_error
+bist_correct
+bist_error_cnt\[3\]
+bist_error_cnt\[2\]
+bist_error_cnt\[1\]
+bist_error_cnt\[0\]
+bist_sdi
+bist_sdo
+
+
+#W
+wb_cyc_i         0000 2 2
+wb_stb_i
+wb_we_i
+wb_adr_i\[7\]
+wb_adr_i\[6\]
+wb_adr_i\[5\]
+wb_adr_i\[4\]
+wb_adr_i\[3\]
+wb_adr_i\[2\]
+wb_adr_i\[1\]
+wb_adr_i\[0\]
+wb_dat_i\[31\]
+wb_dat_i\[30\]
+wb_dat_i\[29\]
+wb_dat_i\[28\]
+wb_dat_i\[27\]
+wb_dat_i\[26\]
+wb_dat_i\[25\]
+wb_dat_i\[24\]
+wb_dat_i\[23\]
+wb_dat_i\[22\]
+wb_dat_i\[21\]
+wb_dat_i\[20\]
+wb_dat_i\[19\]
+wb_dat_i\[18\]
+wb_dat_i\[17\]
+wb_dat_i\[16\]
+wb_dat_i\[15\]
+wb_dat_i\[14\]
+wb_dat_i\[13\]
+wb_dat_i\[12\]
+wb_dat_i\[11\]
+wb_dat_i\[10\]
+wb_dat_i\[9\]
+wb_dat_i\[8\]
+wb_dat_i\[7\]
+wb_dat_i\[6\]
+wb_dat_i\[5\]
+wb_dat_i\[4\]
+wb_dat_i\[3\]
+wb_dat_i\[2\]
+wb_dat_i\[1\]
+wb_dat_i\[0\]
+wb_sel_i\[3\]
+wb_sel_i\[2\]
+wb_sel_i\[1\]
+wb_sel_i\[0\]
+wb_dat_o\[31\]
+wb_dat_o\[30\]
+wb_dat_o\[29\]
+wb_dat_o\[28\]
+wb_dat_o\[27\]
+wb_dat_o\[26\]
+wb_dat_o\[25\]
+wb_dat_o\[24\]
+wb_dat_o\[23\]
+wb_dat_o\[22\]
+wb_dat_o\[21\]
+wb_dat_o\[20\]
+wb_dat_o\[19\]
+wb_dat_o\[18\]
+wb_dat_o\[17\]
+wb_dat_o\[16\]
+wb_dat_o\[15\]
+wb_dat_o\[14\]
+wb_dat_o\[13\]
+wb_dat_o\[12\]
+wb_dat_o\[11\]
+wb_dat_o\[10\]
+wb_dat_o\[9\]
+wb_dat_o\[8\]
+wb_dat_o\[7\]
+wb_dat_o\[6\]
+wb_dat_o\[5\]
+wb_dat_o\[4\]
+wb_dat_o\[3\]
+wb_dat_o\[2\]
+wb_dat_o\[1\]
+wb_dat_o\[0\]
+wb_ack_o
+wb_err_o
+
+#E
+mem_clk_b       0000 0 2
+mem_cen_b
+mem_web_b
+mem_mask_b\[0\]
+mem_mask_b\[1\]
+mem_mask_b\[2\]
+mem_mask_b\[3\]
+mem_addr_b\[0\]
+mem_addr_b\[1\]
+mem_addr_b\[2\]
+mem_addr_b\[3\]
+mem_addr_b\[4\]
+mem_addr_b\[5\]
+mem_addr_b\[6\]
+mem_addr_b\[7\]
+mem_din_b\[0\]
+mem_din_b\[1\]
+mem_din_b\[2\]
+mem_din_b\[3\]
+mem_din_b\[4\]
+mem_din_b\[5\]
+mem_din_b\[6\]
+mem_din_b\[7\]
+mem_din_b\[8\]
+mem_din_b\[9\]
+mem_din_b\[10\]
+mem_din_b\[11\]
+mem_din_b\[12\]
+mem_din_b\[13\]
+mem_din_b\[14\]
+mem_din_b\[15\]
+mem_din_b\[16\]
+mem_din_b\[17\]
+mem_din_b\[18\]
+mem_din_b\[19\]
+mem_din_b\[20\]
+mem_din_b\[21\]
+mem_din_b\[22\]
+mem_din_b\[23\]
+mem_din_b\[24\]
+mem_din_b\[25\]
+mem_din_b\[26\]
+mem_din_b\[27\]
+mem_din_b\[28\]
+mem_din_b\[29\]
+mem_din_b\[30\]
+mem_din_b\[31\]
+
+
+mem_dout_a\[0\]  0100 0 2
+mem_dout_a\[1\]
+mem_dout_a\[2\]
+mem_dout_a\[3\]
+mem_dout_a\[4\]
+mem_dout_a\[5\]
+mem_dout_a\[6\]
+mem_dout_a\[7\]
+mem_dout_a\[8\]
+mem_dout_a\[9\]
+mem_dout_a\[10\]
+mem_dout_a\[11\]
+mem_dout_a\[12\]
+mem_dout_a\[13\]
+mem_dout_a\[14\]
+mem_dout_a\[15\]
+mem_dout_a\[16\]
+mem_dout_a\[17\]
+mem_dout_a\[18\]
+mem_dout_a\[19\]
+mem_dout_a\[20\]
+mem_dout_a\[21\]
+mem_dout_a\[22\]
+mem_dout_a\[23\]
+mem_dout_a\[24\]
+mem_dout_a\[25\]
+mem_dout_a\[26\]
+mem_dout_a\[27\]
+mem_dout_a\[28\]
+mem_dout_a\[29\]
+mem_dout_a\[30\]
+mem_dout_a\[31\]
+
+
+mem_clk_a          0200 0 2
+mem_cen_a
+mem_addr_a\[7\]
+mem_addr_a\[6\]
+mem_addr_a\[5\]
+mem_addr_a\[4\]
+mem_addr_a\[3\]
+mem_addr_a\[2\]
+mem_addr_a\[1\]
+mem_addr_a\[0\]

diff --git a/openlane/mbist/sta.tcl b/openlane/mbist2/sta.tcl
similarity index 100%
copy from openlane/mbist/sta.tcl
copy to openlane/mbist2/sta.tcl


diff --git a/openlane/user_project_wrapper/base.sdc b/openlane/user_project_wrapper/base.sdc
index e65b04c..9e367c7 100644
--- a/openlane/user_project_wrapper/base.sdc
+++ b/openlane/user_project_wrapper/base.sdc

@@ -31,59 +31,961 @@
 ######################################
 # WB MASTER Clock domain input output
 ######################################
-create_clock [get_ports $::env(WBM_CLOCK_PORT)]  -name $::env(WBM_CLOCK_NAME)  -period $::env(WBM_CLOCK_PERIOD)
-set wb_input_delay_value [expr $::env(WBM_CLOCK_PERIOD) * 0.54]
-set wb_output_delay_value [expr $::env(WBM_CLOCK_PERIOD) * 0.54]
-puts "\[INFO\]: Setting wb output delay to:$wb_output_delay_value"
-puts "\[INFO\]: Setting wb input delay to: $wb_input_delay_value"
+create_clock -name user_clock2 -period 100.0000 [get_ports {user_clock2}]
+create_clock -name wbm_clk_i -period 10.0000 [get_ports {wb_clk_i}]
+create_clock -name wbs_clk_i -period 10.0000  [get_pins {u_wb_host/wbs_clk_out}]
 
-set_false_path -from [get_pins {u_wb_host/bist_en}]
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -rise_to [get_clocks {user_clock2}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {user_clock2}] -fall_to [get_clocks {user_clock2}]  -setup 0.2000
 
-set_input_delay 2.0 -clock [get_clocks $::env(WBM_CLOCK_NAME)] {wb_rst_i}
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -setup 0.2000
 
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_stb_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_cyc_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_we_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_sel_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_dat_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_adr_i*]
-set_input_delay  $wb_input_delay_value   -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wb_cti_i*]
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -setup 0.2000
 
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_dat_o*]
-set_output_delay $wb_output_delay_value  -clock [get_clocks $::env(WBM_CLOCK_NAME)] [get_port wbs_ack_o*]
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {user_clock2}]\
+ -group [get_clocks {wbm_clk_i}]\
+ -group [get_clocks {wbs_clk_i}] -comment {Async Clock group}
 
-######################################
-# WishBone Slave Port
-#######################################
-create_clock [get_pins -hierarchical $::env(WBS_CLOCK_PORT)]  -name $::env(WBS_CLOCK_NAME)  -period $::env(WBS_CLOCK_PERIOD)
-######################################
-# BIST Clock domain input output
-######################################
-create_clock [get_pins -hierarchical $::env(BIST_CLOCK_PORT)]  -name $::env(BIST_CLOCK_NAME)  -period $::env(BIST_CLOCK_PERIOD)
+set_input_delay 2.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wb_rst_i}]
 
-set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks $::env(WBM_CLOCK_NAME)] -group [get_clocks $::env(WBS_CLOCK_NAME)] -group [get_clocks $::env(BIST_CLOCK_NAME)] 
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[0]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[10]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[11]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[12]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[13]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[14]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[15]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[16]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[17]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[18]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[19]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[1]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[20]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[21]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[22]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[23]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[24]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[25]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[26]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[27]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[28]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[29]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[2]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[30]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[31]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[3]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[4]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[5]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[6]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[7]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[8]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[9]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[0]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[1]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[2]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[3]}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_stb_i}]
+set_input_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_we_i}]
+
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[10]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[11]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[12]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[13]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[14]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[15]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[16]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[17]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[18]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[19]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[20]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[21]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[22]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[23]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[24]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[25]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[26]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[27]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[28]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[29]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[30]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[31]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[4]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[5]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[6]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[7]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[8]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_adr_i[9]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_cyc_i}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[0]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[1]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[2]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_sel_i[3]}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_stb_i}]
+set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_we_i}]
 
 
-## Add clock uncertainty
-#Note: We have PAD_BIST_CLOCK_NAME => BIST_CLOCK_NAME path only
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_ack_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}]
 
-set_clock_uncertainty -from $::env(WBM_CLOCK_NAME)          -to $::env(WBM_CLOCK_NAME)  -setup 0.200
-set_clock_uncertainty -from $::env(WBS_CLOCK_NAME)          -to $::env(WBS_CLOCK_NAME)  -setup 0.200
-set_clock_uncertainty -from $::env(BIST_CLOCK_NAME)        -to $::env(BIST_CLOCK_NAME)  -setup 0.200
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_ack_o}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}]
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {wbs_ack_o}]
+set_load -pin_load 0.0334 [get_ports {analog_io[28]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[27]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[26]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[25]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[24]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[23]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[22]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[21]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[20]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[19]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[18]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[17]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[16]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[15]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[14]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[13]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[12]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[11]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[10]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[9]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[8]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[7]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[6]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[5]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[4]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[3]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[2]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[1]}]
+set_load -pin_load 0.0334 [get_ports {analog_io[0]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[37]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[36]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[35]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[34]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[33]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[32]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[31]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[30]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
+set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
+set_load -pin_load 0.0334 [get_ports {io_out[37]}]
+set_load -pin_load 0.0334 [get_ports {io_out[36]}]
+set_load -pin_load 0.0334 [get_ports {io_out[35]}]
+set_load -pin_load 0.0334 [get_ports {io_out[34]}]
+set_load -pin_load 0.0334 [get_ports {io_out[33]}]
+set_load -pin_load 0.0334 [get_ports {io_out[32]}]
+set_load -pin_load 0.0334 [get_ports {io_out[31]}]
+set_load -pin_load 0.0334 [get_ports {io_out[30]}]
+set_load -pin_load 0.0334 [get_ports {io_out[29]}]
+set_load -pin_load 0.0334 [get_ports {io_out[28]}]
+set_load -pin_load 0.0334 [get_ports {io_out[27]}]
+set_load -pin_load 0.0334 [get_ports {io_out[26]}]
+set_load -pin_load 0.0334 [get_ports {io_out[25]}]
+set_load -pin_load 0.0334 [get_ports {io_out[24]}]
+set_load -pin_load 0.0334 [get_ports {io_out[23]}]
+set_load -pin_load 0.0334 [get_ports {io_out[22]}]
+set_load -pin_load 0.0334 [get_ports {io_out[21]}]
+set_load -pin_load 0.0334 [get_ports {io_out[20]}]
+set_load -pin_load 0.0334 [get_ports {io_out[19]}]
+set_load -pin_load 0.0334 [get_ports {io_out[18]}]
+set_load -pin_load 0.0334 [get_ports {io_out[17]}]
+set_load -pin_load 0.0334 [get_ports {io_out[16]}]
+set_load -pin_load 0.0334 [get_ports {io_out[15]}]
+set_load -pin_load 0.0334 [get_ports {io_out[14]}]
+set_load -pin_load 0.0334 [get_ports {io_out[13]}]
+set_load -pin_load 0.0334 [get_ports {io_out[12]}]
+set_load -pin_load 0.0334 [get_ports {io_out[11]}]
+set_load -pin_load 0.0334 [get_ports {io_out[10]}]
+set_load -pin_load 0.0334 [get_ports {io_out[9]}]
+set_load -pin_load 0.0334 [get_ports {io_out[8]}]
+set_load -pin_load 0.0334 [get_ports {io_out[7]}]
+set_load -pin_load 0.0334 [get_ports {io_out[6]}]
+set_load -pin_load 0.0334 [get_ports {io_out[5]}]
+set_load -pin_load 0.0334 [get_ports {io_out[4]}]
+set_load -pin_load 0.0334 [get_ports {io_out[3]}]
+set_load -pin_load 0.0334 [get_ports {io_out[2]}]
+set_load -pin_load 0.0334 [get_ports {io_out[1]}]
+set_load -pin_load 0.0334 [get_ports {io_out[0]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[127]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[126]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[125]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[124]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[123]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[122]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[121]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[120]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[119]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[118]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[117]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[116]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[115]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[114]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[113]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[112]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[111]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[110]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[109]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[108]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[107]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[106]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[105]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[104]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[103]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[102]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[101]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[100]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[99]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[98]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[97]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[96]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[95]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[94]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[93]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[92]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[91]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[90]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[89]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[88]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[87]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[86]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[85]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[84]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[83]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[82]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[81]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[80]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[79]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[78]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[77]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[76]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[75]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[74]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[73]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[72]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[71]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[70]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[69]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[68]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[67]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[66]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[65]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[64]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[63]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[62]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[61]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[60]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[59]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[58]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[57]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[56]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[55]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[54]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[53]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[52]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[51]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[50]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[49]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[48]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[47]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[46]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[45]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[44]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[43]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[42]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[41]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[40]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[39]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[38]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[37]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[36]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[35]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[34]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[33]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[32]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[31]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[30]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[29]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[28]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[27]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[26]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[25]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[24]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[23]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[22]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[21]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[20]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[19]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[18]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[17]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[16]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[15]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[14]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[13]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[12]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[11]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[10]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[9]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[8]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[7]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[6]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[5]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[4]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[3]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[2]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[1]}]
+set_load -pin_load 0.0334 [get_ports {la_data_out[0]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
+set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
+set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {analog_io[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[37]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[36]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[35]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[34]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[33]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[32]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[127]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[126]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[125]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[124]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[123]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[122]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[121]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[120]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[119]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[118]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[117]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[116]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[23]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[20]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[17]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[9]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_data_in[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[127]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[112]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[23]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[11]}]
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+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {la_oenb[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_adr_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[3]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[2]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[1]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_sel_i[0]}]
 
-set_clock_uncertainty -from $::env(WBM_CLOCK_NAME)          -to $::env(WBM_CLOCK_NAME)  -hold 0.100
-set_clock_uncertainty -from $::env(WBS_CLOCK_NAME)          -to $::env(WBS_CLOCK_NAME)  -hold 0.100
-set_clock_uncertainty -from $::env(BIST_CLOCK_NAME)        -to $::env(BIST_CLOCK_NAME)  -hold 0.100
+## Case analysis
+set_case_analysis 1 [get_pins {u_intercon/cfg_cska_wi[0]}]
+set_case_analysis 1 [get_pins {u_intercon/cfg_cska_wi[1]}]
+set_case_analysis 0 [get_pins {u_intercon/cfg_cska_wi[2]}]
+set_case_analysis 1 [get_pins {u_intercon/cfg_cska_wi[3]}]
 
-# TODO set this as parameter
-set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
-set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
-puts "\[INFO\]: Setting load to: $cap_load"
-set_load  $cap_load [all_outputs]
+set_case_analysis 0 [get_pins {u_glbl/cfg_cska_glbl[0]}]
+set_case_analysis 0 [get_pins {u_glbl/cfg_cska_glbl[1]}]
+set_case_analysis 0 [get_pins {u_glbl/cfg_cska_glbl[2]}]
+set_case_analysis 1 [get_pins {u_glbl/cfg_cska_glbl[3]}]
 
-## 2 Multi-cycle setup and 0 hold
-set_multicycle_path -setup -from wbs_adr_i* 2
-set_multicycle_path -hold -from wbs_adr_i* 2
+set_case_analysis 0 [get_pins {u_mbist1/cfg_cska_mbist[0]}]
+set_case_analysis 0 [get_pins {u_mbist1/cfg_cska_mbist[1]}]
+set_case_analysis 0 [get_pins {u_mbist1/cfg_cska_mbist[2]}]
+set_case_analysis 1 [get_pins {u_mbist1/cfg_cska_mbist[3]}]
 
-set_multicycle_path -setup -from wbs_we_i* 2
-set_multicycle_path -hold -from wbs_we_i* 2
+set_case_analysis 0 [get_pins {u_mbist2/cfg_cska_mbist[0]}]
+set_case_analysis 0 [get_pins {u_mbist2/cfg_cska_mbist[1]}]
+set_case_analysis 0 [get_pins {u_mbist2/cfg_cska_mbist[2]}]
+set_case_analysis 1 [get_pins {u_mbist2/cfg_cska_mbist[3]}]
+
+set_case_analysis 0 [get_pins {u_mbist3/cfg_cska_mbist[0]}]
+set_case_analysis 0 [get_pins {u_mbist3/cfg_cska_mbist[1]}]
+set_case_analysis 0 [get_pins {u_mbist3/cfg_cska_mbist[2]}]
+set_case_analysis 1 [get_pins {u_mbist3/cfg_cska_mbist[3]}]
+
+set_case_analysis 0 [get_pins {u_mbist4/cfg_cska_mbist[0]}]
+set_case_analysis 0 [get_pins {u_mbist4/cfg_cska_mbist[1]}]
+set_case_analysis 0 [get_pins {u_mbist4/cfg_cska_mbist[2]}]
+set_case_analysis 1 [get_pins {u_mbist4/cfg_cska_mbist[3]}]
+
+set_case_analysis 1 [get_pins {u_wb_host/cfg_cska_wh[0]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[1]}]
+set_case_analysis 1 [get_pins {u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 0 [get_pins {u_wb_host/cfg_cska_wh[3]}]
+
+#disable clock gating check at static clock select pins
+set_false_path -through [get_pins u_wb_host/u_wbs_clk_sel.u_mux/S]

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index fde14a3..56d0de3 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl

@@ -58,17 +58,30 @@
 set ::env(VERILOG_FILES_BLACKBOX) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
 	$script_dir/../../verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v \
+	$script_dir/../../verilog/rtl/sram_macros/sky130_sram_1kbyte_1rw1r_32x256_8.v \
+	$script_dir/../../verilog/gl/wb_interconnect.v \
 	$script_dir/../../verilog/gl/wb_host.v \
-	$script_dir/../../verilog/gl/mbist.v"
+	$script_dir/../../verilog/gl/glbl_cfg.v\
+	$script_dir/../../verilog/gl/mbist1.v\
+	$script_dir/../../verilog/gl/mbist2.v\
+	"
 
 set ::env(EXTRA_LEFS) "\
 	$script_dir/../../lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \
-	$script_dir/../../lef/mbist.lef \
+	$script_dir/../../lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef \
+	$script_dir/../../lef/glbl_cfg.lef \
+	$script_dir/../../lef/mbist1.lef \
+	$script_dir/../../lef/mbist2.lef \
+	$script_dir/../../lef/wb_interconnect.lef \
 	$script_dir/../../lef/wb_host.lef"
 
 set ::env(EXTRA_GDS_FILES) "\
 	$script_dir/../../gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \
-	$script_dir/../../gds/mbist.gds \
+	$script_dir/../../gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds \
+	$script_dir/../../gds/glbl_cfg.gds \
+	$script_dir/../../gds/mbist1.gds \
+	$script_dir/../../gds/mbist2.gds \
+	$script_dir/../../gds/wb_interconnect.gds \
 	$script_dir/../../gds/wb_host.gds"
 
 set ::env(SDC_FILE) "$script_dir/base.sdc"
@@ -100,8 +113,17 @@
 
 set ::env(FP_PDN_MACRO_HOOKS) "\
      u_wb_host	vccd1 vssd1 \
-     u_mbist    vccd1 vssd1 \
-     u_sram_2kb vccd1 vssd1 "
+     u_intercon	vccd1 vssd1 \
+     u_glbl	vccd1 vssd1 \
+     u_mbist1   vccd1 vssd1 \
+     u_mbist2   vccd1 vssd1 \
+     u_mbist3   vccd1 vssd1 \
+     u_mbist4   vccd1 vssd1 \
+     u_sram1_2kb vccd1 vssd1 \
+     u_sram2_2kb vccd1 vssd1 \
+     u_sram3_1kb vccd1 vssd1 \
+     u_sram4_1kb vccd1 vssd1 \
+     "
 
 
 # The following is because there are no std cells in the example wrapper project.

diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 9375415..0dce758 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg

@@ -1,3 +1,12 @@
-u_wb_host               300             300             N
-u_mbist                 300             1000            N
-u_sram_2kb              300             1500            N
+u_wb_host               1200            300            N
+u_glbl                   800            800            N
+u_intercon              1200            800            N
+u_mbist1                1600            800            N
+u_mbist2                1600            1400           N
+u_mbist3                1600            2000           N
+u_mbist4                1600            2600           N
+
+u_sram1_2kb             2000            800            N
+u_sram2_2kb             2000            1400           N
+u_sram3_1kb             2000            2000           N
+u_sram4_1kb             2000            2600           N

diff --git a/openlane/user_project_wrapper/sta.tcl b/openlane/user_project_wrapper/sta.tcl
index be9c773..cb6aebb 100644
--- a/openlane/user_project_wrapper/sta.tcl
+++ b/openlane/user_project_wrapper/sta.tcl

@@ -37,14 +37,24 @@
 
 
 read_verilog netlist/wb_host.v  
-read_verilog netlist/mbist.v
+read_verilog netlist/mbist1.v
+read_verilog netlist/mbist2.v
+read_verilog netlist/glbl_cfg.v
+read_verilog netlist/wb_interconnect.v
 read_verilog netlist/user_project_wrapper.v  
 read_lib  -corner tt   ../../lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+read_lib  -corner tt   ../../lib/sram_1rw1r_32_256_8_sky130_TT_1p8V_25C.lib
 link_design  $::env(DESIGN_NAME)
 
 
-read_spef -path u_mbist    ../../spef/mbist_top.spef  
+read_spef -path u_mbist1    ../../spef/mbist_top1.spef  
+read_spef -path u_mbist2    ../../spef/mbist_top1.spef  
+read_spef -path u_mbist3    ../../spef/mbist_top2.spef  
+read_spef -path u_mbist4    ../../spef/mbist_top2.spef  
 read_spef -path u_wb_host  ../../spef/wb_host.spef  
+read_spef -path u_intercon ../../spef/wb_interconnect.spef
+read_spef -path u_glbl     ../../spef/glbl_cfg.spef
+
 read_spef ../../spef/user_project_wrapper.spef  
 
 

diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 948da33..bd4757d 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl

@@ -26,7 +26,7 @@
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "wbm_clk_i mem_clk"
+set ::env(CLOCK_PORT) "wbm_clk_i wbs_clk_i"
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
@@ -35,11 +35,11 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
+     $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
      $script_dir/../../verilog/rtl/wb_host/src/wb_host.sv \
      $script_dir/../../verilog/rtl/lib/async_fifo.sv      \
      $script_dir/../../verilog/rtl/lib/async_wb.sv        \
      $script_dir/../../verilog/rtl/lib/clk_ctl.v          \
-     $script_dir/../../verilog/rtl/lib/ser_inf_32b.sv     \
      $script_dir/../../verilog/rtl/lib/ctech_cells.sv     \
      $script_dir/../../verilog/rtl/lib/registers.v"
 

diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg
index 6375c1c..9a6b16f 100644
--- a/openlane/wb_host/pin_order.cfg
+++ b/openlane/wb_host/pin_order.cfg

@@ -4,22 +4,73 @@
 
 
 #W
-bist_clk           0000 0 4
-bist_rst_n
-bist_en
-bist_run
-bist_shift
-bist_load
-bist_done
-bist_error
-bist_correct
-bist_error_cnt\[3\]
-bist_error_cnt\[2\]
-bist_error_cnt\[1\]
-bist_error_cnt\[0\]
-bist_sdi
-bist_sdo
 wbd_int_rst_n
+bist_rst_n
+cfg_clk_ctrl1\[31\]
+cfg_clk_ctrl1\[30\]
+cfg_clk_ctrl1\[29\]
+cfg_clk_ctrl1\[28\]
+cfg_clk_ctrl1\[27\]
+cfg_clk_ctrl1\[26\]
+cfg_clk_ctrl1\[25\]
+cfg_clk_ctrl1\[24\]
+cfg_clk_ctrl1\[23\]
+cfg_clk_ctrl1\[22\]
+cfg_clk_ctrl1\[21\]
+cfg_clk_ctrl1\[20\]
+cfg_clk_ctrl1\[19\]
+cfg_clk_ctrl1\[18\]
+cfg_clk_ctrl1\[17\]
+cfg_clk_ctrl1\[16\]
+cfg_clk_ctrl1\[15\]
+cfg_clk_ctrl1\[14\]
+cfg_clk_ctrl1\[13\]
+cfg_clk_ctrl1\[12\]
+cfg_clk_ctrl1\[11\]
+cfg_clk_ctrl1\[10\]
+cfg_clk_ctrl1\[9\]
+cfg_clk_ctrl1\[8\]
+cfg_clk_ctrl1\[7\]
+cfg_clk_ctrl1\[6\]
+cfg_clk_ctrl1\[5\]
+cfg_clk_ctrl1\[4\]
+cfg_clk_ctrl1\[3\]
+cfg_clk_ctrl1\[2\]
+cfg_clk_ctrl1\[1\]
+cfg_clk_ctrl1\[0\]
+
+cfg_clk_ctrl2\[31\]
+cfg_clk_ctrl2\[30\]
+cfg_clk_ctrl2\[29\]
+cfg_clk_ctrl2\[28\]
+cfg_clk_ctrl2\[27\]
+cfg_clk_ctrl2\[26\]
+cfg_clk_ctrl2\[25\]
+cfg_clk_ctrl2\[24\]
+cfg_clk_ctrl2\[23\]
+cfg_clk_ctrl2\[22\]
+cfg_clk_ctrl2\[21\]
+cfg_clk_ctrl2\[20\]
+cfg_clk_ctrl2\[19\]
+cfg_clk_ctrl2\[18\]
+cfg_clk_ctrl2\[17\]
+cfg_clk_ctrl2\[16\]
+cfg_clk_ctrl2\[15\]
+cfg_clk_ctrl2\[14\]
+cfg_clk_ctrl2\[13\]
+cfg_clk_ctrl2\[12\]
+cfg_clk_ctrl2\[11\]
+cfg_clk_ctrl2\[10\]
+cfg_clk_ctrl2\[9\]
+cfg_clk_ctrl2\[8\]
+cfg_clk_ctrl2\[7\]
+cfg_clk_ctrl2\[6\]
+cfg_clk_ctrl2\[5\]
+cfg_clk_ctrl2\[4\]
+cfg_clk_ctrl2\[3\]
+cfg_clk_ctrl2\[2\]
+cfg_clk_ctrl2\[1\]
+cfg_clk_ctrl2\[0\]
 
 
 #E
@@ -229,9 +280,20 @@
 la_data_out\[0\]
 
 #S
-user_clock2         0000 0  2
+user_clock2         0000 0  4
+user_irq\[2\]
+user_irq\[1\]
+user_irq\[0\]
 user_clock1     
-wbm_clk_i       
+cfg_cska_wh\[3\]
+cfg_cska_wh\[2\]
+cfg_cska_wh\[1\]
+cfg_cska_wh\[0\]
+wbs_clk_out   
+wbd_clk_int
+wbd_clk_wh
+wbs_clk_i           
+wbm_clk_i           
 wbm_rst_i       
 wbm_ack_o       
 wbm_cyc_i       
@@ -342,98 +404,109 @@
 
 
 #N
-mem_clk_out      0000 0 2
-mem_clk       
-func_clk_a       
-func_cen_a
-func_addr_a\[8\] 
-func_addr_a\[7\] 
-func_addr_a\[6\] 
-func_addr_a\[5\] 
-func_addr_a\[4\] 
-func_addr_a\[3\] 
-func_addr_a\[2\] 
-func_addr_a\[1\] 
-func_addr_a\[0\] 
-func_dout_a\[31\]
-func_dout_a\[30\]
-func_dout_a\[29\]
-func_dout_a\[28\]
-func_dout_a\[27\]
-func_dout_a\[26\]
-func_dout_a\[25\]
-func_dout_a\[24\]
-func_dout_a\[23\]
-func_dout_a\[22\]
-func_dout_a\[21\]
-func_dout_a\[20\]
-func_dout_a\[19\]
-func_dout_a\[18\]
-func_dout_a\[17\]
-func_dout_a\[16\]
-func_dout_a\[15\]
-func_dout_a\[14\]
-func_dout_a\[13\]
-func_dout_a\[12\]
-func_dout_a\[11\]
-func_dout_a\[10\]
-func_dout_a\[9\]
-func_dout_a\[8\]
-func_dout_a\[7\]
-func_dout_a\[6\]
-func_dout_a\[5\]
-func_dout_a\[4\]
-func_dout_a\[3\]
-func_dout_a\[2\]
-func_dout_a\[1\]
-func_dout_a\[0\]
-
-func_clk_b          200 0 2
-func_cen_b
-func_web_b
-func_mask_b\[3\]
-func_mask_b\[2\]
-func_mask_b\[1\]
-func_mask_b\[0\]
-func_addr_b\[8\]
-func_addr_b\[7\]
-func_addr_b\[6\]
-func_addr_b\[5\]
-func_addr_b\[4\]
-func_addr_b\[3\]
-func_addr_b\[2\]
-func_addr_b\[1\]
-func_addr_b\[0\]
-func_din_b\[31\]
-func_din_b\[30\]
-func_din_b\[29\]
-func_din_b\[28\]
-func_din_b\[27\]
-func_din_b\[26\]
-func_din_b\[25\]
-func_din_b\[24\]
-func_din_b\[23\]
-func_din_b\[22\]
-func_din_b\[21\]
-func_din_b\[20\]
-func_din_b\[19\]
-func_din_b\[18\]
-func_din_b\[17\]
-func_din_b\[16\]
-func_din_b\[15\]
-func_din_b\[14\]
-func_din_b\[13\]
-func_din_b\[12\]
-func_din_b\[11\]
-func_din_b\[10\]
-func_din_b\[9\]
-func_din_b\[8\]
-func_din_b\[7\]
-func_din_b\[6\]
-func_din_b\[5\]
-func_din_b\[4\]
-func_din_b\[3\]
-func_din_b\[2\]
-func_din_b\[1\]
-func_din_b\[0\]
+wbs_stb_o        0000 0 2
+wbs_we_o         
+wbs_adr_o\[31\]  
+wbs_adr_o\[30\]  
+wbs_adr_o\[29\]  
+wbs_adr_o\[28\]  
+wbs_adr_o\[27\]  
+wbs_adr_o\[26\]  
+wbs_adr_o\[25\]  
+wbs_adr_o\[24\]  
+wbs_adr_o\[23\]  
+wbs_adr_o\[22\]  
+wbs_adr_o\[21\]  
+wbs_adr_o\[20\]  
+wbs_adr_o\[19\]  
+wbs_adr_o\[18\]  
+wbs_adr_o\[17\]  
+wbs_adr_o\[16\]  
+wbs_adr_o\[15\]  
+wbs_adr_o\[14\]  
+wbs_adr_o\[13\]  
+wbs_adr_o\[12\]  
+wbs_adr_o\[11\]  
+wbs_adr_o\[10\]  
+wbs_adr_o\[9\]   
+wbs_adr_o\[8\]   
+wbs_adr_o\[7\]   
+wbs_adr_o\[6\]   
+wbs_adr_o\[5\]   
+wbs_adr_o\[4\]   
+wbs_adr_o\[3\]   
+wbs_adr_o\[2\]   
+wbs_adr_o\[1\]   
+wbs_adr_o\[0\]   
+wbs_sel_o\[3\]   
+wbs_sel_o\[2\]   
+wbs_sel_o\[1\]   
+wbs_sel_o\[0\]   
+wbs_dat_o\[31\]  
+wbs_dat_o\[30\]  
+wbs_dat_o\[29\]  
+wbs_dat_o\[28\]  
+wbs_dat_o\[27\]  
+wbs_dat_o\[26\]  
+wbs_dat_o\[25\]  
+wbs_dat_o\[24\]  
+wbs_dat_o\[23\]  
+wbs_dat_o\[22\]  
+wbs_dat_o\[21\]  
+wbs_dat_o\[20\]  
+wbs_dat_o\[19\]  
+wbs_dat_o\[18\]  
+wbs_dat_o\[17\]  
+wbs_dat_o\[16\]  
+wbs_dat_o\[15\]  
+wbs_dat_o\[14\]  
+wbs_dat_o\[13\]  
+wbs_dat_o\[12\]  
+wbs_dat_o\[11\]  
+wbs_dat_o\[10\]  
+wbs_dat_o\[9\]   
+wbs_dat_o\[8\]   
+wbs_dat_o\[7\]   
+wbs_dat_o\[6\]   
+wbs_dat_o\[5\]   
+wbs_dat_o\[4\]   
+wbs_dat_o\[3\]   
+wbs_dat_o\[2\]   
+wbs_dat_o\[1\]   
+wbs_dat_o\[0\]   
+wbs_dat_i\[31\]  
+wbs_dat_i\[30\]  
+wbs_dat_i\[29\]  
+wbs_dat_i\[28\]  
+wbs_dat_i\[27\]  
+wbs_dat_i\[26\]  
+wbs_dat_i\[25\]  
+wbs_dat_i\[24\]  
+wbs_dat_i\[23\]  
+wbs_dat_i\[22\]  
+wbs_dat_i\[21\]  
+wbs_dat_i\[20\]  
+wbs_dat_i\[19\]  
+wbs_dat_i\[18\]  
+wbs_dat_i\[17\]  
+wbs_dat_i\[16\]  
+wbs_dat_i\[15\]  
+wbs_dat_i\[14\]  
+wbs_dat_i\[13\]  
+wbs_dat_i\[12\]  
+wbs_dat_i\[11\]  
+wbs_dat_i\[10\]  
+wbs_dat_i\[9\]   
+wbs_dat_i\[8\]   
+wbs_dat_i\[7\]   
+wbs_dat_i\[6\]   
+wbs_dat_i\[5\]   
+wbs_dat_i\[4\]   
+wbs_dat_i\[3\]   
+wbs_dat_i\[2\]   
+wbs_dat_i\[1\]   
+wbs_dat_i\[0\]   
+wbs_ack_i        
+wbs_err_i        
+wbs_cyc_o      
 

diff --git a/openlane/wb_interconnect/.sta.tcl.swp b/openlane/wb_interconnect/.sta.tcl.swp
new file mode 100644
index 0000000..3db5a52
--- /dev/null
+++ b/openlane/wb_interconnect/.sta.tcl.swp
Binary files differ

diff --git a/openlane/wb_interconnect/base.sdc b/openlane/wb_interconnect/base.sdc
new file mode 100644
index 0000000..dafacea
--- /dev/null
+++ b/openlane/wb_interconnect/base.sdc

@@ -0,0 +1,178 @@
+###############################################################################
+# Created by write_sdc
+# Fri Nov 12 05:00:05 2021
+###############################################################################
+current_design wb_interconnect
+###############################################################################
+# Timing Constraints
+###############################################################################
+create_clock -name clk_i -period 10.0000 [get_ports {clk_i}]
+set_clock_uncertainty -rise_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}]  -hold 0.1000
+set_clock_uncertainty -rise_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}]  -setup 0.2000
+set_clock_uncertainty -fall_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}]  -hold 0.1000
+set_clock_uncertainty -fall_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}]  -setup 0.2000
+
+#Static Signal Clock Skew adjustment
+set_false_path -from [get_ports {cfg_cska_wi[0]}]
+set_false_path -from [get_ports {cfg_cska_wi[1]}]
+set_false_path -from [get_ports {cfg_cska_wi[2]}]
+set_false_path -from [get_ports {cfg_cska_wi[3]}]
+set_max_delay   2 -from [get_ports {wbd_clk_int}]
+set_max_delay   2 -to   [get_ports {wbd_clk_wi}]
+set_input_delay -max 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {rst_n}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_dat_i[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_dat_i[*]}]
+
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_ack_o}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_err_o}]
+
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_cyc_o}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_we_o}]
+
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_cyc_o}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_we_o}]
+
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_cyc_o}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_we_o}]
+
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_cyc_o}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_we_o}]
+
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_adr_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_cyc_o}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_dat_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_sel_o[*]}]
+set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_we_o}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_ack_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_err_o}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[*]}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s4_wbd_dat_o[*]}]
+
+
+###############################################################################
+# Environment
+###############################################################################
+set_load -pin_load 0.0334 [get_ports {m0_wbd_ack_o}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_err_o}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {s3_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s3_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s3_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {s4_wbd_cyc_o}]
+set_load -pin_load 0.0334 [get_ports {s4_wbd_stb_o}]
+set_load -pin_load 0.0334 [get_ports {s4_wbd_we_o}]
+set_load -pin_load 0.0334 [get_ports {wbd_clk_wi}]
+set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[*]}]
+
+set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[*]}]
+
+set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[*]}]
+
+set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[*]}]
+
+set_load -pin_load 0.0334 [get_ports {s4_wbd_adr_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s4_wbd_dat_o[*]}]
+set_load -pin_load 0.0334 [get_ports {s4_wbd_sel_o[*]}]
+
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_cyc_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_stb_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_we_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_ack_i}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s4_wbd_dat_i[*]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s4_wbd_ack_i}]
+###############################################################################
+# Design Rules
+###############################################################################

diff --git a/openlane/mbist/config.tcl b/openlane/wb_interconnect/config.tcl
similarity index 63%
copy from openlane/mbist/config.tcl
copy to openlane/wb_interconnect/config.tcl
index de3c917..c081896 100755
--- a/openlane/mbist/config.tcl
+++ b/openlane/wb_interconnect/config.tcl

@@ -19,14 +19,15 @@
 
 set script_dir [file dirname [file normalize [info script]]]
 # Name
+set ::env(DESIGN_NAME) wb_interconnect
 
-set ::env(DESIGN_NAME) mbist_top
 
 set ::env(DESIGN_IS_CORE) "0"
+set ::env(FP_PDN_CORE_RING) "0"
 
 # Timing configuration
-set ::env(CLOCK_PERIOD) "8"
-set ::env(CLOCK_PORT) "bist_clk u_mem_sel.u_cts_mem_clk_a/X u_mem_sel.u_cts_mem_clk_a/X"
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "clk_i"
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
@@ -35,20 +36,10 @@
 
 # Local sources + no2usb sources
 set ::env(VERILOG_FILES) "\
-     $script_dir/../../verilog/rtl/mbist/src/mbist_addr_gen.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_fsm.sv     \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_op_sel.sv  \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_repair_addr.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_top.sv  \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_sti_sel.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_pat_sel.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_mux.sv \
-     $script_dir/../../verilog/rtl/mbist/src/mbist_data_cmp.sv \
-     $script_dir/../../verilog/rtl/lib/ctech_cells.sv     \
-     $script_dir/../../verilog/rtl/lib/reset_sync.sv \
-	     "
-
-set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/mbist/include ]
+        $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \
+        $script_dir/../../verilog/rtl/lib/wb_stagging.sv                \
+        $script_dir/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv  \
+	"
 
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 set ::env(SDC_FILE) "$script_dir/base.sdc"
@@ -66,19 +57,21 @@
 set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
 
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 400 200"
+set ::env(DIE_AREA) "0 0 150 2200"
 
 
 # If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 1
+set ::env(RUN_CVC) 0
 
 #set ::env(PDN_CFG) $script_dir/pdn.tcl
 
 
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.30"
+set ::env(FP_CORE_UTIL) "50"
+set ::env(PL_TARGET_DENSITY) "0.50"
 
-
+# helps in anteena fix
+set ::env(USE_ARC_ANTENNA_CHECK) "0"
 
 set ::env(FP_IO_VEXTEND) 4
 set ::env(FP_IO_HEXTEND) 4
@@ -90,11 +83,15 @@
 
 set ::env(GLB_RT_MAXLAYER) 5
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
-
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
 
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
-set ::env(QUIT_ON_MAGIC_DRC) "0"
+set ::env(QUIT_ON_MAGIC_DRC) "1"
 set ::env(QUIT_ON_LVS_ERROR) "0"
 set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
+
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0"
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "0"
+

diff --git a/openlane/wb_interconnect/pdn.tcl b/openlane/wb_interconnect/pdn.tcl
new file mode 100644
index 0000000..1fe689b
--- /dev/null
+++ b/openlane/wb_interconnect/pdn.tcl

@@ -0,0 +1,49 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+    }
+    straps {
+	    met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+	    met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)}
+    }
+    connect {{met1 met4} {met4 met5}}
+}
+
+pdngen::specify_grid macro {
+    power_pins "VPWR"
+    ground_pins "VGND"
+    blockages "li1 met1 met2 met3 met4"
+    straps { 
+    } 
+    connect {{met4_PIN_ver met5}}
+}
+
+set ::halo 5
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;

diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
new file mode 100644
index 0000000..f9bc1cb
--- /dev/null
+++ b/openlane/wb_interconnect/pin_order.cfg

@@ -0,0 +1,537 @@
+#BUS_SORT
+
+#MANUAL_PLACE
+
+#S
+m0_wbd_stb_i        0000 0 2
+m0_wbd_we_i         
+m0_wbd_adr_i\[31\]  
+m0_wbd_adr_i\[30\]  
+m0_wbd_adr_i\[29\]  
+m0_wbd_adr_i\[28\]  
+m0_wbd_adr_i\[27\]  
+m0_wbd_adr_i\[26\]  
+m0_wbd_adr_i\[25\]  
+m0_wbd_adr_i\[24\]  
+m0_wbd_adr_i\[23\]  
+m0_wbd_adr_i\[22\]  
+m0_wbd_adr_i\[21\]  
+m0_wbd_adr_i\[20\]  
+m0_wbd_adr_i\[19\]  
+m0_wbd_adr_i\[18\]  
+m0_wbd_adr_i\[17\]  
+m0_wbd_adr_i\[16\]  
+m0_wbd_adr_i\[15\]  
+m0_wbd_adr_i\[14\]  
+m0_wbd_adr_i\[13\]  
+m0_wbd_adr_i\[12\]  
+m0_wbd_adr_i\[11\]  
+m0_wbd_adr_i\[10\]  
+m0_wbd_adr_i\[9\]   
+m0_wbd_adr_i\[8\]   
+m0_wbd_adr_i\[7\]   
+m0_wbd_adr_i\[6\]   
+m0_wbd_adr_i\[5\]   
+m0_wbd_adr_i\[4\]   
+m0_wbd_adr_i\[3\]   
+m0_wbd_adr_i\[2\]   
+m0_wbd_adr_i\[1\]   
+m0_wbd_adr_i\[0\]   
+m0_wbd_sel_i\[3\]   
+m0_wbd_sel_i\[2\]   
+m0_wbd_sel_i\[1\]   
+m0_wbd_sel_i\[0\]   
+m0_wbd_dat_i\[31\]  
+m0_wbd_dat_i\[30\]  
+m0_wbd_dat_i\[29\]  
+m0_wbd_dat_i\[28\]  
+m0_wbd_dat_i\[27\]  
+m0_wbd_dat_i\[26\]  
+m0_wbd_dat_i\[25\]  
+m0_wbd_dat_i\[24\]  
+m0_wbd_dat_i\[23\]  
+m0_wbd_dat_i\[22\]  
+m0_wbd_dat_i\[21\]  
+m0_wbd_dat_i\[20\]  
+m0_wbd_dat_i\[19\]  
+m0_wbd_dat_i\[18\]  
+m0_wbd_dat_i\[17\]  
+m0_wbd_dat_i\[16\]  
+m0_wbd_dat_i\[15\]  
+m0_wbd_dat_i\[14\]  
+m0_wbd_dat_i\[13\]  
+m0_wbd_dat_i\[12\]  
+m0_wbd_dat_i\[11\]  
+m0_wbd_dat_i\[10\]  
+m0_wbd_dat_i\[9\]   
+m0_wbd_dat_i\[8\]   
+m0_wbd_dat_i\[7\]   
+m0_wbd_dat_i\[6\]   
+m0_wbd_dat_i\[5\]   
+m0_wbd_dat_i\[4\]   
+m0_wbd_dat_i\[3\]   
+m0_wbd_dat_i\[2\]   
+m0_wbd_dat_i\[1\]   
+m0_wbd_dat_i\[0\]   
+m0_wbd_dat_o\[31\]  
+m0_wbd_dat_o\[30\]  
+m0_wbd_dat_o\[29\]  
+m0_wbd_dat_o\[28\]  
+m0_wbd_dat_o\[27\]  
+m0_wbd_dat_o\[26\]  
+m0_wbd_dat_o\[25\]  
+m0_wbd_dat_o\[24\]  
+m0_wbd_dat_o\[23\]  
+m0_wbd_dat_o\[22\]  
+m0_wbd_dat_o\[21\]  
+m0_wbd_dat_o\[20\]  
+m0_wbd_dat_o\[19\]  
+m0_wbd_dat_o\[18\]  
+m0_wbd_dat_o\[17\]  
+m0_wbd_dat_o\[16\]  
+m0_wbd_dat_o\[15\]  
+m0_wbd_dat_o\[14\]  
+m0_wbd_dat_o\[13\]  
+m0_wbd_dat_o\[12\]  
+m0_wbd_dat_o\[11\]  
+m0_wbd_dat_o\[10\]  
+m0_wbd_dat_o\[9\]   
+m0_wbd_dat_o\[8\]   
+m0_wbd_dat_o\[7\]   
+m0_wbd_dat_o\[6\]   
+m0_wbd_dat_o\[5\]   
+m0_wbd_dat_o\[4\]   
+m0_wbd_dat_o\[3\]   
+m0_wbd_dat_o\[2\]   
+m0_wbd_dat_o\[1\]   
+m0_wbd_dat_o\[0\]   
+m0_wbd_ack_o        
+m0_wbd_err_o        
+m0_wbd_cyc_i        
+
+cfg_cska_wi\[3\]     100 0 2
+cfg_cska_wi\[2\]     
+cfg_cska_wi\[1\]     
+cfg_cska_wi\[0\] 
+wbd_clk_int
+wbd_clk_wi    
+clk_i               
+rst_n               
+
+#W
+s0_wbd_stb_o        0000 0 2
+s0_wbd_we_o         
+s0_wbd_adr_o\[7\]   
+s0_wbd_adr_o\[6\]   
+s0_wbd_adr_o\[5\]   
+s0_wbd_adr_o\[4\]   
+s0_wbd_adr_o\[3\]   
+s0_wbd_adr_o\[2\]   
+s0_wbd_adr_o\[1\]   
+s0_wbd_adr_o\[0\]   
+s0_wbd_sel_o\[3\]   
+s0_wbd_sel_o\[2\]   
+s0_wbd_sel_o\[1\]   
+s0_wbd_sel_o\[0\]   
+s0_wbd_dat_o\[31\]  
+s0_wbd_dat_o\[30\]  
+s0_wbd_dat_o\[29\]  
+s0_wbd_dat_o\[28\]  
+s0_wbd_dat_o\[27\]  
+s0_wbd_dat_o\[26\]  
+s0_wbd_dat_o\[25\]  
+s0_wbd_dat_o\[24\]  
+s0_wbd_dat_o\[23\]  
+s0_wbd_dat_o\[22\]  
+s0_wbd_dat_o\[21\]  
+s0_wbd_dat_o\[20\]  
+s0_wbd_dat_o\[19\]  
+s0_wbd_dat_o\[18\]  
+s0_wbd_dat_o\[17\]  
+s0_wbd_dat_o\[16\]  
+s0_wbd_dat_o\[15\]  
+s0_wbd_dat_o\[14\]  
+s0_wbd_dat_o\[13\]  
+s0_wbd_dat_o\[12\]  
+s0_wbd_dat_o\[11\]  
+s0_wbd_dat_o\[10\]  
+s0_wbd_dat_o\[9\]   
+s0_wbd_dat_o\[8\]   
+s0_wbd_dat_o\[7\]   
+s0_wbd_dat_o\[6\]   
+s0_wbd_dat_o\[5\]   
+s0_wbd_dat_o\[4\]   
+s0_wbd_dat_o\[3\]   
+s0_wbd_dat_o\[2\]   
+s0_wbd_dat_o\[1\]   
+s0_wbd_dat_o\[0\]   
+s0_wbd_dat_i\[31\]  
+s0_wbd_dat_i\[30\]  
+s0_wbd_dat_i\[29\]  
+s0_wbd_dat_i\[28\]  
+s0_wbd_dat_i\[27\]  
+s0_wbd_dat_i\[26\]  
+s0_wbd_dat_i\[25\]  
+s0_wbd_dat_i\[24\]  
+s0_wbd_dat_i\[23\]  
+s0_wbd_dat_i\[22\]  
+s0_wbd_dat_i\[21\]  
+s0_wbd_dat_i\[20\]  
+s0_wbd_dat_i\[19\]  
+s0_wbd_dat_i\[18\]  
+s0_wbd_dat_i\[17\]  
+s0_wbd_dat_i\[16\]  
+s0_wbd_dat_i\[15\]  
+s0_wbd_dat_i\[14\]  
+s0_wbd_dat_i\[13\]  
+s0_wbd_dat_i\[12\]  
+s0_wbd_dat_i\[11\]  
+s0_wbd_dat_i\[10\]  
+s0_wbd_dat_i\[9\]   
+s0_wbd_dat_i\[8\]   
+s0_wbd_dat_i\[7\]   
+s0_wbd_dat_i\[6\]   
+s0_wbd_dat_i\[5\]   
+s0_wbd_dat_i\[4\]   
+s0_wbd_dat_i\[3\]   
+s0_wbd_dat_i\[2\]   
+s0_wbd_dat_i\[1\]   
+s0_wbd_dat_i\[0\]   
+s0_wbd_ack_i        
+s0_wbd_cyc_o        
+
+
+#E
+s1_wbd_stb_o        0000 0 2
+s1_wbd_we_o         
+s1_wbd_adr_o\[10\]  
+s1_wbd_adr_o\[9\]   
+s1_wbd_adr_o\[8\]   
+s1_wbd_adr_o\[7\]   
+s1_wbd_adr_o\[6\]   
+s1_wbd_adr_o\[5\]   
+s1_wbd_adr_o\[4\]   
+s1_wbd_adr_o\[3\]   
+s1_wbd_adr_o\[2\]   
+s1_wbd_adr_o\[1\]   
+s1_wbd_adr_o\[0\]   
+s1_wbd_sel_o\[3\]   
+s1_wbd_sel_o\[2\]   
+s1_wbd_sel_o\[1\]   
+s1_wbd_sel_o\[0\]   
+s1_wbd_dat_o\[31\]  
+s1_wbd_dat_o\[30\]  
+s1_wbd_dat_o\[29\]  
+s1_wbd_dat_o\[28\]  
+s1_wbd_dat_o\[27\]  
+s1_wbd_dat_o\[26\]  
+s1_wbd_dat_o\[25\]  
+s1_wbd_dat_o\[24\]  
+s1_wbd_dat_o\[23\]  
+s1_wbd_dat_o\[22\]  
+s1_wbd_dat_o\[21\]  
+s1_wbd_dat_o\[20\]  
+s1_wbd_dat_o\[19\]  
+s1_wbd_dat_o\[18\]  
+s1_wbd_dat_o\[17\]  
+s1_wbd_dat_o\[16\]  
+s1_wbd_dat_o\[15\]  
+s1_wbd_dat_o\[14\]  
+s1_wbd_dat_o\[13\]  
+s1_wbd_dat_o\[12\]  
+s1_wbd_dat_o\[11\]  
+s1_wbd_dat_o\[10\]  
+s1_wbd_dat_o\[9\]   
+s1_wbd_dat_o\[8\]   
+s1_wbd_dat_o\[7\]   
+s1_wbd_dat_o\[6\]   
+s1_wbd_dat_o\[5\]   
+s1_wbd_dat_o\[4\]   
+s1_wbd_dat_o\[3\]   
+s1_wbd_dat_o\[2\]   
+s1_wbd_dat_o\[1\]   
+s1_wbd_dat_o\[0\]   
+s1_wbd_dat_i\[31\]  
+s1_wbd_dat_i\[30\]  
+s1_wbd_dat_i\[29\]  
+s1_wbd_dat_i\[28\]  
+s1_wbd_dat_i\[27\]  
+s1_wbd_dat_i\[26\]  
+s1_wbd_dat_i\[25\]  
+s1_wbd_dat_i\[24\]  
+s1_wbd_dat_i\[23\]  
+s1_wbd_dat_i\[22\]  
+s1_wbd_dat_i\[21\]  
+s1_wbd_dat_i\[20\]  
+s1_wbd_dat_i\[19\]  
+s1_wbd_dat_i\[18\]  
+s1_wbd_dat_i\[17\]  
+s1_wbd_dat_i\[16\]  
+s1_wbd_dat_i\[15\]  
+s1_wbd_dat_i\[14\]  
+s1_wbd_dat_i\[13\]  
+s1_wbd_dat_i\[12\]  
+s1_wbd_dat_i\[11\]  
+s1_wbd_dat_i\[10\]  
+s1_wbd_dat_i\[9\]   
+s1_wbd_dat_i\[8\]   
+s1_wbd_dat_i\[7\]   
+s1_wbd_dat_i\[6\]   
+s1_wbd_dat_i\[5\]   
+s1_wbd_dat_i\[4\]   
+s1_wbd_dat_i\[3\]   
+s1_wbd_dat_i\[2\]   
+s1_wbd_dat_i\[1\]   
+s1_wbd_dat_i\[0\]   
+s1_wbd_ack_i        
+s1_wbd_cyc_o        
+
+s2_wbd_stb_o        600 0 2
+s2_wbd_we_o         
+s2_wbd_adr_o\[10\]   
+s2_wbd_adr_o\[9\]   
+s2_wbd_adr_o\[8\]   
+s2_wbd_adr_o\[7\]   
+s2_wbd_adr_o\[6\]   
+s2_wbd_adr_o\[5\]   
+s2_wbd_adr_o\[4\]   
+s2_wbd_adr_o\[3\]   
+s2_wbd_adr_o\[2\]   
+s2_wbd_adr_o\[1\]   
+s2_wbd_adr_o\[0\]   
+s2_wbd_sel_o\[3\]   
+s2_wbd_sel_o\[2\]   
+s2_wbd_sel_o\[1\]   
+s2_wbd_sel_o\[0\]   
+s2_wbd_dat_o\[31\]  
+s2_wbd_dat_o\[30\]  
+s2_wbd_dat_o\[29\]  
+s2_wbd_dat_o\[28\]  
+s2_wbd_dat_o\[27\]  
+s2_wbd_dat_o\[26\]  
+s2_wbd_dat_o\[25\]  
+s2_wbd_dat_o\[24\]  
+s2_wbd_dat_o\[23\]  
+s2_wbd_dat_o\[22\]  
+s2_wbd_dat_o\[21\]  
+s2_wbd_dat_o\[20\]  
+s2_wbd_dat_o\[19\]  
+s2_wbd_dat_o\[18\]  
+s2_wbd_dat_o\[17\]  
+s2_wbd_dat_o\[16\]  
+s2_wbd_dat_o\[15\]  
+s2_wbd_dat_o\[14\]  
+s2_wbd_dat_o\[13\]  
+s2_wbd_dat_o\[12\]  
+s2_wbd_dat_o\[11\]  
+s2_wbd_dat_o\[10\]  
+s2_wbd_dat_o\[9\]   
+s2_wbd_dat_o\[8\]   
+s2_wbd_dat_o\[7\]   
+s2_wbd_dat_o\[6\]   
+s2_wbd_dat_o\[5\]   
+s2_wbd_dat_o\[4\]   
+s2_wbd_dat_o\[3\]   
+s2_wbd_dat_o\[2\]   
+s2_wbd_dat_o\[1\]   
+s2_wbd_dat_o\[0\]   
+s2_wbd_dat_i\[31\]  
+s2_wbd_dat_i\[30\]  
+s2_wbd_dat_i\[29\]  
+s2_wbd_dat_i\[28\]  
+s2_wbd_dat_i\[27\]  
+s2_wbd_dat_i\[26\]  
+s2_wbd_dat_i\[25\]  
+s2_wbd_dat_i\[24\]  
+s2_wbd_dat_i\[23\]  
+s2_wbd_dat_i\[22\] 
+s2_wbd_dat_i\[21\]  
+s2_wbd_dat_i\[20\]  
+s2_wbd_dat_i\[19\]  
+s2_wbd_dat_i\[18\]  
+s2_wbd_dat_i\[17\]  
+s2_wbd_dat_i\[16\]  
+s2_wbd_dat_i\[15\]  
+s2_wbd_dat_i\[14\]  
+s2_wbd_dat_i\[13\]  
+s2_wbd_dat_i\[12\]  
+s2_wbd_dat_i\[11\]  
+s2_wbd_dat_i\[10\]  
+s2_wbd_dat_i\[9\]   
+s2_wbd_dat_i\[8\]   
+s2_wbd_dat_i\[7\]   
+s2_wbd_dat_i\[6\]   
+s2_wbd_dat_i\[5\]   
+s2_wbd_dat_i\[4\]   
+s2_wbd_dat_i\[3\]   
+s2_wbd_dat_i\[2\]   
+s2_wbd_dat_i\[1\]   
+s2_wbd_dat_i\[0\]   
+s2_wbd_ack_i        
+s2_wbd_cyc_o        
+
+s3_wbd_stb_o        1200 0 2
+s3_wbd_we_o         
+s3_wbd_adr_o\[9\]   
+s3_wbd_adr_o\[8\]   
+s3_wbd_adr_o\[7\]   
+s3_wbd_adr_o\[6\]   
+s3_wbd_adr_o\[5\]   
+s3_wbd_adr_o\[4\]   
+s3_wbd_adr_o\[3\]   
+s3_wbd_adr_o\[2\]   
+s3_wbd_adr_o\[1\]   
+s3_wbd_adr_o\[0\]   
+s3_wbd_sel_o\[3\]   
+s3_wbd_sel_o\[2\]   
+s3_wbd_sel_o\[1\]   
+s3_wbd_sel_o\[0\]   
+s3_wbd_dat_o\[31\]  
+s3_wbd_dat_o\[30\]  
+s3_wbd_dat_o\[29\]  
+s3_wbd_dat_o\[28\]  
+s3_wbd_dat_o\[27\]  
+s3_wbd_dat_o\[26\]  
+s3_wbd_dat_o\[25\]  
+s3_wbd_dat_o\[24\]  
+s3_wbd_dat_o\[23\]  
+s3_wbd_dat_o\[22\]  
+s3_wbd_dat_o\[21\]  
+s3_wbd_dat_o\[20\]  
+s3_wbd_dat_o\[19\]  
+s3_wbd_dat_o\[18\]  
+s3_wbd_dat_o\[17\]  
+s3_wbd_dat_o\[16\]  
+s3_wbd_dat_o\[15\]  
+s3_wbd_dat_o\[14\]  
+s3_wbd_dat_o\[13\]  
+s3_wbd_dat_o\[12\]  
+s3_wbd_dat_o\[11\]  
+s3_wbd_dat_o\[10\]  
+s3_wbd_dat_o\[9\]   
+s3_wbd_dat_o\[8\]   
+s3_wbd_dat_o\[7\]   
+s3_wbd_dat_o\[6\]   
+s3_wbd_dat_o\[5\]   
+s3_wbd_dat_o\[4\]   
+s3_wbd_dat_o\[3\]   
+s3_wbd_dat_o\[2\]   
+s3_wbd_dat_o\[1\]   
+s3_wbd_dat_o\[0\]   
+s3_wbd_dat_i\[31\]  
+s3_wbd_dat_i\[30\]  
+s3_wbd_dat_i\[29\]  
+s3_wbd_dat_i\[28\]  
+s3_wbd_dat_i\[27\]  
+s3_wbd_dat_i\[26\]  
+s3_wbd_dat_i\[25\]  
+s3_wbd_dat_i\[24\]  
+s3_wbd_dat_i\[23\]  
+s3_wbd_dat_i\[22\] 
+s3_wbd_dat_i\[21\]  
+s3_wbd_dat_i\[20\]  
+s3_wbd_dat_i\[19\]  
+s3_wbd_dat_i\[18\]  
+s3_wbd_dat_i\[17\]  
+s3_wbd_dat_i\[16\]  
+s3_wbd_dat_i\[15\]  
+s3_wbd_dat_i\[14\]  
+s3_wbd_dat_i\[13\]  
+s3_wbd_dat_i\[12\]  
+s3_wbd_dat_i\[11\]  
+s3_wbd_dat_i\[10\]  
+s3_wbd_dat_i\[9\]   
+s3_wbd_dat_i\[8\]   
+s3_wbd_dat_i\[7\]   
+s3_wbd_dat_i\[6\]   
+s3_wbd_dat_i\[5\]   
+s3_wbd_dat_i\[4\]   
+s3_wbd_dat_i\[3\]   
+s3_wbd_dat_i\[2\]   
+s3_wbd_dat_i\[1\]   
+s3_wbd_dat_i\[0\]   
+s3_wbd_ack_i        
+s3_wbd_cyc_o        
+
+s4_wbd_stb_o        1800 0 2
+s4_wbd_we_o         
+s4_wbd_adr_o\[9\]   
+s4_wbd_adr_o\[8\]   
+s4_wbd_adr_o\[7\]   
+s4_wbd_adr_o\[6\]   
+s4_wbd_adr_o\[5\]   
+s4_wbd_adr_o\[4\]   
+s4_wbd_adr_o\[3\]   
+s4_wbd_adr_o\[2\]   
+s4_wbd_adr_o\[1\]   
+s4_wbd_adr_o\[0\]   
+s4_wbd_sel_o\[3\]   
+s4_wbd_sel_o\[2\]   
+s4_wbd_sel_o\[1\]   
+s4_wbd_sel_o\[0\]   
+s4_wbd_dat_o\[31\]  
+s4_wbd_dat_o\[30\]  
+s4_wbd_dat_o\[29\]  
+s4_wbd_dat_o\[28\]  
+s4_wbd_dat_o\[27\]  
+s4_wbd_dat_o\[26\]  
+s4_wbd_dat_o\[25\]  
+s4_wbd_dat_o\[24\]  
+s4_wbd_dat_o\[23\]  
+s4_wbd_dat_o\[22\]  
+s4_wbd_dat_o\[21\]  
+s4_wbd_dat_o\[20\]  
+s4_wbd_dat_o\[19\]  
+s4_wbd_dat_o\[18\]  
+s4_wbd_dat_o\[17\]  
+s4_wbd_dat_o\[16\]  
+s4_wbd_dat_o\[15\]  
+s4_wbd_dat_o\[14\]  
+s4_wbd_dat_o\[13\]  
+s4_wbd_dat_o\[12\]  
+s4_wbd_dat_o\[11\]  
+s4_wbd_dat_o\[10\]  
+s4_wbd_dat_o\[9\]   
+s4_wbd_dat_o\[8\]   
+s4_wbd_dat_o\[7\]   
+s4_wbd_dat_o\[6\]   
+s4_wbd_dat_o\[5\]   
+s4_wbd_dat_o\[4\]   
+s4_wbd_dat_o\[3\]   
+s4_wbd_dat_o\[2\]   
+s4_wbd_dat_o\[1\]   
+s4_wbd_dat_o\[0\]   
+s4_wbd_dat_i\[31\]  
+s4_wbd_dat_i\[30\]  
+s4_wbd_dat_i\[29\]  
+s4_wbd_dat_i\[28\]  
+s4_wbd_dat_i\[27\]  
+s4_wbd_dat_i\[26\]  
+s4_wbd_dat_i\[25\]  
+s4_wbd_dat_i\[24\]  
+s4_wbd_dat_i\[23\]  
+s4_wbd_dat_i\[22\] 
+s4_wbd_dat_i\[21\]  
+s4_wbd_dat_i\[20\]  
+s4_wbd_dat_i\[19\]  
+s4_wbd_dat_i\[18\]  
+s4_wbd_dat_i\[17\]  
+s4_wbd_dat_i\[16\]  
+s4_wbd_dat_i\[15\]  
+s4_wbd_dat_i\[14\]  
+s4_wbd_dat_i\[13\]  
+s4_wbd_dat_i\[12\]  
+s4_wbd_dat_i\[11\]  
+s4_wbd_dat_i\[10\]  
+s4_wbd_dat_i\[9\]   
+s4_wbd_dat_i\[8\]   
+s4_wbd_dat_i\[7\]   
+s4_wbd_dat_i\[6\]   
+s4_wbd_dat_i\[5\]   
+s4_wbd_dat_i\[4\]   
+s4_wbd_dat_i\[3\]   
+s4_wbd_dat_i\[2\]   
+s4_wbd_dat_i\[1\]   
+s4_wbd_dat_i\[0\]   
+s4_wbd_ack_i        
+s4_wbd_cyc_o        

diff --git a/openlane/wb_interconnect/sta.tcl b/openlane/wb_interconnect/sta.tcl
new file mode 100644
index 0000000..cb809a5
--- /dev/null
+++ b/openlane/wb_interconnect/sta.tcl

@@ -0,0 +1,57 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(CURRENT_NETLIST) runs/wb_interconnect/results/synthesis/wb_interconnect.synthesis_preroute.v
+set ::env(DESIGN_NAME) "wb_interconnect"
+set ::env(CURRENT_SPEF) ../../spef/wb_interconnect.spef
+set ::env(BASE_SDC_FILE) "base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+read_liberty -min $::env(LIB_FASTEST)
+read_liberty -max $::env(LIB_SLOWEST)
+read_verilog $::env(CURRENT_NETLIST)
+link_design  $::env(DESIGN_NAME)
+
+read_spef  $::env(CURRENT_SPEF)
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup  -verbose > unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+report_power 
+report_checks -unique -slack_max -0.0 -group_count 100 
+report_checks -unique -slack_min -0.0 -group_count 100 
+report_checks -path_delay min_max 
+report_checks -group_count 100  -slack_max -0.01  > timing.rpt
+
+report_checks -group_count 100  -slack_min -0.01 >> timing.rpt
+
+

diff --git a/signoff/glbl_cfg/OPENLANE_VERSION b/signoff/glbl_cfg/OPENLANE_VERSION
new file mode 100644
index 0000000..80c7664
--- /dev/null
+++ b/signoff/glbl_cfg/OPENLANE_VERSION

@@ -0,0 +1 @@
+openlane N/A

diff --git a/signoff/glbl_cfg/PDK_SOURCES b/signoff/glbl_cfg/PDK_SOURCES
new file mode 100644
index 0000000..ca3684a
--- /dev/null
+++ b/signoff/glbl_cfg/PDK_SOURCES

@@ -0,0 +1,6 @@
+-ne openlane 
+8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
+-ne skywater-pdk 
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+-ne open_pdks 
+14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad

diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
new file mode 100644
index 0000000..143a995
--- /dev/null
+++ b/signoff/glbl_cfg/final_summary_report.csv

@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,flow_completed,0h2m44s,-1,34496.0,0.0625,17248.0,22.32,548.17,1078,0,0,0,0,0,0,0,1,0,-1,-1,56118,10305,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,34379429.0,0.0,23.92,17.17,1.87,1.98,-1,1093,1786,640,1301,0,0,0,740,0,0,0,0,0,0,0,4,339,281,11,166,765,0,931,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4

diff --git a/signoff/mbist1/OPENLANE_VERSION b/signoff/mbist1/OPENLANE_VERSION
new file mode 100644
index 0000000..80c7664
--- /dev/null
+++ b/signoff/mbist1/OPENLANE_VERSION

@@ -0,0 +1 @@
+openlane N/A

diff --git a/signoff/mbist1/PDK_SOURCES b/signoff/mbist1/PDK_SOURCES
new file mode 100644
index 0000000..ca3684a
--- /dev/null
+++ b/signoff/mbist1/PDK_SOURCES

@@ -0,0 +1,6 @@
+-ne openlane 
+8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
+-ne skywater-pdk 
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+-ne open_pdks 
+14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad

diff --git a/signoff/mbist1/final_summary_report.csv b/signoff/mbist1/final_summary_report.csv
new file mode 100644
index 0000000..8a28c87
--- /dev/null
+++ b/signoff/mbist1/final_summary_report.csv

@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/mbist1,mbist_top1,mbist1,flow_completed,0h4m50s,-1,49880.0,0.05,24940.0,30.9,584.83,1247,0,0,0,0,0,0,-1,11,0,0,-1,94813,15439,-2.97,-3.45,-1,-3.3,-1,-96.9,-108.64,-1,-139.61,-1,48342142.0,33.68,41.51,41.32,8.23,4.68,-1,1173,2529,315,1639,0,0,0,1157,0,0,0,0,0,0,0,4,232,261,16,166,595,0,761,111.11111111111111,9,8,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4

diff --git a/signoff/mbist2/OPENLANE_VERSION b/signoff/mbist2/OPENLANE_VERSION
new file mode 100644
index 0000000..80c7664
--- /dev/null
+++ b/signoff/mbist2/OPENLANE_VERSION

@@ -0,0 +1 @@
+openlane N/A

diff --git a/signoff/mbist2/PDK_SOURCES b/signoff/mbist2/PDK_SOURCES
new file mode 100644
index 0000000..ca3684a
--- /dev/null
+++ b/signoff/mbist2/PDK_SOURCES

@@ -0,0 +1,6 @@
+-ne openlane 
+8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
+-ne skywater-pdk 
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+-ne open_pdks 
+14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad

diff --git a/signoff/mbist2/final_summary_report.csv b/signoff/mbist2/final_summary_report.csv
new file mode 100644
index 0000000..e28708f
--- /dev/null
+++ b/signoff/mbist2/final_summary_report.csv

@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/mbist2,mbist_top2,mbist2,flow_completed,0h3m46s,-1,47080.0,0.05,23540.0,29.07,558.92,1177,0,0,0,0,0,0,-1,0,0,0,-1,73830,13504,-2.55,-3.03,-1,-3.22,-1,-86.73,-97.34,-1,-127.26,-1,44786491.0,24.11,36.18,28.45,9.41,0.26,-1,1120,2443,315,1606,0,0,0,1090,0,0,0,0,0,0,0,4,219,245,16,166,595,0,761,111.11111111111111,9,8,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4

diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 715b1c8..8892364 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h6m12s,-1,0.5837484433374844,10.2784,0.2918742216687422,-1,500.51,3,0,0,0,0,0,0,-1,0,0,-1,-1,605051,2144,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,0.93,1.45,0.12,0.06,-1,60,843,60,843,0,0,0,3,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h18m16s,-1,2.1404109589041096,10.2784,1.0702054794520548,-1,512.0,11,0,0,0,0,0,0,-1,0,0,-1,-1,996902,6096,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.05,2.28,2.21,0.08,0.13,-1,148,1674,148,1674,0,0,0,11,0,0,0,0,0,0,0,4,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0

diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index d977764..f682046 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h7m51s,-1,50283.33333333334,0.12,25141.66666666667,28.0,605.29,3017,0,0,0,0,0,0,0,3,0,0,-1,163509,26410,0.0,-0.32,-1,0.0,-1,0.0,-9.1,-1,0.0,-1,104829193.0,4.06,36.24,25.62,6.37,1.56,-1,1353,3716,627,2954,0,0,0,1466,0,0,0,0,0,0,0,4,710,926,12,204,1560,0,1764,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h5m32s,-1,45300.0,0.12,22650.0,26.77,606.54,2718,0,0,0,0,0,0,0,3,0,0,-1,167703,26005,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,123482009.0,4.87,36.56,26.85,6.78,0.27,-1,1165,3352,658,2843,0,0,0,1301,0,0,0,0,0,0,0,4,709,844,13,204,1560,0,1764,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4

diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION
new file mode 100644
index 0000000..80c7664
--- /dev/null
+++ b/signoff/wb_interconnect/OPENLANE_VERSION

@@ -0,0 +1 @@
+openlane N/A

diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES
new file mode 100644
index 0000000..ca3684a
--- /dev/null
+++ b/signoff/wb_interconnect/PDK_SOURCES

@@ -0,0 +1,6 @@
+-ne openlane 
+8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b
+-ne skywater-pdk 
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+-ne open_pdks 
+14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad

diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
new file mode 100644
index 0000000..21d6546
--- /dev/null
+++ b/signoff/wb_interconnect/final_summary_report.csv

@@ -0,0 +1,2 @@
+,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h5m39s,-1,5824.242424242424,0.33,2912.121212121212,2.63,613.77,961,0,-1,-1,-1,-1,0,0,1,0,-1,-1,352615,12599,-1.97,0.0,-1,-0.83,-1,-1.97,0.0,-1,-0.83,-1,306869576.0,20.31,9.0,35.51,0.38,10.03,-1,475,2106,155,1786,0,0,0,703,0,0,0,0,0,0,0,4,239,323,8,1600,4010,0,5610,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.5,0.0,sky130_fd_sc_hd,4,4

diff --git a/spi/lvs/glbl_cfg.spice.gz b/spi/lvs/glbl_cfg.spice.gz
new file mode 100644
index 0000000..105ac20
--- /dev/null
+++ b/spi/lvs/glbl_cfg.spice.gz
Binary files differ

diff --git a/spi/lvs/mbist.spice.gz b/spi/lvs/mbist.spice.gz
deleted file mode 100644
index 863665f..0000000
--- a/spi/lvs/mbist.spice.gz
+++ /dev/null
Binary files differ

diff --git a/spi/lvs/mbist1.spice.gz b/spi/lvs/mbist1.spice.gz
new file mode 100644
index 0000000..c4c00dc
--- /dev/null
+++ b/spi/lvs/mbist1.spice.gz
Binary files differ

diff --git a/spi/lvs/mbist2.spice.gz b/spi/lvs/mbist2.spice.gz
new file mode 100644
index 0000000..1133548
--- /dev/null
+++ b/spi/lvs/mbist2.spice.gz
Binary files differ

diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz
index 72b769d..4841e2b 100644
--- a/spi/lvs/user_project_wrapper.spice.gz
+++ b/spi/lvs/user_project_wrapper.spice.gz
Binary files differ

diff --git a/spi/lvs/wb_host.spice.gz b/spi/lvs/wb_host.spice.gz
index a302828..24c9693 100644
--- a/spi/lvs/wb_host.spice.gz
+++ b/spi/lvs/wb_host.spice.gz
Binary files differ

diff --git a/spi/lvs/wb_interconnect.spice.gz b/spi/lvs/wb_interconnect.spice.gz
new file mode 100644
index 0000000..422f32a
--- /dev/null
+++ b/spi/lvs/wb_interconnect.spice.gz
Binary files differ

diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 02cad66..e249499 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v

@@ -174,44 +174,53 @@
    fork
       begin
 	  // Default Value Check
-	  // assign cfg_glb_ctrl         = reg_1[7:0];
-          // assign cfg_bist_clk_ctrl    = reg_1[11:8];
-          // assign cfg_mem_clk_ctrl     = reg_1[15:12];
-          // assign cfg_bank_sel         = reg_1[23:16];
-	  $display("Step-1, BIST CLK: CLOCK1, MEM CLK: CLOCK1 ");
+	  // assign cfg_glb_ctrl         = reg_0[7:0];
+          // assign cfg_wb_clk_ctrl      = reg_0[11:8];
+
+	  $display("Step-1, WBS CLK: CLOCK1");
 	  test_step = 1;
-          wb_user_core_write('h3080_0004,{16'h0,4'h0,4'h0,8'h00});
-	  clock_monitor(CLK1_PERIOD,CLK1_PERIOD);
+          wb_user_core_write('h3080_0000,{20'h0,4'h0,8'h00});
+	  clock_monitor(CLK1_PERIOD);
 
-	  $display("Step-2, BIST CLK: CLOCK2, MEM CLK: CLOCK2 ");
+	  $display("Step-2, WBS CLK: CLOCK1/2");
 	  test_step = 2;
-          wb_user_core_write('h3080_0004,{16'h0,4'h8,4'h8,8'h00});
-	  clock_monitor(CLK2_PERIOD,CLK2_PERIOD);
+          wb_user_core_write('h3080_0000,{20'h0,4'h8,8'h00});
+	  clock_monitor(2*CLK1_PERIOD);
 
-	  $display("Step-3, BIST CLK: CLOCK1/2, MEM CLK: CLOCK1/2");
+	  $display("Step-3, WBS CLK: CLOCK1/(2+1)");
 	  test_step = 3;
-          wb_user_core_write('h3080_0004,{16'h0,4'h4,4'h4,8'h00});
-	  clock_monitor(2*CLK1_PERIOD,2*CLK1_PERIOD);
+          wb_user_core_write('h3080_0000,{20'h0,4'h9,8'h00});
+	  clock_monitor(3*CLK1_PERIOD);
 
-	  $display("Step-4, BIST CLK: CLOCK1/(2+1), MEM CLK: CLOCK1/(2+1)");
+	  $display("Step-4, WBS CLK: CLOCK1/(2+2)");
 	  test_step = 4;
-          wb_user_core_write('h3080_0004,{16'h0,4'h5,4'h5,8'h00});
-	  clock_monitor(3*CLK1_PERIOD,3*CLK1_PERIOD);
+          wb_user_core_write('h3080_0000,{20'h0,4'hA,8'h00});
+	  clock_monitor(4*CLK1_PERIOD);
 
-	  $display("Step-5, BIST CLK: CLOCK1/(2+2), MEM CLK: CLOCK1/(2+2)");
+	  $display("Step-5, WBS CLK: CLOCK1/(2+3)");
 	  test_step = 5;
-          wb_user_core_write('h3080_0004,{16'h0,4'h6,4'h6,8'h00});
-	  clock_monitor(4*CLK1_PERIOD,4*CLK1_PERIOD);
+          wb_user_core_write('h3080_0000,{20'h0,4'hB,8'h00});
+	  clock_monitor(5*CLK1_PERIOD);
 
-	  $display("Step-6, BIST CLK: CLOCK1/(2+3), MEM CLK: CLOCK1/(2+3)");
+	  $display("Step-6, WBS CLK: CLOCK1/(2+4)");
 	  test_step = 6;
-          wb_user_core_write('h3080_0004,{16'h0,4'h7,4'h7,8'h00});
-	  clock_monitor(5*CLK1_PERIOD,5*CLK1_PERIOD);
+          wb_user_core_write('h3080_0000,{20'h0,4'hC,8'h00});
+	  clock_monitor(6*CLK1_PERIOD);
 
-	  $display("Step-7, BIST CLK: CLOCK2/(2+3), MEM CLK: CLOCK2/(2+3)");
+	  $display("Step-7, WBS CLK: CLOCK2/(2+5)");
 	  test_step = 6;
-          wb_user_core_write('h3080_0004,{16'h0,4'hF,4'hF,8'h00});
-	  clock_monitor(5*CLK2_PERIOD,5*CLK2_PERIOD);
+          wb_user_core_write('h3080_0000,{20'h0,4'hD,8'h00});
+	  clock_monitor(7*CLK1_PERIOD);
+
+	  $display("Step-8, WBS CLK: CLOCK2/(2+6)");
+	  test_step = 8;
+          wb_user_core_write('h3080_0000,{20'h0,4'hE,8'h00});
+	  clock_monitor(8*CLK1_PERIOD);
+
+	  $display("Step-9, WBS CLK: CLOCK2/(2+7)");
+	  test_step = 9;
+          wb_user_core_write('h3080_0000,{20'h0,4'hF,8'h00});
+	  clock_monitor(9*CLK1_PERIOD);
       end
    
       begin
@@ -296,70 +305,20 @@
 	force u_top.u_wb_host.u_buf_bist_rst.VGND =VSS;
 	force u_top.u_wb_host.u_buf_bist_rst.VNB = VSS;
 
-	force u_top.u_wb_host.u_clkbuf_bist.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_bist.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_bist.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_bist.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_mem.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_mem.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_mem.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_mem.VNB = VSS;
-
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-	
-	force u_top.u_wb_host.u_mem_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_mem_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_mem_ref_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_mem_ref_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_mem_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_mem_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_mem_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_mem_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_a_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_a_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_a_sel.u_mux.VGND =VSS;
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_a_sel.u_mux.VNB = VSS;
-	
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_b_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_b_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_b_sel.u_mux.VGND =VSS;
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_b_sel.u_mux.VNB = VSS;
-
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_a.VPWR =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_a.VPB  =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_a.VGND =VSS;
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_a.VNB = VSS;
-
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_b.VPWR =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_b.VPB  =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_b.VGND =VSS;
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_b.VNB = VSS;
+	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
+	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
 
     end
 `endif    
 
 
 task clock_monitor;
-input [15:0] exp_bist_period;
-input [15:0] exp_mem_period;
+input [15:0] exp_wbs_period;
 begin
-   force clock_mon = u_top.u_wb_host.bist_clk;
-   check_clock_period("BIST CLock",exp_bist_period);
-   release clock_mon;
-
-   force clock_mon = u_top.u_wb_host.mem_clk;
-   check_clock_period("MEM Clock",exp_mem_period);
+   force clock_mon = u_top.u_wb_host.wbs_clk_out;
+   check_clock_period("WBS Clock",exp_wbs_period);
    release clock_mon;
 
 end

diff --git a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
index 5e9914e..afe05e8 100644
--- a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
+++ b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v

@@ -108,7 +108,7 @@
 
 		test_fail = 0;
 		// Remove Wb Reset
-		wb_user_core_write('h3080_0004,'h1);
+		wb_user_core_write('h3080_0000,'h1);
 
 	    	$display("###################################################");
 	    	$display(" MBIST Test with Without Address Failure");
@@ -118,8 +118,9 @@
 		// [0]   - Bist Done      - 1
 		// [1]   - Bist Error     - 0
 		// [2]   - Bist Correct   - 0
-		// [6:3] - Bist Error Cnt - 4'h0
-		insert_fault(0,0,7'h1);
+		// [3]   - Reserved       - 0
+		// [7:4] - Bist Error Cnt - 4'h0
+		insert_fault(0,0,32'h01010101);
 
           	if(test_fail == 0) begin
 	    	    $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Passed");
@@ -129,15 +130,16 @@
 	    	$display("###################################################");
 	    	$display(" MBIST Test with Single Address Failure");
 	    	$display("###################################################");
-                $dumpon;
+                $dumpoff;
 		   // Check Is there is any BIST Error
 		   // [0]   - Bist Done      - 1
 		   // [1]   - Bist Error     - 0
 		   // [2]   - Bist Correct   - 1
-		   // [6:3] - Bist Error Cnt - 4'h1
+		   // [3]   - Reserved       - 0
+		   // [7:4] - Bist Error Cnt - 4'h1
 		   //if(read_data[6:0]  != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1
 		faultaddr[0] = 9'h10;
-		insert_fault(1,1,7'hD);
+		insert_fault(1,1,32'h15151515);
 
           	if(test_fail == 0) begin
 	    	    $display("Monitor: Step-2: BIST Test with One Memory Error insertion test Passed");
@@ -153,11 +155,12 @@
 		// [0]   - Bist Done      - 1
 		// [1]   - Bist Error     - 0
 		// [2]   - Bist Correct   - 1
-		// [6:3] - Bist Error Cnt - 4'h2
+		// [3]   - Reserved       - 0
+		// [7:4] - Bist Error Cnt - 4'h2
 		//if(read_data[6:0]  != 7'b0010101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x2
 		faultaddr[0] = 9'h10;
 		faultaddr[1] = 9'h20;
-		insert_fault(2,0,7'h15);
+		insert_fault(2,0,32'h25252525);
 
           	if(test_fail == 0) begin
 	    	    $display("Monitor: Step-3: BIST Test with Two Memory Error insertion test Passed");
@@ -168,16 +171,17 @@
 	    	$display(" MBIST Test with Three Address Failure");
 	    	$display("###################################################");
 
-		   // Check Is there is any BIST Error
-		   // [0]   - Bist Done      - 1
-		   // [1]   - Bist Error     - 0
-		   // [2]   - Bist Correct   - 1
-		   // [6:3] - Bist Error Cnt - 4'h3
-		   //if(read_data[6:0]  != 7'b0011101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x3
+		// Check Is there is any BIST Error
+		// [0]   - Bist Done      - 1
+		// [1]   - Bist Error     - 0
+		// [2]   - Bist Correct   - 1
+		// [3]   - Reserved       - 0
+		// [7:4] - Bist Error Cnt - 4'h3
+		//if(read_data[6:0]  != 7'b0011101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x3
 		faultaddr[0] = 9'h10;
 		faultaddr[1] = 9'h20;
 		faultaddr[2] = 9'h30;
-		insert_fault(3,1,7'h1D);
+		insert_fault(3,1,32'h35353535);
 
           	if(test_fail == 0) begin
 	    	    $display("Monitor: Step-4: BIST Test with Three Memory Error insertion test Passed");
@@ -188,17 +192,18 @@
 	    	$display("###################################################");
 	    	$display(" MBIST Test with Fours Address Failure");
 	    	$display("###################################################");
-		   // Check Is there is any BIST Error
-		   // [0]   - Bist Done      - 1
-		   // [1]   - Bist Error     - 0
-		   // [2]   - Bist Correct   - 1
-		   // [6:3] - Bist Error Cnt - 4'h4
-		   //if(read_data[6:0]  != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4
+		// Check Is there is any BIST Error
+		// [0]   - Bist Done      - 1
+		// [1]   - Bist Error     - 0
+		// [2]   - Bist Correct   - 1
+		// [3]   - Reserved       - 0
+		// [7:4] - Bist Error Cnt - 4'h4
+		//if(read_data[6:0]  != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4
 		faultaddr[0] = 9'h10;
 		faultaddr[1] = 9'h20;
 		faultaddr[2] = 9'h30;
 		faultaddr[3] = 9'h40;
-		insert_fault(4,0,7'h25);
+		insert_fault(4,0,32'h45454545);
 
           	if(test_fail == 0) begin
 	    	    $display("Monitor: Step-5: BIST Test with Four Memory Error insertion test Passed");
@@ -206,20 +211,22 @@
 	    	    $display("Monitor: Step-5: BIST Test with Four Memory Error insertion test Failed");
 		end
 
+		$dumpon;
 	    	$display("###################################################");
 	    	$display(" MBIST Test with Fours Address(Continous Starting Addrsess) Failure");
 	    	$display("###################################################");
-		   // Check Is there is any BIST Error
-		   // [0]   - Bist Done      - 1
-		   // [1]   - Bist Error     - 0
-		   // [2]   - Bist Correct   - 1
-		   // [6:3] - Bist Error Cnt - 4'h4
-		   //if(read_data[6:0]  != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4
+		// Check Is there is any BIST Error
+		// [0]   - Bist Done      - 1
+		// [1]   - Bist Error     - 0
+		// [2]   - Bist Correct   - 1
+		// [3]   - Reserved       - 0
+		// [7:4] - Bist Error Cnt - 4'h4
+		//if(read_data[6:0]  != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4
 		faultaddr[0] = 9'h0;
 		faultaddr[1] = 9'h1;
 		faultaddr[2] = 9'h2;
 		faultaddr[3] = 9'h3;
-		insert_fault(4,0,7'h25);
+		insert_fault(4,0,32'h45454545);
 
           	if(test_fail == 0) begin
 	    	    $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Passed");
@@ -230,17 +237,18 @@
 	    	$display("###################################################");
 	    	$display(" MBIST Test with Fours Address(Last Addrsess) Failure");
 	    	$display("###################################################");
-		   // Check Is there is any BIST Error
-		   // [0]   - Bist Done      - 1
-		   // [1]   - Bist Error     - 0
-		   // [2]   - Bist Correct   - 1
-		   // [6:3] - Bist Error Cnt - 4'h4
-		   //if(read_data[6:0]  != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4
-		faultaddr[0] = 9'h1F8;
-		faultaddr[1] = 9'h1F9;
-		faultaddr[2] = 9'h1FA;
-		faultaddr[3] = 9'h1FB;
-		insert_fault(4,0,7'h25);
+		// Check Is there is any BIST Error
+		// [0]   - Bist Done      - 1
+		// [1]   - Bist Error     - 0
+		// [2]   - Bist Correct   - 1
+		// [3]   - Reserved       - 0
+		// [7:4] - Bist Error Cnt - 4'h4
+		//if(read_data[6:0]  != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4
+		faultaddr[0] = 9'hF8;
+		faultaddr[1] = 9'hF9;
+		faultaddr[2] = 9'hFA;
+		faultaddr[3] = 9'hFB;
+		insert_fault(4,0,32'h45454545);
 
           	if(test_fail == 0) begin
 	    	    $display("Monitor: Step-5.3: BIST Test with Four Memory Error insertion test Passed");
@@ -250,18 +258,19 @@
 	    	$display("###################################################");
 	    	$display(" MBIST Test with Five Address Failure");
 	    	$display("###################################################");
-		   // Check Is there is any BIST Error
-		   // [0]   - Bist Done      - 1
-		   // [1]   - Bist Error     - 1
-		   // [2]   - Bist Correct   - 1
-		   // [6:3] - Bist Error Cnt - 4'h4
-		   //if(read_data[6:0]  != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4
+		// Check Is there is any BIST Error
+		// [0]   - Bist Done      - 1
+		// [1]   - Bist Error     - 1
+		// [2]   - Bist Correct   - 1
+		// [3]   - Reserved       - 0
+		// [7:4] - Bist Error Cnt - 4'h4
+		//if(read_data[6:0]  != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4
 		faultaddr[0] = 9'h10;
 		faultaddr[1] = 9'h20;
 		faultaddr[2] = 9'h30;
 		faultaddr[3] = 9'h40;
 		faultaddr[4] = 9'h50;
-		insert_fault(5,1,7'h27);
+		insert_fault(5,1,32'h47474747);
 
           	if(test_fail == 0) begin
 	    	    $display("Monitor: Step-5: BIST Test with Five Memory Error insertion test Passed");
@@ -274,25 +283,54 @@
 	    	$display("###################################################");
 		$dumpon;
 		// Remove the Bist Enable and Bist Run
-                wb_user_core_write('h3080_0008,'h000);
+                wb_user_core_write('h3000_0008,'h000);
   
 	        // Fill Random Data	
 		for (i=0; i< 9'h1FC; i=i+1) begin
    	            writemem[i] = $random;
-                    wb_user_core_write('h3000_0000+(i*4),writemem[i]);
+                    wb_user_core_write('h3000_1000+(i*4),writemem[i]);
+                    wb_user_core_write('h3000_2000+(i*4),writemem[i]);
+		    if(i < 9'h0FC) begin // SRAM3/SRAM4 are 1KB
+                       wb_user_core_write('h3000_3000+(i*4),writemem[i]);
+                       wb_user_core_write('h3000_4000+(i*4),writemem[i]);
+	            end
 		end
 		for (i=0; i< 9'h1FC; i=i+1) begin
-                    wb_user_core_read_check('h3000_0000+(i*4),read_data,writemem[i],32'hFFFFFFFF);
+                    wb_user_core_read_check('h3000_1000+(i*4),read_data,writemem[i],32'hFFFFFFFF);
+                    wb_user_core_read_check('h3000_2000+(i*4),read_data,writemem[i],32'hFFFFFFFF);
+		    if(i < 9'h0FC) begin // SRAM3/SRAM4 are 1KB
+                       wb_user_core_read_check('h3000_3000+(i*4),read_data,writemem[i],32'hFFFFFFFF);
+                       wb_user_core_read_check('h3000_4000+(i*4),read_data,writemem[i],32'hFFFFFFFF);
+	            end
 		end
 
 		// Cross-check Reducency address hold the failure address data
 		// Is last Error inserted address are 0x10,0x20,0x30,0x40
 		// So Address 0x1FC = Data[0x10], 0x1FD = Data[0x20]
 		//    Address 0x1FE = Data[0x30], 0x1FF = Data[0x40]
-                wb_user_core_read_check('h3000_0000 + (9'h1FC *4),read_data,writemem[9'h10],32'hFFFFFFFF);
-                wb_user_core_read_check('h3000_0000 + (9'h1FD *4),read_data,writemem[9'h20],32'hFFFFFFFF);
-                wb_user_core_read_check('h3000_0000 + (9'h1FE *4),read_data,writemem[9'h30],32'hFFFFFFFF);
-                wb_user_core_read_check('h3000_0000 + (9'h1FF *4),read_data,writemem[9'h40],32'hFFFFFFFF);
+		// Check 2kb SRAM1
+                wb_user_core_read_check('h3000_1000 + (9'h1FC *4),read_data,writemem[9'h10],32'hFFFFFFFF);
+                wb_user_core_read_check('h3000_1000 + (9'h1FD *4),read_data,writemem[9'h20],32'hFFFFFFFF);
+                wb_user_core_read_check('h3000_1000 + (9'h1FE *4),read_data,writemem[9'h30],32'hFFFFFFFF);
+                wb_user_core_read_check('h3000_1000 + (9'h1FF *4),read_data,writemem[9'h40],32'hFFFFFFFF);
+
+		// Check 2kb SRAM2
+                wb_user_core_read_check('h3000_2000 + (9'h1FC *4),read_data,writemem[9'h11],32'hFFFFFFFF);
+                wb_user_core_read_check('h3000_2000 + (9'h1FD *4),read_data,writemem[9'h21],32'hFFFFFFFF);
+                wb_user_core_read_check('h3000_2000 + (9'h1FE *4),read_data,writemem[9'h31],32'hFFFFFFFF);
+                wb_user_core_read_check('h3000_2000 + (9'h1FF *4),read_data,writemem[9'h41],32'hFFFFFFFF);
+
+		// Check 1kb SRAM3
+                wb_user_core_read_check('h3000_3000 + (8'hFC *4),read_data,writemem[9'h12],32'hFFFFFFFF);
+                wb_user_core_read_check('h3000_3000 + (8'hFD *4),read_data,writemem[9'h22],32'hFFFFFFFF);
+                wb_user_core_read_check('h3000_3000 + (8'hFE *4),read_data,writemem[9'h32],32'hFFFFFFFF);
+                wb_user_core_read_check('h3000_3000 + (8'hFF *4),read_data,writemem[9'h42],32'hFFFFFFFF);
+
+		// Check 1kb SRAM4
+                wb_user_core_read_check('h3000_4000 + (8'hFC *4),read_data,writemem[9'h13],32'hFFFFFFFF);
+                wb_user_core_read_check('h3000_4000 + (8'hFD *4),read_data,writemem[9'h23],32'hFFFFFFFF);
+                wb_user_core_read_check('h3000_4000 + (8'hFE *4),read_data,writemem[9'h33],32'hFFFFFFFF);
+                wb_user_core_read_check('h3000_4000 + (8'hFF *4),read_data,writemem[9'h43],32'hFFFFFFFF);
 
           	if(test_fail == 0) begin
 	    	    $display("Monitor: Step-5: BIST Test with Functional access test Passed");
@@ -346,7 +384,6 @@
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
-
 	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
 	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
 	force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
@@ -357,55 +394,95 @@
 	force u_top.u_wb_host.u_buf_bist_rst.VGND =VSS;
 	force u_top.u_wb_host.u_buf_bist_rst.VNB = VSS;
 
-	force u_top.u_wb_host.u_clkbuf_bist.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_bist.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_bist.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_bist.VNB = VSS;
+	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
+	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
 
-	force u_top.u_wb_host.u_clkbuf_mem.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_mem.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_mem.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_mem.VNB = VSS;
+	// MBIST1
+	force u_top.u_mbist1.u_mem_sel.u_mem_clk_a_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_mbist1.u_mem_sel.u_mem_clk_a_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_mbist1.u_mem_sel.u_mem_clk_a_sel.u_mux.VGND =VSS;
+	force u_top.u_mbist1.u_mem_sel.u_mem_clk_a_sel.u_mux.VNB = VSS;
 
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
+	force u_top.u_mbist1.u_mem_sel.u_mem_clk_b_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_mbist1.u_mem_sel.u_mem_clk_b_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_mbist1.u_mem_sel.u_mem_clk_b_sel.u_mux.VGND =VSS;
+	force u_top.u_mbist1.u_mem_sel.u_mem_clk_b_sel.u_mux.VNB = VSS;
 
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-	
-	force u_top.u_wb_host.u_mem_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_mem_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_mem_ref_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_mem_ref_sel.u_mux.VNB = VSS;
+	force u_top.u_mbist1.u_mem_sel.u_cts_mem_clk_a.VPWR =USER_VDD1V8;
+	force u_top.u_mbist1.u_mem_sel.u_cts_mem_clk_a.VPB  =USER_VDD1V8;
+	force u_top.u_mbist1.u_mem_sel.u_cts_mem_clk_a.VGND =VSS;
+	force u_top.u_mbist1.u_mem_sel.u_cts_mem_clk_a.VNB = VSS;
 
-	force u_top.u_wb_host.u_mem_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_mem_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_mem_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_mem_clk_sel.u_mux.VNB = VSS;
+	force u_top.u_mbist1.u_mem_sel.u_cts_mem_clk_b.VPWR =USER_VDD1V8;
+	force u_top.u_mbist1.u_mem_sel.u_cts_mem_clk_b.VPB  =USER_VDD1V8;
+	force u_top.u_mbist1.u_mem_sel.u_cts_mem_clk_b.VGND =VSS;
+	force u_top.u_mbist1.u_mem_sel.u_cts_mem_clk_b.VNB = VSS;
 
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_a_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_a_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_a_sel.u_mux.VGND =VSS;
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_a_sel.u_mux.VNB = VSS;
-	
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_b_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_b_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_b_sel.u_mux.VGND =VSS;
-	force u_top.u_mbist.u_mem_sel.u_mem_clk_b_sel.u_mux.VNB = VSS;
+	// MBIST2
+	force u_top.u_mbist2.u_mem_sel.u_mem_clk_a_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_mbist2.u_mem_sel.u_mem_clk_a_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_mbist2.u_mem_sel.u_mem_clk_a_sel.u_mux.VGND =VSS;
+	force u_top.u_mbist2.u_mem_sel.u_mem_clk_a_sel.u_mux.VNB = VSS;
 
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_a.VPWR =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_a.VPB  =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_a.VGND =VSS;
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_a.VNB = VSS;
+	force u_top.u_mbist2.u_mem_sel.u_mem_clk_b_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_mbist2.u_mem_sel.u_mem_clk_b_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_mbist2.u_mem_sel.u_mem_clk_b_sel.u_mux.VGND =VSS;
+	force u_top.u_mbist2.u_mem_sel.u_mem_clk_b_sel.u_mux.VNB = VSS;
 
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_b.VPWR =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_b.VPB  =USER_VDD1V8;
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_b.VGND =VSS;
-	force u_top.u_mbist.u_mem_sel.u_cts_mem_clk_b.VNB = VSS;
+	force u_top.u_mbist2.u_mem_sel.u_cts_mem_clk_a.VPWR =USER_VDD1V8;
+	force u_top.u_mbist2.u_mem_sel.u_cts_mem_clk_a.VPB  =USER_VDD1V8;
+	force u_top.u_mbist2.u_mem_sel.u_cts_mem_clk_a.VGND =VSS;
+	force u_top.u_mbist2.u_mem_sel.u_cts_mem_clk_a.VNB = VSS;
+
+	force u_top.u_mbist2.u_mem_sel.u_cts_mem_clk_b.VPWR =USER_VDD1V8;
+	force u_top.u_mbist2.u_mem_sel.u_cts_mem_clk_b.VPB  =USER_VDD1V8;
+	force u_top.u_mbist2.u_mem_sel.u_cts_mem_clk_b.VGND =VSS;
+	force u_top.u_mbist2.u_mem_sel.u_cts_mem_clk_b.VNB = VSS;
+
+	// MBIST3
+	force u_top.u_mbist3.u_mem_sel.u_mem_clk_a_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_mbist3.u_mem_sel.u_mem_clk_a_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_mbist3.u_mem_sel.u_mem_clk_a_sel.u_mux.VGND =VSS;
+	force u_top.u_mbist3.u_mem_sel.u_mem_clk_a_sel.u_mux.VNB = VSS;
+
+	force u_top.u_mbist3.u_mem_sel.u_mem_clk_b_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_mbist3.u_mem_sel.u_mem_clk_b_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_mbist3.u_mem_sel.u_mem_clk_b_sel.u_mux.VGND =VSS;
+	force u_top.u_mbist3.u_mem_sel.u_mem_clk_b_sel.u_mux.VNB = VSS;
+
+	force u_top.u_mbist3.u_mem_sel.u_cts_mem_clk_a.VPWR =USER_VDD1V8;
+	force u_top.u_mbist3.u_mem_sel.u_cts_mem_clk_a.VPB  =USER_VDD1V8;
+	force u_top.u_mbist3.u_mem_sel.u_cts_mem_clk_a.VGND =VSS;
+	force u_top.u_mbist3.u_mem_sel.u_cts_mem_clk_a.VNB = VSS;
+
+	force u_top.u_mbist3.u_mem_sel.u_cts_mem_clk_b.VPWR =USER_VDD1V8;
+	force u_top.u_mbist3.u_mem_sel.u_cts_mem_clk_b.VPB  =USER_VDD1V8;
+	force u_top.u_mbist3.u_mem_sel.u_cts_mem_clk_b.VGND =VSS;
+	force u_top.u_mbist3.u_mem_sel.u_cts_mem_clk_b.VNB = VSS;
+
+	// MBIST4
+	force u_top.u_mbist4.u_mem_sel.u_mem_clk_a_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_mbist4.u_mem_sel.u_mem_clk_a_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_mbist4.u_mem_sel.u_mem_clk_a_sel.u_mux.VGND =VSS;
+	force u_top.u_mbist4.u_mem_sel.u_mem_clk_a_sel.u_mux.VNB = VSS;
+
+	force u_top.u_mbist4.u_mem_sel.u_mem_clk_b_sel.u_mux.VPWR =USER_VDD1V8;
+	force u_top.u_mbist4.u_mem_sel.u_mem_clk_b_sel.u_mux.VPB  =USER_VDD1V8;
+	force u_top.u_mbist4.u_mem_sel.u_mem_clk_b_sel.u_mux.VGND =VSS;
+	force u_top.u_mbist4.u_mem_sel.u_mem_clk_b_sel.u_mux.VNB = VSS;
+
+	force u_top.u_mbist4.u_mem_sel.u_cts_mem_clk_a.VPWR =USER_VDD1V8;
+	force u_top.u_mbist4.u_mem_sel.u_cts_mem_clk_a.VPB  =USER_VDD1V8;
+	force u_top.u_mbist4.u_mem_sel.u_cts_mem_clk_a.VGND =VSS;
+	force u_top.u_mbist4.u_mem_sel.u_cts_mem_clk_a.VNB = VSS;
+
+	force u_top.u_mbist4.u_mem_sel.u_cts_mem_clk_b.VPWR =USER_VDD1V8;
+	force u_top.u_mbist4.u_mem_sel.u_cts_mem_clk_b.VPB  =USER_VDD1V8;
+	force u_top.u_mbist4.u_mem_sel.u_cts_mem_clk_b.VGND =VSS;
+	force u_top.u_mbist4.u_mem_sel.u_cts_mem_clk_b.VNB = VSS;
+
     end
 `endif    
 
@@ -417,55 +494,110 @@
 task insert_fault;
 input [3:0]  num_fault;
 input        fault_type; // 0 -> struck at 0 and 1 -> struck at 1
-input [6:0]  mbist_signature;
+input [31:0]  mbist_signature;
 reg [31:0] datain;
 integer j;
 begin
    repeat (2) @(posedge clock);
    // Remove the Bist Enable and Bist Run
-   wb_user_core_write('h3080_0008,'h000);
-   // Apply WB and BIST RESET
-   wb_user_core_write('h3080_0004,'h000);
-   // Set the Bist Enable and Bist Run
-   wb_user_core_write('h3080_0008,'h003);
+   wb_user_core_write('h3000_0008,'h000);
    // Remove WB and BIST RESET
-   wb_user_core_write('h3080_0004,'h003);
+   wb_user_core_write('h3080_0000,'h001);
+   // Set the Bist Enable and Bist Run
+   wb_user_core_write('h3000_0008,'h3333);
+   // Remove WB and BIST RESET
+   wb_user_core_write('h3080_0000,'h003);
    fork
    begin
       // Check for MBIST Done
       read_data = 'h0;
       while (read_data[0] != 1'b1) begin
-         wb_user_core_read('h3080_000C,read_data);
+         wb_user_core_read('h3000_000C,read_data);
       end
       // Check Is there is any BIST Error
       // [0]   - Bist Done      
       // [1]   - Bist Error     
       // [2]   - Bist Correct   
-      // [6:3] - Bist Error Cnt 
-      wb_user_core_read_check('h3080_000C,read_data,{25'h0,mbist_signature},32'h7F);
+      // [3]   - Reserved
+      // [7:4] - Bist Error Cnt 
+      wb_user_core_read_check('h3000_000C,read_data,mbist_signature,32'hFFFFFFFF);
    end
    // Insert  Error Insertion
    begin
       while(1) begin
          repeat (1) @(posedge clock);
          #1;
-         if(u_top.u_sram_2kb.web0 == 1'b0 && 
-	   ((num_fault > 0 && u_top.u_sram_2kb.addr0 == faultaddr[0]) ||
-	    (num_fault > 1 && u_top.u_sram_2kb.addr0 == faultaddr[1]) ||
-	    (num_fault > 2 && u_top.u_sram_2kb.addr0 == faultaddr[2]) ||
-	    (num_fault > 3 && u_top.u_sram_2kb.addr0 == faultaddr[3]) ||
-	    (num_fault > 4 && u_top.u_sram_2kb.addr0 == faultaddr[4]) ||
-	    (num_fault > 5 && u_top.u_sram_2kb.addr0 == faultaddr[5]) ||
-	    (num_fault > 6 && u_top.u_sram_2kb.addr0 == faultaddr[6]) ||
-	    (num_fault > 7 && u_top.u_sram_2kb.addr0 == faultaddr[7])))
+         if(u_top.u_sram1_2kb.web0 == 1'b0 && 
+	   ((num_fault > 0 && u_top.u_sram1_2kb.addr0 == faultaddr[0]) ||
+	    (num_fault > 1 && u_top.u_sram1_2kb.addr0 == faultaddr[1]) ||
+	    (num_fault > 2 && u_top.u_sram1_2kb.addr0 == faultaddr[2]) ||
+	    (num_fault > 3 && u_top.u_sram1_2kb.addr0 == faultaddr[3]) ||
+	    (num_fault > 4 && u_top.u_sram1_2kb.addr0 == faultaddr[4]) ||
+	    (num_fault > 5 && u_top.u_sram1_2kb.addr0 == faultaddr[5]) ||
+	    (num_fault > 6 && u_top.u_sram1_2kb.addr0 == faultaddr[6]) ||
+	    (num_fault > 7 && u_top.u_sram1_2kb.addr0 == faultaddr[7])))
              begin
 	   if(fault_type == 0) // Struck at 0
-	      force u_top.u_sram_2kb.din0 = u_top.mem_din_b  & 32'hFFFF_FFFE;
+	      force u_top.u_sram1_2kb.din0 = u_top.mem1_din_b  & 32'hFFFF_FFFE;
 	   else
-	      force u_top.u_sram_2kb.din0 = u_top.mem_din_b | 32'h1;
+	      force u_top.u_sram1_2kb.din0 = u_top.mem1_din_b | 32'h1;
    	   -> error_insert;
          end else begin
-            release u_top.u_sram_2kb.din0;
+            release u_top.u_sram1_2kb.din0;
+         end
+         if(u_top.u_sram2_2kb.web0 == 1'b0 && 
+	   ((num_fault > 0 && u_top.u_sram2_2kb.addr0 == faultaddr[0]+1) ||
+	    (num_fault > 1 && u_top.u_sram2_2kb.addr0 == faultaddr[1]+1) ||
+	    (num_fault > 2 && u_top.u_sram2_2kb.addr0 == faultaddr[2]+1) ||
+	    (num_fault > 3 && u_top.u_sram2_2kb.addr0 == faultaddr[3]+1) ||
+	    (num_fault > 4 && u_top.u_sram2_2kb.addr0 == faultaddr[4]+1) ||
+	    (num_fault > 5 && u_top.u_sram2_2kb.addr0 == faultaddr[5]+1) ||
+	    (num_fault > 6 && u_top.u_sram2_2kb.addr0 == faultaddr[6]+1) ||
+	    (num_fault > 7 && u_top.u_sram2_2kb.addr0 == faultaddr[7]+1)))
+             begin
+	   if(fault_type == 0) // Struck at 0
+	      force u_top.u_sram2_2kb.din0 = u_top.mem2_din_b  & 32'hFFFF_FFFE;
+	   else
+	      force u_top.u_sram2_2kb.din0 = u_top.mem2_din_b | 32'h1;
+   	   -> error_insert;
+         end else begin
+            release u_top.u_sram2_2kb.din0;
+         end
+         if(u_top.u_sram3_1kb.web0 == 1'b0 && 
+	   ((num_fault > 0 && u_top.u_sram3_1kb.addr0 == faultaddr[0]+2) ||
+	    (num_fault > 1 && u_top.u_sram3_1kb.addr0 == faultaddr[1]+2) ||
+	    (num_fault > 2 && u_top.u_sram3_1kb.addr0 == faultaddr[2]+2) ||
+	    (num_fault > 3 && u_top.u_sram3_1kb.addr0 == faultaddr[3]+2) ||
+	    (num_fault > 4 && u_top.u_sram3_1kb.addr0 == faultaddr[4]+2) ||
+	    (num_fault > 5 && u_top.u_sram3_1kb.addr0 == faultaddr[5]+2) ||
+	    (num_fault > 6 && u_top.u_sram3_1kb.addr0 == faultaddr[6]+2) ||
+	    (num_fault > 7 && u_top.u_sram3_1kb.addr0 == faultaddr[7]+2)))
+             begin
+	   if(fault_type == 0) // Struck at 0
+	      force u_top.u_sram3_1kb.din0 = u_top.mem3_din_b  & 32'hFFFF_FFFE;
+	   else
+	      force u_top.u_sram3_1kb.din0 = u_top.mem3_din_b | 32'h1;
+   	   -> error_insert;
+         end else begin
+            release u_top.u_sram3_1kb.din0;
+         end
+         if(u_top.u_sram4_1kb.web0 == 1'b0 && 
+	   ((num_fault > 0 && u_top.u_sram4_1kb.addr0 == faultaddr[0]+3) ||
+	    (num_fault > 1 && u_top.u_sram4_1kb.addr0 == faultaddr[1]+3) ||
+	    (num_fault > 2 && u_top.u_sram4_1kb.addr0 == faultaddr[2]+3) ||
+	    (num_fault > 3 && u_top.u_sram4_1kb.addr0 == faultaddr[3]+3) ||
+	    (num_fault > 4 && u_top.u_sram4_1kb.addr0 == faultaddr[4]+3) ||
+	    (num_fault > 5 && u_top.u_sram4_1kb.addr0 == faultaddr[5]+3) ||
+	    (num_fault > 6 && u_top.u_sram4_1kb.addr0 == faultaddr[6]+3) ||
+	    (num_fault > 7 && u_top.u_sram4_1kb.addr0 == faultaddr[7]+3)))
+             begin
+	   if(fault_type == 0) // Struck at 0
+	      force u_top.u_sram4_1kb.din0 = u_top.mem4_din_b  & 32'hFFFF_FFFE;
+	   else
+	      force u_top.u_sram4_1kb.din0 = u_top.mem4_din_b | 32'h1;
+   	   -> error_insert;
+         end else begin
+            release u_top.u_sram4_1kb.din0;
          end
       end
    end
@@ -479,16 +611,16 @@
    disable fork; //disable pending fork activity
 
    if(num_fault == 1)
-       wb_user_core_read_check('h3080_0014,read_data,{16'h0,7'h0,faultaddr[0]},32'h0000_FFFF);
+       wb_user_core_read_check('h3000_0014,read_data,{16'h0,7'h0,faultaddr[0]},32'h0000_FFFF);
    if(num_fault == 2)
-       wb_user_core_read_check('h3080_0014,read_data,{7'h0,faultaddr[1],7'h0,faultaddr[0]},32'hFFFF_FFFF);
+       wb_user_core_read_check('h3000_0014,read_data,{7'h0,faultaddr[1],7'h0,faultaddr[0]},32'hFFFF_FFFF);
    if(num_fault == 3) begin
-       wb_user_core_read_check('h3080_0014,read_data,{7'h0,faultaddr[1],7'h0,faultaddr[0]},32'hFFFF_FFFF);
-       wb_user_core_read_check('h3080_0014,read_data,{16'h0,7'h0,faultaddr[2]},32'h0000_FFFF);
+       wb_user_core_read_check('h3000_0014,read_data,{7'h0,faultaddr[1],7'h0,faultaddr[0]},32'hFFFF_FFFF);
+       wb_user_core_read_check('h3000_0014,read_data,{16'h0,7'h0,faultaddr[2]},32'h0000_FFFF);
    end
    if(num_fault >= 4) begin
-       wb_user_core_read_check('h3080_0014,read_data,{7'h0,faultaddr[1],7'h0,faultaddr[0]},32'hFFFF_FFFF);
-       wb_user_core_read_check('h3080_0014,read_data,{7'h0,faultaddr[3],7'h0,faultaddr[2]},32'hFFFF_FFFF);
+       wb_user_core_read_check('h3000_0014,read_data,{7'h0,faultaddr[1],7'h0,faultaddr[0]},32'hFFFF_FFFF);
+       wb_user_core_read_check('h3000_0014,read_data,{7'h0,faultaddr[3],7'h0,faultaddr[2]},32'hFFFF_FFFF);
    end
 end
 endtask

diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index eed8da9..3dd3911 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c

@@ -23,6 +23,8 @@
 #define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
 
 #define reg_mprj_wbhost_reg0 (*(volatile uint32_t*)0x30800000)
+#define reg_mprj_glbl_reg0 (*(volatile uint32_t*)0x30000000)
+#define reg_mprj_glbl_reg1 (*(volatile uint32_t*)0x30000004)
 
 void main()
 {
@@ -78,14 +80,19 @@
     // Flag start of the test
 	reg_mprj_datal = 0xAB600000;
 
+    // Remove Wishbone Reset
+    reg_mprj_wbhost_reg0 = 0x1;
 
-    if (reg_mprj_wbhost_reg0 != 0xAABBCCDD) bFail = 1;
+    if (reg_mprj_glbl_reg0 != 0x44332211) bFail = 1;
+    if (reg_mprj_glbl_reg1 != 0xDDCCBBAA) bFail = 1;
 
     // Write software Write & Read Register
-    reg_mprj_wbhost_reg0  = 0x11223344; 
+    reg_mprj_glbl_reg0  = 0x11223344; 
+    reg_mprj_glbl_reg1  = 0x22334455; 
 
 
-    if (reg_mprj_wbhost_reg0  != 0x11223344) bFail = 1;
+    if (reg_mprj_glbl_reg0  != 0x11223344) bFail = 1;
+    if (reg_mprj_glbl_reg1  != 0x22334455) bFail = 1;
 
     if(bFail == 0) {
         reg_mprj_datal = 0xAB610000;

diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index b32f900..c02797d 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v

@@ -153,5 +153,26 @@
 		.io3()			// not used
 	);
 
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+
+	force uut.mprj.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_wb_rst.VGND =VSS;
+	force uut.mprj.u_wb_host.u_buf_wb_rst.VNB = VSS;
+
+	force uut.mprj.u_wb_host.u_buf_bist_rst.VPWR =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_bist_rst.VPB  =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_buf_bist_rst.VGND =VSS;
+	force uut.mprj.u_wb_host.u_buf_bist_rst.VNB = VSS;
+
+	force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VPB  =USER_VDD1V8;
+	force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
+	force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
+
+    end
+`endif    
 endmodule
-`default_nettype wire
\ No newline at end of file
+`default_nettype wire

diff --git a/verilog/gl/glbl_cfg.v b/verilog/gl/glbl_cfg.v
new file mode 100644
index 0000000..d53e9db
--- /dev/null
+++ b/verilog/gl/glbl_cfg.v

@@ -0,0 +1,34823 @@
+module glbl_cfg (mclk,
+    reg_ack,
+    reg_cs,
+    reg_wr,
+    reset_n,
+    vccd1,
+    vssd1,
+    wbd_clk_glbl,
+    wbd_clk_int,
+    bist_correct,
+    bist_done,
+    bist_en,
+    bist_error,
+    bist_error_cnt0,
+    bist_error_cnt1,
+    bist_error_cnt2,
+    bist_error_cnt3,
+    bist_load,
+    bist_run,
+    bist_sdi,
+    bist_sdo,
+    bist_shift,
+    cfg_cska_glbl,
+    reg_addr,
+    reg_be,
+    reg_rdata,
+    reg_wdata);
+ input mclk;
+ output reg_ack;
+ input reg_cs;
+ input reg_wr;
+ input reset_n;
+ input vccd1;
+ input vssd1;
+ output wbd_clk_glbl;
+ input wbd_clk_int;
+ input [3:0] bist_correct;
+ input [3:0] bist_done;
+ output [3:0] bist_en;
+ input [3:0] bist_error;
+ input [3:0] bist_error_cnt0;
+ input [3:0] bist_error_cnt1;
+ input [3:0] bist_error_cnt2;
+ input [3:0] bist_error_cnt3;
+ output [3:0] bist_load;
+ output [3:0] bist_run;
+ output [3:0] bist_sdi;
+ input [3:0] bist_sdo;
+ output [3:0] bist_shift;
+ input [3:0] cfg_cska_glbl;
+ input [7:0] reg_addr;
+ input [3:0] reg_be;
+ output [31:0] reg_rdata;
+ input [31:0] reg_wdata;
+
+ wire _0000_;
+ wire _0001_;
+ wire _0002_;
+ wire _0003_;
+ wire _0004_;
+ wire _0005_;
+ wire _0006_;
+ wire _0007_;
+ wire _0008_;
+ wire _0009_;
+ wire _0010_;
+ wire _0011_;
+ wire _0012_;
+ wire _0013_;
+ wire _0014_;
+ wire _0015_;
+ wire _0016_;
+ wire _0017_;
+ wire _0018_;
+ wire _0019_;
+ wire _0020_;
+ wire _0021_;
+ wire _0022_;
+ wire _0023_;
+ wire _0024_;
+ wire _0025_;
+ wire _0026_;
+ wire _0027_;
+ wire _0028_;
+ wire _0029_;
+ wire _0030_;
+ wire _0031_;
+ wire _0032_;
+ wire _0033_;
+ wire _0034_;
+ wire _0035_;
+ wire _0036_;
+ wire _0037_;
+ wire _0038_;
+ wire _0039_;
+ wire _0040_;
+ wire _0041_;
+ wire _0042_;
+ wire _0043_;
+ wire _0044_;
+ wire _0045_;
+ wire _0046_;
+ wire _0047_;
+ wire _0048_;
+ wire _0049_;
+ wire _0050_;
+ wire _0051_;
+ wire _0052_;
+ wire _0053_;
+ wire _0054_;
+ wire _0055_;
+ wire _0056_;
+ wire _0057_;
+ wire _0058_;
+ wire _0059_;
+ wire _0060_;
+ wire _0061_;
+ wire _0062_;
+ wire _0063_;
+ wire _0064_;
+ wire _0065_;
+ wire _0066_;
+ wire _0067_;
+ wire _0068_;
+ wire _0069_;
+ wire _0070_;
+ wire _0071_;
+ wire _0072_;
+ wire _0073_;
+ wire _0074_;
+ wire _0075_;
+ wire _0076_;
+ wire _0077_;
+ wire _0078_;
+ wire _0079_;
+ wire _0080_;
+ wire _0081_;
+ wire _0082_;
+ wire _0083_;
+ wire _0084_;
+ wire _0085_;
+ wire _0086_;
+ wire _0087_;
+ wire _0088_;
+ wire _0089_;
+ wire _0090_;
+ wire _0091_;
+ wire _0092_;
+ wire _0093_;
+ wire _0094_;
+ wire _0095_;
+ wire _0096_;
+ wire _0097_;
+ wire _0098_;
+ wire _0099_;
+ wire _0100_;
+ wire _0101_;
+ wire _0102_;
+ wire _0103_;
+ wire _0104_;
+ wire _0105_;
+ wire _0106_;
+ wire _0107_;
+ wire _0108_;
+ wire _0109_;
+ wire _0110_;
+ wire _0111_;
+ wire _0112_;
+ wire _0113_;
+ wire _0114_;
+ wire _0115_;
+ wire _0116_;
+ wire _0117_;
+ wire _0118_;
+ wire _0119_;
+ wire _0120_;
+ wire _0121_;
+ wire _0122_;
+ wire _0123_;
+ wire _0124_;
+ wire _0125_;
+ wire _0126_;
+ wire _0127_;
+ wire _0128_;
+ wire _0129_;
+ wire _0130_;
+ wire _0131_;
+ wire _0132_;
+ wire _0133_;
+ wire _0134_;
+ wire _0135_;
+ wire _0136_;
+ wire _0137_;
+ wire _0138_;
+ wire _0139_;
+ wire _0140_;
+ wire _0141_;
+ wire _0142_;
+ wire _0143_;
+ wire _0144_;
+ wire _0145_;
+ wire _0146_;
+ wire _0147_;
+ wire _0148_;
+ wire _0149_;
+ wire _0150_;
+ wire _0151_;
+ wire _0152_;
+ wire _0153_;
+ wire _0154_;
+ wire _0155_;
+ wire _0156_;
+ wire _0157_;
+ wire _0158_;
+ wire _0159_;
+ wire _0160_;
+ wire _0161_;
+ wire _0162_;
+ wire _0163_;
+ wire _0164_;
+ wire _0165_;
+ wire _0166_;
+ wire _0167_;
+ wire _0168_;
+ wire _0169_;
+ wire _0170_;
+ wire _0171_;
+ wire _0172_;
+ wire _0173_;
+ wire _0174_;
+ wire _0175_;
+ wire _0176_;
+ wire _0177_;
+ wire _0178_;
+ wire _0179_;
+ wire _0180_;
+ wire _0181_;
+ wire _0182_;
+ wire _0183_;
+ wire _0184_;
+ wire _0185_;
+ wire _0186_;
+ wire _0187_;
+ wire _0188_;
+ wire _0189_;
+ wire _0190_;
+ wire _0191_;
+ wire _0192_;
+ wire _0193_;
+ wire _0194_;
+ wire _0195_;
+ wire _0196_;
+ wire _0197_;
+ wire _0198_;
+ wire _0199_;
+ wire _0200_;
+ wire _0201_;
+ wire _0202_;
+ wire _0203_;
+ wire _0204_;
+ wire _0205_;
+ wire _0206_;
+ wire _0207_;
+ wire _0208_;
+ wire _0209_;
+ wire _0210_;
+ wire _0211_;
+ wire _0212_;
+ wire _0213_;
+ wire _0214_;
+ wire _0215_;
+ wire _0216_;
+ wire _0217_;
+ wire _0218_;
+ wire _0219_;
+ wire _0220_;
+ wire _0221_;
+ wire _0222_;
+ wire _0223_;
+ wire _0224_;
+ wire _0225_;
+ wire _0226_;
+ wire _0227_;
+ wire _0228_;
+ wire _0229_;
+ wire _0230_;
+ wire _0231_;
+ wire _0232_;
+ wire _0233_;
+ wire _0234_;
+ wire _0235_;
+ wire _0236_;
+ wire _0237_;
+ wire _0238_;
+ wire _0239_;
+ wire _0240_;
+ wire _0241_;
+ wire _0242_;
+ wire _0243_;
+ wire _0244_;
+ wire _0245_;
+ wire _0246_;
+ wire _0247_;
+ wire _0248_;
+ wire _0249_;
+ wire _0250_;
+ wire _0251_;
+ wire _0252_;
+ wire _0253_;
+ wire _0254_;
+ wire _0255_;
+ wire _0256_;
+ wire _0257_;
+ wire _0258_;
+ wire _0259_;
+ wire _0260_;
+ wire _0261_;
+ wire _0262_;
+ wire _0263_;
+ wire _0264_;
+ wire _0265_;
+ wire _0266_;
+ wire _0267_;
+ wire _0268_;
+ wire _0269_;
+ wire _0270_;
+ wire _0271_;
+ wire _0272_;
+ wire _0273_;
+ wire _0274_;
+ wire _0275_;
+ wire _0276_;
+ wire _0277_;
+ wire _0278_;
+ wire _0279_;
+ wire _0280_;
+ wire _0281_;
+ wire _0282_;
+ wire _0283_;
+ wire _0284_;
+ wire _0285_;
+ wire _0286_;
+ wire _0287_;
+ wire _0288_;
+ wire _0289_;
+ wire _0290_;
+ wire _0291_;
+ wire _0292_;
+ wire _0293_;
+ wire _0294_;
+ wire _0295_;
+ wire _0296_;
+ wire _0297_;
+ wire _0298_;
+ wire _0299_;
+ wire _0300_;
+ wire _0301_;
+ wire _0302_;
+ wire _0303_;
+ wire _0304_;
+ wire _0305_;
+ wire _0306_;
+ wire _0307_;
+ wire _0308_;
+ wire _0309_;
+ wire _0310_;
+ wire _0311_;
+ wire _0312_;
+ wire _0313_;
+ wire _0314_;
+ wire _0315_;
+ wire _0316_;
+ wire _0317_;
+ wire _0318_;
+ wire _0319_;
+ wire _0320_;
+ wire _0321_;
+ wire _0322_;
+ wire _0323_;
+ wire _0324_;
+ wire _0325_;
+ wire _0326_;
+ wire _0327_;
+ wire _0328_;
+ wire _0329_;
+ wire _0330_;
+ wire _0331_;
+ wire _0332_;
+ wire _0333_;
+ wire _0334_;
+ wire _0335_;
+ wire _0336_;
+ wire _0337_;
+ wire _0338_;
+ wire _0339_;
+ wire _0340_;
+ wire _0341_;
+ wire _0342_;
+ wire _0343_;
+ wire _0344_;
+ wire _0345_;
+ wire _0346_;
+ wire _0347_;
+ wire _0348_;
+ wire _0349_;
+ wire _0350_;
+ wire _0351_;
+ wire _0352_;
+ wire _0353_;
+ wire _0354_;
+ wire _0355_;
+ wire _0356_;
+ wire _0357_;
+ wire _0358_;
+ wire _0359_;
+ wire _0360_;
+ wire _0361_;
+ wire _0362_;
+ wire _0363_;
+ wire _0364_;
+ wire _0365_;
+ wire _0366_;
+ wire _0367_;
+ wire _0368_;
+ wire _0369_;
+ wire _0370_;
+ wire _0371_;
+ wire _0372_;
+ wire _0373_;
+ wire _0374_;
+ wire _0375_;
+ wire _0376_;
+ wire _0377_;
+ wire _0378_;
+ wire _0379_;
+ wire _0380_;
+ wire _0381_;
+ wire _0382_;
+ wire _0383_;
+ wire _0384_;
+ wire _0385_;
+ wire _0386_;
+ wire _0387_;
+ wire _0388_;
+ wire _0389_;
+ wire _0390_;
+ wire _0391_;
+ wire _0392_;
+ wire _0393_;
+ wire _0394_;
+ wire _0395_;
+ wire _0396_;
+ wire _0397_;
+ wire _0398_;
+ wire _0399_;
+ wire _0400_;
+ wire _0401_;
+ wire _0402_;
+ wire _0403_;
+ wire _0404_;
+ wire _0405_;
+ wire _0406_;
+ wire _0407_;
+ wire _0408_;
+ wire _0409_;
+ wire _0410_;
+ wire _0411_;
+ wire _0412_;
+ wire _0413_;
+ wire _0414_;
+ wire _0415_;
+ wire _0416_;
+ wire _0417_;
+ wire _0418_;
+ wire _0419_;
+ wire _0420_;
+ wire _0421_;
+ wire _0422_;
+ wire _0423_;
+ wire _0424_;
+ wire _0425_;
+ wire _0426_;
+ wire _0427_;
+ wire _0428_;
+ wire _0429_;
+ wire _0430_;
+ wire _0431_;
+ wire _0432_;
+ wire _0433_;
+ wire _0434_;
+ wire _0435_;
+ wire _0436_;
+ wire _0437_;
+ wire _0438_;
+ wire _0439_;
+ wire _0440_;
+ wire _0441_;
+ wire _0442_;
+ wire _0443_;
+ wire _0444_;
+ wire _0445_;
+ wire _0446_;
+ wire _0447_;
+ wire _0448_;
+ wire _0449_;
+ wire _0450_;
+ wire _0451_;
+ wire _0452_;
+ wire _0453_;
+ wire _0454_;
+ wire _0455_;
+ wire _0456_;
+ wire _0457_;
+ wire _0458_;
+ wire _0459_;
+ wire _0460_;
+ wire _0461_;
+ wire _0462_;
+ wire _0463_;
+ wire _0464_;
+ wire _0465_;
+ wire _0466_;
+ wire _0467_;
+ wire _0468_;
+ wire _0469_;
+ wire _0470_;
+ wire _0471_;
+ wire _0472_;
+ wire _0473_;
+ wire _0474_;
+ wire _0475_;
+ wire _0476_;
+ wire _0477_;
+ wire _0478_;
+ wire _0479_;
+ wire _0480_;
+ wire _0481_;
+ wire _0482_;
+ wire _0483_;
+ wire _0484_;
+ wire _0485_;
+ wire _0486_;
+ wire _0487_;
+ wire _0488_;
+ wire _0489_;
+ wire _0490_;
+ wire _0491_;
+ wire _0492_;
+ wire _0493_;
+ wire _0494_;
+ wire _0495_;
+ wire _0496_;
+ wire _0497_;
+ wire _0498_;
+ wire _0499_;
+ wire _0500_;
+ wire _0501_;
+ wire _0502_;
+ wire _0503_;
+ wire _0504_;
+ wire _0505_;
+ wire _0506_;
+ wire _0507_;
+ wire _0508_;
+ wire _0509_;
+ wire _0510_;
+ wire _0511_;
+ wire _0512_;
+ wire _0513_;
+ wire _0514_;
+ wire _0515_;
+ wire _0516_;
+ wire _0517_;
+ wire _0518_;
+ wire _0519_;
+ wire _0520_;
+ wire _0521_;
+ wire _0522_;
+ wire _0523_;
+ wire _0524_;
+ wire _0525_;
+ wire _0526_;
+ wire _0527_;
+ wire _0528_;
+ wire _0529_;
+ wire _0530_;
+ wire _0531_;
+ wire _0532_;
+ wire _0533_;
+ wire _0534_;
+ wire _0535_;
+ wire _0536_;
+ wire _0537_;
+ wire _0538_;
+ wire _0539_;
+ wire _0540_;
+ wire _0541_;
+ wire _0542_;
+ wire _0543_;
+ wire _0544_;
+ wire _0545_;
+ wire _0546_;
+ wire _0547_;
+ wire _0548_;
+ wire _0549_;
+ wire _0550_;
+ wire _0551_;
+ wire _0552_;
+ wire _0553_;
+ wire _0554_;
+ wire _0555_;
+ wire _0556_;
+ wire _0557_;
+ wire _0558_;
+ wire _0559_;
+ wire _0560_;
+ wire _0561_;
+ wire _0562_;
+ wire _0563_;
+ wire _0564_;
+ wire _0565_;
+ wire _0566_;
+ wire _0567_;
+ wire _0568_;
+ wire _0569_;
+ wire _0570_;
+ wire _0571_;
+ wire _0572_;
+ wire _0573_;
+ wire _0574_;
+ wire _0575_;
+ wire _0576_;
+ wire _0577_;
+ wire _0578_;
+ wire _0579_;
+ wire _0580_;
+ wire _0581_;
+ wire _0582_;
+ wire _0583_;
+ wire _0584_;
+ wire _0585_;
+ wire _0586_;
+ wire _0587_;
+ wire _0588_;
+ wire _0589_;
+ wire _0590_;
+ wire _0591_;
+ wire _0592_;
+ wire _0593_;
+ wire _0594_;
+ wire _0595_;
+ wire _0596_;
+ wire _0597_;
+ wire _0598_;
+ wire _0599_;
+ wire _0600_;
+ wire _0601_;
+ wire _0602_;
+ wire _0603_;
+ wire _0604_;
+ wire _0605_;
+ wire _0606_;
+ wire _0607_;
+ wire _0608_;
+ wire _0609_;
+ wire _0610_;
+ wire _0611_;
+ wire _0612_;
+ wire _0613_;
+ wire _0614_;
+ wire _0615_;
+ wire _0616_;
+ wire _0617_;
+ wire _0618_;
+ wire _0619_;
+ wire _0620_;
+ wire _0621_;
+ wire _0622_;
+ wire _0623_;
+ wire _0624_;
+ wire _0625_;
+ wire _0626_;
+ wire _0627_;
+ wire _0628_;
+ wire _0629_;
+ wire _0630_;
+ wire _0631_;
+ wire _0632_;
+ wire _0633_;
+ wire _0634_;
+ wire _0635_;
+ wire _0636_;
+ wire _0637_;
+ wire _0638_;
+ wire _0639_;
+ wire _0640_;
+ wire _0641_;
+ wire _0642_;
+ wire _0643_;
+ wire _0644_;
+ wire _0645_;
+ wire _0646_;
+ wire _0647_;
+ wire _0648_;
+ wire _0649_;
+ wire _0650_;
+ wire _0651_;
+ wire _0652_;
+ wire _0653_;
+ wire _0654_;
+ wire _0655_;
+ wire _0656_;
+ wire _0657_;
+ wire _0658_;
+ wire _0659_;
+ wire _0660_;
+ wire _0661_;
+ wire _0662_;
+ wire _0663_;
+ wire _0664_;
+ wire _0665_;
+ wire _0666_;
+ wire _0667_;
+ wire _0668_;
+ wire _0669_;
+ wire _0670_;
+ wire _0671_;
+ wire _0672_;
+ wire _0673_;
+ wire _0674_;
+ wire _0675_;
+ wire _0676_;
+ wire _0677_;
+ wire _0678_;
+ wire _0679_;
+ wire _0680_;
+ wire _0681_;
+ wire _0682_;
+ wire _0683_;
+ wire _0684_;
+ wire _0685_;
+ wire _0686_;
+ wire _0687_;
+ wire _0688_;
+ wire _0689_;
+ wire _0690_;
+ wire _0691_;
+ wire _0692_;
+ wire _0693_;
+ wire _0694_;
+ wire _0695_;
+ wire _0696_;
+ wire _0697_;
+ wire _0698_;
+ wire _0699_;
+ wire _0700_;
+ wire _0701_;
+ wire _0702_;
+ wire _0703_;
+ wire _0704_;
+ wire _0705_;
+ wire _0706_;
+ wire _0707_;
+ wire _0708_;
+ wire _0709_;
+ wire _0710_;
+ wire _0711_;
+ wire _0712_;
+ wire _0713_;
+ wire _0714_;
+ wire _0715_;
+ wire _0716_;
+ wire _0717_;
+ wire _0718_;
+ wire _0719_;
+ wire _0720_;
+ wire _0721_;
+ wire _0722_;
+ wire _0723_;
+ wire _0724_;
+ wire _0725_;
+ wire _0726_;
+ wire _0727_;
+ wire _0728_;
+ wire _0729_;
+ wire _0730_;
+ wire _0731_;
+ wire _0732_;
+ wire _0733_;
+ wire _0734_;
+ wire _0735_;
+ wire _0736_;
+ wire _0737_;
+ wire _0738_;
+ wire _0739_;
+ wire _0740_;
+ wire _0741_;
+ wire _0742_;
+ wire _0743_;
+ wire _0744_;
+ wire _0745_;
+ wire _0746_;
+ wire _0747_;
+ wire _0748_;
+ wire _0749_;
+ wire _0750_;
+ wire _0751_;
+ wire _0752_;
+ wire _0753_;
+ wire _0754_;
+ wire _0755_;
+ wire _0756_;
+ wire _0757_;
+ wire _0758_;
+ wire _0759_;
+ wire _0760_;
+ wire _0761_;
+ wire _0762_;
+ wire _0763_;
+ wire _0764_;
+ wire _0765_;
+ wire _0766_;
+ wire _0767_;
+ wire _0768_;
+ wire _0769_;
+ wire _0770_;
+ wire _0771_;
+ wire _0772_;
+ wire _0773_;
+ wire _0774_;
+ wire _0775_;
+ wire _0776_;
+ wire _0777_;
+ wire _0778_;
+ wire _0779_;
+ wire _0780_;
+ wire _0781_;
+ wire _0782_;
+ wire _0783_;
+ wire _0784_;
+ wire _0785_;
+ wire _0786_;
+ wire _0787_;
+ wire _0788_;
+ wire _0789_;
+ wire _0790_;
+ wire _0791_;
+ wire _0792_;
+ wire _0793_;
+ wire _0794_;
+ wire _0795_;
+ wire _0796_;
+ wire _0797_;
+ wire _0798_;
+ wire _0799_;
+ wire _0800_;
+ wire _0801_;
+ wire _0802_;
+ wire _0803_;
+ wire _0804_;
+ wire _0805_;
+ wire _0806_;
+ wire _0807_;
+ wire _0808_;
+ wire _0809_;
+ wire _0810_;
+ wire _0811_;
+ wire _0812_;
+ wire _0813_;
+ wire _0814_;
+ wire _0815_;
+ wire _0816_;
+ wire _0817_;
+ wire _0818_;
+ wire _0819_;
+ wire _0820_;
+ wire _0821_;
+ wire clknet_0_mclk;
+ wire clknet_1_0_0_mclk;
+ wire clknet_1_1_0_mclk;
+ wire clknet_2_0_0_mclk;
+ wire clknet_2_1_0_mclk;
+ wire clknet_2_2_0_mclk;
+ wire clknet_2_3_0_mclk;
+ wire clknet_leaf_0_mclk;
+ wire clknet_leaf_10_mclk;
+ wire clknet_leaf_11_mclk;
+ wire clknet_leaf_12_mclk;
+ wire clknet_leaf_13_mclk;
+ wire clknet_leaf_14_mclk;
+ wire clknet_leaf_15_mclk;
+ wire clknet_leaf_16_mclk;
+ wire clknet_leaf_17_mclk;
+ wire clknet_leaf_18_mclk;
+ wire clknet_leaf_19_mclk;
+ wire clknet_leaf_1_mclk;
+ wire clknet_leaf_20_mclk;
+ wire clknet_leaf_21_mclk;
+ wire clknet_leaf_22_mclk;
+ wire clknet_leaf_23_mclk;
+ wire clknet_leaf_24_mclk;
+ wire clknet_leaf_25_mclk;
+ wire clknet_leaf_26_mclk;
+ wire clknet_leaf_27_mclk;
+ wire clknet_leaf_28_mclk;
+ wire clknet_leaf_2_mclk;
+ wire clknet_leaf_3_mclk;
+ wire clknet_leaf_4_mclk;
+ wire clknet_leaf_5_mclk;
+ wire clknet_leaf_6_mclk;
+ wire clknet_leaf_7_mclk;
+ wire clknet_leaf_8_mclk;
+ wire clknet_leaf_9_mclk;
+ wire net1;
+ wire net10;
+ wire net100;
+ wire net101;
+ wire net102;
+ wire net103;
+ wire net104;
+ wire net105;
+ wire net106;
+ wire net107;
+ wire net108;
+ wire net109;
+ wire net11;
+ wire net110;
+ wire net111;
+ wire net112;
+ wire net113;
+ wire net114;
+ wire net115;
+ wire net116;
+ wire net117;
+ wire net118;
+ wire net119;
+ wire net12;
+ wire net120;
+ wire net121;
+ wire net122;
+ wire net123;
+ wire net124;
+ wire net125;
+ wire net126;
+ wire net127;
+ wire net128;
+ wire net129;
+ wire net13;
+ wire net130;
+ wire net131;
+ wire net132;
+ wire net133;
+ wire net134;
+ wire net135;
+ wire net136;
+ wire net137;
+ wire net138;
+ wire net139;
+ wire net14;
+ wire net140;
+ wire net141;
+ wire net142;
+ wire net143;
+ wire net144;
+ wire net145;
+ wire net15;
+ wire net16;
+ wire net17;
+ wire net18;
+ wire net19;
+ wire net2;
+ wire net20;
+ wire net21;
+ wire net22;
+ wire net23;
+ wire net24;
+ wire net25;
+ wire net26;
+ wire net27;
+ wire net28;
+ wire net29;
+ wire net3;
+ wire net30;
+ wire net31;
+ wire net32;
+ wire net33;
+ wire net34;
+ wire net35;
+ wire net36;
+ wire net37;
+ wire net38;
+ wire net39;
+ wire net4;
+ wire net40;
+ wire net41;
+ wire net42;
+ wire net43;
+ wire net44;
+ wire net45;
+ wire net46;
+ wire net47;
+ wire net48;
+ wire net49;
+ wire net5;
+ wire net50;
+ wire net51;
+ wire net52;
+ wire net53;
+ wire net54;
+ wire net55;
+ wire net56;
+ wire net57;
+ wire net58;
+ wire net59;
+ wire net6;
+ wire net60;
+ wire net61;
+ wire net62;
+ wire net63;
+ wire net64;
+ wire net65;
+ wire net66;
+ wire net67;
+ wire net68;
+ wire net69;
+ wire net7;
+ wire net70;
+ wire net71;
+ wire net72;
+ wire net73;
+ wire net74;
+ wire net75;
+ wire net76;
+ wire net77;
+ wire net78;
+ wire net79;
+ wire net8;
+ wire net80;
+ wire net81;
+ wire net82;
+ wire net83;
+ wire net84;
+ wire net85;
+ wire net86;
+ wire net87;
+ wire net88;
+ wire net89;
+ wire net9;
+ wire net90;
+ wire net91;
+ wire net92;
+ wire net93;
+ wire net94;
+ wire net95;
+ wire net96;
+ wire net97;
+ wire net98;
+ wire net99;
+ wire \u_bist_ctrl_be0.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be0.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be0.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be0.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be0.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be0.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be0.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be0.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be1.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be1.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be1.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be1.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be1.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be1.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be1.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be1.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be2.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be2.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be2.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be2.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be2.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be2.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be2.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be2.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be3.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be3.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be3.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be3.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be3.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be3.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be3.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_bist_ctrl_be3.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_reg0_be0.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_reg0_be0.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_reg0_be0.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_reg0_be0.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_reg0_be0.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_reg0_be0.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_reg0_be0.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_reg0_be0.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_reg0_be1.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_reg0_be1.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_reg0_be1.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_reg0_be1.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_reg0_be1.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_reg0_be1.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_reg0_be1.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_reg0_be1.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_reg0_be2.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_reg0_be2.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_reg0_be2.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_reg0_be2.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_reg0_be2.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_reg0_be2.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_reg0_be2.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_reg0_be2.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_reg0_be3.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_reg0_be3.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_reg0_be3.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_reg0_be3.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_reg0_be3.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_reg0_be3.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_reg0_be3.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_reg0_be3.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_reg1_be0.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_reg1_be0.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_reg1_be0.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_reg1_be0.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_reg1_be0.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_reg1_be0.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_reg1_be0.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_reg1_be0.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_reg1_be1.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_reg1_be1.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_reg1_be1.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_reg1_be1.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_reg1_be1.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_reg1_be1.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_reg1_be1.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_reg1_be1.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_reg1_be2.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_reg1_be2.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_reg1_be2.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_reg1_be2.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_reg1_be2.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_reg1_be2.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_reg1_be2.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_reg1_be2.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_reg1_be3.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_reg1_be3.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_reg1_be3.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_reg1_be3.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_reg1_be3.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_reg1_be3.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_reg1_be3.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_reg1_be3.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_ser_intf.bit_cnt[0] ;
+ wire \u_ser_intf.bit_cnt[1] ;
+ wire \u_ser_intf.bit_cnt[2] ;
+ wire \u_ser_intf.bit_cnt[3] ;
+ wire \u_ser_intf.bit_cnt[4] ;
+ wire \u_ser_intf.bit_cnt[5] ;
+ wire \u_ser_intf.reg_ack ;
+ wire \u_ser_intf.reg_rdata[0] ;
+ wire \u_ser_intf.reg_rdata[10] ;
+ wire \u_ser_intf.reg_rdata[11] ;
+ wire \u_ser_intf.reg_rdata[12] ;
+ wire \u_ser_intf.reg_rdata[13] ;
+ wire \u_ser_intf.reg_rdata[14] ;
+ wire \u_ser_intf.reg_rdata[15] ;
+ wire \u_ser_intf.reg_rdata[16] ;
+ wire \u_ser_intf.reg_rdata[17] ;
+ wire \u_ser_intf.reg_rdata[18] ;
+ wire \u_ser_intf.reg_rdata[19] ;
+ wire \u_ser_intf.reg_rdata[1] ;
+ wire \u_ser_intf.reg_rdata[20] ;
+ wire \u_ser_intf.reg_rdata[21] ;
+ wire \u_ser_intf.reg_rdata[22] ;
+ wire \u_ser_intf.reg_rdata[23] ;
+ wire \u_ser_intf.reg_rdata[24] ;
+ wire \u_ser_intf.reg_rdata[25] ;
+ wire \u_ser_intf.reg_rdata[26] ;
+ wire \u_ser_intf.reg_rdata[27] ;
+ wire \u_ser_intf.reg_rdata[28] ;
+ wire \u_ser_intf.reg_rdata[29] ;
+ wire \u_ser_intf.reg_rdata[2] ;
+ wire \u_ser_intf.reg_rdata[30] ;
+ wire \u_ser_intf.reg_rdata[31] ;
+ wire \u_ser_intf.reg_rdata[3] ;
+ wire \u_ser_intf.reg_rdata[4] ;
+ wire \u_ser_intf.reg_rdata[5] ;
+ wire \u_ser_intf.reg_rdata[6] ;
+ wire \u_ser_intf.reg_rdata[7] ;
+ wire \u_ser_intf.reg_rdata[8] ;
+ wire \u_ser_intf.reg_rdata[9] ;
+ wire \u_ser_intf.sdi ;
+ wire \u_ser_intf.sdo ;
+ wire \u_ser_intf.shift ;
+ wire \u_ser_intf.shift_data[0] ;
+ wire \u_ser_intf.shift_data[10] ;
+ wire \u_ser_intf.shift_data[11] ;
+ wire \u_ser_intf.shift_data[12] ;
+ wire \u_ser_intf.shift_data[13] ;
+ wire \u_ser_intf.shift_data[14] ;
+ wire \u_ser_intf.shift_data[15] ;
+ wire \u_ser_intf.shift_data[16] ;
+ wire \u_ser_intf.shift_data[17] ;
+ wire \u_ser_intf.shift_data[18] ;
+ wire \u_ser_intf.shift_data[19] ;
+ wire \u_ser_intf.shift_data[1] ;
+ wire \u_ser_intf.shift_data[20] ;
+ wire \u_ser_intf.shift_data[21] ;
+ wire \u_ser_intf.shift_data[22] ;
+ wire \u_ser_intf.shift_data[23] ;
+ wire \u_ser_intf.shift_data[24] ;
+ wire \u_ser_intf.shift_data[25] ;
+ wire \u_ser_intf.shift_data[26] ;
+ wire \u_ser_intf.shift_data[27] ;
+ wire \u_ser_intf.shift_data[28] ;
+ wire \u_ser_intf.shift_data[29] ;
+ wire \u_ser_intf.shift_data[2] ;
+ wire \u_ser_intf.shift_data[30] ;
+ wire \u_ser_intf.shift_data[31] ;
+ wire \u_ser_intf.shift_data[3] ;
+ wire \u_ser_intf.shift_data[4] ;
+ wire \u_ser_intf.shift_data[5] ;
+ wire \u_ser_intf.shift_data[6] ;
+ wire \u_ser_intf.shift_data[7] ;
+ wire \u_ser_intf.shift_data[8] ;
+ wire \u_ser_intf.shift_data[9] ;
+ wire \u_ser_intf.state ;
+ wire \u_skew_glbl.clk_d1 ;
+ wire \u_skew_glbl.clk_d10 ;
+ wire \u_skew_glbl.clk_d11 ;
+ wire \u_skew_glbl.clk_d12 ;
+ wire \u_skew_glbl.clk_d13 ;
+ wire \u_skew_glbl.clk_d14 ;
+ wire \u_skew_glbl.clk_d15 ;
+ wire \u_skew_glbl.clk_d2 ;
+ wire \u_skew_glbl.clk_d3 ;
+ wire \u_skew_glbl.clk_d4 ;
+ wire \u_skew_glbl.clk_d5 ;
+ wire \u_skew_glbl.clk_d6 ;
+ wire \u_skew_glbl.clk_d7 ;
+ wire \u_skew_glbl.clk_d8 ;
+ wire \u_skew_glbl.clk_d9 ;
+ wire \u_skew_glbl.d00 ;
+ wire \u_skew_glbl.d01 ;
+ wire \u_skew_glbl.d02 ;
+ wire \u_skew_glbl.d03 ;
+ wire \u_skew_glbl.d04 ;
+ wire \u_skew_glbl.d05 ;
+ wire \u_skew_glbl.d06 ;
+ wire \u_skew_glbl.d07 ;
+ wire \u_skew_glbl.d10 ;
+ wire \u_skew_glbl.d11 ;
+ wire \u_skew_glbl.d12 ;
+ wire \u_skew_glbl.d13 ;
+ wire \u_skew_glbl.d20 ;
+ wire \u_skew_glbl.d21 ;
+ wire wb_req;
+ wire wb_req_d;
+
+ sky130_fd_sc_hd__diode_2 ANTENNA__0822__A (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0826__A2 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0826__B2 (.DIODE(_0651_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0827__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0827__B2 (.DIODE(_0651_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0828__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0828__B1 (.DIODE(_0651_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0830__A (.DIODE(_0652_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0831__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0832__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0833__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0834__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0835__A (.DIODE(_0652_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0836__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0837__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0838__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0839__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0840__A (.DIODE(_0652_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0841__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0842__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0843__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0844__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0845__A (.DIODE(_0652_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0846__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0847__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0848__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0849__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0851__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0852__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0853__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0854__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0856__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0857__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0858__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0859__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0861__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0862__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0863__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0864__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0865__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0866__A1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0866__A2 (.DIODE(\u_ser_intf.sdi ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0866__B2 (.DIODE(\u_ser_intf.shift_data[0] ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0875__A (.DIODE(net69),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0877__A (.DIODE(_0669_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0879__A2_N (.DIODE(_0667_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0880__A (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0881__A (.DIODE(_0667_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0882__A (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0882__B (.DIODE(_0066_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0933__B1 (.DIODE(\u_ser_intf.shift_data[0] ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0938__C (.DIODE(_0697_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0939__A (.DIODE(_0694_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0939__B (.DIODE(_0698_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0943__B1 (.DIODE(net60),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0945__B (.DIODE(_0698_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0949__B1 (.DIODE(net61),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0950__B1 (.DIODE(net62),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0951__B1 (.DIODE(net63),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0952__B1 (.DIODE(net64),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0955__B1 (.DIODE(net65),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0956__A1 (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[5].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0956__B1 (.DIODE(net66),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0957__A1 (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[6].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0957__B1 (.DIODE(net68),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0959__A (.DIODE(_0710_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0959__B (.DIODE(_0698_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0963__B1 (.DIODE(net51),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0964__B1 (.DIODE(net52),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0965__B1 (.DIODE(net53),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0966__B1 (.DIODE(net54),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0969__B1 (.DIODE(net55),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0970__B1 (.DIODE(net57),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0971__B1 (.DIODE(net58),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0972__B1 (.DIODE(net59),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0974__A (.DIODE(_0717_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0974__B (.DIODE(_0698_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0978__B1 (.DIODE(net74),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0979__B1 (.DIODE(net75),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0980__B1 (.DIODE(net76),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0981__B1 (.DIODE(net46),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0984__B1 (.DIODE(net47),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0985__B1 (.DIODE(net48),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0986__B1 (.DIODE(net49),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0987__B1 (.DIODE(net50),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0988__B1 (.DIODE(net45),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0989__B1 (.DIODE(net56),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0990__B1 (.DIODE(net67),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0993__B1 (.DIODE(net70),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0994__B1 (.DIODE(net71),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0995__B1 (.DIODE(net72),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0996__B1 (.DIODE(net73),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0998__C (.DIODE(_0726_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0999__A (.DIODE(_0694_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__0999__B (.DIODE(_0727_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1003__B1 (.DIODE(net60),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1004__B (.DIODE(_0727_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1008__B1 (.DIODE(net61),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1009__B1 (.DIODE(net62),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1010__B1 (.DIODE(net63),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1011__B1 (.DIODE(net64),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1014__B1 (.DIODE(net65),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1015__B1 (.DIODE(net66),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1016__B1 (.DIODE(net68),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1017__A (.DIODE(_0710_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1017__B (.DIODE(_0727_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1021__B1 (.DIODE(net51),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1022__B1 (.DIODE(net52),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1023__B1 (.DIODE(net53),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1024__B1 (.DIODE(net54),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1027__B1 (.DIODE(net55),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1028__B1 (.DIODE(net57),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1029__B1 (.DIODE(net58),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1030__B1 (.DIODE(net59),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1031__A (.DIODE(_0717_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1031__B (.DIODE(_0727_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1035__B1 (.DIODE(net74),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1036__B1 (.DIODE(net75),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1037__B1 (.DIODE(net76),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1038__B1 (.DIODE(net46),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1041__B1 (.DIODE(net47),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1042__B1 (.DIODE(net48),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1043__B1 (.DIODE(net49),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1044__B1 (.DIODE(net50),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1046__C (.DIODE(_0750_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1047__B (.DIODE(_0751_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1051__B1 (.DIODE(net69),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1052__B1 (.DIODE(net45),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1053__B1 (.DIODE(net56),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1054__B1 (.DIODE(net67),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1057__B1 (.DIODE(net70),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1058__B1 (.DIODE(net71),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1059__B1 (.DIODE(net72),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1060__B1 (.DIODE(net73),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1061__A (.DIODE(_0694_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1061__B (.DIODE(_0751_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1065__B1 (.DIODE(net60),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1066__B1 (.DIODE(net61),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1067__B1 (.DIODE(net62),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1068__B1 (.DIODE(net63),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1071__B1 (.DIODE(net64),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1072__B1 (.DIODE(net65),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1073__B1 (.DIODE(net66),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1074__B1 (.DIODE(net68),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1075__A (.DIODE(_0710_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1075__B (.DIODE(_0751_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1079__B1 (.DIODE(net51),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1080__B1 (.DIODE(net52),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1081__B1 (.DIODE(net53),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1082__B1 (.DIODE(net54),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1085__B1 (.DIODE(net55),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1086__B1 (.DIODE(net57),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1087__B1 (.DIODE(net58),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1088__B1 (.DIODE(net59),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1089__A (.DIODE(_0717_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1089__B (.DIODE(_0751_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1093__B1 (.DIODE(net74),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1094__B1 (.DIODE(net75),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1095__B1 (.DIODE(net76),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1096__B1 (.DIODE(net46),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1099__B1 (.DIODE(net47),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1100__B1 (.DIODE(net48),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1101__B1 (.DIODE(net49),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1102__B1 (.DIODE(net50),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1103__A1 (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[7].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1103__B1 (.DIODE(net69),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1104__B1 (.DIODE(net45),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1105__B1 (.DIODE(net56),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1106__B1 (.DIODE(net67),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1109__B1 (.DIODE(net70),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1110__B1 (.DIODE(net71),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1111__B1 (.DIODE(net72),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1112__B1 (.DIODE(net73),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1120__A2 (.DIODE(_0066_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1120__B1 (.DIODE(\u_ser_intf.shift ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1122__B (.DIODE(net100),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1123__B (.DIODE(\u_ser_intf.reg_ack ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1125__A2 (.DIODE(_0033_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1125__B1 (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1159__A1 (.DIODE(net105),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1161__A1 (.DIODE(net104),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1163__A1 (.DIODE(net103),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1164__A1 (.DIODE(net102),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1173__A1 (.DIODE(net127),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1175__A1 (.DIODE(net126),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1176__A1 (.DIODE(net123),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1177__A1 (.DIODE(net112),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1179__A1 (.DIODE(\u_ser_intf.reg_ack ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1179__B1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1181__A (.DIODE(_0651_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1183__A (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1189__C1 (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1197__A (.DIODE(_0669_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1199__B (.DIODE(net64),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1201__B (.DIODE(net65),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1203__B (.DIODE(net66),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1205__B (.DIODE(net68),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1210__A (.DIODE(_0343_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1211__A (.DIODE(_0344_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1213__A (.DIODE(_0697_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1214__A (.DIODE(_0347_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1217__A (.DIODE(_0350_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1218__A (.DIODE(_0351_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1221__A (.DIODE(_0726_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1222__A (.DIODE(_0355_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1224__A (.DIODE(_0750_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1225__A (.DIODE(_0358_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1245__A (.DIODE(_0358_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1247__A (.DIODE(_0343_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1250__A (.DIODE(_0726_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1253__A (.DIODE(_0347_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1254__A2 (.DIODE(_0382_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1254__B2 (.DIODE(_0384_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1255__A2 (.DIODE(_0376_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1255__B2 (.DIODE(_0379_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1265__A (.DIODE(_0344_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1267__A (.DIODE(_0347_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1269__A (.DIODE(_0351_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1272__A (.DIODE(_0355_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1274__A (.DIODE(_0358_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1302__A (.DIODE(_0344_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1304__A (.DIODE(_0347_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1306__A (.DIODE(_0351_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1309__A (.DIODE(_0355_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1311__A (.DIODE(_0358_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1326__A2 (.DIODE(_0382_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1326__B2 (.DIODE(_0384_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1327__A2 (.DIODE(_0376_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1327__B2 (.DIODE(_0379_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1335__B1 (.DIODE(_0453_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1345__A (.DIODE(_0344_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1347__A (.DIODE(_0697_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1350__A (.DIODE(_0351_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1351__B1 (.DIODE(_0469_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1353__A (.DIODE(_0355_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1355__A (.DIODE(_0750_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1362__B1 (.DIODE(_0480_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1388__A (.DIODE(_0350_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1389__B1 (.DIODE(_0503_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1400__A2 (.DIODE(_0382_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1400__B2 (.DIODE(_0384_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1401__A2 (.DIODE(_0376_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1401__B2 (.DIODE(_0379_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1405__B1 (.DIODE(_0518_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1413__B1 (.DIODE(_0525_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1421__B1 (.DIODE(_0532_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1431__A (.DIODE(_0350_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1432__B1 (.DIODE(_0541_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1442__B1 (.DIODE(_0551_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1450__B1 (.DIODE(_0558_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1458__B1 (.DIODE(_0565_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1467__A2 (.DIODE(_0382_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1467__B2 (.DIODE(_0384_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1468__A2 (.DIODE(_0376_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1468__B2 (.DIODE(_0379_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1474__A (.DIODE(_0350_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1483__A (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[5].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1491__A (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[6].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1499__A (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[7].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1505__C1 (.DIODE(_0607_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1506__A (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[6].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1506__B (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[7].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1506__D (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[5].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1507__A (.DIODE(_0608_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1508__A (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[6].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1508__B (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[7].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1508__D (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[5].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1510__A (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[6].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1510__B (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[7].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1512__A (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[6].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1512__B (.DIODE(\u_bist_ctrl_be3.gen_bit_reg[7].u_bit_reg.data_out ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1516__B (.DIODE(net45),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1518__B (.DIODE(net56),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1520__B (.DIODE(net67),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1522__B (.DIODE(net70),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1525__B (.DIODE(net71),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1527__B (.DIODE(net72),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1529__B (.DIODE(net73),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1531__B (.DIODE(net74),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1534__B (.DIODE(net75),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1536__B (.DIODE(net76),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1538__B (.DIODE(net46),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1540__B (.DIODE(net47),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1543__B (.DIODE(net48),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1545__B (.DIODE(net49),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1547__B (.DIODE(net50),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1549__B (.DIODE(net51),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1552__B (.DIODE(net52),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1554__B (.DIODE(net53),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1556__B (.DIODE(net54),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1558__B (.DIODE(net55),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1561__B (.DIODE(net57),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1563__B (.DIODE(net58),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1565__B (.DIODE(net59),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1567__B (.DIODE(net60),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1569__B (.DIODE(net61),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1571__B (.DIODE(net62),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1573__B (.DIODE(net63),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1575__A (.DIODE(\u_ser_intf.shift ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1576__B (.DIODE(_0608_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1580__A (.DIODE(\u_ser_intf.sdi ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1581__B (.DIODE(_0608_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1585__B1 (.DIODE(net69),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1598__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1599__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1600__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1601__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1602__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1603__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1604__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1605__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1606__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1607__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1608__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1609__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1610__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1611__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1612__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1613__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1614__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1615__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1616__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1617__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1618__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1619__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1620__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1621__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1622__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1623__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1624__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1625__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1626__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1627__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1628__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1629__S (.DIODE(_0067_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1630__A0 (.DIODE(_0066_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1630__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1634__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1635__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1636__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1637__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1638__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1639__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1640__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1641__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1642__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1643__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1644__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1645__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1646__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1647__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1648__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1649__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1650__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1651__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1652__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1653__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1654__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1655__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1656__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1657__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1658__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1659__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1660__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1661__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1662__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1663__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1664__S (.DIODE(\u_ser_intf.state ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1665__RESET_B (.DIODE(net139),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1666__D (.DIODE(_0033_),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1666__RESET_B (.DIODE(net143),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1667__RESET_B (.DIODE(net143),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1668__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1669__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1670__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1671__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1672__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1673__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1674__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1675__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1676__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1677__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1678__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1679__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1680__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1681__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1682__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1683__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1684__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1685__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1686__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1687__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1688__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1689__RESET_B (.DIODE(net139),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1690__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1691__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1692__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1693__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1694__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1695__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1696__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1697__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1698__RESET_B (.DIODE(net144),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1699__RESET_B (.DIODE(net78),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1700__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1701__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1702__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1703__RESET_B (.DIODE(net137),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1704__RESET_B (.DIODE(net137),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1705__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1706__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1707__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1708__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1709__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1710__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1711__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1712__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1713__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1714__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1715__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1716__RESET_B (.DIODE(net144),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1717__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1718__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1719__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1720__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1721__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1722__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1723__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1724__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1725__RESET_B (.DIODE(net143),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1726__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1727__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1728__RESET_B (.DIODE(net142),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1729__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1730__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1731__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1732__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1733__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1734__RESET_B (.DIODE(net142),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1735__RESET_B (.DIODE(net142),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1736__RESET_B (.DIODE(net142),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1737__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1738__RESET_B (.DIODE(net142),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1739__RESET_B (.DIODE(net142),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1740__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1741__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1742__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1743__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1744__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1745__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1746__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1747__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1748__RESET_B (.DIODE(net142),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1749__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1750__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1751__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1752__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1753__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1754__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1755__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1756__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1757__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1758__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1759__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1760__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1761__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1762__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1763__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1764__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1765__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1766__RESET_B (.DIODE(net143),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1767__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1768__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1769__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1770__RESET_B (.DIODE(net143),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1771__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1772__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1773__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1774__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1775__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1776__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1777__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1778__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1779__RESET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1780__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1781__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1782__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1783__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1784__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1785__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1786__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1787__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1788__RESET_B (.DIODE(net138),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1789__RESET_B (.DIODE(net138),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1790__RESET_B (.DIODE(net138),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1791__RESET_B (.DIODE(net138),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1792__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1793__RESET_B (.DIODE(net139),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1794__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1795__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1796__RESET_B (.DIODE(net144),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1797__RESET_B (.DIODE(net143),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1798__RESET_B (.DIODE(net140),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1799__RESET_B (.DIODE(net143),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1800__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1801__RESET_B (.DIODE(net142),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1802__RESET_B (.DIODE(net138),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1803__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1804__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1805__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1806__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1807__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1808__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1809__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1810__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1811__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1812__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1813__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1814__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1815__RESET_B (.DIODE(net137),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1816__RESET_B (.DIODE(net137),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1817__RESET_B (.DIODE(net137),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1818__RESET_B (.DIODE(net137),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1819__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1820__RESET_B (.DIODE(net137),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1821__RESET_B (.DIODE(net137),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1822__RESET_B (.DIODE(net137),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1823__RESET_B (.DIODE(net137),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1824__RESET_B (.DIODE(net137),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1825__RESET_B (.DIODE(net138),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1826__RESET_B (.DIODE(net137),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1827__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1828__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1829__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1830__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1831__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1832__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1833__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1834__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1835__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1836__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1837__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1838__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1839__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1840__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1841__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1842__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1843__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1844__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1845__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1846__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1847__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1848__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1849__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1850__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1851__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1852__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1853__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1854__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1855__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1856__RESET_B (.DIODE(net141),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1857__RESET_B (.DIODE(net142),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1858__RESET_B (.DIODE(net142),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1859__RESET_B (.DIODE(net144),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1860__RESET_B (.DIODE(net142),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1861__RESET_B (.DIODE(net142),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1862__RESET_B (.DIODE(net142),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1863__RESET_B (.DIODE(net142),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1864__RESET_B (.DIODE(net140),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1865__RESET_B (.DIODE(net140),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1866__RESET_B (.DIODE(net139),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1867__RESET_B (.DIODE(net134),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1868__RESET_B (.DIODE(net136),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__1869__SET_B (.DIODE(net145),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_mclk_A (.DIODE(mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_1_0_0_mclk_A (.DIODE(clknet_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_1_1_0_mclk_A (.DIODE(clknet_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_0_mclk_A (.DIODE(clknet_2_0_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_10_mclk_A (.DIODE(clknet_2_3_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_11_mclk_A (.DIODE(clknet_2_3_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_12_mclk_A (.DIODE(clknet_2_3_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_13_mclk_A (.DIODE(clknet_2_3_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_14_mclk_A (.DIODE(clknet_2_3_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_15_mclk_A (.DIODE(clknet_2_3_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_16_mclk_A (.DIODE(clknet_2_3_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_17_mclk_A (.DIODE(clknet_2_2_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_18_mclk_A (.DIODE(clknet_2_2_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_19_mclk_A (.DIODE(clknet_2_2_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_1_mclk_A (.DIODE(clknet_2_1_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_20_mclk_A (.DIODE(clknet_2_2_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_21_mclk_A (.DIODE(clknet_2_2_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_22_mclk_A (.DIODE(clknet_2_2_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_23_mclk_A (.DIODE(clknet_2_2_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_24_mclk_A (.DIODE(clknet_2_0_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_25_mclk_A (.DIODE(clknet_2_0_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_26_mclk_A (.DIODE(clknet_2_0_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_27_mclk_A (.DIODE(clknet_2_0_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_28_mclk_A (.DIODE(clknet_2_0_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_2_mclk_A (.DIODE(clknet_2_0_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_3_mclk_A (.DIODE(clknet_2_1_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_4_mclk_A (.DIODE(clknet_2_1_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_5_mclk_A (.DIODE(clknet_2_1_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_6_mclk_A (.DIODE(clknet_2_1_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_7_mclk_A (.DIODE(clknet_2_1_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_8_mclk_A (.DIODE(clknet_2_1_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_leaf_9_mclk_A (.DIODE(clknet_2_1_0_mclk),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input10_A (.DIODE(bist_error[1]),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA_input11_A (.DIODE(bist_error[2]),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANT
commit	c928ee3b18cb4dcb77c15ce375cdfc78f9d18ef2	[log] [tgz]
author	dineshannayya <dinesh.annayya@gmail.com>	Fri Nov 19 21:20:20 2021 +0530
committer	dineshannayya <dinesh.annayya@gmail.com>	Fri Nov 19 21:20:20 2021 +0530
tree	f306da5cd1908a4e5171ca0482c28567707d8117
parent	7e64246e9aeac33073daa9f5b9ef7b376d34d7b7 [diff]