#BUS_SORT | |
#MANUAL_PLACE | |
#N | |
cfg_cska_mbist\[3\] 0000 0 4 | |
cfg_cska_mbist\[2\] | |
cfg_cska_mbist\[1\] | |
cfg_cska_mbist\[0\] | |
wbd_clk_int | |
wbd_clk_mbist | |
wb_clk_i | |
rst_n | |
bist_en | |
bist_run | |
bist_shift | |
bist_load | |
bist_done | |
bist_error | |
bist_correct | |
bist_error_cnt\[3\] | |
bist_error_cnt\[2\] | |
bist_error_cnt\[1\] | |
bist_error_cnt\[0\] | |
bist_sdi | |
bist_sdo | |
#W | |
wb_cyc_i 0000 2 2 | |
wb_stb_i | |
wb_we_i | |
wb_adr_i\[7\] | |
wb_adr_i\[6\] | |
wb_adr_i\[5\] | |
wb_adr_i\[4\] | |
wb_adr_i\[3\] | |
wb_adr_i\[2\] | |
wb_adr_i\[1\] | |
wb_adr_i\[0\] | |
wb_dat_i\[31\] | |
wb_dat_i\[30\] | |
wb_dat_i\[29\] | |
wb_dat_i\[28\] | |
wb_dat_i\[27\] | |
wb_dat_i\[26\] | |
wb_dat_i\[25\] | |
wb_dat_i\[24\] | |
wb_dat_i\[23\] | |
wb_dat_i\[22\] | |
wb_dat_i\[21\] | |
wb_dat_i\[20\] | |
wb_dat_i\[19\] | |
wb_dat_i\[18\] | |
wb_dat_i\[17\] | |
wb_dat_i\[16\] | |
wb_dat_i\[15\] | |
wb_dat_i\[14\] | |
wb_dat_i\[13\] | |
wb_dat_i\[12\] | |
wb_dat_i\[11\] | |
wb_dat_i\[10\] | |
wb_dat_i\[9\] | |
wb_dat_i\[8\] | |
wb_dat_i\[7\] | |
wb_dat_i\[6\] | |
wb_dat_i\[5\] | |
wb_dat_i\[4\] | |
wb_dat_i\[3\] | |
wb_dat_i\[2\] | |
wb_dat_i\[1\] | |
wb_dat_i\[0\] | |
wb_sel_i\[3\] | |
wb_sel_i\[2\] | |
wb_sel_i\[1\] | |
wb_sel_i\[0\] | |
wb_dat_o\[31\] | |
wb_dat_o\[30\] | |
wb_dat_o\[29\] | |
wb_dat_o\[28\] | |
wb_dat_o\[27\] | |
wb_dat_o\[26\] | |
wb_dat_o\[25\] | |
wb_dat_o\[24\] | |
wb_dat_o\[23\] | |
wb_dat_o\[22\] | |
wb_dat_o\[21\] | |
wb_dat_o\[20\] | |
wb_dat_o\[19\] | |
wb_dat_o\[18\] | |
wb_dat_o\[17\] | |
wb_dat_o\[16\] | |
wb_dat_o\[15\] | |
wb_dat_o\[14\] | |
wb_dat_o\[13\] | |
wb_dat_o\[12\] | |
wb_dat_o\[11\] | |
wb_dat_o\[10\] | |
wb_dat_o\[9\] | |
wb_dat_o\[8\] | |
wb_dat_o\[7\] | |
wb_dat_o\[6\] | |
wb_dat_o\[5\] | |
wb_dat_o\[4\] | |
wb_dat_o\[3\] | |
wb_dat_o\[2\] | |
wb_dat_o\[1\] | |
wb_dat_o\[0\] | |
wb_ack_o | |
wb_err_o | |
#E | |
mem_clk_b 0000 0 2 | |
mem_cen_b | |
mem_web_b | |
mem_mask_b\[0\] | |
mem_mask_b\[1\] | |
mem_mask_b\[2\] | |
mem_mask_b\[3\] | |
mem_addr_b\[0\] | |
mem_addr_b\[1\] | |
mem_addr_b\[2\] | |
mem_addr_b\[3\] | |
mem_addr_b\[4\] | |
mem_addr_b\[5\] | |
mem_addr_b\[6\] | |
mem_addr_b\[7\] | |
mem_din_b\[0\] | |
mem_din_b\[1\] | |
mem_din_b\[2\] | |
mem_din_b\[3\] | |
mem_din_b\[4\] | |
mem_din_b\[5\] | |
mem_din_b\[6\] | |
mem_din_b\[7\] | |
mem_din_b\[8\] | |
mem_din_b\[9\] | |
mem_din_b\[10\] | |
mem_din_b\[11\] | |
mem_din_b\[12\] | |
mem_din_b\[13\] | |
mem_din_b\[14\] | |
mem_din_b\[15\] | |
mem_din_b\[16\] | |
mem_din_b\[17\] | |
mem_din_b\[18\] | |
mem_din_b\[19\] | |
mem_din_b\[20\] | |
mem_din_b\[21\] | |
mem_din_b\[22\] | |
mem_din_b\[23\] | |
mem_din_b\[24\] | |
mem_din_b\[25\] | |
mem_din_b\[26\] | |
mem_din_b\[27\] | |
mem_din_b\[28\] | |
mem_din_b\[29\] | |
mem_din_b\[30\] | |
mem_din_b\[31\] | |
mem_dout_a\[0\] 0100 0 2 | |
mem_dout_a\[1\] | |
mem_dout_a\[2\] | |
mem_dout_a\[3\] | |
mem_dout_a\[4\] | |
mem_dout_a\[5\] | |
mem_dout_a\[6\] | |
mem_dout_a\[7\] | |
mem_dout_a\[8\] | |
mem_dout_a\[9\] | |
mem_dout_a\[10\] | |
mem_dout_a\[11\] | |
mem_dout_a\[12\] | |
mem_dout_a\[13\] | |
mem_dout_a\[14\] | |
mem_dout_a\[15\] | |
mem_dout_a\[16\] | |
mem_dout_a\[17\] | |
mem_dout_a\[18\] | |
mem_dout_a\[19\] | |
mem_dout_a\[20\] | |
mem_dout_a\[21\] | |
mem_dout_a\[22\] | |
mem_dout_a\[23\] | |
mem_dout_a\[24\] | |
mem_dout_a\[25\] | |
mem_dout_a\[26\] | |
mem_dout_a\[27\] | |
mem_dout_a\[28\] | |
mem_dout_a\[29\] | |
mem_dout_a\[30\] | |
mem_dout_a\[31\] | |
mem_clk_a 0200 0 2 | |
mem_cen_a | |
mem_addr_a\[7\] | |
mem_addr_a\[6\] | |
mem_addr_a\[5\] | |
mem_addr_a\[4\] | |
mem_addr_a\[3\] | |
mem_addr_a\[2\] | |
mem_addr_a\[1\] | |
mem_addr_a\[0\] |