Simulations/pre_synthesis/add.vcd

$date
	Tue Oct 19 09:16:28 2021
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
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$var wire 18 ( q [17:0] $end
$var wire 19 ) temp1 [18:0] $end
$var wire 19 * temp [18:0] $end
$var wire 19 + sum [18:0] $end
$var wire 19 , b [18:0] $end
$var wire 19 - a [18:0] $end
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#0
$dumpvars
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