tree: a1ebaa6ab44e31abcefaf704551c085011a96b06 [path history] [tgz]
  1. caravel/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. precheck_results/
  9. signoff/
  10. Simulations/
  11. spi/
  12. verilog/
  13. info.yaml
  14. LICENSE
  15. Makefile
  16. README.md
  17. README.md.bak
README.md

High Speed Adder

This projects aims to design an high speed adder based on recursive doubling technique and fabricate at the SKY130nm technology node.

Specifications

Inputs: in1, in2 each of 18 bits
        Mode for add/sub selection
Output: Sum which is of 19 bits.

Block Diagram

EDA Tools and Environment

Pre-Synthesis Simulation

Post-Synthesis Simulation

RTL to GDSII