commit: d2b79dbd8d5c7c1dbc34ccae3ef1603d3ff4d978
[log] [tgz]
author: abdullahyildiz <abdullah.yildiz@yongatek.com>
Sat Jun 12 17:25:07 2021 +0300
committer: abdullahyildiz <abdullah.yildiz@yongatek.com>
Sat Jun 12 17:25:07 2021 +0300
tree: 994c94da00cc44580ec0e8eb9dc8268760ce21cb
parent: c0dc05396ca537c9dc86875c494e6f0c802cf91d [diff]
parent: e796ddf270be3be480543ad6d9e7a4e578ec39dc [diff]

Merge branch 'main' of https://github.com/yongatek/caravel_yonga-lz4-decoder into main

tree: 994c94da00cc44580ec0e8eb9dc8268760ce21cb

README.md

YONGA-LZ4 Decoder

Table of contents

Overview
Simulation
Checklist for Open-MPW Submission

Overview

YONGA-LZ4 Decoder is an implementation of the decoder of the popular LZ4 compression algorithm.

Simulation

TBA

Checklist for Open-MPW Submission

[x] The project repo adheres to the same directory structure in this repo
[x] The project repo contain info.yaml at the project root
[x] Top level macro is named user_project_wrapper
[x] Full Chip Simulation passes for RTL and GL (gate-level)
[x] The hardened Macros are LVS and DRC clean
[x] The hardened user_project_wrapper adheres to the same pin order specified at pin_order
[x] XOR check passes with zero total difference.
[ ] Openlane summary reports are retained under ./signoff/