verilog: Fixing include path.

The include lines previously had,
`include "sky130_fd_sc_hd__o221a.pp.functional.v"`
but the actual filename is
`include "sky130_fd_sc_hd__o221a.functional.pp.v"`.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
150 files changed
tree: 69cd9ea3253996d4ff220796ac8038857631121f
  1. .gitignore
  2. LICENSE
  3. README.rst
  4. cells/
  5. models/
  6. tech/
  7. timing/