Cleanup trailing whitespace in DRC files. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
diff --git a/rules/klayout/drc/rule_decks/10v_ldnmos.drc b/rules/klayout/drc/rule_decks/10v_ldnmos.drc index e008dbc..2d2a76f 100644 --- a/rules/klayout/drc/rule_decks/10v_ldnmos.drc +++ b/rules/klayout/drc/rule_decks/10v_ldnmos.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -117,7 +117,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -126,12 +126,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -198,41 +198,41 @@ #================================================ #-------------------10V LDNMOS------------------- -#================================================ +#================================================ # Rule MDN.1: Min MVSD width (for litho purpose). is 1µm logger.info("Executing rule MDN.1") mdn1_l1 = mvsd.width(1.um, euclidian).polygons(0.001) mdn1_l1.output("MDN.1", "MDN.1 : Min MVSD width (for litho purpose). : 1µm") -mdn1_l1.forget +mdn1_l1.forget if CONNECTIVITY_RULES -logger.info("CONNECTIVITY_RULES section") +logger.info("CONNECTIVITY_RULES section") -connected_mdn_2a, unconnected_mdn_2b = conn_space(mvsd, 1, 2, euclidian) +connected_mdn_2a, unconnected_mdn_2b = conn_space(mvsd, 1, 2, euclidian) # Rule MDN.2a: Min MVSD space [Same Potential]. is 1µm logger.info("Executing rule MDN.2a") mdn2a_l1 = connected_mdn_2a mdn2a_l1.output("MDN.2a", "MDN.2a : Min MVSD space [Same Potential]. : 1µm") -mdn2a_l1.forget +mdn2a_l1.forget # Rule MDN.2b: Min MVSD space [Diff Potential]. is 2µm logger.info("Executing rule MDN.2b") mdn2b_l1 = unconnected_mdn_2b mdn2b_l1.output("MDN.2b", "MDN.2b : Min MVSD space [Diff Potential]. : 2µm") -mdn2b_l1.forget +mdn2b_l1.forget else -logger.info("CONNECTIVITY_RULES disabled section") +logger.info("CONNECTIVITY_RULES disabled section") # Rule MDN.2b: Min MVSD space [Diff Potential]. is 2µm logger.info("Executing rule MDN.2b") mdn2b_l1 = mvsd.space(2.um, euclidian).polygons(0.001) mdn2b_l1.output("MDN.2b", "MDN.2b : Min MVSD space [Diff Potential]. : 2µm") -mdn2b_l1.forget +mdn2b_l1.forget -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES gate_mdn = poly2.and(comp).inside(ldmos_xtor).inside(dualgate) # Rule MDN.3a: Min transistor channel length. is 0.6µm @@ -253,7 +253,7 @@ logger.info("Executing rule MDN.4a") mdn4a_l1 = gate_mdn.edges.not(mvsd).interacting(mvsd).width(4.um, euclidian).polygons(0.001) mdn4a_l1.output("MDN.4a", "MDN.4a : Min transistor channel width. : 4µm") -mdn4a_l1.forget +mdn4a_l1.forget # Rule MDN.4b: Max transistor channel width. logger.info("Executing rule MDN.4b") @@ -274,7 +274,7 @@ logger.info("Executing rule MDN.5aii") mdn5aii_l1 = pcomp.interacting(ncomp).inside(ldmos_xtor).inside(dualgate).not(nplus).separation(mvsd, 0.92.um, euclidian).polygons(0.001) mdn5aii_l1.output("MDN.5aii", "MDN.5aii : Min PCOMP (Pplus AND COMP) space to LDNMOS Drain MVSD (source and body tap butted). PCOMP (Pplus AND COMP) intercept with LDNMOS Drain MVSD is not allowed. : 0.92µm") -mdn5aii_l1.forget +mdn5aii_l1.forget ncomp_mdn5b = ncomp.inside(ldmos_xtor).inside(dualgate) pcomp_mdn5b = pcomp.inside(ldmos_xtor).inside(dualgate) @@ -286,7 +286,7 @@ ncomp_mdn5b.forget pcomp_mdn5b.forget -mdn_5c_ncompsd = ncomp.inside(ldmos_xtor).inside(dualgate).interacting(mvsd).sized(0.36.um).sized(-0.36.um).extents +mdn_5c_ncompsd = ncomp.inside(ldmos_xtor).inside(dualgate).interacting(mvsd).sized(0.36.um).sized(-0.36.um).extents mdn_5c_error = mdn_5c_ncompsd.edges.centers(0, 0.99).not_interacting(mdn_5c_ncompsd.drc(separation(pcomp, euclidian) <= 15.um).polygons(0.001)) # Rule MDN.5c: Maximum distance of the nearest edge of the substrate tab from NCOMP edge. is 15µm logger.info("Executing rule MDN.5c") @@ -321,9 +321,9 @@ mdn7a_l1.forget if CONNECTIVITY_RULES -logger.info("CONNECTIVITY_RULES section") +logger.info("CONNECTIVITY_RULES section") -connected_mdn_8a, unconnected_mdn_8b = conn_separation(mvsd, nwell, 1, 2, euclidian) +connected_mdn_8a, unconnected_mdn_8b = conn_separation(mvsd, nwell, 1, 2, euclidian) # Rule MDN.8a: Min LDNMOS drain MVSD space to any other equal potential Nwell space. logger.info("Executing rule MDN.8a") @@ -338,7 +338,7 @@ mdn8b_l1.forget else -logger.info("CONNECTIVITY_RULES disabled section") +logger.info("CONNECTIVITY_RULES disabled section") # Rule MDN.8b: Min LDNMOS drain MVSD space to any other different potential Nwell space. logger.info("Executing rule MDN.8b") @@ -346,13 +346,13 @@ mdn8b_l1.output("MDN.8b", "MDN.8b : Min LDNMOS drain MVSD space to any other different potential Nwell space.") mdn8b_l1.forget -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES # Rule MDN.9: Min LDNMOS drain MVSD space to NCOMP (Nplus AND COMP) outside LDNMOS drain MVSD. is 4µm logger.info("Executing rule MDN.9") mdn9_l1 = mvsd.inside(dualgate).inside(ldmos_xtor).separation(ncomp.not_interacting(mvsd), 4.um, euclidian).polygons(0.001) mdn9_l1.output("MDN.9", "MDN.9 : Min LDNMOS drain MVSD space to NCOMP (Nplus AND COMP) outside LDNMOS drain MVSD. : 4µm") -mdn9_l1.forget +mdn9_l1.forget # rule MDN.10 is not a DRC check @@ -361,7 +361,7 @@ logger.info("Executing rule MDN.10a") mdn10a_l1 = poly_mdn10.width(1.2.um, euclidian).polygons(0.001) mdn10a_l1.output("MDN.10a", "MDN.10a : Min LDNMOS POLY2 width. : 1.2µm") -mdn10a_l1.forget +mdn10a_l1.forget # Rule MDN.10b: Min POLY2 extension beyond COMP in the width direction of the transistor (other than the LDNMOS drain direction). is 0.4µm logger.info("Executing rule MDN.10b") @@ -405,7 +405,7 @@ logger.info("Executing rule MDN.10eii") mdn10eii_l1 = poly_mdn10.separation(pcomp.not(nplus).interacting(ncomp.not(pplus)), 0.32.um, euclidian).polygons(0.001) mdn10eii_l1.output("MDN.10eii", "MDN.10eii : Min POLY2 space to Psub tap (source and body tap butted). : 0.32µm") -mdn10eii_l1.forget +mdn10eii_l1.forget # Rule MDN.10f: Poly2 interconnect in HV region (LDMOS_XTOR marked region) not allowed. Also, any Poly2 interconnect with poly2 to substrate potential greater than 6V is not allowed. logger.info("Executing rule MDN.10f") @@ -486,7 +486,7 @@ logger.info("Executing rule MDN.15a") mdn15a_l1 = comp.inside(mvsd).inside(dualgate).inside(ldmos_xtor).width(0.22.um, euclidian).polygons(0.001) mdn15a_l1.output("MDN.15a", "MDN.15a : Min LDNMOS drain COMP width. : 0.22µm") -mdn15a_l1.forget +mdn15a_l1.forget # Rule MDN.15b: Min LDNMOS drain COMP enclose contact. is 0µm logger.info("Executing rule MDN.15b")
diff --git a/rules/klayout/drc/rule_decks/10v_ldpmos.drc b/rules/klayout/drc/rule_decks/10v_ldpmos.drc index c9a1ac4..c09453d 100644 --- a/rules/klayout/drc/rule_decks/10v_ldpmos.drc +++ b/rules/klayout/drc/rule_decks/10v_ldpmos.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -118,7 +118,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -127,12 +127,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -224,7 +224,7 @@ connect(metal5, via5) connect(via5, metaltop) -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES #================================================ #------------ PRE-DEFINED FUNCTIONS ------------- @@ -250,7 +250,7 @@ end end unconnected_output = unconnected_errors.polygons.or(singularity_errors.polygons(0.001)) - return connected_output, unconnected_output + return connected_output, unconnected_output end def conn_separation(layer1, layer2, conn_val,not_conn_val, mode) @@ -279,10 +279,10 @@ if CONNECTIVITY_RULES logger.info("Connectivity rules enabled, Netlist object will be generated.") netlist -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES # === LAYOUT EXTENT === -CHIP = extent.sized(0.0) +CHIP = extent.sized(0.0) logger.info("Total area of the design is #{CHIP.area()} um^2.") @@ -290,7 +290,7 @@ #================================================ #-------------------10V LDPMOS------------------- -#================================================ +#================================================ mdp_source = (pcomp).interacting(poly2.and(dualgate).and(ldmos_xtor).and(mvpsd)).not(poly2) ldpmos = poly2.and(pcomp).and(dualgate).not(mvpsd).inside(ldmos_xtor) @@ -312,7 +312,7 @@ logger.info("Executing rule MDP.2") mdp2_l1 = poly2.and(comp).inside(ldmos_xtor).inside(dualgate).edges.not(mvpsd).interacting(mvpsd).width(4.um, euclidian).polygons(0.001) mdp2_l1.output("MDP.2", "MDP.2 : Minimum transistor channel width. : 4µm") -mdp2_l1.forget +mdp2_l1.forget mdp3_1 = ldpmos.or(mvpsd).or(mdp_source).not_interacting(ncomp.holes).inside(dualgate).inside(ldmos_xtor) mdp3_2 = ncomp.holes.not_interacting(ncomp.interacting(mdp_source)).not_interacting(mvpsd,1,1).inside(dualgate).inside(ldmos_xtor) @@ -344,7 +344,7 @@ logger.info("Executing rule MDP.3b") mdp3b_l1 = ncomp_mdp3b.not(poly2).not(mvpsd).separation(pcomp_mdp3b.not(poly2).not(mvpsd), 0.4.um, euclidian).polygons(0.001) mdp3b_l1.output("MDP.3b", "MDP.3b : Min NCOMP (Nplus AND COMP) space to PCOMP in DNWELL (Pplus AND COMP AND DNWELL). Use butted source and DNWELL contacts otherwise and that is best for Latch-up immunity as well. : 0.4µm") -mdp3b_l1.forget +mdp3b_l1.forget ncomp_mdp3b.forget pcomp_mdp3b.forget @@ -372,7 +372,7 @@ logger.info("Executing rule MDP.4a") mdp4a_l1 = pcomp.inside(ldmos_xtor).inside(dualgate).separation(dnwell.inside(ldmos_xtor).inside(dualgate), 2.5.um, euclidian).polygons(0.001) mdp4a_l1.output("MDP.4a", "MDP.4a : Min PCOMP (Pplus AND COMP) space to DNWELL. : 2.5µm") -mdp4a_l1.forget +mdp4a_l1.forget mdp4b_dnwell_edges = dnwell.inside(ldmos_xtor).inside(dualgate).edges.centers(0, 0.99) mdp4b_not_error = dnwell.drc(separation(pcomp.inside(ldmos_xtor.interacting(mvpsd)).inside(dualgate).not_interacting(mvpsd), euclidian) <= 15.um).polygons(0.001) @@ -416,19 +416,19 @@ logger.info("Executing rule MDP.7") mdp7_l1 = ldmos_xtor.separation(nwell.outside(ldmos_xtor), 2.um, euclidian).polygons(0.001) mdp7_l1.output("MDP.7", "MDP.7 : Minimum LDMOS_XTOR layer space to Nwell outside LDMOS_XTOR. : 2µm") -mdp7_l1.forget +mdp7_l1.forget # Rule MDP.8: Minimum LDMOS_XTOR layer space to NCOMP outside LDMOS_XTOR. is 1.5µm logger.info("Executing rule MDP.8") mdp8_l1 = ldmos_xtor.separation(ncomp.outside(ldmos_xtor), 1.5.um, euclidian).polygons(0.001) mdp8_l1.output("MDP.8", "MDP.8 : Minimum LDMOS_XTOR layer space to NCOMP outside LDMOS_XTOR. : 1.5µm") -mdp8_l1.forget +mdp8_l1.forget # Rule MDP.9a: Min LDPMOS POLY2 width. is 1.2µm logger.info("Executing rule MDP.9a") mdp9a_l1 = poly2.inside(dnwell.and(dualgate).and(ldmos_xtor)).width(1.2.um, euclidian).polygons(0.001) mdp9a_l1.output("MDP.9a", "MDP.9a : Min LDPMOS POLY2 width. : 1.2µm") -mdp9a_l1.forget +mdp9a_l1.forget mdp9b_1 = poly2.inside(dnwell.and(dualgate).and(ldmos_xtor)).edges.interacting(mvpsd).not(mvpsd).enclosing(comp.edges,0.4.um).edges mdp9b_2 = poly2.inside(dnwell.and(dualgate).and(ldmos_xtor)).edges.interacting(mvpsd).not(mvpsd).interacting(pcomp) @@ -490,32 +490,32 @@ mdp10_l1.forget if CONNECTIVITY_RULES -logger.info("CONNECTIVITY_RULES section") +logger.info("CONNECTIVITY_RULES section") -connected_mdp_10b, unconnected_mdp_10a = conn_space(mvpsd, 1, 2, euclidian) +connected_mdp_10b, unconnected_mdp_10a = conn_space(mvpsd, 1, 2, euclidian) # Rule MDP.10a: Min MVPSD space within LDMOS_XTOR marking [diff potential]. is 2µm logger.info("Executing rule MDP.10a") mdp10a_l1 = unconnected_mdp_10a mdp10a_l1.output("MDP.10a", "MDP.10a : Min MVPSD space within LDMOS_XTOR marking [diff potential]. : 2µm") -mdp10a_l1.forget +mdp10a_l1.forget # Rule MDP.10b: Min MVPSD space [same potential]. Merge if space less than 1um. is 1µm logger.info("Executing rule MDP.10b") mdp10b_l1 = connected_mdp_10b mdp10b_l1.output("MDP.10b", "MDP.10b : Min MVPSD space [same potential]. Merge if space less than 1um. : 1µm") -mdp10b_l1.forget +mdp10b_l1.forget else -logger.info("CONNECTIVITY_RULES disabled section") +logger.info("CONNECTIVITY_RULES disabled section") # Rule MDP.10a: Min MVPSD space within LDMOS_XTOR marking [diff potential]. is 2µm logger.info("Executing rule MDP.10a") mdp10a_l1 = mvpsd.space(2.um, euclidian).polygons(0.001) mdp10a_l1.output("MDP.10a", "MDP.10a : Min MVPSD space within LDMOS_XTOR marking [diff potential]. : 2µm") -mdp10a_l1.forget +mdp10a_l1.forget -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES # Rule MDP.11: Min MVPSD enclosing PCOMP in the drain (MVPSD AND COMP NOT POLY2) direction and in the direction along the transistor width. logger.info("Executing rule MDP.11") @@ -561,13 +561,13 @@ logger.info("Executing rule MDP.15") mdp15_l1 = dnwell.separation(dnwell.covering(mvpsd).inside(dualgate).inside(ldmos_xtor), 6.um, euclidian).polygons(0.001) mdp15_l1.output("MDP.15", "MDP.15 : Min DNWELL enclosing MVPSD to any DNWELL spacing. : 6µm") -mdp15_l1.forget +mdp15_l1.forget # Rule MDP.16a: Min LDPMOS drain COMP width. is 0.22µm logger.info("Executing rule MDP.16a") mdp16a_l1 = comp.inside(mvpsd).inside(dualgate).inside(ldmos_xtor).width(0.22.um, euclidian).polygons(0.001) mdp16a_l1.output("MDP.16a", "MDP.16a : Min LDPMOS drain COMP width. : 0.22µm") -mdp16a_l1.forget +mdp16a_l1.forget # Rule MDP.16b: Min LDPMOS drain COMP enclose contact. is 0µm logger.info("Executing rule MDP.16b")
diff --git a/rules/klayout/drc/rule_decks/3.3v_sram.drc b/rules/klayout/drc/rule_decks/3.3v_sram.drc index 19a496d..52cb68b 100644 --- a/rules/klayout/drc/rule_decks/3.3v_sram.drc +++ b/rules/klayout/drc/rule_decks/3.3v_sram.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -116,7 +116,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -125,12 +125,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -197,7 +197,7 @@ #================================================ #-------------------3.3V SRAM-------------------- -#================================================ +#================================================ # Rule S.DF.4c_LV: Min. (Nwell overlap of PCOMP) outside DNWELL. is 0.4µm logger.info("Executing rule S.DF.4c_LV") @@ -213,7 +213,7 @@ logger.info("Executing rule S.DF.16_LV") sdf16_l1 = ncomp.outside(nwell).outside(dnwell).inside(sramcore).separation(nwell.outside(dnwell).inside(sramcore), 0.4.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) sdf16_l1.output("S.DF.16_LV", "S.DF.16_LV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.4µm") -sdf16_l1.forget +sdf16_l1.forget # Rule S.CO.3_LV: Poly2 overlap of contact. is 0.04µm logger.info("Executing rule S.CO.3_LV") @@ -245,7 +245,7 @@ logger.info("Executing rule S.M1.1_LV") sm11_l1 = metal1.and(sramcore).width(0.22.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) sm11_l1.output("S.M1.1_LV", "S.M1.1_LV : min. metal1 width : 0.22µm") -sm11_l1.forget +sm11_l1.forget exec_end_time = Time.now
diff --git a/rules/klayout/drc/rule_decks/5v_sram.drc b/rules/klayout/drc/rule_decks/5v_sram.drc index db61f7a..cad6d54 100644 --- a/rules/klayout/drc/rule_decks/5v_sram.drc +++ b/rules/klayout/drc/rule_decks/5v_sram.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -116,7 +116,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -125,12 +125,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -197,7 +197,7 @@ #================================================ #--------------------5V SRAM--------------------- -#================================================ +#================================================ # Rule S.DF.4c_MV: Min. (Nwell overlap of PCOMP) outside DNWELL. is 0.45µm logger.info("Executing rule S.DF.4c_MV") @@ -219,7 +219,7 @@ logger.info("Executing rule S.DF.7_MV") sdf7_l1 = pcomp.inside(dnwell).inside(sramcore).separation(lvpwell.inside(dnwell).inside(sramcore), 0.45.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) sdf7_l1.output("S.DF.7_MV", "S.DF.7_MV : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.45µm") -sdf7_l1.forget +sdf7_l1.forget # Rule S.DF.8_MV: Min. (LVPWELL overlap of NCOMP) Inside DNWELL. is 0.45µm logger.info("Executing rule S.DF.8_MV") @@ -235,19 +235,19 @@ logger.info("Executing rule S.DF.16_MV") sdf16_l1 = ncomp.outside(nwell).outside(dnwell).inside(sramcore).separation(nwell.outside(dnwell).inside(sramcore), 0.45.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) sdf16_l1.output("S.DF.16_MV", "S.DF.16_MV : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.45µm") -sdf16_l1.forget +sdf16_l1.forget # Rule S.PL.5a_MV: Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. is 0.12µm logger.info("Executing rule S.PL.5a_MV") spl5a_l1 = poly2.inside(sramcore).separation(comp.inside(sramcore), 0.12.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) spl5a_l1.output("S.PL.5a_MV", "S.PL.5a_MV : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.12µm") -spl5a_l1.forget +spl5a_l1.forget # Rule S.PL.5b_MV: Space from field Poly2 to related COMP. is 0.12µm logger.info("Executing rule S.PL.5b_MV") spl5b_l1 = poly2.inside(sramcore).separation(comp.inside(sramcore), 0.12.um, euclidian).polygons(0.001).overlapping(v5_xtor).overlapping(dualgate) spl5b_l1.output("S.PL.5b_MV", "S.PL.5b_MV : Space from field Poly2 to related COMP. : 0.12µm") -spl5b_l1.forget +spl5b_l1.forget # Rule S.CO.4_MV: COMP overlap of contact. is 0.04µm logger.info("Executing rule S.CO.4_MV")
diff --git a/rules/klayout/drc/rule_decks/comp.drc b/rules/klayout/drc/rule_decks/comp.drc index 0f9cba1..080bb31 100644 --- a/rules/klayout/drc/rule_decks/comp.drc +++ b/rules/klayout/drc/rule_decks/comp.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -125,7 +125,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -134,12 +134,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -206,7 +206,7 @@ #================================================ #----------------------COMP---------------------- -#================================================ +#================================================ if FEOL @@ -222,13 +222,13 @@ logger.info("Executing rule DF.1a_3.3V") df1a_l1 = comp.width(0.22.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) df1a_l1.output("DF.1a_3.3V", "DF.1a_3.3V : Min. COMP Width. : 0.22µm") -df1a_l1.forget +df1a_l1.forget # Rule DF.1a_5V: Min. COMP Width. is 0.3µm logger.info("Executing rule DF.1a_5V") df1a_l1 = comp.not_inside(mvsd).not_inside(mvpsd).width(0.3.um, euclidian).polygons(0.001).overlapping(dualgate) df1a_l1.output("DF.1a_5V", "DF.1a_5V : Min. COMP Width. : 0.3µm") -df1a_l1.forget +df1a_l1.forget # rule DF.1b_3.3V is not a DRC check @@ -238,13 +238,13 @@ logger.info("Executing rule DF.1c_3.3V") df1c_l1 = comp.and(mos_cap_mk).width(1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) df1c_l1.output("DF.1c_3.3V", "DF.1c_3.3V : Min. COMP Width for MOSCAP. : 1µm") -df1c_l1.forget +df1c_l1.forget # Rule DF.1c_5V: Min. COMP Width for MOSCAP. is 1µm logger.info("Executing rule DF.1c_5V") df1c_l1 = comp.and(mos_cap_mk).width(1.um, euclidian).polygons(0.001).overlapping(dualgate) df1c_l1.output("DF.1c_5V", "DF.1c_5V : Min. COMP Width for MOSCAP. : 1µm") -df1c_l1.forget +df1c_l1.forget df_2a = comp.not(poly2).edges.and(tgate.edges) # Rule DF.2a_3.3V: Min Channel Width. is nil,0.22µm @@ -278,13 +278,13 @@ logger.info("Executing rule DF.3a_3.3V") df3a_l1 = comp.not(otp_mk).space(0.28.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) df3a_l1.output("DF.3a_3.3V", "DF.3a_3.3V : Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. : 0.28µm") -df3a_l1.forget +df3a_l1.forget # Rule DF.3a_5V: Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. is 0.36µm logger.info("Executing rule DF.3a_5V") df3a_l1 = comp.not(otp_mk).space(0.36.um, euclidian).polygons(0.001).overlapping(dualgate) df3a_l1.output("DF.3a_5V", "DF.3a_5V : Min. COMP Space P-substrate tap (PCOMP outside NWELL and DNWELL) can be butted for different voltage devices as the potential is same. : 0.36µm") -df3a_l1.forget +df3a_l1.forget df_3b_same_well = ncomp.inside(nwell).not_outside(pcomp.inside(nwell)).or(ncomp.inside(lvpwell).not_outside(pcomp.inside(lvpwell))) df_3b_moscap = ncomp.inside(nwell).interacting(pcomp.inside(nwell)).or(ncomp.inside(lvpwell).interacting(pcomp.inside(lvpwell))).inside(mos_cap_mk) @@ -306,7 +306,7 @@ logger.info("Executing rule DF.3c_3.3V") df3c_l1 = comp.inside(drc_bjt).space(0.32.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) df3c_l1.output("DF.3c_3.3V", "DF.3c_3.3V : Min. COMP Space in BJT area (area marked by DRC_BJT layer). : 0.32µm") -df3c_l1.forget +df3c_l1.forget # Rule DF.3c_5V: Min. COMP Space in BJT area (area marked by DRC_BJT layer) hasn’t been assessed. logger.info("Executing rule DF.3c_5V") @@ -319,13 +319,13 @@ logger.info("Executing rule DF.4a_3.3V") df4a_l1 = ntap_dnwell.separation(lvpwell.inside(dnwell), 0.12.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) df4a_l1.output("DF.4a_3.3V", "DF.4a_3.3V : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.12µm") -df4a_l1.forget +df4a_l1.forget # Rule DF.4a_5V: Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. is 0.16µm logger.info("Executing rule DF.4a_5V") df4a_l1 = ntap_dnwell.separation(lvpwell.inside(dnwell), 0.16.um, euclidian).polygons(0.001).overlapping(dualgate) df4a_l1.output("DF.4a_5V", "DF.4a_5V : Min. (LVPWELL Space to NCOMP well tap) inside DNWELL. : 0.16µm") -df4a_l1.forget +df4a_l1.forget # Rule DF.4b_3.3V: Min. DNWELL overlap of NCOMP well tap. is 0.62µm logger.info("Executing rule DF.4b_3.3V") @@ -447,13 +447,13 @@ logger.info("Executing rule DF.7_3.3V") df7_l1 = pcomp.inside(dnwell).separation(pwell_dnwell, 0.43.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) df7_l1.output("DF.7_3.3V", "DF.7_3.3V : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.43µm") -df7_l1.forget +df7_l1.forget # Rule DF.7_5V: Min. (LVPWELL Spacer to PCOMP) inside DNWELL. is 0.6µm logger.info("Executing rule DF.7_5V") df7_l1 = pcomp.inside(dnwell).outside(sramcore).separation(pwell_dnwell, 0.6.um, euclidian).polygons(0.001).overlapping(dualgate) df7_l1.output("DF.7_5V", "DF.7_5V : Min. (LVPWELL Spacer to PCOMP) inside DNWELL. : 0.6µm") -df7_l1.forget +df7_l1.forget # Rule DF.8_3.3V: Min. (LVPWELL overlap of NCOMP) Inside DNWELL. is 0.43µm logger.info("Executing rule DF.8_3.3V") @@ -480,34 +480,34 @@ logger.info("Executing rule DF.9_3.3V") df9_l1 = comp.not(otp_mk).with_area(nil, 0.2025.um).not_interacting(v5_xtor).not_interacting(dualgate) df9_l1.output("DF.9_3.3V", "DF.9_3.3V : Min. COMP area (um2). : 0.2025µm²") -df9_l1.forget +df9_l1.forget # Rule DF.9_5V: Min. COMP area (um2). is 0.2025µm² logger.info("Executing rule DF.9_5V") df9_l1 = comp.not(otp_mk).with_area(nil, 0.2025.um).overlapping(dualgate) df9_l1.output("DF.9_5V", "DF.9_5V : Min. COMP area (um2). : 0.2025µm²") -df9_l1.forget +df9_l1.forget # Rule DF.10_3.3V: Min. field area (um2). is 0.26µm² logger.info("Executing rule DF.10_3.3V") df10_l1 = comp.holes.not(comp).with_area(nil, 0.26.um).not_interacting(v5_xtor).not_interacting(dualgate) df10_l1.output("DF.10_3.3V", "DF.10_3.3V : Min. field area (um2). : 0.26µm²") -df10_l1.forget +df10_l1.forget # Rule DF.10_5V: Min. field area (um2). is 0.26µm² logger.info("Executing rule DF.10_5V") df10_l1 = comp.holes.not(comp).with_area(nil, 0.26.um).overlapping(dualgate) df10_l1.output("DF.10_5V", "DF.10_5V : Min. field area (um2). : 0.26µm²") -df10_l1.forget +df10_l1.forget comp_butt = comp.interacting(ncomp.interacting(pcomp).outside(pcomp)) # Rule DF.11_3.3V: Min. Length of butting COMP edge. is 0.3µm logger.info("Executing rule DF.11_3.3V") df11_l1 = comp_butt.width(0.3.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) df11_l1.output("DF.11_3.3V", "DF.11_3.3V : Min. Length of butting COMP edge. : 0.3µm") -df11_l1.forget +df11_l1.forget # Rule DF.11_5V: Min. Length of butting COMP edge. is 0.3µm logger.info("Executing rule DF.11_5V") df11_l1 = comp_butt.width(0.3.um, euclidian).polygons(0.001).overlapping(dualgate) df11_l1.output("DF.11_5V", "DF.11_5V : Min. Length of butting COMP edge. : 0.3µm") -df11_l1.forget +df11_l1.forget comp_butt.forget # Rule DF.12_3.3V: COMP not covered by Nplus or Pplus is forbidden (except those COMP under marking). @@ -563,51 +563,51 @@ logger.info("Executing rule DF.16_3.3V") df16_l1 = ncomp_df16.not_inside(ymtp_mk).outside(sramcore).separation(nwell.outside(dnwell).not_inside(ymtp_mk), 0.43.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) df16_l1.output("DF.16_3.3V", "DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.43µm") -df16_l1.forget +df16_l1.forget # Rule DF.16_5V: Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). is 0.6µm logger.info("Executing rule DF.16_5V") df16_l1 = ncomp_df16.not_inside(ymtp_mk).outside(sramcore).separation(nwell.outside(dnwell).not_inside(ymtp_mk), 0.6.um, euclidian).polygons(0.001).overlapping(dualgate) df16_l1.output("DF.16_5V", "DF.16_5V : Min. space from (Nwell outside DNWELL) to (NCOMP outside Nwell and DNWELL). : 0.6µm") -df16_l1.forget +df16_l1.forget pcomp_df17 = pcomp.outside(nwell).outside(dnwell) # Rule DF.17_3.3V: Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). is 0.12µm logger.info("Executing rule DF.17_3.3V") df17_l1 = pcomp_df17.separation(nwell.outside(dnwell), 0.12.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) df17_l1.output("DF.17_3.3V", "DF.17_3.3V : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.12µm") -df17_l1.forget +df17_l1.forget # Rule DF.17_5V: Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). is 0.16µm logger.info("Executing rule DF.17_5V") df17_l1 = pcomp_df17.separation(nwell.outside(dnwell), 0.16.um, euclidian).polygons(0.001).overlapping(dualgate) df17_l1.output("DF.17_5V", "DF.17_5V : Min. space from (Nwell Outside DNWELL) to (PCOMP outside Nwell and DNWELL). : 0.16µm") -df17_l1.forget +df17_l1.forget # Rule DF.18_3.3V: Min. DNWELL space to (PCOMP outside Nwell and DNWELL). is 2.5µm logger.info("Executing rule DF.18_3.3V") df18_l1 = pcomp_df17.separation(dnwell, 2.5.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) df18_l1.output("DF.18_3.3V", "DF.18_3.3V : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm") -df18_l1.forget +df18_l1.forget # Rule DF.18_5V: Min. DNWELL space to (PCOMP outside Nwell and DNWELL). is 2.5µm logger.info("Executing rule DF.18_5V") df18_l1 = pcomp_df17.separation(dnwell, 2.5.um, euclidian).polygons(0.001).overlapping(dualgate) df18_l1.output("DF.18_5V", "DF.18_5V : Min. DNWELL space to (PCOMP outside Nwell and DNWELL). : 2.5µm") -df18_l1.forget +df18_l1.forget pcomp_df17.forget # Rule DF.19_3.3V: Min. DNWELL space to (NCOMP outside Nwell and DNWELL). is 3.2µm logger.info("Executing rule DF.19_3.3V") df19_l1 = ncomp_df16.separation(dnwell, 3.2.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) df19_l1.output("DF.19_3.3V", "DF.19_3.3V : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.2µm") -df19_l1.forget +df19_l1.forget # Rule DF.19_5V: Min. DNWELL space to (NCOMP outside Nwell and DNWELL). is 3.28µm logger.info("Executing rule DF.19_5V") df19_l1 = ncomp_df16.separation(dnwell, 3.28.um, euclidian).polygons(0.001).overlapping(dualgate) df19_l1.output("DF.19_5V", "DF.19_5V : Min. DNWELL space to (NCOMP outside Nwell and DNWELL). : 3.28µm") -df19_l1.forget +df19_l1.forget ncomp_df16.forget
diff --git a/rules/klayout/drc/rule_decks/contact.drc b/rules/klayout/drc/rule_decks/contact.drc index 0c126a3..8142221 100644 --- a/rules/klayout/drc/rule_decks/contact.drc +++ b/rules/klayout/drc/rule_decks/contact.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -117,7 +117,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -126,12 +126,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -198,7 +198,7 @@ #================================================ #--------------------CONTACT--------------------- -#================================================ +#================================================ if FEOL @@ -214,7 +214,7 @@ logger.info("Executing rule CO.2a") co2a_l1 = contact.space(0.25.um, euclidian).polygons(0.001) co2a_l1.output("CO.2a", "CO.2a : min. contact spacing : 0.25µm") -co2a_l1.forget +co2a_l1.forget merged_co1 = contact.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.63.um , nil).extents.inside(metal1) contact_mask = merged_co1.size(1).not(contact).with_holes(16, nil) @@ -223,7 +223,7 @@ logger.info("Executing rule CO.2b") co2b_l1 = selected_co1.space(0.28.um, euclidian).polygons(0.001) co2b_l1.output("CO.2b", "CO.2b : Space in 4x4 or larger contact array. : 0.28µm") -co2b_l1.forget +co2b_l1.forget merged_co1.forget contact_mask.forget @@ -306,13 +306,13 @@ logger.info("Executing rule CO.7") co7_l1 = contact.not_outside(comp).not(otp_mk).separation(tgate.not(otp_mk), 0.15.um, euclidian).polygons(0.001) co7_l1.output("CO.7", "CO.7 : Space from COMP contact to Poly2 on COMP. : 0.15µm") -co7_l1.forget +co7_l1.forget # Rule CO.8: Space from Poly2 contact to COMP. is 0.17µm logger.info("Executing rule CO.8") co8_l1 = contact.not_outside(poly2).separation(comp, 0.17.um, euclidian).polygons(0.001) co8_l1.output("CO.8", "CO.8 : Space from Poly2 contact to COMP. : 0.17µm") -co8_l1.forget +co8_l1.forget # Rule CO.9: Contact on NCOMP to PCOMP butting edge is forbidden (contact must not straddle butting edge). logger.info("Executing rule CO.9") @@ -332,10 +332,10 @@ co11_l1.output("CO.11", "CO.11 : Contact on field oxide is forbidden.") co11_l1.forget -end #FEOL +end #FEOL if BEOL -logger.info("BEOL section") +logger.info("BEOL section") end #FEOL
diff --git a/rules/klayout/drc/rule_decks/dnwell.drc b/rules/klayout/drc/rule_decks/dnwell.drc index 5ca48e0..c989465 100644 --- a/rules/klayout/drc/rule_decks/dnwell.drc +++ b/rules/klayout/drc/rule_decks/dnwell.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -115,7 +115,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -124,12 +124,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -221,7 +221,7 @@ connect(metal5, via5) connect(via5, metaltop) -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES #================================================ #------------ PRE-DEFINED FUNCTIONS ------------- @@ -247,7 +247,7 @@ end end unconnected_output = unconnected_errors.polygons.or(singularity_errors.polygons(0.001)) - return connected_output, unconnected_output + return connected_output, unconnected_output end def conn_separation(layer1, layer2, conn_val,not_conn_val, mode) @@ -276,10 +276,10 @@ if CONNECTIVITY_RULES logger.info("Connectivity rules enabled, Netlist object will be generated.") netlist -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES # === LAYOUT EXTENT === -CHIP = extent.sized(0.0) +CHIP = extent.sized(0.0) logger.info("Total area of the design is #{CHIP.area()} um^2.") @@ -287,7 +287,7 @@ #================================================ #---------------------DNWELL--------------------- -#================================================ +#================================================ if FEOL @@ -297,35 +297,35 @@ logger.info("Executing rule DN.1") dn1_l1 = dnwell.width(1.7.um, euclidian).polygons(0.001) dn1_l1.output("DN.1", "DN.1 : Min. DNWELL Width : 1.7µm") -dn1_l1.forget +dn1_l1.forget if CONNECTIVITY_RULES -logger.info("CONNECTIVITY_RULES section") +logger.info("CONNECTIVITY_RULES section") -connected_dnwell, unconnected_dnwell = conn_space(dnwell, 2.5, 5.42, euclidian) +connected_dnwell, unconnected_dnwell = conn_space(dnwell, 2.5, 5.42, euclidian) # Rule DN.2a: Min. DNWELL Space (Equi-potential), Merge if the space is less than is 2.5µm logger.info("Executing rule DN.2a") dn2a_l1 = connected_dnwell dn2a_l1.output("DN.2a", "DN.2a : Min. DNWELL Space (Equi-potential), Merge if the space is less than : 2.5µm") -dn2a_l1.forget +dn2a_l1.forget # Rule DN.2b: Min. DNWELL Space (Different potential) is 5.42µm logger.info("Executing rule DN.2b") dn2b_l1 = unconnected_dnwell dn2b_l1.output("DN.2b", "DN.2b : Min. DNWELL Space (Different potential) : 5.42µm") -dn2b_l1.forget +dn2b_l1.forget else -logger.info("CONNECTIVITY_RULES disabled section") +logger.info("CONNECTIVITY_RULES disabled section") # Rule DN.2b_: Min. DNWELL Space (Different potential) is 5.42µm logger.info("Executing rule DN.2b_") dn2b_l1 = dnwell.isolated(5.42.um, euclidian).polygons(0.001) dn2b_l1.output("DN.2b_", "DN.2b_ : Min. DNWELL Space (Different potential) : 5.42µm") -dn2b_l1.forget +dn2b_l1.forget -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES dn3_1 = dnwell.not_inside(pcomp.holes.not(pcomp).interacting(dnwell, 1..1).extents) dn3_2 = dnwell.inside((pcomp.holes.not(pcomp).covering(nat.or(ncomp).or(nwell).not_interacting(dnwell))))
diff --git a/rules/klayout/drc/rule_decks/drc_bjt.drc b/rules/klayout/drc/rule_decks/drc_bjt.drc index 1100840..4c77867 100644 --- a/rules/klayout/drc/rule_decks/drc_bjt.drc +++ b/rules/klayout/drc/rule_decks/drc_bjt.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -114,7 +114,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -123,12 +123,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -195,7 +195,7 @@ #================================================ #--------------------DRC_BJT--------------------- -#================================================ +#================================================ # Rule BJT.1: Min. DRC_BJT overlap of DNWELL for NPN BJT. logger.info("Executing rule BJT.1") @@ -213,7 +213,7 @@ logger.info("Executing rule BJT.3") bjt3_l1 = comp.outside(drc_bjt).separation(drc_bjt, 0.1.um, euclidian).polygons(0.001) bjt3_l1.output("BJT.3", "BJT.3 : Minimum space of DRC_BJT layer to unrelated COMP. : 0.1µm") -bjt3_l1.forget +bjt3_l1.forget exec_end_time = Time.now
diff --git a/rules/klayout/drc/rule_decks/dualgate.drc b/rules/klayout/drc/rule_decks/dualgate.drc index 064c91c..5cba8db 100644 --- a/rules/klayout/drc/rule_decks/dualgate.drc +++ b/rules/klayout/drc/rule_decks/dualgate.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -113,7 +113,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -122,12 +122,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -194,7 +194,7 @@ #================================================ #--------------------DUALGATE-------------------- -#================================================ +#================================================ if FEOL @@ -214,13 +214,13 @@ logger.info("Executing rule DV.2") dv2_l1 = dualgate.space(0.44.um, euclidian).polygons(0.001) dv2_l1.output("DV.2", "DV.2 : Min. Dualgate Space. Merge if Space is less than this design rule. : 0.44µm") -dv2_l1.forget +dv2_l1.forget # Rule DV.3: Min. Dualgate to COMP space [unrelated]. is 0.24µm logger.info("Executing rule DV.3") dv3_l1 = dualgate.separation(comp.outside(dualgate), 0.24.um, euclidian).polygons(0.001) dv3_l1.output("DV.3", "DV.3 : Min. Dualgate to COMP space [unrelated]. : 0.24µm") -dv3_l1.forget +dv3_l1.forget # rule DV.4 is not a DRC check @@ -228,7 +228,7 @@ logger.info("Executing rule DV.5") dv5_l1 = dualgate.width(0.7.um, euclidian).polygons(0.001) dv5_l1.output("DV.5", "DV.5 : Min. Dualgate width. : 0.7µm") -dv5_l1.forget +dv5_l1.forget comp_dv = comp.not(pcomp.outside(nwell)) # Rule DV.6: Min. Dualgate enclose COMP (except substrate tap). is 0.24µm
diff --git a/rules/klayout/drc/rule_decks/dummy_exclude_layers.drc b/rules/klayout/drc/rule_decks/dummy_exclude_layers.drc index b057a84..0858f56 100644 --- a/rules/klayout/drc/rule_decks/dummy_exclude_layers.drc +++ b/rules/klayout/drc/rule_decks/dummy_exclude_layers.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -113,7 +113,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -122,12 +122,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -194,7 +194,7 @@ #================================================ #--------------DUMMY EXCLUDE LAYERS-------------- -#================================================ +#================================================ # rule DE.1 is not a DRC check @@ -202,7 +202,7 @@ logger.info("Executing rule DE.2") de2_l1 = ndmy.or(pmndmy).width(0.8.um, euclidian).polygons(0.001) de2_l1.output("DE.2", "DE.2 : Minimum NDMY or PMNDMY size (x or y dimension in um). : 0.8µm") -de2_l1.forget +de2_l1.forget de3_ndmy_area = ndmy.with_area(15000.um, nil) # Rule DE.3: If size greater than 15000 um2 then two sides should not be greater than (um). @@ -216,7 +216,7 @@ logger.info("Executing rule DE.4") de4_l1 = ndmy.space(20.um, euclidian).polygons(0.001) de4_l1.output("DE.4", "DE.4 : Minimum NDMY to NDMY space (Merge if space is less). : 20µm") -de4_l1.forget +de4_l1.forget exec_end_time = Time.now
diff --git a/rules/klayout/drc/rule_decks/efuse.drc b/rules/klayout/drc/rule_decks/efuse.drc index 421a281..237c5a7 100644 --- a/rules/klayout/drc/rule_decks/efuse.drc +++ b/rules/klayout/drc/rule_decks/efuse.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -120,7 +120,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -129,12 +129,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -201,7 +201,7 @@ #================================================ #---------------------EFUSE---------------------- -#================================================ +#================================================ # Rule EF.01: Min. (Poly2 butt PLFUSE) within EFUSE_MK and Pplus. logger.info("Executing rule EF.01") @@ -283,13 +283,13 @@ logger.info("Executing rule EF.10") ef10_l1 = cathode.space(0.26.um, euclidian).polygons(0.001) ef10_l1.output("EF.10", "EF.10 : Min. Cathode Poly2 to Poly2 space. : 0.26µm") -ef10_l1.forget +ef10_l1.forget # Rule EF.11: Min. Anode Poly2 to Poly2 space. is 0.26µm logger.info("Executing rule EF.11") ef11_l1 = anode.space(0.26.um, euclidian).polygons(0.001) ef11_l1.output("EF.11", "EF.11 : Min. Anode Poly2 to Poly2 space. : 0.26µm") -ef11_l1.forget +ef11_l1.forget cont_ef = contact.and(plfuse.inside(efuse_mk)) # Rule EF.12: Min. Space of Cathode Contact to PLFUSE end. @@ -333,7 +333,7 @@ logger.info("Executing rule EF.17") ef17_l1 = efuse_mk.space(0.26.um, euclidian).polygons(0.001) ef17_l1.output("EF.17", "EF.17 : Min. Space of EFUSE_MK to EFUSE_MK. : 0.26µm") -ef17_l1.forget +ef17_l1.forget # Rule EF.18: PLFUSE must sit on field oxide (NOT COMP), no cross with any COMP, Nplus, Pplus, ESD, SAB, Resistor, Metal1, Metal2. logger.info("Executing rule EF.18") @@ -351,7 +351,7 @@ logger.info("Executing rule EF.20") ef20_l1 = plfuse.separation(comp.or(nplus).or(esd).or(sab).or(resistor), 2.73.um, euclidian).polygons(0.001) ef20_l1.output("EF.20", "EF.20 : Min. PLFUSE space to COMP, Nplus, Pplus, Resistor, ESD, SAB. : 2.73µm") -ef20_l1.forget +ef20_l1.forget ef_21_fuse = poly2.interacting(plfuse).inside(efuse_mk.and(pplus)).extents.edges ef_21_anode = anode.edges.not_interacting(anode.edges.interacting(plfuse))
diff --git a/rules/klayout/drc/rule_decks/esd.drc b/rules/klayout/drc/rule_decks/esd.drc index bbd2533..2744944 100644 --- a/rules/klayout/drc/rule_decks/esd.drc +++ b/rules/klayout/drc/rule_decks/esd.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -113,7 +113,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -122,12 +122,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -194,7 +194,7 @@ #================================================ #----------------------ESD----------------------- -#================================================ +#================================================ if FEOL @@ -204,19 +204,19 @@ logger.info("Executing rule ESD.1") esd1_l1 = esd.width(0.6.um, euclidian).polygons(0.001) esd1_l1.output("ESD.1", "ESD.1 : Minimum width of an ESD implant area. : 0.6µm") -esd1_l1.forget +esd1_l1.forget # Rule ESD.2: Minimum space between two ESD implant areas. (Merge if the space is less than 0.6um). is 0.6µm logger.info("Executing rule ESD.2") esd2_l1 = esd.space(0.6.um, euclidian).polygons(0.001) esd2_l1.output("ESD.2", "ESD.2 : Minimum space between two ESD implant areas. (Merge if the space is less than 0.6um). : 0.6µm") -esd2_l1.forget +esd2_l1.forget # Rule ESD.3a: Minimum space to NCOMP. is 0.6µm logger.info("Executing rule ESD.3a") esd3a_l1 = esd.separation(ncomp, 0.6.um, euclidian).polygons(0.001) esd3a_l1.output("ESD.3a", "ESD.3a : Minimum space to NCOMP. : 0.6µm") -esd3a_l1.forget +esd3a_l1.forget # Rule ESD.3b: Min/max space to a butted PCOMP. logger.info("Executing rule ESD.3b") @@ -234,18 +234,18 @@ logger.info("Executing rule ESD.4b") esd4b_l1 = esd.overlap(comp, 0.45.um, euclidian).polygons(0.001) esd4b_l1.output("ESD.4b", "ESD.4b : Minimum overlap of an ESD implant edge to a COMP. : 0.45µm") -esd4b_l1.forget +esd4b_l1.forget # Rule ESD.5a: Minimum ESD area (um2). is 0.49µm² logger.info("Executing rule ESD.5a") esd5a_l1 = esd.with_area(nil, 0.49.um) esd5a_l1.output("ESD.5a", "ESD.5a : Minimum ESD area (um2). : 0.49µm²") -esd5a_l1.forget +esd5a_l1.forget # Rule ESD.5b: Minimum field area enclosed by ESD implant (um2). is 0.49µm² logger.info("Executing rule ESD.5b") esd5b_l1 = esd.holes.with_area(nil, 0.49.um) esd5b_l1.output("ESD.5b", "ESD.5b : Minimum field area enclosed by ESD implant (um2). : 0.49µm²") -esd5b_l1.forget +esd5b_l1.forget # Rule ESD.6: Extension perpendicular to Poly2 gate. is 0.45µm logger.info("Executing rule ESD.6") esd6_l1 = esd.edges.enclosing(poly2.edges.interacting(tgate.edges), 0.45.um, projection).polygons(0.001) @@ -268,7 +268,7 @@ logger.info("Executing rule ESD.pl") esdpl_l1 = poly2.interacting(esd).edges.and(tgate.edges).width(0.8.um, euclidian).polygons(0.001).overlapping(dualgate) esdpl_l1.output("ESD.pl", "ESD.pl : Minimum gate length of 5V/6V gate NMOS. : 0.8µm") -esdpl_l1.forget +esdpl_l1.forget # Rule ESD.9: ESD implant layer must be overlapped by Dualgate layer (as ESD implant option is only for 5V/6V devices). logger.info("Executing rule ESD.9")
diff --git a/rules/klayout/drc/rule_decks/geometry_rules.drc b/rules/klayout/drc/rule_decks/geometry_rules.drc index 8203007..535feea 100644 --- a/rules/klayout/drc/rule_decks/geometry_rules.drc +++ b/rules/klayout/drc/rule_decks/geometry_rules.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -217,7 +217,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -226,12 +226,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -298,436 +298,436 @@ #================================================ #-----------------GEOMETRY RULES----------------- -#================================================ +#================================================ if OFFGRID -logger.info("OFFGRID-ANGLES section") +logger.info("OFFGRID-ANGLES section") logger.info("Executing rule comp_OFFGRID") comp.ongrid(0.005).output("comp_OFFGRID", "OFFGRID : OFFGRID vertex on comp") -comp.with_angle(0 .. 45).output("comp_angle", "ACUTE : non 45 degree angle comp") +comp.with_angle(0 .. 45).output("comp_angle", "ACUTE : non 45 degree angle comp") logger.info("Executing rule dnwell_OFFGRID") dnwell.ongrid(0.005).output("dnwell_OFFGRID", "OFFGRID : OFFGRID vertex on dnwell") -dnwell.with_angle(0 .. 45).output("dnwell_angle", "ACUTE : non 45 degree angle dnwell") +dnwell.with_angle(0 .. 45).output("dnwell_angle", "ACUTE : non 45 degree angle dnwell") logger.info("Executing rule nwell_OFFGRID") nwell.ongrid(0.005).output("nwell_OFFGRID", "OFFGRID : OFFGRID vertex on nwell") -nwell.with_angle(0 .. 45).output("nwell_angle", "ACUTE : non 45 degree angle nwell") +nwell.with_angle(0 .. 45).output("nwell_angle", "ACUTE : non 45 degree angle nwell") logger.info("Executing rule lvpwell_OFFGRID") lvpwell.ongrid(0.005).output("lvpwell_OFFGRID", "OFFGRID : OFFGRID vertex on lvpwell") -lvpwell.with_angle(0 .. 45).output("lvpwell_angle", "ACUTE : non 45 degree angle lvpwell") +lvpwell.with_angle(0 .. 45).output("lvpwell_angle", "ACUTE : non 45 degree angle lvpwell") logger.info("Executing rule dualgate_OFFGRID") dualgate.ongrid(0.005).output("dualgate_OFFGRID", "OFFGRID : OFFGRID vertex on dualgate") -dualgate.with_angle(0 .. 45).output("dualgate_angle", "ACUTE : non 45 degree angle dualgate") +dualgate.with_angle(0 .. 45).output("dualgate_angle", "ACUTE : non 45 degree angle dualgate") logger.info("Executing rule poly2_OFFGRID") poly2.ongrid(0.005).output("poly2_OFFGRID", "OFFGRID : OFFGRID vertex on poly2") -poly2.with_angle(0 .. 45).output("poly2_angle", "ACUTE : non 45 degree angle poly2") +poly2.with_angle(0 .. 45).output("poly2_angle", "ACUTE : non 45 degree angle poly2") logger.info("Executing rule nplus_OFFGRID") nplus.ongrid(0.005).output("nplus_OFFGRID", "OFFGRID : OFFGRID vertex on nplus") -nplus.with_angle(0 .. 45).output("nplus_angle", "ACUTE : non 45 degree angle nplus") +nplus.with_angle(0 .. 45).output("nplus_angle", "ACUTE : non 45 degree angle nplus") logger.info("Executing rule pplus_OFFGRID") pplus.ongrid(0.005).output("pplus_OFFGRID", "OFFGRID : OFFGRID vertex on pplus") -pplus.with_angle(0 .. 45).output("pplus_angle", "ACUTE : non 45 degree angle pplus") +pplus.with_angle(0 .. 45).output("pplus_angle", "ACUTE : non 45 degree angle pplus") logger.info("Executing rule sab_OFFGRID") sab.ongrid(0.005).output("sab_OFFGRID", "OFFGRID : OFFGRID vertex on sab") -sab.with_angle(0 .. 45).output("sab_angle", "ACUTE : non 45 degree angle sab") +sab.with_angle(0 .. 45).output("sab_angle", "ACUTE : non 45 degree angle sab") logger.info("Executing rule esd_OFFGRID") esd.ongrid(0.005).output("esd_OFFGRID", "OFFGRID : OFFGRID vertex on esd") -esd.with_angle(0 .. 45).output("esd_angle", "ACUTE : non 45 degree angle esd") +esd.with_angle(0 .. 45).output("esd_angle", "ACUTE : non 45 degree angle esd") logger.info("Executing rule contact_OFFGRID") contact.ongrid(0.005).output("contact_OFFGRID", "OFFGRID : OFFGRID vertex on contact") -contact.with_angle(0 .. 45).output("contact_angle", "ACUTE : non 45 degree angle contact") +contact.with_angle(0 .. 45).output("contact_angle", "ACUTE : non 45 degree angle contact") logger.info("Executing rule metal1_OFFGRID") metal1.ongrid(0.005).output("metal1_OFFGRID", "OFFGRID : OFFGRID vertex on metal1") -metal1.with_angle(0 .. 45).output("metal1_angle", "ACUTE : non 45 degree angle metal1") +metal1.with_angle(0 .. 45).output("metal1_angle", "ACUTE : non 45 degree angle metal1") logger.info("Executing rule via1_OFFGRID") via1.ongrid(0.005).output("via1_OFFGRID", "OFFGRID : OFFGRID vertex on via1") -via1.with_angle(0 .. 45).output("via1_angle", "ACUTE : non 45 degree angle via1") +via1.with_angle(0 .. 45).output("via1_angle", "ACUTE : non 45 degree angle via1") logger.info("Executing rule metal2_OFFGRID") metal2.ongrid(0.005).output("metal2_OFFGRID", "OFFGRID : OFFGRID vertex on metal2") -metal2.with_angle(0 .. 45).output("metal2_angle", "ACUTE : non 45 degree angle metal2") +metal2.with_angle(0 .. 45).output("metal2_angle", "ACUTE : non 45 degree angle metal2") logger.info("Executing rule via2_OFFGRID") via2.ongrid(0.005).output("via2_OFFGRID", "OFFGRID : OFFGRID vertex on via2") -via2.with_angle(0 .. 45).output("via2_angle", "ACUTE : non 45 degree angle via2") +via2.with_angle(0 .. 45).output("via2_angle", "ACUTE : non 45 degree angle via2") logger.info("Executing rule metal3_OFFGRID") metal3.ongrid(0.005).output("metal3_OFFGRID", "OFFGRID : OFFGRID vertex on metal3") -metal3.with_angle(0 .. 45).output("metal3_angle", "ACUTE : non 45 degree angle metal3") +metal3.with_angle(0 .. 45).output("metal3_angle", "ACUTE : non 45 degree angle metal3") logger.info("Executing rule via3_OFFGRID") via3.ongrid(0.005).output("via3_OFFGRID", "OFFGRID : OFFGRID vertex on via3") -via3.with_angle(0 .. 45).output("via3_angle", "ACUTE : non 45 degree angle via3") +via3.with_angle(0 .. 45).output("via3_angle", "ACUTE : non 45 degree angle via3") logger.info("Executing rule metal4_OFFGRID") metal4.ongrid(0.005).output("metal4_OFFGRID", "OFFGRID : OFFGRID vertex on metal4") -metal4.with_angle(0 .. 45).output("metal4_angle", "ACUTE : non 45 degree angle metal4") +metal4.with_angle(0 .. 45).output("metal4_angle", "ACUTE : non 45 degree angle metal4") logger.info("Executing rule via4_OFFGRID") via4.ongrid(0.005).output("via4_OFFGRID", "OFFGRID : OFFGRID vertex on via4") -via4.with_angle(0 .. 45).output("via4_angle", "ACUTE : non 45 degree angle via4") +via4.with_angle(0 .. 45).output("via4_angle", "ACUTE : non 45 degree angle via4") logger.info("Executing rule metal5_OFFGRID") metal5.ongrid(0.005).output("metal5_OFFGRID", "OFFGRID : OFFGRID vertex on metal5") -metal5.with_angle(0 .. 45).output("metal5_angle", "ACUTE : non 45 degree angle metal5") +metal5.with_angle(0 .. 45).output("metal5_angle", "ACUTE : non 45 degree angle metal5") logger.info("Executing rule via5_OFFGRID") via5.ongrid(0.005).output("via5_OFFGRID", "OFFGRID : OFFGRID vertex on via5") -via5.with_angle(0 .. 45).output("via5_angle", "ACUTE : non 45 degree angle via5") +via5.with_angle(0 .. 45).output("via5_angle", "ACUTE : non 45 degree angle via5") logger.info("Executing rule metaltop_OFFGRID") metaltop.ongrid(0.005).output("metaltop_OFFGRID", "OFFGRID : OFFGRID vertex on metaltop") -metaltop.with_angle(0 .. 45).output("metaltop_angle", "ACUTE : non 45 degree angle metaltop") +metaltop.with_angle(0 .. 45).output("metaltop_angle", "ACUTE : non 45 degree angle metaltop") logger.info("Executing rule pad_OFFGRID") pad.ongrid(0.005).output("pad_OFFGRID", "OFFGRID : OFFGRID vertex on pad") -pad.with_angle(0 .. 45).output("pad_angle", "ACUTE : non 45 degree angle pad") +pad.with_angle(0 .. 45).output("pad_angle", "ACUTE : non 45 degree angle pad") logger.info("Executing rule resistor_OFFGRID") resistor.ongrid(0.005).output("resistor_OFFGRID", "OFFGRID : OFFGRID vertex on resistor") -resistor.with_angle(0 .. 45).output("resistor_angle", "ACUTE : non 45 degree angle resistor") +resistor.with_angle(0 .. 45).output("resistor_angle", "ACUTE : non 45 degree angle resistor") logger.info("Executing rule fhres_OFFGRID") fhres.ongrid(0.005).output("fhres_OFFGRID", "OFFGRID : OFFGRID vertex on fhres") -fhres.with_angle(0 .. 45).output("fhres_angle", "ACUTE : non 45 degree angle fhres") +fhres.with_angle(0 .. 45).output("fhres_angle", "ACUTE : non 45 degree angle fhres") logger.info("Executing rule fusetop_OFFGRID") fusetop.ongrid(0.005).output("fusetop_OFFGRID", "OFFGRID : OFFGRID vertex on fusetop") -fusetop.with_angle(0 .. 45).output("fusetop_angle", "ACUTE : non 45 degree angle fusetop") +fusetop.with_angle(0 .. 45).output("fusetop_angle", "ACUTE : non 45 degree angle fusetop") logger.info("Executing rule fusewindow_d_OFFGRID") fusewindow_d.ongrid(0.005).output("fusewindow_d_OFFGRID", "OFFGRID : OFFGRID vertex on fusewindow_d") -fusewindow_d.with_angle(0 .. 45).output("fusewindow_d_angle", "ACUTE : non 45 degree angle fusewindow_d") +fusewindow_d.with_angle(0 .. 45).output("fusewindow_d_angle", "ACUTE : non 45 degree angle fusewindow_d") logger.info("Executing rule polyfuse_OFFGRID") polyfuse.ongrid(0.005).output("polyfuse_OFFGRID", "OFFGRID : OFFGRID vertex on polyfuse") -polyfuse.with_angle(0 .. 45).output("polyfuse_angle", "ACUTE : non 45 degree angle polyfuse") +polyfuse.with_angle(0 .. 45).output("polyfuse_angle", "ACUTE : non 45 degree angle polyfuse") logger.info("Executing rule mvsd_OFFGRID") mvsd.ongrid(0.005).output("mvsd_OFFGRID", "OFFGRID : OFFGRID vertex on mvsd") -mvsd.with_angle(0 .. 45).output("mvsd_angle", "ACUTE : non 45 degree angle mvsd") +mvsd.with_angle(0 .. 45).output("mvsd_angle", "ACUTE : non 45 degree angle mvsd") logger.info("Executing rule mvpsd_OFFGRID") mvpsd.ongrid(0.005).output("mvpsd_OFFGRID", "OFFGRID : OFFGRID vertex on mvpsd") -mvpsd.with_angle(0 .. 45).output("mvpsd_angle", "ACUTE : non 45 degree angle mvpsd") +mvpsd.with_angle(0 .. 45).output("mvpsd_angle", "ACUTE : non 45 degree angle mvpsd") logger.info("Executing rule nat_OFFGRID") nat.ongrid(0.005).output("nat_OFFGRID", "OFFGRID : OFFGRID vertex on nat") -nat.with_angle(0 .. 45).output("nat_angle", "ACUTE : non 45 degree angle nat") +nat.with_angle(0 .. 45).output("nat_angle", "ACUTE : non 45 degree angle nat") logger.info("Executing rule comp_dummy_OFFGRID") comp_dummy.ongrid(0.005).output("comp_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on comp_dummy") -comp_dummy.with_angle(0 .. 45).output("comp_dummy_angle", "ACUTE : non 45 degree angle comp_dummy") +comp_dummy.with_angle(0 .. 45).output("comp_dummy_angle", "ACUTE : non 45 degree angle comp_dummy") logger.info("Executing rule poly2_dummy_OFFGRID") poly2_dummy.ongrid(0.005).output("poly2_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on poly2_dummy") -poly2_dummy.with_angle(0 .. 45).output("poly2_dummy_angle", "ACUTE : non 45 degree angle poly2_dummy") +poly2_dummy.with_angle(0 .. 45).output("poly2_dummy_angle", "ACUTE : non 45 degree angle poly2_dummy") logger.info("Executing rule metal1_dummy_OFFGRID") metal1_dummy.ongrid(0.005).output("metal1_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_dummy") -metal1_dummy.with_angle(0 .. 45).output("metal1_dummy_angle", "ACUTE : non 45 degree angle metal1_dummy") +metal1_dummy.with_angle(0 .. 45).output("metal1_dummy_angle", "ACUTE : non 45 degree angle metal1_dummy") logger.info("Executing rule metal2_dummy_OFFGRID") metal2_dummy.ongrid(0.005).output("metal2_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_dummy") -metal2_dummy.with_angle(0 .. 45).output("metal2_dummy_angle", "ACUTE : non 45 degree angle metal2_dummy") +metal2_dummy.with_angle(0 .. 45).output("metal2_dummy_angle", "ACUTE : non 45 degree angle metal2_dummy") logger.info("Executing rule metal3_dummy_OFFGRID") metal3_dummy.ongrid(0.005).output("metal3_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_dummy") -metal3_dummy.with_angle(0 .. 45).output("metal3_dummy_angle", "ACUTE : non 45 degree angle metal3_dummy") +metal3_dummy.with_angle(0 .. 45).output("metal3_dummy_angle", "ACUTE : non 45 degree angle metal3_dummy") logger.info("Executing rule metal4_dummy_OFFGRID") metal4_dummy.ongrid(0.005).output("metal4_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_dummy") -metal4_dummy.with_angle(0 .. 45).output("metal4_dummy_angle", "ACUTE : non 45 degree angle metal4_dummy") +metal4_dummy.with_angle(0 .. 45).output("metal4_dummy_angle", "ACUTE : non 45 degree angle metal4_dummy") logger.info("Executing rule metal5_dummy_OFFGRID") metal5_dummy.ongrid(0.005).output("metal5_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_dummy") -metal5_dummy.with_angle(0 .. 45).output("metal5_dummy_angle", "ACUTE : non 45 degree angle metal5_dummy") +metal5_dummy.with_angle(0 .. 45).output("metal5_dummy_angle", "ACUTE : non 45 degree angle metal5_dummy") logger.info("Executing rule metaltop_dummy_OFFGRID") metaltop_dummy.ongrid(0.005).output("metaltop_dummy_OFFGRID", "OFFGRID : OFFGRID vertex on metaltop_dummy") -metaltop_dummy.with_angle(0 .. 45).output("metaltop_dummy_angle", "ACUTE : non 45 degree angle metaltop_dummy") +metaltop_dummy.with_angle(0 .. 45).output("metaltop_dummy_angle", "ACUTE : non 45 degree angle metaltop_dummy") logger.info("Executing rule comp_label_OFFGRID") comp_label.ongrid(0.005).output("comp_label_OFFGRID", "OFFGRID : OFFGRID vertex on comp_label") -comp_label.with_angle(0 .. 45).output("comp_label_angle", "ACUTE : non 45 degree angle comp_label") +comp_label.with_angle(0 .. 45).output("comp_label_angle", "ACUTE : non 45 degree angle comp_label") logger.info("Executing rule poly2_label_OFFGRID") poly2_label.ongrid(0.005).output("poly2_label_OFFGRID", "OFFGRID : OFFGRID vertex on poly2_label") -poly2_label.with_angle(0 .. 45).output("poly2_label_angle", "ACUTE : non 45 degree angle poly2_label") +poly2_label.with_angle(0 .. 45).output("poly2_label_angle", "ACUTE : non 45 degree angle poly2_label") logger.info("Executing rule metal1_label_OFFGRID") metal1_label.ongrid(0.005).output("metal1_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_label") -metal1_label.with_angle(0 .. 45).output("metal1_label_angle", "ACUTE : non 45 degree angle metal1_label") +metal1_label.with_angle(0 .. 45).output("metal1_label_angle", "ACUTE : non 45 degree angle metal1_label") logger.info("Executing rule metal2_label_OFFGRID") metal2_label.ongrid(0.005).output("metal2_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_label") -metal2_label.with_angle(0 .. 45).output("metal2_label_angle", "ACUTE : non 45 degree angle metal2_label") +metal2_label.with_angle(0 .. 45).output("metal2_label_angle", "ACUTE : non 45 degree angle metal2_label") logger.info("Executing rule metal3_label_OFFGRID") metal3_label.ongrid(0.005).output("metal3_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_label") -metal3_label.with_angle(0 .. 45).output("metal3_label_angle", "ACUTE : non 45 degree angle metal3_label") +metal3_label.with_angle(0 .. 45).output("metal3_label_angle", "ACUTE : non 45 degree angle metal3_label") logger.info("Executing rule metal4_label_OFFGRID") metal4_label.ongrid(0.005).output("metal4_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_label") -metal4_label.with_angle(0 .. 45).output("metal4_label_angle", "ACUTE : non 45 degree angle metal4_label") +metal4_label.with_angle(0 .. 45).output("metal4_label_angle", "ACUTE : non 45 degree angle metal4_label") logger.info("Executing rule metal5_label_OFFGRID") metal5_label.ongrid(0.005).output("metal5_label_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_label") -metal5_label.with_angle(0 .. 45).output("metal5_label_angle", "ACUTE : non 45 degree angle metal5_label") +metal5_label.with_angle(0 .. 45).output("metal5_label_angle", "ACUTE : non 45 degree angle metal5_label") logger.info("Executing rule metaltop_label_OFFGRID") metaltop_label.ongrid(0.005).output("metaltop_label_OFFGRID", "OFFGRID : OFFGRID vertex on metaltop_label") -metaltop_label.with_angle(0 .. 45).output("metaltop_label_angle", "ACUTE : non 45 degree angle metaltop_label") +metaltop_label.with_angle(0 .. 45).output("metaltop_label_angle", "ACUTE : non 45 degree angle metaltop_label") logger.info("Executing rule metal1_slot_OFFGRID") metal1_slot.ongrid(0.005).output("metal1_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_slot") -metal1_slot.with_angle(0 .. 45).output("metal1_slot_angle", "ACUTE : non 45 degree angle metal1_slot") +metal1_slot.with_angle(0 .. 45).output("metal1_slot_angle", "ACUTE : non 45 degree angle metal1_slot") logger.info("Executing rule metal2_slot_OFFGRID") metal2_slot.ongrid(0.005).output("metal2_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_slot") -metal2_slot.with_angle(0 .. 45).output("metal2_slot_angle", "ACUTE : non 45 degree angle metal2_slot") +metal2_slot.with_angle(0 .. 45).output("metal2_slot_angle", "ACUTE : non 45 degree angle metal2_slot") logger.info("Executing rule metal3_slot_OFFGRID") metal3_slot.ongrid(0.005).output("metal3_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_slot") -metal3_slot.with_angle(0 .. 45).output("metal3_slot_angle", "ACUTE : non 45 degree angle metal3_slot") +metal3_slot.with_angle(0 .. 45).output("metal3_slot_angle", "ACUTE : non 45 degree angle metal3_slot") logger.info("Executing rule metal4_slot_OFFGRID") metal4_slot.ongrid(0.005).output("metal4_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_slot") -metal4_slot.with_angle(0 .. 45).output("metal4_slot_angle", "ACUTE : non 45 degree angle metal4_slot") +metal4_slot.with_angle(0 .. 45).output("metal4_slot_angle", "ACUTE : non 45 degree angle metal4_slot") logger.info("Executing rule metal5_slot_OFFGRID") metal5_slot.ongrid(0.005).output("metal5_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_slot") -metal5_slot.with_angle(0 .. 45).output("metal5_slot_angle", "ACUTE : non 45 degree angle metal5_slot") +metal5_slot.with_angle(0 .. 45).output("metal5_slot_angle", "ACUTE : non 45 degree angle metal5_slot") logger.info("Executing rule metaltop_slot_OFFGRID") metaltop_slot.ongrid(0.005).output("metaltop_slot_OFFGRID", "OFFGRID : OFFGRID vertex on metaltop_slot") -metaltop_slot.with_angle(0 .. 45).output("metaltop_slot_angle", "ACUTE : non 45 degree angle metaltop_slot") +metaltop_slot.with_angle(0 .. 45).output("metaltop_slot_angle", "ACUTE : non 45 degree angle metaltop_slot") logger.info("Executing rule ubmpperi_OFFGRID") ubmpperi.ongrid(0.005).output("ubmpperi_OFFGRID", "OFFGRID : OFFGRID vertex on ubmpperi") -ubmpperi.with_angle(0 .. 45).output("ubmpperi_angle", "ACUTE : non 45 degree angle ubmpperi") +ubmpperi.with_angle(0 .. 45).output("ubmpperi_angle", "ACUTE : non 45 degree angle ubmpperi") logger.info("Executing rule ubmparray_OFFGRID") ubmparray.ongrid(0.005).output("ubmparray_OFFGRID", "OFFGRID : OFFGRID vertex on ubmparray") -ubmparray.with_angle(0 .. 45).output("ubmparray_angle", "ACUTE : non 45 degree angle ubmparray") +ubmparray.with_angle(0 .. 45).output("ubmparray_angle", "ACUTE : non 45 degree angle ubmparray") logger.info("Executing rule ubmeplate_OFFGRID") ubmeplate.ongrid(0.005).output("ubmeplate_OFFGRID", "OFFGRID : OFFGRID vertex on ubmeplate") -ubmeplate.with_angle(0 .. 45).output("ubmeplate_angle", "ACUTE : non 45 degree angle ubmeplate") +ubmeplate.with_angle(0 .. 45).output("ubmeplate_angle", "ACUTE : non 45 degree angle ubmeplate") logger.info("Executing rule schottky_diode_OFFGRID") schottky_diode.ongrid(0.005).output("schottky_diode_OFFGRID", "OFFGRID : OFFGRID vertex on schottky_diode") -schottky_diode.with_angle(0 .. 45).output("schottky_diode_angle", "ACUTE : non 45 degree angle schottky_diode") +schottky_diode.with_angle(0 .. 45).output("schottky_diode_angle", "ACUTE : non 45 degree angle schottky_diode") logger.info("Executing rule zener_OFFGRID") zener.ongrid(0.005).output("zener_OFFGRID", "OFFGRID : OFFGRID vertex on zener") -zener.with_angle(0 .. 45).output("zener_angle", "ACUTE : non 45 degree angle zener") +zener.with_angle(0 .. 45).output("zener_angle", "ACUTE : non 45 degree angle zener") logger.info("Executing rule res_mk_OFFGRID") res_mk.ongrid(0.005).output("res_mk_OFFGRID", "OFFGRID : OFFGRID vertex on res_mk") -res_mk.with_angle(0 .. 45).output("res_mk_angle", "ACUTE : non 45 degree angle res_mk") +res_mk.with_angle(0 .. 45).output("res_mk_angle", "ACUTE : non 45 degree angle res_mk") logger.info("Executing rule opc_drc_OFFGRID") opc_drc.ongrid(0.005).output("opc_drc_OFFGRID", "OFFGRID : OFFGRID vertex on opc_drc") -opc_drc.with_angle(0 .. 45).output("opc_drc_angle", "ACUTE : non 45 degree angle opc_drc") +opc_drc.with_angle(0 .. 45).output("opc_drc_angle", "ACUTE : non 45 degree angle opc_drc") logger.info("Executing rule ndmy_OFFGRID") ndmy.ongrid(0.005).output("ndmy_OFFGRID", "OFFGRID : OFFGRID vertex on ndmy") -ndmy.with_angle(0 .. 45).output("ndmy_angle", "ACUTE : non 45 degree angle ndmy") +ndmy.with_angle(0 .. 45).output("ndmy_angle", "ACUTE : non 45 degree angle ndmy") logger.info("Executing rule pmndmy_OFFGRID") pmndmy.ongrid(0.005).output("pmndmy_OFFGRID", "OFFGRID : OFFGRID vertex on pmndmy") -pmndmy.with_angle(0 .. 45).output("pmndmy_angle", "ACUTE : non 45 degree angle pmndmy") +pmndmy.with_angle(0 .. 45).output("pmndmy_angle", "ACUTE : non 45 degree angle pmndmy") logger.info("Executing rule v5_xtor_OFFGRID") v5_xtor.ongrid(0.005).output("v5_xtor_OFFGRID", "OFFGRID : OFFGRID vertex on v5_xtor") -v5_xtor.with_angle(0 .. 45).output("v5_xtor_angle", "ACUTE : non 45 degree angle v5_xtor") +v5_xtor.with_angle(0 .. 45).output("v5_xtor_angle", "ACUTE : non 45 degree angle v5_xtor") logger.info("Executing rule cap_mk_OFFGRID") cap_mk.ongrid(0.005).output("cap_mk_OFFGRID", "OFFGRID : OFFGRID vertex on cap_mk") -cap_mk.with_angle(0 .. 45).output("cap_mk_angle", "ACUTE : non 45 degree angle cap_mk") +cap_mk.with_angle(0 .. 45).output("cap_mk_angle", "ACUTE : non 45 degree angle cap_mk") logger.info("Executing rule mos_cap_mk_OFFGRID") mos_cap_mk.ongrid(0.005).output("mos_cap_mk_OFFGRID", "OFFGRID : OFFGRID vertex on mos_cap_mk") -mos_cap_mk.with_angle(0 .. 45).output("mos_cap_mk_angle", "ACUTE : non 45 degree angle mos_cap_mk") +mos_cap_mk.with_angle(0 .. 45).output("mos_cap_mk_angle", "ACUTE : non 45 degree angle mos_cap_mk") logger.info("Executing rule ind_mk_OFFGRID") ind_mk.ongrid(0.005).output("ind_mk_OFFGRID", "OFFGRID : OFFGRID vertex on ind_mk") -ind_mk.with_angle(0 .. 45).output("ind_mk_angle", "ACUTE : non 45 degree angle ind_mk") +ind_mk.with_angle(0 .. 45).output("ind_mk_angle", "ACUTE : non 45 degree angle ind_mk") logger.info("Executing rule diode_mk_OFFGRID") diode_mk.ongrid(0.005).output("diode_mk_OFFGRID", "OFFGRID : OFFGRID vertex on diode_mk") -diode_mk.with_angle(0 .. 45).output("diode_mk_angle", "ACUTE : non 45 degree angle diode_mk") +diode_mk.with_angle(0 .. 45).output("diode_mk_angle", "ACUTE : non 45 degree angle diode_mk") logger.info("Executing rule drc_bjt_OFFGRID") drc_bjt.ongrid(0.005).output("drc_bjt_OFFGRID", "OFFGRID : OFFGRID vertex on drc_bjt") -drc_bjt.with_angle(0 .. 45).output("drc_bjt_angle", "ACUTE : non 45 degree angle drc_bjt") +drc_bjt.with_angle(0 .. 45).output("drc_bjt_angle", "ACUTE : non 45 degree angle drc_bjt") logger.info("Executing rule lvs_bjt_OFFGRID") lvs_bjt.ongrid(0.005).output("lvs_bjt_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_bjt") -lvs_bjt.with_angle(0 .. 45).output("lvs_bjt_angle", "ACUTE : non 45 degree angle lvs_bjt") +lvs_bjt.with_angle(0 .. 45).output("lvs_bjt_angle", "ACUTE : non 45 degree angle lvs_bjt") logger.info("Executing rule mim_l_mk_OFFGRID") mim_l_mk.ongrid(0.005).output("mim_l_mk_OFFGRID", "OFFGRID : OFFGRID vertex on mim_l_mk") -mim_l_mk.with_angle(0 .. 45).output("mim_l_mk_angle", "ACUTE : non 45 degree angle mim_l_mk") +mim_l_mk.with_angle(0 .. 45).output("mim_l_mk_angle", "ACUTE : non 45 degree angle mim_l_mk") logger.info("Executing rule latchup_mk_OFFGRID") latchup_mk.ongrid(0.005).output("latchup_mk_OFFGRID", "OFFGRID : OFFGRID vertex on latchup_mk") -latchup_mk.with_angle(0 .. 45).output("latchup_mk_angle", "ACUTE : non 45 degree angle latchup_mk") +latchup_mk.with_angle(0 .. 45).output("latchup_mk_angle", "ACUTE : non 45 degree angle latchup_mk") logger.info("Executing rule guard_ring_mk_OFFGRID") guard_ring_mk.ongrid(0.005).output("guard_ring_mk_OFFGRID", "OFFGRID : OFFGRID vertex on guard_ring_mk") -guard_ring_mk.with_angle(0 .. 45).output("guard_ring_mk_angle", "ACUTE : non 45 degree angle guard_ring_mk") +guard_ring_mk.with_angle(0 .. 45).output("guard_ring_mk_angle", "ACUTE : non 45 degree angle guard_ring_mk") logger.info("Executing rule otp_mk_OFFGRID") otp_mk.ongrid(0.005).output("otp_mk_OFFGRID", "OFFGRID : OFFGRID vertex on otp_mk") -otp_mk.with_angle(0 .. 45).output("otp_mk_angle", "ACUTE : non 45 degree angle otp_mk") +otp_mk.with_angle(0 .. 45).output("otp_mk_angle", "ACUTE : non 45 degree angle otp_mk") logger.info("Executing rule mtpmark_OFFGRID") mtpmark.ongrid(0.005).output("mtpmark_OFFGRID", "OFFGRID : OFFGRID vertex on mtpmark") -mtpmark.with_angle(0 .. 45).output("mtpmark_angle", "ACUTE : non 45 degree angle mtpmark") +mtpmark.with_angle(0 .. 45).output("mtpmark_angle", "ACUTE : non 45 degree angle mtpmark") logger.info("Executing rule neo_ee_mk_OFFGRID") neo_ee_mk.ongrid(0.005).output("neo_ee_mk_OFFGRID", "OFFGRID : OFFGRID vertex on neo_ee_mk") -neo_ee_mk.with_angle(0 .. 45).output("neo_ee_mk_angle", "ACUTE : non 45 degree angle neo_ee_mk") +neo_ee_mk.with_angle(0 .. 45).output("neo_ee_mk_angle", "ACUTE : non 45 degree angle neo_ee_mk") logger.info("Executing rule sramcore_OFFGRID") sramcore.ongrid(0.005).output("sramcore_OFFGRID", "OFFGRID : OFFGRID vertex on sramcore") -sramcore.with_angle(0 .. 45).output("sramcore_angle", "ACUTE : non 45 degree angle sramcore") +sramcore.with_angle(0 .. 45).output("sramcore_angle", "ACUTE : non 45 degree angle sramcore") logger.info("Executing rule lvs_rf_OFFGRID") lvs_rf.ongrid(0.005).output("lvs_rf_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_rf") -lvs_rf.with_angle(0 .. 45).output("lvs_rf_angle", "ACUTE : non 45 degree angle lvs_rf") +lvs_rf.with_angle(0 .. 45).output("lvs_rf_angle", "ACUTE : non 45 degree angle lvs_rf") logger.info("Executing rule lvs_drain_OFFGRID") lvs_drain.ongrid(0.005).output("lvs_drain_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_drain") -lvs_drain.with_angle(0 .. 45).output("lvs_drain_angle", "ACUTE : non 45 degree angle lvs_drain") +lvs_drain.with_angle(0 .. 45).output("lvs_drain_angle", "ACUTE : non 45 degree angle lvs_drain") logger.info("Executing rule ind_mk_OFFGRID") ind_mk.ongrid(0.005).output("ind_mk_OFFGRID", "OFFGRID : OFFGRID vertex on ind_mk") -ind_mk.with_angle(0 .. 45).output("ind_mk_angle", "ACUTE : non 45 degree angle ind_mk") +ind_mk.with_angle(0 .. 45).output("ind_mk_angle", "ACUTE : non 45 degree angle ind_mk") logger.info("Executing rule hvpolyrs_OFFGRID") hvpolyrs.ongrid(0.005).output("hvpolyrs_OFFGRID", "OFFGRID : OFFGRID vertex on hvpolyrs") -hvpolyrs.with_angle(0 .. 45).output("hvpolyrs_angle", "ACUTE : non 45 degree angle hvpolyrs") +hvpolyrs.with_angle(0 .. 45).output("hvpolyrs_angle", "ACUTE : non 45 degree angle hvpolyrs") logger.info("Executing rule lvs_io_OFFGRID") lvs_io.ongrid(0.005).output("lvs_io_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_io") -lvs_io.with_angle(0 .. 45).output("lvs_io_angle", "ACUTE : non 45 degree angle lvs_io") +lvs_io.with_angle(0 .. 45).output("lvs_io_angle", "ACUTE : non 45 degree angle lvs_io") logger.info("Executing rule probe_mk_OFFGRID") probe_mk.ongrid(0.005).output("probe_mk_OFFGRID", "OFFGRID : OFFGRID vertex on probe_mk") -probe_mk.with_angle(0 .. 45).output("probe_mk_angle", "ACUTE : non 45 degree angle probe_mk") +probe_mk.with_angle(0 .. 45).output("probe_mk_angle", "ACUTE : non 45 degree angle probe_mk") logger.info("Executing rule esd_mk_OFFGRID") esd_mk.ongrid(0.005).output("esd_mk_OFFGRID", "OFFGRID : OFFGRID vertex on esd_mk") -esd_mk.with_angle(0 .. 45).output("esd_mk_angle", "ACUTE : non 45 degree angle esd_mk") +esd_mk.with_angle(0 .. 45).output("esd_mk_angle", "ACUTE : non 45 degree angle esd_mk") logger.info("Executing rule lvs_source_OFFGRID") lvs_source.ongrid(0.005).output("lvs_source_OFFGRID", "OFFGRID : OFFGRID vertex on lvs_source") -lvs_source.with_angle(0 .. 45).output("lvs_source_angle", "ACUTE : non 45 degree angle lvs_source") +lvs_source.with_angle(0 .. 45).output("lvs_source_angle", "ACUTE : non 45 degree angle lvs_source") logger.info("Executing rule well_diode_mk_OFFGRID") well_diode_mk.ongrid(0.005).output("well_diode_mk_OFFGRID", "OFFGRID : OFFGRID vertex on well_diode_mk") -well_diode_mk.with_angle(0 .. 45).output("well_diode_mk_angle", "ACUTE : non 45 degree angle well_diode_mk") +well_diode_mk.with_angle(0 .. 45).output("well_diode_mk_angle", "ACUTE : non 45 degree angle well_diode_mk") logger.info("Executing rule ldmos_xtor_OFFGRID") ldmos_xtor.ongrid(0.005).output("ldmos_xtor_OFFGRID", "OFFGRID : OFFGRID vertex on ldmos_xtor") -ldmos_xtor.with_angle(0 .. 45).output("ldmos_xtor_angle", "ACUTE : non 45 degree angle ldmos_xtor") +ldmos_xtor.with_angle(0 .. 45).output("ldmos_xtor_angle", "ACUTE : non 45 degree angle ldmos_xtor") logger.info("Executing rule plfuse_OFFGRID") plfuse.ongrid(0.005).output("plfuse_OFFGRID", "OFFGRID : OFFGRID vertex on plfuse") -plfuse.with_angle(0 .. 45).output("plfuse_angle", "ACUTE : non 45 degree angle plfuse") +plfuse.with_angle(0 .. 45).output("plfuse_angle", "ACUTE : non 45 degree angle plfuse") logger.info("Executing rule efuse_mk_OFFGRID") efuse_mk.ongrid(0.005).output("efuse_mk_OFFGRID", "OFFGRID : OFFGRID vertex on efuse_mk") -efuse_mk.with_angle(0 .. 45).output("efuse_mk_angle", "ACUTE : non 45 degree angle efuse_mk") +efuse_mk.with_angle(0 .. 45).output("efuse_mk_angle", "ACUTE : non 45 degree angle efuse_mk") logger.info("Executing rule mcell_feol_mk_OFFGRID") mcell_feol_mk.ongrid(0.005).output("mcell_feol_mk_OFFGRID", "OFFGRID : OFFGRID vertex on mcell_feol_mk") -mcell_feol_mk.with_angle(0 .. 45).output("mcell_feol_mk_angle", "ACUTE : non 45 degree angle mcell_feol_mk") +mcell_feol_mk.with_angle(0 .. 45).output("mcell_feol_mk_angle", "ACUTE : non 45 degree angle mcell_feol_mk") logger.info("Executing rule ymtp_mk_OFFGRID") ymtp_mk.ongrid(0.005).output("ymtp_mk_OFFGRID", "OFFGRID : OFFGRID vertex on ymtp_mk") -ymtp_mk.with_angle(0 .. 45).output("ymtp_mk_angle", "ACUTE : non 45 degree angle ymtp_mk") +ymtp_mk.with_angle(0 .. 45).output("ymtp_mk_angle", "ACUTE : non 45 degree angle ymtp_mk") logger.info("Executing rule dev_wf_mk_OFFGRID") dev_wf_mk.ongrid(0.005).output("dev_wf_mk_OFFGRID", "OFFGRID : OFFGRID vertex on dev_wf_mk") -dev_wf_mk.with_angle(0 .. 45).output("dev_wf_mk_angle", "ACUTE : non 45 degree angle dev_wf_mk") +dev_wf_mk.with_angle(0 .. 45).output("dev_wf_mk_angle", "ACUTE : non 45 degree angle dev_wf_mk") logger.info("Executing rule metal1_blk_OFFGRID") metal1_blk.ongrid(0.005).output("metal1_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_blk") -metal1_blk.with_angle(0 .. 45).output("metal1_blk_angle", "ACUTE : non 45 degree angle metal1_blk") +metal1_blk.with_angle(0 .. 45).output("metal1_blk_angle", "ACUTE : non 45 degree angle metal1_blk") logger.info("Executing rule metal2_blk_OFFGRID") metal2_blk.ongrid(0.005).output("metal2_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_blk") -metal2_blk.with_angle(0 .. 45).output("metal2_blk_angle", "ACUTE : non 45 degree angle metal2_blk") +metal2_blk.with_angle(0 .. 45).output("metal2_blk_angle", "ACUTE : non 45 degree angle metal2_blk") logger.info("Executing rule metal3_blk_OFFGRID") metal3_blk.ongrid(0.005).output("metal3_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_blk") -metal3_blk.with_angle(0 .. 45).output("metal3_blk_angle", "ACUTE : non 45 degree angle metal3_blk") +metal3_blk.with_angle(0 .. 45).output("metal3_blk_angle", "ACUTE : non 45 degree angle metal3_blk") logger.info("Executing rule metal4_blk_OFFGRID") metal4_blk.ongrid(0.005).output("metal4_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_blk") -metal4_blk.with_angle(0 .. 45).output("metal4_blk_angle", "ACUTE : non 45 degree angle metal4_blk") +metal4_blk.with_angle(0 .. 45).output("metal4_blk_angle", "ACUTE : non 45 degree angle metal4_blk") logger.info("Executing rule metal5_blk_OFFGRID") metal5_blk.ongrid(0.005).output("metal5_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_blk") -metal5_blk.with_angle(0 .. 45).output("metal5_blk_angle", "ACUTE : non 45 degree angle metal5_blk") +metal5_blk.with_angle(0 .. 45).output("metal5_blk_angle", "ACUTE : non 45 degree angle metal5_blk") logger.info("Executing rule metalt_blk_OFFGRID") metalt_blk.ongrid(0.005).output("metalt_blk_OFFGRID", "OFFGRID : OFFGRID vertex on metalt_blk") -metalt_blk.with_angle(0 .. 45).output("metalt_blk_angle", "ACUTE : non 45 degree angle metalt_blk") +metalt_blk.with_angle(0 .. 45).output("metalt_blk_angle", "ACUTE : non 45 degree angle metalt_blk") logger.info("Executing rule pr_bndry_OFFGRID") pr_bndry.ongrid(0.005).output("pr_bndry_OFFGRID", "OFFGRID : OFFGRID vertex on pr_bndry") -pr_bndry.with_angle(0 .. 45).output("pr_bndry_angle", "ACUTE : non 45 degree angle pr_bndry") +pr_bndry.with_angle(0 .. 45).output("pr_bndry_angle", "ACUTE : non 45 degree angle pr_bndry") logger.info("Executing rule mdiode_OFFGRID") mdiode.ongrid(0.005).output("mdiode_OFFGRID", "OFFGRID : OFFGRID vertex on mdiode") -mdiode.with_angle(0 .. 45).output("mdiode_angle", "ACUTE : non 45 degree angle mdiode") +mdiode.with_angle(0 .. 45).output("mdiode_angle", "ACUTE : non 45 degree angle mdiode") logger.info("Executing rule metal1_res_OFFGRID") metal1_res.ongrid(0.005).output("metal1_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal1_res") -metal1_res.with_angle(0 .. 45).output("metal1_res_angle", "ACUTE : non 45 degree angle metal1_res") +metal1_res.with_angle(0 .. 45).output("metal1_res_angle", "ACUTE : non 45 degree angle metal1_res") logger.info("Executing rule metal2_res_OFFGRID") metal2_res.ongrid(0.005).output("metal2_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal2_res") -metal2_res.with_angle(0 .. 45).output("metal2_res_angle", "ACUTE : non 45 degree angle metal2_res") +metal2_res.with_angle(0 .. 45).output("metal2_res_angle", "ACUTE : non 45 degree angle metal2_res") logger.info("Executing rule metal3_res_OFFGRID") metal3_res.ongrid(0.005).output("metal3_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal3_res") -metal3_res.with_angle(0 .. 45).output("metal3_res_angle", "ACUTE : non 45 degree angle metal3_res") +metal3_res.with_angle(0 .. 45).output("metal3_res_angle", "ACUTE : non 45 degree angle metal3_res") logger.info("Executing rule metal4_res_OFFGRID") metal4_res.ongrid(0.005).output("metal4_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal4_res") -metal4_res.with_angle(0 .. 45).output("metal4_res_angle", "ACUTE : non 45 degree angle metal4_res") +metal4_res.with_angle(0 .. 45).output("metal4_res_angle", "ACUTE : non 45 degree angle metal4_res") logger.info("Executing rule metal5_res_OFFGRID") metal5_res.ongrid(0.005).output("metal5_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal5_res") -metal5_res.with_angle(0 .. 45).output("metal5_res_angle", "ACUTE : non 45 degree angle metal5_res") +metal5_res.with_angle(0 .. 45).output("metal5_res_angle", "ACUTE : non 45 degree angle metal5_res") logger.info("Executing rule metal6_res_OFFGRID") metal6_res.ongrid(0.005).output("metal6_res_OFFGRID", "OFFGRID : OFFGRID vertex on metal6_res") -metal6_res.with_angle(0 .. 45).output("metal6_res_angle", "ACUTE : non 45 degree angle metal6_res") +metal6_res.with_angle(0 .. 45).output("metal6_res_angle", "ACUTE : non 45 degree angle metal6_res") logger.info("Executing rule border_OFFGRID") border.ongrid(0.005).output("border_OFFGRID", "OFFGRID : OFFGRID vertex on border") -border.with_angle(0 .. 45).output("border_angle", "ACUTE : non 45 degree angle border") +border.with_angle(0 .. 45).output("border_angle", "ACUTE : non 45 degree angle border") -end #OFFGRID-ANGLES +end #OFFGRID-ANGLES exec_end_time = Time.now
diff --git a/rules/klayout/drc/rule_decks/h_poly_resistor.drc b/rules/klayout/drc/rule_decks/h_poly_resistor.drc index 87a7877..4a689db 100644 --- a/rules/klayout/drc/rule_decks/h_poly_resistor.drc +++ b/rules/klayout/drc/rule_decks/h_poly_resistor.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -115,7 +115,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -124,12 +124,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -196,7 +196,7 @@ #================================================ #----------------H POLY RESISTOR----------------- -#================================================ +#================================================ hres_poly = poly2.interacting(pplus).interacting(sab).interacting(res_mk).interacting(resistor) hres1_poly = poly2.interacting(pplus).interacting(sab).interacting(res_mk) @@ -204,19 +204,19 @@ logger.info("Executing rule HRES.1") hres1_l1 = resistor.interacting(hres1_poly).space(0.4.um, euclidian).polygons(0.001) hres1_l1.output("HRES.1", "HRES.1 : Minimum space. Note : Merge if the spacing is less than 0.4 um. : 0.4µm") -hres1_l1.forget +hres1_l1.forget # Rule HRES.2: Minimum width of Poly2 resistor. is 1µm logger.info("Executing rule HRES.2") hres2_l1 = hres_poly.width(1.um, euclidian).polygons(0.001) hres2_l1.output("HRES.2", "HRES.2 : Minimum width of Poly2 resistor. : 1µm") -hres2_l1.forget +hres2_l1.forget # Rule HRES.3: Minimum space between Poly2 resistors. is 0.4µm logger.info("Executing rule HRES.3") hres3_l1 = hres_poly.space(0.4.um, euclidian).polygons(0.001) hres3_l1.output("HRES.3", "HRES.3 : Minimum space between Poly2 resistors. : 0.4µm") -hres3_l1.forget +hres3_l1.forget # Rule HRES.4: Minimum RESISTOR overlap of Poly2 resistor. is 0.4µm logger.info("Executing rule HRES.4") @@ -232,7 +232,7 @@ logger.info("Executing rule HRES.5") hres5_l1 = resistor.interacting(hres1_poly).separation(poly2.not_interacting(sab), 0.3.um, euclidian).polygons(0.001) hres5_l1.output("HRES.5", "HRES.5 : Minimum RESISTOR space to unrelated Poly2. : 0.3µm") -hres5_l1.forget +hres5_l1.forget # Rule HRES.6: Minimum RESISTOR space to COMP. logger.info("Executing rule HRES.6") @@ -284,7 +284,7 @@ # rule HRES.11 is not a DRC check mk_hres12a = res_mk.edges.not(poly2.not(pplus).and(sab).edges).inside_part(poly2) -# Rule HRES.12a: P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. +# Rule HRES.12a: P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. logger.info("Executing rule HRES.12a") hres12a_l1 = res_mk.interacting(resistor).interacting(mk_hres12a) hres12a_l1.output("HRES.12a", "HRES.12a : P type Poly2 resistor (high sheet rho) shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by Pplus space) and width covering the width of Poly2. ")
diff --git a/rules/klayout/drc/rule_decks/lvpwell.drc b/rules/klayout/drc/rule_decks/lvpwell.drc index 3ac662b..14cedda 100644 --- a/rules/klayout/drc/rule_decks/lvpwell.drc +++ b/rules/klayout/drc/rule_decks/lvpwell.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -116,7 +116,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -125,12 +125,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -222,7 +222,7 @@ connect(metal5, via5) connect(via5, metaltop) -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES #================================================ #------------ PRE-DEFINED FUNCTIONS ------------- @@ -248,7 +248,7 @@ end end unconnected_output = unconnected_errors.polygons.or(singularity_errors.polygons(0.001)) - return connected_output, unconnected_output + return connected_output, unconnected_output end def conn_separation(layer1, layer2, conn_val,not_conn_val, mode) @@ -277,10 +277,10 @@ if CONNECTIVITY_RULES logger.info("Connectivity rules enabled, Netlist object will be generated.") netlist -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES # === LAYOUT EXTENT === -CHIP = extent.sized(0.0) +CHIP = extent.sized(0.0) logger.info("Total area of the design is #{CHIP.area()} um^2.") @@ -288,7 +288,7 @@ #================================================ #--------------------LVPWELL--------------------- -#================================================ +#================================================ if FEOL @@ -298,61 +298,61 @@ logger.info("Executing rule LPW.1_3.3V") lpw1_l1 = lvpwell.width(0.6.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) lpw1_l1.output("LPW.1_3.3V", "LPW.1_3.3V : Min. LVPWELL Width. : 0.6µm") -lpw1_l1.forget +lpw1_l1.forget # Rule LPW.1_5V: Min. LVPWELL Width. is 0.74µm logger.info("Executing rule LPW.1_5V") lpw1_l1 = lvpwell.width(0.74.um, euclidian).polygons(0.001).overlapping(dualgate) lpw1_l1.output("LPW.1_5V", "LPW.1_5V : Min. LVPWELL Width. : 0.74µm") -lpw1_l1.forget +lpw1_l1.forget if CONNECTIVITY_RULES -logger.info("CONNECTIVITY_RULES section") +logger.info("CONNECTIVITY_RULES section") -connected_lvpwell_3p3v, unconnected_lvpwell_3p3v = conn_space(lvpwell, 0.86, 1.4, euclidian) +connected_lvpwell_3p3v, unconnected_lvpwell_3p3v = conn_space(lvpwell, 0.86, 1.4, euclidian) -connected_lvpwell_5p0v, unconnected_lvpwell_5p0v = conn_space(lvpwell, 0.86, 1.7, euclidian) +connected_lvpwell_5p0v, unconnected_lvpwell_5p0v = conn_space(lvpwell, 0.86, 1.7, euclidian) # Rule LPW.2a_3.3V: Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. is 1.4µm logger.info("Executing rule LPW.2a_3.3V") lpw2a_l1 = unconnected_lvpwell_3p3v.not_interacting(v5_xtor).not_interacting(dualgate) lpw2a_l1.output("LPW.2a_3.3V", "LPW.2a_3.3V : Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. : 1.4µm") -lpw2a_l1.forget +lpw2a_l1.forget # Rule LPW.2a_5V: Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. is 1.7µm logger.info("Executing rule LPW.2a_5V") lpw2a_l1 = unconnected_lvpwell_5p0v.overlapping(dualgate) lpw2a_l1.output("LPW.2a_5V", "LPW.2a_5V : Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. : 1.7µm") -lpw2a_l1.forget +lpw2a_l1.forget # Rule LPW.2b_3.3V: Min. LVPWELL to LVPWELL Space [Equi potential]. is 0.86µm logger.info("Executing rule LPW.2b_3.3V") lpw2b_l1 = connected_lvpwell_3p3v.not_interacting(v5_xtor).not_interacting(dualgate) lpw2b_l1.output("LPW.2b_3.3V", "LPW.2b_3.3V : Min. LVPWELL to LVPWELL Space [Equi potential]. : 0.86µm") -lpw2b_l1.forget +lpw2b_l1.forget # Rule LPW.2b_5V: Min. LVPWELL to LVPWELL Space [Equi potential]. is 0.86µm logger.info("Executing rule LPW.2b_5V") lpw2b_l1 = connected_lvpwell_5p0v.overlapping(dualgate) lpw2b_l1.output("LPW.2b_5V", "LPW.2b_5V : Min. LVPWELL to LVPWELL Space [Equi potential]. : 0.86µm") -lpw2b_l1.forget +lpw2b_l1.forget else -logger.info("CONNECTIVITY_RULES disabled section") +logger.info("CONNECTIVITY_RULES disabled section") # Rule LPW.2a_3.3V_: Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. is 1.4µm logger.info("Executing rule LPW.2a_3.3V_") lpw2a_l1 = lvpwell.isolated(1.4.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) lpw2a_l1.output("LPW.2a_3.3V_", "LPW.2a_3.3V_ : Min. LVPWELL to LVWELL Space (Inside DNWELL) [Different potential]. : 1.4µm") -lpw2a_l1.forget +lpw2a_l1.forget # Rule LPW.2a_5V_: Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. is 1.7µm logger.info("Executing rule LPW.2a_5V_") lpw2a_l1 = lvpwell.isolated(1.7.um, euclidian).polygons(0.001).overlapping(dualgate) lpw2a_l1.output("LPW.2a_5V_", "LPW.2a_5V_ : Min. LVPWELL to LVPWELL Space (Inside DNWELL) [Different potential]. : 1.7µm") -lpw2a_l1.forget +lpw2a_l1.forget -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES # Rule LPW.3_3.3V: Min. DNWELL enclose LVPWELL. is 2.5µm logger.info("Executing rule LPW.3_3.3V") @@ -394,7 +394,7 @@ logger.info("Executing rule LPW.11") lpw11_l1 = lvpwell.outside(dnwell).separation(dnwell, 1.5.um, euclidian).polygons(0.001) lpw11_l1.output("LPW.11", "LPW.11 : Min. (LVPWELL outside DNWELL) space to DNWELL. : 1.5µm") -lpw11_l1.forget +lpw11_l1.forget # Rule LPW.12: LVPWELL cannot overlap with Nwell. logger.info("Executing rule LPW.12")
diff --git a/rules/klayout/drc/rule_decks/lvs_bjt.drc b/rules/klayout/drc/rule_decks/lvs_bjt.drc index cc7c9dd..6cf8f16 100644 --- a/rules/klayout/drc/rule_decks/lvs_bjt.drc +++ b/rules/klayout/drc/rule_decks/lvs_bjt.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -114,7 +114,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -123,12 +123,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -195,7 +195,7 @@ #================================================ #--------------------LVS_BJT--------------------- -#================================================ +#================================================ vnpn_e = ncomp.interacting(lvs_bjt).inside(dnwell) vpnp_e = pcomp.inside(nwell).interacting(lvs_bjt)
diff --git a/rules/klayout/drc/rule_decks/mcell.drc b/rules/klayout/drc/rule_decks/mcell.drc index 55b99db..7224f76 100644 --- a/rules/klayout/drc/rule_decks/mcell.drc +++ b/rules/klayout/drc/rule_decks/mcell.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -112,7 +112,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -121,12 +121,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -193,30 +193,30 @@ #================================================ #---------------------MCELL---------------------- -#================================================ +#================================================ # Rule MC.1: min. mcell width is 0.4µm logger.info("Executing rule MC.1") mc1_l1 = mcell_feol_mk.width(0.4.um, euclidian).polygons(0.001) mc1_l1.output("MC.1", "MC.1 : min. mcell width : 0.4µm") -mc1_l1.forget +mc1_l1.forget # Rule MC.2: min. mcell spacing is 0.4µm logger.info("Executing rule MC.2") mc2_l1 = mcell_feol_mk.space(0.4.um, euclidian).polygons(0.001) mc2_l1.output("MC.2", "MC.2 : min. mcell spacing : 0.4µm") -mc2_l1.forget +mc2_l1.forget # Rule MC.3: Minimum Mcell area is 0.35µm² logger.info("Executing rule MC.3") mc3_l1 = mcell_feol_mk.with_area(nil, 0.35.um) mc3_l1.output("MC.3", "MC.3 : Minimum Mcell area : 0.35µm²") -mc3_l1.forget +mc3_l1.forget # Rule MC.4: Minimum area enclosed by Mcell is 0.35µm² logger.info("Executing rule MC.4") mc4_l1 = mcell_feol_mk.holes.with_area(nil, 0.35.um) mc4_l1.output("MC.4", "MC.4 : Minimum area enclosed by Mcell : 0.35µm²") -mc4_l1.forget +mc4_l1.forget exec_end_time = Time.now run_time = exec_end_time - exec_start_time
diff --git a/rules/klayout/drc/rule_decks/metal1.drc b/rules/klayout/drc/rule_decks/metal1.drc index 5c515b8..a1cfa6a 100644 --- a/rules/klayout/drc/rule_decks/metal1.drc +++ b/rules/klayout/drc/rule_decks/metal1.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -113,7 +113,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -122,12 +122,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -194,7 +194,7 @@ #================================================ #---------------------METAL1--------------------- -#================================================ +#================================================ if BEOL @@ -204,25 +204,25 @@ logger.info("Executing rule M1.1") m11_l1 = metal1.not(sramcore).width(0.23.um, euclidian).polygons(0.001) m11_l1.output("M1.1", "M1.1 : min. metal1 width : 0.23µm") -m11_l1.forget +m11_l1.forget # Rule M1.2a: min. metal1 spacing is 0.23µm logger.info("Executing rule M1.2a") m12a_l1 = metal1.space(0.23.um, euclidian).polygons(0.001) m12a_l1.output("M1.2a", "M1.2a : min. metal1 spacing : 0.23µm") -m12a_l1.forget +m12a_l1.forget # Rule M1.2b: Space to wide Metal1 (length & width > 10um) is 0.3µm logger.info("Executing rule M1.2b") m12b_l1 = metal1.separation(metal1.not_interacting(metal1.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) m12b_l1.output("M1.2b", "M1.2b : Space to wide Metal1 (length & width > 10um) : 0.3µm") -m12b_l1.forget +m12b_l1.forget # Rule M1.3: Minimum Metal1 area is 0.1444µm² logger.info("Executing rule M1.3") m13_l1 = metal1.with_area(nil, 0.1444.um) m13_l1.output("M1.3", "M1.3 : Minimum Metal1 area : 0.1444µm²") -m13_l1.forget +m13_l1.forget end #BEOL
diff --git a/rules/klayout/drc/rule_decks/metal2.drc b/rules/klayout/drc/rule_decks/metal2.drc index 32d6cd6..d600d95 100644 --- a/rules/klayout/drc/rule_decks/metal2.drc +++ b/rules/klayout/drc/rule_decks/metal2.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -112,7 +112,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -121,12 +121,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -193,7 +193,7 @@ #================================================ #---------------------METAL2--------------------- -#================================================ +#================================================ if BEOL @@ -203,25 +203,25 @@ logger.info("Executing rule M2.1") m21_l1 = metal2.width(0.28.um, euclidian).polygons(0.001) m21_l1.output("M2.1", "M2.1 : min. metal2 width : 0.28µm") -m21_l1.forget +m21_l1.forget # Rule M2.2a: min. metal2 spacing is 0.28µm logger.info("Executing rule M2.2a") m22a_l1 = metal2.space(0.28.um, euclidian).polygons(0.001) m22a_l1.output("M2.2a", "M2.2a : min. metal2 spacing : 0.28µm") -m22a_l1.forget +m22a_l1.forget # Rule M2.2b: Space to wide Metal2 (length & width > 10um) is 0.3µm logger.info("Executing rule M2.2b") m22b_l1 = metal2.separation(metal2.not_interacting(metal2.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) m22b_l1.output("M2.2b", "M2.2b : Space to wide Metal2 (length & width > 10um) : 0.3µm") -m22b_l1.forget +m22b_l1.forget # Rule M2.3: Minimum metal2 area is 0.1444µm² logger.info("Executing rule M2.3") m23_l1 = metal2.with_area(nil, 0.1444.um) m23_l1.output("M2.3", "M2.3 : Minimum metal2 area : 0.1444µm²") -m23_l1.forget +m23_l1.forget end #BEOL
diff --git a/rules/klayout/drc/rule_decks/metal3.drc b/rules/klayout/drc/rule_decks/metal3.drc index b5a4219..edee0f0 100644 --- a/rules/klayout/drc/rule_decks/metal3.drc +++ b/rules/klayout/drc/rule_decks/metal3.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -112,7 +112,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -121,12 +121,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -193,7 +193,7 @@ #================================================ #---------------------METAL3--------------------- -#================================================ +#================================================ if BEOL @@ -203,25 +203,25 @@ logger.info("Executing rule M3.1") m31_l1 = metal3.width(0.28.um, euclidian).polygons(0.001) m31_l1.output("M3.1", "M3.1 : min. metal3 width : 0.28µm") -m31_l1.forget +m31_l1.forget # Rule M3.2a: min. metal3 spacing is 0.28µm logger.info("Executing rule M3.2a") m32a_l1 = metal3.space(0.28.um, euclidian).polygons(0.001) m32a_l1.output("M3.2a", "M3.2a : min. metal3 spacing : 0.28µm") -m32a_l1.forget +m32a_l1.forget # Rule M3.2b: Space to wide Metal3 (length & width > 10um) is 0.3µm logger.info("Executing rule M3.2b") m32b_l1 = metal3.separation(metal3.not_interacting(metal3.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) m32b_l1.output("M3.2b", "M3.2b : Space to wide Metal3 (length & width > 10um) : 0.3µm") -m32b_l1.forget +m32b_l1.forget # Rule M3.3: Minimum metal3 area is 0.1444µm² logger.info("Executing rule M3.3") m33_l1 = metal3.with_area(nil, 0.1444.um) m33_l1.output("M3.3", "M3.3 : Minimum metal3 area : 0.1444µm²") -m33_l1.forget +m33_l1.forget end #BEOL
diff --git a/rules/klayout/drc/rule_decks/metal4.drc b/rules/klayout/drc/rule_decks/metal4.drc index 4db92c4..a638157 100644 --- a/rules/klayout/drc/rule_decks/metal4.drc +++ b/rules/klayout/drc/rule_decks/metal4.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -112,7 +112,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -121,12 +121,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -193,7 +193,7 @@ #================================================ #---------------------METAL4--------------------- -#================================================ +#================================================ if BEOL @@ -203,25 +203,25 @@ logger.info("Executing rule M4.1") m41_l1 = metal4.width(0.28.um, euclidian).polygons(0.001) m41_l1.output("M4.1", "M4.1 : min. metal4 width : 0.28µm") -m41_l1.forget +m41_l1.forget # Rule M4.2a: min. metal4 spacing is 0.28µm logger.info("Executing rule M4.2a") m42a_l1 = metal4.space(0.28.um, euclidian).polygons(0.001) m42a_l1.output("M4.2a", "M4.2a : min. metal4 spacing : 0.28µm") -m42a_l1.forget +m42a_l1.forget # Rule M4.2b: Space to wide Metal4 (length & width > 10um) is 0.3µm logger.info("Executing rule M4.2b") m42b_l1 = metal4.separation(metal4.not_interacting(metal4.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) m42b_l1.output("M4.2b", "M4.2b : Space to wide Metal4 (length & width > 10um) : 0.3µm") -m42b_l1.forget +m42b_l1.forget # Rule M4.3: Minimum metal4 area is 0.1444µm² logger.info("Executing rule M4.3") m43_l1 = metal4.with_area(nil, 0.1444.um) m43_l1.output("M4.3", "M4.3 : Minimum metal4 area : 0.1444µm²") -m43_l1.forget +m43_l1.forget end #BEOL
diff --git a/rules/klayout/drc/rule_decks/metal5.drc b/rules/klayout/drc/rule_decks/metal5.drc index 4960e06..2b99920 100644 --- a/rules/klayout/drc/rule_decks/metal5.drc +++ b/rules/klayout/drc/rule_decks/metal5.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -112,7 +112,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -121,12 +121,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -193,7 +193,7 @@ #================================================ #---------------------METAL5--------------------- -#================================================ +#================================================ if BEOL @@ -203,25 +203,25 @@ logger.info("Executing rule M5.1") m51_l1 = metal5.width(0.28.um, euclidian).polygons(0.001) m51_l1.output("M5.1", "M5.1 : min. metal5 width : 0.28µm") -m51_l1.forget +m51_l1.forget # Rule M5.2a: min. metal5 spacing is 0.28µm logger.info("Executing rule M5.2a") m52a_l1 = metal5.space(0.28.um, euclidian).polygons(0.001) m52a_l1.output("M5.2a", "M5.2a : min. metal5 spacing : 0.28µm") -m52a_l1.forget +m52a_l1.forget # Rule M5.2b: Space to wide Metal5 (length & width > 10um) is 0.3µm logger.info("Executing rule M5.2b") m52b_l1 = metal5.separation(metal5.not_interacting(metal5.edges.with_length(nil, 10.um)), 0.3.um, euclidian).polygons(0.001) m52b_l1.output("M5.2b", "M5.2b : Space to wide Metal5 (length & width > 10um) : 0.3µm") -m52b_l1.forget +m52b_l1.forget # Rule M5.3: Minimum metal5 area is 0.1444µm² logger.info("Executing rule M5.3") m53_l1 = metal5.with_area(nil, 0.1444.um) m53_l1.output("M5.3", "M5.3 : Minimum metal5 area : 0.1444µm²") -m53_l1.forget +m53_l1.forget end #BEOL
diff --git a/rules/klayout/drc/rule_decks/metaltop.drc b/rules/klayout/drc/rule_decks/metaltop.drc index b46285b..49a33db 100644 --- a/rules/klayout/drc/rule_decks/metaltop.drc +++ b/rules/klayout/drc/rule_decks/metaltop.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -114,7 +114,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -123,12 +123,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -204,7 +204,7 @@ via5 = polygons(82 , 0 ) metaltop = polygons(53 , 0 ) top_via = via5 - topmin1_via = via4 + topmin1_via = via4 top_metal = metaltop topmin1_metal = metal5 elsif METAL_LEVEL == "5LM" @@ -213,7 +213,7 @@ via4 = polygons(41 , 0 ) metal5 = polygons(81 , 0 ) top_via = via4 - topmin1_via = via3 + topmin1_via = via3 top_metal = metal5 topmin1_metal = metal4 elsif METAL_LEVEL == "4LM" @@ -222,7 +222,7 @@ via3 = polygons(40 , 0 ) metal4 = polygons(46 , 0 ) top_via = via3 - topmin1_via = via2 + topmin1_via = via2 top_metal = metal4 topmin1_metal = metal3 elsif METAL_LEVEL == "3LM" @@ -247,84 +247,84 @@ #================================================ #--------------------METALTOP-------------------- -#================================================ +#================================================ if BEOL logger.info("BEOL section") if METAL_TOP == "6K" -logger.info("MetalTop thickness 6k section") +logger.info("MetalTop thickness 6k section") # Rule MT.1: min. metaltop width is 0.36µm logger.info("Executing rule MT.1") mt1_l1 = metaltop.width(0.36.um, euclidian).polygons(0.001) mt1_l1.output("MT.1", "MT.1 : min. metaltop width : 0.36µm") -mt1_l1.forget +mt1_l1.forget # Rule MT.2a: min. metaltop spacing is 0.38µm logger.info("Executing rule MT.2a") mt2a_l1 = metaltop.space(0.38.um, euclidian).polygons(0.001) mt2a_l1.output("MT.2a", "MT.2a : min. metaltop spacing : 0.38µm") -mt2a_l1.forget +mt2a_l1.forget # Rule MT.4: Minimum MetalTop area is 0.5625µm² logger.info("Executing rule MT.4") mt4_l1 = metaltop.with_area(nil, 0.5625.um) mt4_l1.output("MT.4", "MT.4 : Minimum MetalTop area : 0.5625µm²") -mt4_l1.forget +mt4_l1.forget elsif METAL_TOP == "9K" -logger.info("MetalTop thickness 9k/11k section") +logger.info("MetalTop thickness 9k/11k section") # Rule MT.1: min. metaltop width is 0.44µm logger.info("Executing rule MT.1") mt1_l1 = metaltop.width(0.44.um, euclidian).polygons(0.001) mt1_l1.output("MT.1", "MT.1 : min. metaltop width : 0.44µm") -mt1_l1.forget +mt1_l1.forget # Rule MT.2a: min. metaltop spacing is 0.46µm logger.info("Executing rule MT.2a") mt2a_l1 = metaltop.space(0.46.um, euclidian).polygons(0.001) mt2a_l1.output("MT.2a", "MT.2a : min. metaltop spacing : 0.46µm") -mt2a_l1.forget +mt2a_l1.forget # Rule MT.4: Minimum MetalTop area is 0.5625µm² logger.info("Executing rule MT.4") mt4_l1 = metaltop.with_area(nil, 0.5625.um) mt4_l1.output("MT.4", "MT.4 : Minimum MetalTop area : 0.5625µm²") -mt4_l1.forget +mt4_l1.forget elsif METAL_TOP == "30K" -logger.info("MetalTop thickness 30K section") +logger.info("MetalTop thickness 30K section") # Rule MT30.1a: Min. thick MetalTop width. is 1.8µm logger.info("Executing rule MT30.1a") mt301a_l1 = metaltop.width(1.8.um, euclidian).polygons(0.001) mt301a_l1.output("MT30.1a", "MT30.1a : Min. thick MetalTop width. : 1.8µm") -mt301a_l1.forget +mt301a_l1.forget # Rule MT30.1b: Min width for >1000um long metal line (based on metal edge). is 2.2µm logger.info("Executing rule MT30.1b") mt301b_l1 = metaltop.interacting(metaltop.edges.with_length(1000.um, nil)).width(2.2.um, euclidian).polygons(0.001) mt301b_l1.output("MT30.1b", "MT30.1b : Min width for >1000um long metal line (based on metal edge). : 2.2µm") -mt301b_l1.forget +mt301b_l1.forget # Rule MT30.2: Min. thick MetalTop space. is 1.8µm logger.info("Executing rule MT30.2") mt302_l1 = metaltop.space(1.8.um, euclidian).polygons(0.001) mt302_l1.output("MT30.2", "MT30.2 : Min. thick MetalTop space. : 1.8µm") -mt302_l1.forget +mt302_l1.forget # Rule MT30.3: The separation of two corners should satisfy the minimum spacing. is 1.8µm logger.info("Executing rule MT30.3") mt303_l1 = metaltop.space(1.8.um, euclidian).polygons(0.001) mt303_l1.output("MT30.3", "MT30.3 : The separation of two corners should satisfy the minimum spacing. : 1.8µm") -mt303_l1.forget +mt303_l1.forget # Rule MT30.4: The separation of single metal line from a any degree metal line should satisfy the minimum spacing. is 1.8µm logger.info("Executing rule MT30.4") mt304_l1 = metaltop.space(1.8.um, euclidian).polygons(0.001) mt304_l1.output("MT30.4", "MT30.4 : The separation of single metal line from a any degree metal line should satisfy the minimum spacing. : 1.8µm") -mt304_l1.forget +mt304_l1.forget # Rule MT30.5: Minimum thick MetalTop enclose underlying via (for example: via5 for 6LM case) [Outside Not Allowed]. logger.info("Executing rule MT30.5") @@ -356,9 +356,9 @@ mt30p8_via.forget mt30p8_mask.forget mt30p8_slct_via.forget -end #METAL_TOP +end #METAL_TOP -end #BEOL +end #BEOL exec_end_time = Time.now
diff --git a/rules/klayout/drc/rule_decks/mim_capacitor_option_a_.drc b/rules/klayout/drc/rule_decks/mim_capacitor_option_a_.drc index 61182c2..a81f022 100644 --- a/rules/klayout/drc/rule_decks/mim_capacitor_option_a_.drc +++ b/rules/klayout/drc/rule_decks/mim_capacitor_option_a_.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -116,7 +116,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -125,12 +125,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -197,10 +197,10 @@ #================================================ #------------MIM CAPACITOR OPTION A ------------- -#================================================ +#================================================ if MIM_OPTION == "A" -logger.info("MIM Capacitor Option A section") +logger.info("MIM Capacitor Option A section") mim_virtual = fusetop.sized(1.06.um).and(metal2.interacting(fusetop)) # Rule MIM.1: Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). is 1.2µm @@ -240,13 +240,13 @@ logger.info("Executing rule MIM.5") mim5_l1 = fusetop.separation(via2.interacting(metal2), 0.4.um, euclidian).polygons(0.001) mim5_l1.output("MIM.5", "MIM.5 : Minimum spacing between top plate and the Via2 connecting to the bottom plate. : 0.4µm") -mim5_l1.forget +mim5_l1.forget # Rule MIM.6: Minimum spacing between unrelated top plates. is 0.6µm logger.info("Executing rule MIM.6") mim6_l1 = fusetop.space(0.6.um, euclidian).polygons(0.001) mim6_l1.output("MIM.6", "MIM.6 : Minimum spacing between unrelated top plates. : 0.6µm") -mim6_l1.forget +mim6_l1.forget # Rule MIM.7: Min FuseTop enclosure by CAP_MK. logger.info("Executing rule MIM.7") @@ -258,7 +258,7 @@ logger.info("Executing rule MIM.8a") mim8a_l1 = fusetop.with_area(nil, 25.um) mim8a_l1.output("MIM.8a", "MIM.8a : Minimum MIM cap area (defined by FuseTop area) (um2). : 25µm²") -mim8a_l1.forget +mim8a_l1.forget # Rule MIM.8b: Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). is 10000µm logger.info("Executing rule MIM.8b") mim8b_l1 = fusetop.with_area(10000.um,nil).not_in(fusetop.with_area(10000.um)) @@ -269,7 +269,7 @@ logger.info("Executing rule MIM.9") mim9_l1 = via2.inside(fusetop).space(0.5.um, euclidian).polygons(0.001) mim9_l1.output("MIM.9", "MIM.9 : Min. via spacing for sea of via on MIM top plate. : 0.5µm") -mim9_l1.forget +mim9_l1.forget # Rule MIM.10: (a) There cannot be any Via1 touching MIM bottom plate Metal2. (b) MIM bottom plate Metal2 can only be connected through the higher Via (Via2). logger.info("Executing rule MIM.10") @@ -294,7 +294,7 @@ logger.info("Executing rule MIM.11") mim11_l1 = mim11_large_metal2_violation mim11_l1.output("MIM.11", "MIM.11 : Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIM.8b rule. : -µm") -mim11_l1.forget +mim11_l1.forget mim11_large_metal2.forget mim11_large_metal2_violation.forget
diff --git a/rules/klayout/drc/rule_decks/mim_capacitor_option_b.drc b/rules/klayout/drc/rule_decks/mim_capacitor_option_b.drc index eaea93d..7f3be6f 100644 --- a/rules/klayout/drc/rule_decks/mim_capacitor_option_b.drc +++ b/rules/klayout/drc/rule_decks/mim_capacitor_option_b.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -113,7 +113,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -122,12 +122,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -203,7 +203,7 @@ via5 = polygons(82 , 0 ) metaltop = polygons(53 , 0 ) top_via = via5 - topmin1_via = via4 + topmin1_via = via4 top_metal = metaltop topmin1_metal = metal5 elsif METAL_LEVEL == "5LM" @@ -212,7 +212,7 @@ via4 = polygons(41 , 0 ) metal5 = polygons(81 , 0 ) top_via = via4 - topmin1_via = via3 + topmin1_via = via3 top_metal = metal5 topmin1_metal = metal4 elsif METAL_LEVEL == "4LM" @@ -221,7 +221,7 @@ via3 = polygons(40 , 0 ) metal4 = polygons(46 , 0 ) top_via = via3 - topmin1_via = via2 + topmin1_via = via2 top_metal = metal4 topmin1_metal = metal3 elsif METAL_LEVEL == "3LM" @@ -246,10 +246,10 @@ #================================================ #-------------MIM CAPACITOR OPTION B------------- -#================================================ +#================================================ if MIM_OPTION == "B" -logger.info("mim11_metal2_polygon_layer.interacting(fuse_in_polygon) section") +logger.info("mim11_metal2_polygon_layer.interacting(fuse_in_polygon) section") mimtm_virtual = fusetop.sized(1.06.um).and(topmin1_metal.interacting(fusetop)) # Rule MIMTM.1: Minimum MiM bottom plate spacing to the bottom plate metal (whether adjacent MiM or routing metal). is 1.2µm @@ -289,13 +289,13 @@ logger.info("Executing rule MIMTM.5") mimtm5_l1 = fusetop.separation(top_via.interacting(topmin1_metal), 0.4.um, euclidian).polygons(0.001) mimtm5_l1.output("MIMTM.5", "MIMTM.5 : Minimum spacing between top plate and the Vian-1 connecting to the bottom plate. : 0.4µm") -mimtm5_l1.forget +mimtm5_l1.forget # Rule MIMTM.6: Minimum spacing between unrelated top plates. is 0.6µm logger.info("Executing rule MIMTM.6") mimtm6_l1 = fusetop.space(0.6.um, euclidian).polygons(0.001) mimtm6_l1.output("MIMTM.6", "MIMTM.6 : Minimum spacing between unrelated top plates. : 0.6µm") -mimtm6_l1.forget +mimtm6_l1.forget # Rule MIMTM.7: Min FuseTop enclosure by CAP_MK. logger.info("Executing rule MIMTM.7") @@ -307,7 +307,7 @@ logger.info("Executing rule MIMTM.8a") mimtm8a_l1 = fusetop.with_area(nil, 25.um) mimtm8a_l1.output("MIMTM.8a", "MIMTM.8a : Minimum MIM cap area (defined by FuseTop area) (um2). : 25µm²") -mimtm8a_l1.forget +mimtm8a_l1.forget # Rule MIMTM.8b: Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required) (um2). is 10000µm logger.info("Executing rule MIMTM.8b") mimtm8b_l1 = fusetop.with_area(10000.um,nil).not_in(fusetop.with_area(10000.um)) @@ -318,7 +318,7 @@ logger.info("Executing rule MIMTM.9") mimtm9_l1 = top_via.inside(fusetop).space(0.5.um, euclidian).polygons(0.001) mimtm9_l1.output("MIMTM.9", "MIMTM.9 : Min. Via (Vian-1) spacing for sea of Via on MIM top plate. : 0.5µm") -mimtm9_l1.forget +mimtm9_l1.forget # Rule MIMTM.10: (a) There cannot be any Vian-2 touching MIM bottom plate Metaln-1. (b) MIM bottom plate Metaln-1 can only be connected through the higher Via (Vian-1). logger.info("Executing rule MIMTM.10") @@ -343,16 +343,16 @@ logger.info("Executing rule MIMTM.11") mimtm11_l1 = mimtm11_large_topmin1_metal_violation mimtm11_l1.output("MIMTM.11", "MIMTM.11 : Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed MIMTM.8b rule. : -µm") -mimtm11_l1.forget +mimtm11_l1.forget mimtm11_large_topmin1_metal.forget mimtm11_large_topmin1_metal_violation.forget # rule MIMTM.12 is not a DRC check else -logger.info("MIM Capacitor Option B not Selected") +logger.info("MIM Capacitor Option B not Selected") -end #MIM_OPTION +end #MIM_OPTION exec_end_time = Time.now
diff --git a/rules/klayout/drc/rule_decks/n+_poly_resistor.drc b/rules/klayout/drc/rule_decks/n+_poly_resistor.drc index 7ca5411..e7d6c74 100644 --- a/rules/klayout/drc/rule_decks/n+_poly_resistor.drc +++ b/rules/klayout/drc/rule_decks/n+_poly_resistor.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -115,7 +115,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -124,12 +124,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -196,20 +196,20 @@ #================================================ #----------------N+ POLY RESISTOR---------------- -#================================================ +#================================================ lres_poly = poly2.and(nplus).interacting(sab).interacting(res_mk) # Rule LRES.1: Minimum width of Poly2 resistor. is 0.8µm logger.info("Executing rule LRES.1") lres1_l1 = lres_poly.width(0.8.um, euclidian).polygons(0.001) lres1_l1.output("LRES.1", "LRES.1 : Minimum width of Poly2 resistor. : 0.8µm") -lres1_l1.forget +lres1_l1.forget # Rule LRES.2: Minimum space between Poly2 resistors. is 0.4µm logger.info("Executing rule LRES.2") lres2_l1 = lres_poly.isolated(0.4.um, euclidian).polygons(0.001) lres2_l1.output("LRES.2", "LRES.2 : Minimum space between Poly2 resistors. : 0.4µm") -lres2_l1.forget +lres2_l1.forget # Rule LRES.3: Minimum space from Poly2 resistor to COMP. logger.info("Executing rule LRES.3") @@ -221,7 +221,7 @@ logger.info("Executing rule LRES.4") lres4_l1 = lres_poly.separation(poly2.not_interacting(sab), 0.6.um, euclidian).polygons(0.001) lres4_l1.output("LRES.4", "LRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm") -lres4_l1.forget +lres4_l1.forget # Rule LRES.5: Minimum Nplus implant overlap of Poly2 resistor. is 0.3µm logger.info("Executing rule LRES.5") @@ -250,7 +250,7 @@ # rule LRES.8 is not a DRC check mk_lres9 = res_mk.edges.not(poly2.and(nplus).and(sab).edges).inside_part(poly2) -# Rule LRES.9a: Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. +# Rule LRES.9a: Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. logger.info("Executing rule LRES.9a") lres9a_l1 = res_mk.interacting(lres_poly).interacting(mk_lres9) lres9a_l1.output("LRES.9a", "LRES.9a : Nplus Poly2 resistor shall be covered by RES_MK marking. RES_MK length shall be coincide with resistor length (Defined by SAB length) and width covering the width of Poly2. ")
diff --git a/rules/klayout/drc/rule_decks/native_vt_nmos.drc b/rules/klayout/drc/rule_decks/native_vt_nmos.drc index 42af250..3861943 100644 --- a/rules/klayout/drc/rule_decks/native_vt_nmos.drc +++ b/rules/klayout/drc/rule_decks/native_vt_nmos.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -113,7 +113,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -122,12 +122,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -202,7 +202,7 @@ #================================================ #-----------------NATIVE VT NMOS----------------- -#================================================ +#================================================ # Rule NAT.1: Min. NAT Overlap of COMP of Native Vt NMOS. is 2µm logger.info("Executing rule NAT.1") @@ -214,30 +214,30 @@ logger.info("Executing rule NAT.2") nat2_l1 = nat.separation(comp.outside(nat), 0.3.um, euclidian).polygons(0.001) nat2_l1.output("NAT.2", "NAT.2 : Space to unrelated COMP (outside NAT). : 0.3µm") -nat2_l1.forget +nat2_l1.forget # Rule NAT.3: Space to NWell edge. is 0.5µm logger.info("Executing rule NAT.3") nat3_l1 = nat.separation(nwell, 0.5.um, euclidian).polygons(0.001) nat3_l1.output("NAT.3", "NAT.3 : Space to NWell edge. : 0.5µm") -nat3_l1.forget +nat3_l1.forget # Rule NAT.4: Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). is 1.8µm logger.info("Executing rule NAT.4") nat4_l1 = poly2.edges.and(ngate.edges).not(nwell).interacting(nat).width(1.8.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) nat4_l1.output("NAT.4", "NAT.4 : Minimum channel length for 3.3V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm") -nat4_l1.forget +nat4_l1.forget # Rule NAT.5: Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). is 1.8µm logger.info("Executing rule NAT.5") nat5_l1 = poly2.edges.and(ngate.edges).not(nwell).interacting(nat).width(1.8.um, euclidian).polygons(0.001).overlapping(dualgate) nat5_l1.output("NAT.5", "NAT.5 : Minimum channel length for 6.0V Native Vt NMOS (For smaller L Ioff will be higher than Spec). : 1.8µm") -nat5_l1.forget +nat5_l1.forget if CONNECTIVITY_RULES -logger.info("CONNECTIVITY_RULES section") +logger.info("CONNECTIVITY_RULES section") -connected_nat, unconnected_nat = conn_space(natcompsd, 10, 10, transparent) +connected_nat, unconnected_nat = conn_space(natcompsd, 10, 10, transparent) # Rule NAT.6: Two or more COMPs if connected to different potential are not allowed under same NAT layer. logger.info("Executing rule NAT.6") @@ -245,14 +245,14 @@ nat6_l1.output("NAT.6", "NAT.6 : Two or more COMPs if connected to different potential are not allowed under same NAT layer.") nat6_l1.forget -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES natcompsd.forget # Rule NAT.7: Minimum NAT to NAT spacing. is 0.74µm logger.info("Executing rule NAT.7") nat7_l1 = nat.space(0.74.um, euclidian).polygons(0.001) nat7_l1.output("NAT.7", "NAT.7 : Minimum NAT to NAT spacing. : 0.74µm") -nat7_l1.forget +nat7_l1.forget # Rule NAT.8: Min. Dualgate overlap of NAT (for 5V/6V) native VT NMOS only. logger.info("Executing rule NAT.8")
diff --git a/rules/klayout/drc/rule_decks/nplus.drc b/rules/klayout/drc/rule_decks/nplus.drc index 8818293..e3126a8 100644 --- a/rules/klayout/drc/rule_decks/nplus.drc +++ b/rules/klayout/drc/rule_decks/nplus.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -115,7 +115,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -124,12 +124,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -196,7 +196,7 @@ #================================================ #---------------------NPLUS---------------------- -#================================================ +#================================================ if FEOL @@ -206,19 +206,19 @@ logger.info("Executing rule NP.1") np1_l1 = nplus.width(0.4.um, euclidian).polygons(0.001) np1_l1.output("NP.1", "NP.1 : min. nplus width : 0.4µm") -np1_l1.forget +np1_l1.forget # Rule NP.2: min. nplus spacing is 0.4µm logger.info("Executing rule NP.2") np2_l1 = nplus.space(0.4.um, euclidian).polygons(0.001) np2_l1.output("NP.2", "NP.2 : min. nplus spacing : 0.4µm") -np2_l1.forget +np2_l1.forget # Rule NP.3a: Space to PCOMP for PCOMP: (1) Inside Nwell (2) Outside LVPWELL but inside DNWELL. is 0.16µm logger.info("Executing rule NP.3a") np3a_l1 = nplus.separation((pcomp.inside(nwell)).or(pcomp.outside(lvpwell).inside(dnwell)), 0.16.um, euclidian).polygons(0.001) np3a_l1.output("NP.3a", "NP.3a : Space to PCOMP for PCOMP: (1) Inside Nwell (2) Outside LVPWELL but inside DNWELL. : 0.16µm") -np3a_l1.forget +np3a_l1.forget np_3bi_extend = lvpwell.inside(dnwell).sized(-0.429.um) np_3bi = pcomp.edges.and(lvpwell.inside(dnwell).not(np_3bi_extend)) @@ -226,7 +226,7 @@ logger.info("Executing rule NP.3bi") np3bi_l1 = nplus.not_outside(lvpwell).inside(dnwell).edges.separation(np_3bi, 0.16.um, euclidian).polygons(0.001) np3bi_l1.output("NP.3bi", "NP.3bi : Space to PCOMP: For Inside DNWELL, inside LVPWELL:(i) For PCOMP overlap by LVPWELL < 0.43um. : 0.16µm") -np3bi_l1.forget +np3bi_l1.forget np_3bi_extend.forget np_3bi.forget @@ -236,7 +236,7 @@ logger.info("Executing rule NP.3bii") np3bii_l1 = nplus.not_outside(lvpwell).inside(dnwell).edges.separation(np_3bii, 0.08.um, euclidian).polygons(0.001) np3bii_l1.output("NP.3bii", "NP.3bii : Space to PCOMP: For Inside DNWELL, inside LVPWELL:(ii) For PCOMP overlap by LVPWELL >= 0.43um. : 0.08µm") -np3bii_l1.forget +np3bii_l1.forget np_3bii_extend.forget np_3bii.forget @@ -352,18 +352,18 @@ logger.info("Executing rule NP.7") np7_l1 = nplus.separation(poly2.and(sab), 0.18.um, euclidian).polygons(0.001) np7_l1.output("NP.7", "NP.7 : Space to unrelated unsalicided Poly2. : 0.18µm") -np7_l1.forget +np7_l1.forget # Rule NP.8a: Minimum Nplus area (um2). is 0.35µm² logger.info("Executing rule NP.8a") np8a_l1 = nplus.with_area(nil, 0.35.um) np8a_l1.output("NP.8a", "NP.8a : Minimum Nplus area (um2). : 0.35µm²") -np8a_l1.forget +np8a_l1.forget # Rule NP.8b: Minimum area enclosed by Nplus (um2). is 0.35µm² logger.info("Executing rule NP.8b") np8b_l1 = nplus.holes.with_area(nil, 0.35.um) np8b_l1.output("NP.8b", "NP.8b : Minimum area enclosed by Nplus (um2). : 0.35µm²") -np8b_l1.forget +np8b_l1.forget # Rule NP.9: Overlap of unsalicided Poly2. is 0.18µm logger.info("Executing rule NP.9") np9_l1 = nplus.enclosing(poly2.and(sab), 0.18.um, euclidian).polygons(0.001)
diff --git a/rules/klayout/drc/rule_decks/nwell.drc b/rules/klayout/drc/rule_decks/nwell.drc index 22f917d..5c33f12 100644 --- a/rules/klayout/drc/rule_decks/nwell.drc +++ b/rules/klayout/drc/rule_decks/nwell.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -117,7 +117,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -126,12 +126,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -223,7 +223,7 @@ connect(metal5, via5) connect(via5, metaltop) -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES #================================================ #------------ PRE-DEFINED FUNCTIONS ------------- @@ -249,7 +249,7 @@ end end unconnected_output = unconnected_errors.polygons.or(singularity_errors.polygons(0.001)) - return connected_output, unconnected_output + return connected_output, unconnected_output end def conn_separation(layer1, layer2, conn_val,not_conn_val, mode) @@ -278,10 +278,10 @@ if CONNECTIVITY_RULES logger.info("Connectivity rules enabled, Netlist object will be generated.") netlist -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES # === LAYOUT EXTENT === -CHIP = extent.sized(0.0) +CHIP = extent.sized(0.0) logger.info("Total area of the design is #{CHIP.area()} um^2.") @@ -289,7 +289,7 @@ #================================================ #---------------------NWELL---------------------- -#================================================ +#================================================ if FEOL @@ -299,86 +299,86 @@ logger.info("Executing rule NW.1a_3.3V") nw1a_l1 = nwell.width(0.86.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) nw1a_l1.output("NW.1a_3.3V", "NW.1a_3.3V : Min. Nwell Width (This is only for litho purpose on the generated area). : 0.86µm") -nw1a_l1.forget +nw1a_l1.forget # Rule NW.1a_5V: Min. Nwell Width (This is only for litho purpose on the generated area). is 0.86µm logger.info("Executing rule NW.1a_5V") nw1a_l1 = nwell.width(0.86.um, euclidian).polygons(0.001).overlapping(dualgate) nw1a_l1.output("NW.1a_5V", "NW.1a_5V : Min. Nwell Width (This is only for litho purpose on the generated area). : 0.86µm") -nw1a_l1.forget +nw1a_l1.forget nw_1b = nwell.outside(dnwell).and(res_mk).not(comp).not(poly2) # Rule NW.1b_3.3V: Min. Nwell Width as a resistor (Outside DNWELL only). is 2µm logger.info("Executing rule NW.1b_3.3V") nw1b_l1 = nw_1b.width(2.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) nw1b_l1.output("NW.1b_3.3V", "NW.1b_3.3V : Min. Nwell Width as a resistor (Outside DNWELL only). : 2µm") -nw1b_l1.forget +nw1b_l1.forget # Rule NW.1b_5V: Min. Nwell Width as a resistor (Outside DNWELL only). is 2µm logger.info("Executing rule NW.1b_5V") nw1b_l1 = nw_1b.width(2.um, euclidian).polygons(0.001).overlapping(dualgate) nw1b_l1.output("NW.1b_5V", "NW.1b_5V : Min. Nwell Width as a resistor (Outside DNWELL only). : 2µm") -nw1b_l1.forget +nw1b_l1.forget if CONNECTIVITY_RULES -logger.info("CONNECTIVITY_RULES section") +logger.info("CONNECTIVITY_RULES section") -connected_nwell_3p3v, unconnected_nwell_3p3v = conn_space(nwell, 0.6, 1.4, euclidian) +connected_nwell_3p3v, unconnected_nwell_3p3v = conn_space(nwell, 0.6, 1.4, euclidian) -connected_nwell_5p0v, unconnected_nwell_5p0v = conn_space(nwell, 0.74, 1.7, euclidian) +connected_nwell_5p0v, unconnected_nwell_5p0v = conn_space(nwell, 0.74, 1.7, euclidian) # Rule NW.2a_3.3V: Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. is 0.6µm logger.info("Executing rule NW.2a_3.3V") nw2a_l1 = connected_nwell_3p3v.not_inside(ymtp_mk).not_interacting(v5_xtor).not_interacting(dualgate) nw2a_l1.output("NW.2a_3.3V", "NW.2a_3.3V : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.6µm") -nw2a_l1.forget +nw2a_l1.forget # Rule NW.2a_5V: Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. is 0.74µm logger.info("Executing rule NW.2a_5V") nw2a_l1 = connected_nwell_5p0v.not_inside(ymtp_mk).overlapping(dualgate) nw2a_l1.output("NW.2a_5V", "NW.2a_5V : Min. Nwell Space (Outside DNWELL) [Equi-potential], Merge if the space is less than. : 0.74µm") -nw2a_l1.forget +nw2a_l1.forget # Rule NW.2b_3.3V: Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.4µm logger.info("Executing rule NW.2b_3.3V") nw2b_l1 = unconnected_nwell_3p3v.not_interacting(v5_xtor).not_interacting(dualgate) nw2b_l1.output("NW.2b_3.3V", "NW.2b_3.3V : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.4µm") -nw2b_l1.forget +nw2b_l1.forget # Rule NW.2b_5V: Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.7µm logger.info("Executing rule NW.2b_5V") nw2b_l1 = unconnected_nwell_5p0v.overlapping(dualgate) nw2b_l1.output("NW.2b_5V", "NW.2b_5V : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.7µm") -nw2b_l1.forget +nw2b_l1.forget else -logger.info("CONNECTIVITY_RULES disabled section") +logger.info("CONNECTIVITY_RULES disabled section") # Rule NW.2b_3.3V_: Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.4µm logger.info("Executing rule NW.2b_3.3V_") nw2b_l1 = nwell.isolated(1.4.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) nw2b_l1.output("NW.2b_3.3V_", "NW.2b_3.3V_ : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.4µm") -nw2b_l1.forget +nw2b_l1.forget # Rule NW.2b_5V_: Min. Nwell Space (Outside DNWELL) [Different potential]. is 1.7µm logger.info("Executing rule NW.2b_5V_") nw2b_l1 = nwell.isolated(1.7.um, euclidian).polygons(0.001).overlapping(dualgate) nw2b_l1.output("NW.2b_5V_", "NW.2b_5V_ : Min. Nwell Space (Outside DNWELL) [Different potential]. : 1.7µm") -nw2b_l1.forget +nw2b_l1.forget -end #CONNECTIVITY_RULES +end #CONNECTIVITY_RULES # Rule NW.3_3.3V: Min. Nwell to DNWELL space. is 3.1µm logger.info("Executing rule NW.3_3.3V") nw3_l1 = nwell.separation(dnwell, 3.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) nw3_l1.output("NW.3_3.3V", "NW.3_3.3V : Min. Nwell to DNWELL space. : 3.1µm") -nw3_l1.forget +nw3_l1.forget # Rule NW.3_5V: Min. Nwell to DNWELL space. is 3.1µm logger.info("Executing rule NW.3_5V") nw3_l1 = nwell.separation(dnwell, 3.1.um, euclidian).polygons(0.001).overlapping(dualgate) nw3_l1.output("NW.3_5V", "NW.3_5V : Min. Nwell to DNWELL space. : 3.1µm") -nw3_l1.forget +nw3_l1.forget # Rule NW.4_3.3V: Min. Nwell to LVPWELL space. logger.info("Executing rule NW.4_3.3V")
diff --git a/rules/klayout/drc/rule_decks/otp_mk.drc b/rules/klayout/drc/rule_decks/otp_mk.drc index 0e735a6..3ac5504 100644 --- a/rules/klayout/drc/rule_decks/otp_mk.drc +++ b/rules/klayout/drc/rule_decks/otp_mk.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -114,7 +114,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -123,12 +123,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -195,13 +195,13 @@ #================================================ #---------------------OTP_MK--------------------- -#================================================ +#================================================ # Rule O.DF.3a: Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. is 0.24µm logger.info("Executing rule O.DF.3a") odf3a_l1 = comp.and(otp_mk).space(0.24.um, euclidian).polygons(0.001) odf3a_l1.output("O.DF.3a", "O.DF.3a : Min. COMP Space. P-substrate tap (PCOMP outside NWELL) can be butted for different voltage devices as the potential is same. : 0.24µm") -odf3a_l1.forget +odf3a_l1.forget # Rule O.DF.6: Min. COMP extend beyond poly2 (it also means source/drain overhang). is 0.22µm logger.info("Executing rule O.DF.6") @@ -213,18 +213,18 @@ logger.info("Executing rule O.DF.9") odf9_l1 = comp.and(otp_mk).with_area(nil, 0.1444.um) odf9_l1.output("O.DF.9", "O.DF.9 : Min. COMP area (um2). : 0.1444µm²") -odf9_l1.forget +odf9_l1.forget # Rule O.PL.2: Min. poly2 width. is 0.22µm logger.info("Executing rule O.PL.2") opl2_l1 = poly2.edges.and(tgate.edges).and(otp_mk).width(0.22.um, euclidian).polygons(0.001) opl2_l1.output("O.PL.2", "O.PL.2 : Min. poly2 width. : 0.22µm") -opl2_l1.forget +opl2_l1.forget # Rule O.PL.3a: Min. poly2 Space on COMP. is 0.18µm logger.info("Executing rule O.PL.3a") opl3a_l1 = (tgate).or(poly2.not(comp)).and(otp_mk).space(0.18.um, euclidian).polygons(0.001) opl3a_l1.output("O.PL.3a", "O.PL.3a : Min. poly2 Space on COMP. : 0.18µm") -opl3a_l1.forget +opl3a_l1.forget # Rule O.PL.4: Min. extension beyond COMP to form Poly2 end cap. is 0.14µm logger.info("Executing rule O.PL.4") @@ -240,13 +240,13 @@ logger.info("Executing rule O.SB.2") osb2_l1 = sab.and(otp_mk).space(0.28.um, euclidian).polygons(0.001) osb2_l1.output("O.SB.2", "O.SB.2 : Min. salicide Block Space. : 0.28µm") -osb2_l1.forget +osb2_l1.forget # Rule O.SB.3: Min. space from salicide block to unrelated COMP. is 0.09µm logger.info("Executing rule O.SB.3") osb3_l1 = sab.outside(comp).and(otp_mk).separation(comp.outside(sab), 0.09.um, euclidian).polygons(0.001) osb3_l1.output("O.SB.3", "O.SB.3 : Min. space from salicide block to unrelated COMP. : 0.09µm") -osb3_l1.forget +osb3_l1.forget # Rule O.SB.4: Min. space from salicide block to contact. logger.info("Executing rule O.SB.4") @@ -260,7 +260,7 @@ logger.info("Executing rule O.SB.5b_3.3V") osb5b_l1 = sab.outside(tgate).and(otp_mk).separation(tgate.outside(sab), 0.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) osb5b_l1.output("O.SB.5b_3.3V", "O.SB.5b_3.3V : Min. space from salicide block to unrelated Poly2 on COMP. : 0.1µm") -osb5b_l1.forget +osb5b_l1.forget # rule O.SB.5b_5V is not a DRC check @@ -282,19 +282,19 @@ logger.info("Executing rule O.SB.13_3.3V") osb13_l1 = sab.and(otp_mk).with_area(nil, 1.488.um).not_interacting(v5_xtor).not_interacting(dualgate) osb13_l1.output("O.SB.13_3.3V", "O.SB.13_3.3V : Min. area of silicide block (um2). : 1.488µm²") -osb13_l1.forget +osb13_l1.forget # Rule O.SB.13_5V: Min. area of silicide block (um2). is 2µm² logger.info("Executing rule O.SB.13_5V") osb13_l1 = sab.and(otp_mk).and(v5_xtor).with_area(nil, 2.um) osb13_l1.output("O.SB.13_5V", "O.SB.13_5V : Min. area of silicide block (um2). : 2µm²") -osb13_l1.forget +osb13_l1.forget # rule O.SB.15b is not a DRC check # Rule O.CO.7: Min. space from COMP contact to Poly2 on COMP. is 0.13µm logger.info("Executing rule O.CO.7") oco7_l1 = contact.not_outside(comp).and(otp_mk).separation(tgate.and(otp_mk), 0.13.um, euclidian).polygons(0.001) oco7_l1.output("O.CO.7", "O.CO.7 : Min. space from COMP contact to Poly2 on COMP. : 0.13µm") -oco7_l1.forget +oco7_l1.forget # Rule O.PL.ORT: Orientation-restricted gates must have the gate width aligned along the X-axis (poly line running horizontally) in reference to wafer notch down. is 0µm logger.info("Executing rule O.PL.ORT")
diff --git a/rules/klayout/drc/rule_decks/p+_poly_resistor.drc b/rules/klayout/drc/rule_decks/p+_poly_resistor.drc index 12f971f..8c24e0b 100644 --- a/rules/klayout/drc/rule_decks/p+_poly_resistor.drc +++ b/rules/klayout/drc/rule_decks/p+_poly_resistor.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -115,7 +115,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -124,12 +124,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -196,20 +196,20 @@ #================================================ #----------------P+ POLY RESISTOR---------------- -#================================================ +#================================================ pres_poly = poly2.and(pplus).interacting(sab).interacting(res_mk).not_interacting(resistor) # Rule PRES.1: Minimum width of Poly2 resistor. is 0.8µm logger.info("Executing rule PRES.1") pres1_l1 = pres_poly.width(0.8.um, euclidian).polygons(0.001) pres1_l1.output("PRES.1", "PRES.1 : Minimum width of Poly2 resistor. : 0.8µm") -pres1_l1.forget +pres1_l1.forget # Rule PRES.2: Minimum space between Poly2 resistors. is 0.4µm logger.info("Executing rule PRES.2") pres2_l1 = pres_poly.isolated(0.4.um, euclidian).polygons(0.001) pres2_l1.output("PRES.2", "PRES.2 : Minimum space between Poly2 resistors. : 0.4µm") -pres2_l1.forget +pres2_l1.forget # Rule PRES.3: Minimum space from Poly2 resistor to COMP. logger.info("Executing rule PRES.3") @@ -221,7 +221,7 @@ logger.info("Executing rule PRES.4") pres4_l1 = pres_poly.separation(poly2.not_interacting(sab), 0.6.um, euclidian).polygons(0.001) pres4_l1.output("PRES.4", "PRES.4 : Minimum space from Poly2 resistor to unrelated Poly2. : 0.6µm") -pres4_l1.forget +pres4_l1.forget # Rule PRES.5: Minimum Plus implant overlap of Poly2 resistor. is 0.3µm logger.info("Executing rule PRES.5")
diff --git a/rules/klayout/drc/rule_decks/poly2.drc b/rules/klayout/drc/rule_decks/poly2.drc index e3afbf0..f9015f1 100644 --- a/rules/klayout/drc/rule_decks/poly2.drc +++ b/rules/klayout/drc/rule_decks/poly2.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -118,7 +118,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -127,12 +127,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -199,7 +199,7 @@ #================================================ #---------------------POLY2---------------------- -#================================================ +#================================================ if FEOL @@ -209,31 +209,31 @@ logger.info("Executing rule PL.1_3.3V") pl1_l1 = poly2.outside(plfuse).not(ymtp_mk).width(0.18.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) pl1_l1.output("PL.1_3.3V", "PL.1_3.3V : Interconnect Width (outside PLFUSE). : 0.18µm") -pl1_l1.forget +pl1_l1.forget # Rule PL.1_5V: Interconnect Width (outside PLFUSE). is 0.2µm logger.info("Executing rule PL.1_5V") pl1_l1 = poly2.outside(plfuse).not(ymtp_mk).width(0.2.um, euclidian).polygons(0.001).overlapping(dualgate) pl1_l1.output("PL.1_5V", "PL.1_5V : Interconnect Width (outside PLFUSE). : 0.2µm") -pl1_l1.forget +pl1_l1.forget # Rule PL.1a_3.3V: Interconnect Width (inside PLFUSE). is 0.18µm logger.info("Executing rule PL.1a_3.3V") pl1a_l1 = poly2.inside(plfuse).width(0.18.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) pl1a_l1.output("PL.1a_3.3V", "PL.1a_3.3V : Interconnect Width (inside PLFUSE). : 0.18µm") -pl1a_l1.forget +pl1a_l1.forget # Rule PL.1a_5V: Interconnect Width (inside PLFUSE). is 0.18µm logger.info("Executing rule PL.1a_5V") pl1a_l1 = poly2.inside(plfuse).width(0.18.um, euclidian).polygons(0.001).overlapping(dualgate) pl1a_l1.output("PL.1a_5V", "PL.1a_5V : Interconnect Width (inside PLFUSE). : 0.18µm") -pl1a_l1.forget +pl1a_l1.forget # Rule PL.2_3.3V: Gate Width (Channel Length). is 0.28µm logger.info("Executing rule PL.2_3.3V") pl2_l1 = poly2.edges.and(tgate.edges).not(otp_mk).not(ymtp_mk).width(0.28.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) pl2_l1.output("PL.2_3.3V", "PL.2_3.3V : Gate Width (Channel Length). : 0.28µm") -pl2_l1.forget +pl2_l1.forget pl_2_5v_n = comp.not(poly2).edges.and(ngate.edges).and(v5_xtor).and(dualgate).space(0.6.um, euclidian).polygons pl_2_5v_p = comp.not(poly2).edges.and(pgate.edges).and(v5_xtor).and(dualgate).space(0.5.um, euclidian).polygons @@ -253,13 +253,13 @@ logger.info("Executing rule PL.3a_3.3V") pl3a_l1 = (tgate).or(poly2.not(comp)).not(otp_mk).space(0.24.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) pl3a_l1.output("PL.3a_3.3V", "PL.3a_3.3V : Space on COMP/Field. : 0.24µm") -pl3a_l1.forget +pl3a_l1.forget # Rule PL.3a_5V: Space on COMP/Field. is 0.24µm logger.info("Executing rule PL.3a_5V") pl3a_l1 = (tgate).or(poly2.not(comp)).not(otp_mk).space(0.24.um, euclidian).polygons(0.001).overlapping(dualgate) pl3a_l1.output("PL.3a_5V", "PL.3a_5V : Space on COMP/Field. : 0.24µm") -pl3a_l1.forget +pl3a_l1.forget # rule PL.3b_3.3V is not a DRC check @@ -283,25 +283,25 @@ logger.info("Executing rule PL.5a_3.3V") pl5a_l1 = poly_pl.separation(comp_pl, 0.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) pl5a_l1.output("PL.5a_3.3V", "PL.5a_3.3V : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.1µm") -pl5a_l1.forget +pl5a_l1.forget # Rule PL.5a_5V: Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. is 0.3µm logger.info("Executing rule PL.5a_5V") pl5a_l1 = poly_pl.outside(sramcore).separation(comp_pl, 0.3.um, euclidian).polygons(0.001).overlapping(dualgate) pl5a_l1.output("PL.5a_5V", "PL.5a_5V : Space from field Poly2 to unrelated COMP Spacer from field Poly2 to Guard-ring. : 0.3µm") -pl5a_l1.forget +pl5a_l1.forget # Rule PL.5b_3.3V: Space from field Poly2 to related COMP. is 0.1µm logger.info("Executing rule PL.5b_3.3V") pl5b_l1 = poly_pl.separation(comp_pl, 0.1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) pl5b_l1.output("PL.5b_3.3V", "PL.5b_3.3V : Space from field Poly2 to related COMP. : 0.1µm") -pl5b_l1.forget +pl5b_l1.forget # Rule PL.5b_5V: Space from field Poly2 to related COMP. is 0.3µm logger.info("Executing rule PL.5b_5V") pl5b_l1 = poly_pl.outside(sramcore).separation(comp_pl, 0.3.um, euclidian).polygons(0.001).overlapping(dualgate) pl5b_l1.output("PL.5b_5V", "PL.5b_5V : Space from field Poly2 to related COMP. : 0.3µm") -pl5b_l1.forget +pl5b_l1.forget poly_pl.forget comp_pl.forget @@ -318,13 +318,13 @@ logger.info("Executing rule PL.7_3.3V") pl7_l1 = poly_45deg.width(0.3.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) pl7_l1.output("PL.7_3.3V", "PL.7_3.3V : 45 degree bent gate width : 0.3µm") -pl7_l1.forget +pl7_l1.forget # Rule PL.7_5V: 45 degree bent gate width is 0.7µm logger.info("Executing rule PL.7_5V") pl7_l1 = poly_45deg.width(0.7.um, euclidian).polygons(0.001).overlapping(dualgate) pl7_l1.output("PL.7_5V", "PL.7_5V : 45 degree bent gate width : 0.7µm") -pl7_l1.forget +pl7_l1.forget poly_45deg.forget # Rule PL.9: Poly2 inter connect connecting 3.3V and 5V areas (area inside and outside Dualgate) are not allowed. They shall be done though metal lines only.
diff --git a/rules/klayout/drc/rule_decks/pplus.drc b/rules/klayout/drc/rule_decks/pplus.drc index a31a6ff..945aa59 100644 --- a/rules/klayout/drc/rule_decks/pplus.drc +++ b/rules/klayout/drc/rule_decks/pplus.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -116,7 +116,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -125,12 +125,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -197,7 +197,7 @@ #================================================ #---------------------PPLUS---------------------- -#================================================ +#================================================ if FEOL @@ -207,26 +207,26 @@ logger.info("Executing rule PP.1") pp1_l1 = pplus.width(0.4.um, euclidian).polygons(0.001) pp1_l1.output("PP.1", "PP.1 : min. pplus width : 0.4µm") -pp1_l1.forget +pp1_l1.forget # Rule PP.2: min. pplus spacing is 0.4µm logger.info("Executing rule PP.2") pp2_l1 = pplus.space(0.4.um, euclidian).polygons(0.001) pp2_l1.output("PP.2", "PP.2 : min. pplus spacing : 0.4µm") -pp2_l1.forget +pp2_l1.forget # Rule PP.3a: Space to NCOMP for NCOMP (1) inside LVPWELL (2) outside NWELL and DNWELL. is 0.16µm logger.info("Executing rule PP.3a") pp3a_l1 = pplus.separation((ncomp.inside(lvpwell)).or(ncomp.outside(nwell).outside(dnwell)), 0.16.um, euclidian).polygons(0.001) pp3a_l1.output("PP.3a", "PP.3a : Space to NCOMP for NCOMP (1) inside LVPWELL (2) outside NWELL and DNWELL. : 0.16µm") -pp3a_l1.forget +pp3a_l1.forget pp_3bi = ncomp.edges.not(lvpwell.inside(dnwell).sized(0.429.um)) # Rule PP.3bi: Space to NCOMP: For Inside DNWELL. (i) NCOMP space to LVPWELL >= 0.43um. is 0.08µm logger.info("Executing rule PP.3bi") pp3bi_l1 = pplus.inside(dnwell).edges.separation(pp_3bi, 0.08.um, euclidian).polygons(0.001) pp3bi_l1.output("PP.3bi", "PP.3bi : Space to NCOMP: For Inside DNWELL. (i) NCOMP space to LVPWELL >= 0.43um. : 0.08µm") -pp3bi_l1.forget +pp3bi_l1.forget pp_3bi.forget pp_3bii = ncomp.edges.and(lvpwell.inside(dnwell).sized(0.429.um)) @@ -234,7 +234,7 @@ logger.info("Executing rule PP.3bii") pp3bii_l1 = pplus.inside(dnwell).edges.separation(pp_3bii, 0.16.um, euclidian).polygons(0.001) pp3bii_l1.output("PP.3bii", "PP.3bii : Space to NCOMP: For Inside DNWELL. (ii) NCOMP space to LVPWELL < 0.43um. : 0.16µm") -pp3bii_l1.forget +pp3bii_l1.forget pp_3bii.forget pp_3ci_extend = nwell.outside(dnwell).sized(-0.429.um) @@ -243,7 +243,7 @@ logger.info("Executing rule PP.3ci") pp3ci_l1 = pplus.outside(dnwell).edges.separation(pp_3ci, 0.08.um, euclidian).polygons(0.001) pp3ci_l1.output("PP.3ci", "PP.3ci : Space to NCOMP: For Outside DNWELL, inside Nwell: (i) NWELL Overlap of NCOMP >= 0.43um. : 0.08µm") -pp3ci_l1.forget +pp3ci_l1.forget pp_3ci_extend.forget pp_3ci.forget @@ -253,7 +253,7 @@ logger.info("Executing rule PP.3cii") pp3cii_l1 = pplus.outside(dnwell).edges.separation(pp_3cii, 0.16.um, euclidian).polygons(0.001) pp3cii_l1.output("PP.3cii", "PP.3cii : Space to NCOMP: For Outside DNWELL, inside Nwell: (ii) NWELL Overlap of NCOMP 0.43um. : 0.16µm") -pp3cii_l1.forget +pp3cii_l1.forget pp_3cii_extend.forget pp_3cii.forget @@ -353,18 +353,18 @@ logger.info("Executing rule PP.7") pp7_l1 = pplus.separation(poly2.and(sab), 0.18.um, euclidian).polygons(0.001) pp7_l1.output("PP.7", "PP.7 : Space to unrelated unsalicided Poly2. : 0.18µm") -pp7_l1.forget +pp7_l1.forget # Rule PP.8a: Minimum Pplus area (um2). is 0.35µm² logger.info("Executing rule PP.8a") pp8a_l1 = pplus.with_area(nil, 0.35.um) pp8a_l1.output("PP.8a", "PP.8a : Minimum Pplus area (um2). : 0.35µm²") -pp8a_l1.forget +pp8a_l1.forget # Rule PP.8b: Minimum area enclosed by Pplus (um2). is 0.35µm² logger.info("Executing rule PP.8b") pp8b_l1 = pplus.holes.with_area(nil, 0.35.um) pp8b_l1.output("PP.8b", "PP.8b : Minimum area enclosed by Pplus (um2). : 0.35µm²") -pp8b_l1.forget +pp8b_l1.forget # Rule PP.9: Overlap of unsalicided Poly2. is 0.18µm logger.info("Executing rule PP.9") pp9_l1 = pplus.enclosing(poly2.not_interacting(resistor).and(sab), 0.18.um, euclidian).polygons(0.001)
diff --git a/rules/klayout/drc/rule_decks/sab.drc b/rules/klayout/drc/rule_decks/sab.drc index e021b27..86e64f3 100644 --- a/rules/klayout/drc/rule_decks/sab.drc +++ b/rules/klayout/drc/rule_decks/sab.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -118,7 +118,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -127,12 +127,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -199,7 +199,7 @@ #================================================ #----------------------SAB----------------------- -#================================================ +#================================================ if FEOL @@ -209,19 +209,19 @@ logger.info("Executing rule SB.1") sb1_l1 = sab.width(0.42.um, euclidian).polygons(0.001) sb1_l1.output("SB.1", "SB.1 : min. sab width : 0.42µm") -sb1_l1.forget +sb1_l1.forget # Rule SB.2: min. sab spacing is 0.42µm logger.info("Executing rule SB.2") sb2_l1 = sab.outside(otp_mk).space(0.42.um, euclidian).polygons(0.001) sb2_l1.output("SB.2", "SB.2 : min. sab spacing : 0.42µm") -sb2_l1.forget +sb2_l1.forget # Rule SB.3: Space from salicide block to unrelated COMP. is 0.22µm logger.info("Executing rule SB.3") sb3_l1 = sab.outside(comp).outside(otp_mk).separation(comp.outside(sab), 0.22.um, euclidian).polygons(0.001) sb3_l1.output("SB.3", "SB.3 : Space from salicide block to unrelated COMP. : 0.22µm") -sb3_l1.forget +sb3_l1.forget # Rule SB.4: Space from salicide block to contact. logger.info("Executing rule SB.4") @@ -233,13 +233,13 @@ logger.info("Executing rule SB.5a") sb5a_l1 = sab.outside(poly2.not(comp)).outside(otp_mk).separation(poly2.not(comp).outside(sab), 0.3.um, euclidian).polygons(0.001) sb5a_l1.output("SB.5a", "SB.5a : Space from salicide block to unrelated Poly2 on field. : 0.3µm") -sb5a_l1.forget +sb5a_l1.forget # Rule SB.5b: Space from salicide block to unrelated Poly2 on COMP. is 0.28µm logger.info("Executing rule SB.5b") sb5b_l1 = sab.outside(tgate).outside(otp_mk).separation(tgate.outside(sab), 0.28.um, euclidian).polygons(0.001) sb5b_l1.output("SB.5b", "SB.5b : Space from salicide block to unrelated Poly2 on COMP. : 0.28µm") -sb5b_l1.forget +sb5b_l1.forget # Rule SB.6: Salicide block extension beyond related COMP. is 0.22µm logger.info("Executing rule SB.6") @@ -287,7 +287,7 @@ logger.info("Executing rule SB.13") sb13_l1 = sab.outside(otp_mk).with_area(nil, 2.um) sb13_l1.output("SB.13", "SB.13 : Min. area (um2). : 2µm²") -sb13_l1.forget +sb13_l1.forget # Rule SB.14a: Space from unsalicided Nplus Poly2 to unsalicided Pplus Poly2. (Unsalicided Nplus Poly2 must not fall within a square of 0.56um x 0.56um at unsalicided Pplus Poly2 corners). is 0.56µm logger.info("Executing rule SB.14a") sb14a_l1 = poly2.and(nplus).and(sab).separation(poly2.and(pplus).and(sab), 0.56.um, square).polygons @@ -304,7 +304,7 @@ logger.info("Executing rule SB.15a") sb15a_l1 = poly2.and(sab).separation(nplus.or(pplus), 0.18.um, euclidian).polygons(0.001) sb15a_l1.output("SB.15a", "SB.15a : Space from unsalicided Poly2 to unrelated Nplus/Pplus. : 0.18µm") -sb15a_l1.forget +sb15a_l1.forget sb_15b_1 = poly2.interacting(nplus.or(pplus)).and(sab).edges.not(poly2.edges.and(sab)).separation(nplus.or(pplus).edges, 0.32.um, projection).polygons(0.001) sb_15b_2 = poly2.interacting(nplus.or(pplus)).and(sab).separation(nplus.or(pplus), 0.32.um, projection).polygons(0.001)
diff --git a/rules/klayout/drc/rule_decks/via1.drc b/rules/klayout/drc/rule_decks/via1.drc index 30806d2..00f78ee 100644 --- a/rules/klayout/drc/rule_decks/via1.drc +++ b/rules/klayout/drc/rule_decks/via1.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -114,7 +114,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -123,12 +123,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -195,7 +195,7 @@ #================================================ #----------------------VIA1---------------------- -#================================================ +#================================================ if BEOL @@ -211,7 +211,7 @@ logger.info("Executing rule V1.2a") v12a_l1 = via1.space(0.26.um, euclidian).polygons(0.001) v12a_l1.output("V1.2a", "V1.2a : min. via1 spacing : 0.26µm") -v12a_l1.forget +v12a_l1.forget merged_via1 = via1.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal1) via1_mask = merged_via1.size(1).not(via1).with_holes(16, nil) @@ -220,7 +220,7 @@ logger.info("Executing rule V1.2b") v12b_l1 = selected_via1.space(0.36.um, euclidian).polygons(0.001) v12b_l1.output("V1.2b", "V1.2b : Via1 Space in 4x4 or larger via1 array : 0.36µm") -v12b_l1.forget +v12b_l1.forget merged_via1.forget via1_mask.forget
diff --git a/rules/klayout/drc/rule_decks/via2.drc b/rules/klayout/drc/rule_decks/via2.drc index 964d234..2daaf11 100644 --- a/rules/klayout/drc/rule_decks/via2.drc +++ b/rules/klayout/drc/rule_decks/via2.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -114,7 +114,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -123,12 +123,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -195,7 +195,7 @@ #================================================ #----------------------VIA2---------------------- -#================================================ +#================================================ if BEOL @@ -211,7 +211,7 @@ logger.info("Executing rule V2.2a") v22a_l1 = via2.space(0.26.um, euclidian).polygons(0.001) v22a_l1.output("V2.2a", "V2.2a : min. via2 spacing : 0.26µm") -v22a_l1.forget +v22a_l1.forget merged_via2 = via2.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal2) via2_mask = merged_via2.size(1).not(via2).with_holes(16, nil) @@ -220,7 +220,7 @@ logger.info("Executing rule V2.2b") v22b_l1 = selected_via2.space(0.36.um, euclidian).polygons(0.001) v22b_l1.output("V2.2b", "V2.2b : Via2 Space in 4x4 or larger via2 array : 0.36µm") -v22b_l1.forget +v22b_l1.forget merged_via2.forget via2_mask.forget
diff --git a/rules/klayout/drc/rule_decks/via3.drc b/rules/klayout/drc/rule_decks/via3.drc index 058b553..81d9604 100644 --- a/rules/klayout/drc/rule_decks/via3.drc +++ b/rules/klayout/drc/rule_decks/via3.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -114,7 +114,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -123,12 +123,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -195,7 +195,7 @@ #================================================ #----------------------VIA3---------------------- -#================================================ +#================================================ if BEOL @@ -211,7 +211,7 @@ logger.info("Executing rule V3.2a") v32a_l1 = via3.space(0.26.um, euclidian).polygons(0.001) v32a_l1.output("V3.2a", "V3.2a : min. via3 spacing : 0.26µm") -v32a_l1.forget +v32a_l1.forget merged_via3 = via3.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal3) via3_mask = merged_via3.size(1).not(via3).with_holes(16, nil) @@ -220,7 +220,7 @@ logger.info("Executing rule V3.2b") v32b_l1 = selected_via3.space(0.36.um, euclidian).polygons(0.001) v32b_l1.output("V3.2b", "V3.2b : Via3 Space in 4x4 or larger via3 array : 0.36µm") -v32b_l1.forget +v32b_l1.forget merged_via3.forget via3_mask.forget
diff --git a/rules/klayout/drc/rule_decks/via4.drc b/rules/klayout/drc/rule_decks/via4.drc index 93bfe4d..44cddb3 100644 --- a/rules/klayout/drc/rule_decks/via4.drc +++ b/rules/klayout/drc/rule_decks/via4.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -114,7 +114,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -123,12 +123,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -195,7 +195,7 @@ #================================================ #----------------------VIA4---------------------- -#================================================ +#================================================ if BEOL @@ -211,7 +211,7 @@ logger.info("Executing rule V4.2a") v42a_l1 = via4.space(0.26.um, euclidian).polygons(0.001) v42a_l1.output("V4.2a", "V4.2a : min. via4 spacing : 0.26µm") -v42a_l1.forget +v42a_l1.forget merged_via4 = via4.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal4) via4_mask = merged_via4.size(1).not(via4).with_holes(16, nil) @@ -220,7 +220,7 @@ logger.info("Executing rule V4.2b") v42b_l1 = selected_via4.space(0.36.um, euclidian).polygons(0.001) v42b_l1.output("V4.2b", "V4.2b : Via4 Space in 4x4 or larger Vian array : 0.36µm") -v42b_l1.forget +v42b_l1.forget merged_via4.forget via4_mask.forget
diff --git a/rules/klayout/drc/rule_decks/via5.drc b/rules/klayout/drc/rule_decks/via5.drc index 30d6373..6e950d1 100644 --- a/rules/klayout/drc/rule_decks/via5.drc +++ b/rules/klayout/drc/rule_decks/via5.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -114,7 +114,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -123,12 +123,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -195,7 +195,7 @@ #================================================ #----------------------VIA5---------------------- -#================================================ +#================================================ if BEOL @@ -211,7 +211,7 @@ logger.info("Executing rule V5.2a") v52a_l1 = via5.space(0.26.um, euclidian).polygons(0.001) v52a_l1.output("V5.2a", "V5.2a : min. via5 spacing : 0.26µm") -v52a_l1.forget +v52a_l1.forget merged_via5 = via5.sized(0.18.um).sized(-0.18.um).with_bbox_min(1.82.um , nil).extents.inside(metal5) via5_mask = merged_via5.size(1).not(via5).with_holes(16, nil) @@ -220,7 +220,7 @@ logger.info("Executing rule V5.2b") v52b_l1 = selected_via5.space(0.36.um, euclidian).polygons(0.001) v52b_l1.output("V5.2b", "V5.2b : Via5 Space in 4x4 or larger via5 array : 0.36µm") -v52b_l1.forget +v52b_l1.forget merged_via5.forget via5_mask.forget
diff --git a/rules/klayout/drc/rule_decks/ymtp_mk.drc b/rules/klayout/drc/rule_decks/ymtp_mk.drc index 350103b..96bb507 100644 --- a/rules/klayout/drc/rule_decks/ymtp_mk.drc +++ b/rules/klayout/drc/rule_decks/ymtp_mk.drc
@@ -32,7 +32,7 @@ logger.info("Loading database to memory is complete.") -if $report +if $report logger.info("GF180MCU Klayout DRC runset output at: %s" % [$report]) report("DRC Run Report at", $report) else @@ -49,29 +49,29 @@ end # === TILING MODE === -if $run_mode == "tiling" +if $run_mode == "tiling" # use a tile size of 1mm - not used in deep mode- # tiles(500.um) # use a tile border of 10 micron: # tile_borders(10.um) tiles(1000) - logger.info("Tiling mode is enabled.") + logger.info("Tiling mode is enabled.") elsif $run_mode == "deep" #=== HIER MODE === deep - logger.info("deep mode is enabled.") + logger.info("deep mode is enabled.") elsif $run_mode == "flat" #=== FLAT MODE === flat - logger.info("flat mode is enabled.") + logger.info("flat mode is enabled.") else #=== FLAT MODE === flat - logger.info("flat mode is enabled.") - + logger.info("flat mode is enabled.") + end # run_mode #================================================ @@ -116,7 +116,7 @@ end # FEOL # BEOL -if $beol == "false" +if $beol == "false" BEOL = $beol logger.info("BEOL is disabled.") else @@ -125,12 +125,12 @@ end # BEOL # connectivity rules -if $conn_drc == "true" +if $conn_drc == "true" CONNECTIVITY_RULES = $conn_drc - logger.info("connectivity rules are enabled.") + logger.info("connectivity rules are enabled.") else CONNECTIVITY_RULES = false - logger.info("connectivity rules are disabled.") + logger.info("connectivity rules are disabled.") end # connectivity rules # METAL_TOP @@ -197,19 +197,19 @@ #================================================ #--------------------YMTP_MK--------------------- -#================================================ +#================================================ # Rule Y.NW.2b_3.3V: Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. is 1µm logger.info("Executing rule Y.NW.2b_3.3V") ynw2b_l1 = nwell.outside(dnwell).inside(ymtp_mk).space(1.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) ynw2b_l1.output("Y.NW.2b_3.3V", "Y.NW.2b_3.3V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm") -ynw2b_l1.forget +ynw2b_l1.forget # Rule Y.NW.2b_5V: Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. is 1µm logger.info("Executing rule Y.NW.2b_5V") ynw2b_l1 = nwell.outside(dnwell).inside(ymtp_mk).space(1.um, euclidian).polygons(0.001).overlapping(dualgate) ynw2b_l1.output("Y.NW.2b_5V", "Y.NW.2b_5V : Min. Nwell Space (Outside DNWELL, Inside YMTP_MK) [Different potential]. : 1µm") -ynw2b_l1.forget +ynw2b_l1.forget # rule Y.DF.4d_3.3V is not a DRC check @@ -225,19 +225,19 @@ logger.info("Executing rule Y.DF.16_3.3V") ydf16_l1 = ncomp.outside(nwell).outside(dnwell).separation(nwell.outside(dnwell), 0.27.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) ydf16_l1.output("Y.DF.16_3.3V", "Y.DF.16_3.3V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.27µm") -ydf16_l1.forget +ydf16_l1.forget # Rule Y.DF.16_5V: Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). is 0.23µm logger.info("Executing rule Y.DF.16_5V") ydf16_l1 = ncomp.outside(nwell).outside(dnwell).separation(nwell.outside(dnwell), 0.23.um, euclidian).polygons(0.001).overlapping(dualgate) ydf16_l1.output("Y.DF.16_5V", "Y.DF.16_5V : Min. space from (Nwell outside DNWELL) to (unrelated NCOMP outside Nwell and DNWELL) (inside YMTP_MK). : 0.23µm") -ydf16_l1.forget +ydf16_l1.forget # Rule Y.PL.1_3.3V: Interconnect Width (inside YMTP_MK). is 0.13µm logger.info("Executing rule Y.PL.1_3.3V") ypl1_l1 = poly2.outside(plfuse).and(ymtp_mk).width(0.13.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) ypl1_l1.output("Y.PL.1_3.3V", "Y.PL.1_3.3V : Interconnect Width (inside YMTP_MK). : 0.13µm") -ypl1_l1.forget +ypl1_l1.forget # Rule Y.PL.1_5V: Interconnect Width (inside YMTP_MK). This rule is currently not applicable for 5V. logger.info("Executing rule Y.PL.1_5V") @@ -249,13 +249,13 @@ logger.info("Executing rule Y.PL.2_3.3V") ypl2_l1 = poly2.edges.and(tgate.edges).not(otp_mk).and(ymtp_mk).width(0.13.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) ypl2_l1.output("Y.PL.2_3.3V", "Y.PL.2_3.3V : Gate Width (Channel Length) (inside YMTP_MK). : 0.13µm") -ypl2_l1.forget +ypl2_l1.forget # Rule Y.PL.2_5V: Gate Width (Channel Length) (inside YMTP_MK). is 0.47µm logger.info("Executing rule Y.PL.2_5V") ypl2_l1 = poly2.edges.and(tgate.edges).not(otp_mk).and(ymtp_mk).width(0.47.um, euclidian).polygons(0.001).overlapping(dualgate) ypl2_l1.output("Y.PL.2_5V", "Y.PL.2_5V : Gate Width (Channel Length) (inside YMTP_MK). : 0.47µm") -ypl2_l1.forget +ypl2_l1.forget # Rule Y.PL.4_5V: Poly2 extension beyond COMP to form Poly2 end cap (inside YMTP_MK). is 0.16µm logger.info("Executing rule Y.PL.4_5V") @@ -267,25 +267,25 @@ logger.info("Executing rule Y.PL.5a_3.3V") ypl5a_l1 = poly2.and(ymtp_mk).separation(comp.and(ymtp_mk), 0.04.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) ypl5a_l1.output("Y.PL.5a_3.3V", "Y.PL.5a_3.3V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.04µm") -ypl5a_l1.forget +ypl5a_l1.forget # Rule Y.PL.5a_5V: Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). is 0.2µm logger.info("Executing rule Y.PL.5a_5V") ypl5a_l1 = poly2.and(ymtp_mk).separation(comp.and(ymtp_mk), 0.2.um, euclidian).polygons(0.001).overlapping(dualgate) ypl5a_l1.output("Y.PL.5a_5V", "Y.PL.5a_5V : Space from field Poly2 to unrelated COMP (inside YMTP_MK). Space from field Poly2 to Guard-ring (inside YMTP_MK). : 0.2µm") -ypl5a_l1.forget +ypl5a_l1.forget # Rule Y.PL.5b_3.3V: Space from field Poly2 to related COMP (inside YMTP_MK). is 0.04µm logger.info("Executing rule Y.PL.5b_3.3V") ypl5b_l1 = poly2.and(ymtp_mk).separation(comp.and(ymtp_mk), 0.04.um, euclidian).polygons(0.001).not_interacting(v5_xtor).not_interacting(dualgate) ypl5b_l1.output("Y.PL.5b_3.3V", "Y.PL.5b_3.3V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.04µm") -ypl5b_l1.forget +ypl5b_l1.forget # Rule Y.PL.5b_5V: Space from field Poly2 to related COMP (inside YMTP_MK). is 0.2µm logger.info("Executing rule Y.PL.5b_5V") ypl5b_l1 = poly2.and(ymtp_mk).separation(comp.and(ymtp_mk), 0.2.um, euclidian).polygons(0.001).overlapping(dualgate) ypl5b_l1.output("Y.PL.5b_5V", "Y.PL.5b_5V : Space from field Poly2 to related COMP (inside YMTP_MK). : 0.2µm") -ypl5b_l1.forget +ypl5b_l1.forget # rule Y.PL.6_3.3V is not a DRC check